// // ----------------------------------------------------------------------------- // Copyright (c) 2011-2014 Qualcomm Atheros, Inc. All rights reserved. // ----------------------------------------------------------------------------- // FILE : chn_reg_map.h // DESCRIPTION : Software Header File for WiFi 2.5 // THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT // ----------------------------------------------------------------------------- // #ifndef _PHY_CHN_REG_MAP_H_ #define _PHY_CHN_REG_MAP_H_ #ifndef __PHY_CHN_REG_MAP_BASE_ADDRESS #define __PHY_CHN_REG_MAP_BASE_ADDRESS (0x10400) #endif // 0x0 (PHY_BB_TIMING_CONTROLS_1) #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB 31 #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MSB 31 #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK 0x80000000 #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK) >> PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB) #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB) & PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK) #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB 29 #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MSB 30 #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK 0x60000000 #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK) >> PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB) #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB) & PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK) #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB 28 #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MSB 28 #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK 0x10000000 #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK) >> PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB) #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB) & PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK) #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB 27 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MSB 27 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK 0x8000000 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK) >> PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB) #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB) & PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK) #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB 25 #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MSB 26 #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK 0x6000000 #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK) >> PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB) #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB) & PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK) #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB 24 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MSB 24 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK 0x1000000 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK) >> PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB) #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB) & PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK) #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB 23 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MSB 23 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK 0x800000 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK) >> PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB) #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB) & PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK) #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB 22 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MSB 22 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK 0x400000 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK) >> PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB) #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB) & PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK) #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB 20 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MSB 21 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK 0x300000 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK) >> PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB) #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB) & PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK) #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB 18 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MSB 19 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK 0xc0000 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK) >> PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB) #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB) & PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK) #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB 7 #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MSB 12 #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK 0x1f80 #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK) >> PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB) #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB) & PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK) #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB 0 #define PHY_BB_TIMING_CONTROLS_1_STE_THR_MSB 6 #define PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK 0x7f #define PHY_BB_TIMING_CONTROLS_1_STE_THR_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK) >> PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB) #define PHY_BB_TIMING_CONTROLS_1_STE_THR_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB) & PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK) #define PHY_BB_TIMING_CONTROLS_1_STE_THR_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_1_ADDRESS (0x0 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TIMING_CONTROLS_1_RSTMASK 0xfffc1fff #define PHY_BB_TIMING_CONTROLS_1_RESET 0x0 // 0x4 (PHY_BB_TIMING_CONTROLS_2) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB 31 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MSB 31 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK 0x80000000 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK) >> PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB) & PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB 30 #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MSB 30 #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK 0x40000000 #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK) >> PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB) #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB) & PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK) #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB 29 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MSB 29 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK 0x20000000 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK) >> PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB) & PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB 28 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MSB 28 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK 0x10000000 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK) >> PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB) & PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB 27 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MSB 27 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK 0x8000000 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK) >> PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB) & PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB 24 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MSB 26 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK 0x7000000 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK) >> PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB) #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB) & PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK) #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_PILOT_INTERPOLATION_LSB 23 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_PILOT_INTERPOLATION_MSB 23 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_PILOT_INTERPOLATION_MASK 0x800000 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_PILOT_INTERPOLATION_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_ENABLE_PILOT_INTERPOLATION_MASK) >> PHY_BB_TIMING_CONTROLS_2_ENABLE_PILOT_INTERPOLATION_LSB) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_PILOT_INTERPOLATION_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_ENABLE_PILOT_INTERPOLATION_LSB) & PHY_BB_TIMING_CONTROLS_2_ENABLE_PILOT_INTERPOLATION_MASK) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_PILOT_INTERPOLATION_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB 16 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MSB 22 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK 0x7f0000 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK) >> PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB) #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB) & PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK) #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB 15 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MSB 15 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK 0x8000 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK) >> PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB) & PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MIMO_LSB 14 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MIMO_MSB 14 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MIMO_MASK 0x4000 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MIMO_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MIMO_MASK) >> PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MIMO_LSB) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MIMO_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MIMO_LSB) & PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MIMO_MASK) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MIMO_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB 13 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MSB 13 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK 0x2000 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK) >> PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB) & PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK) #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB 12 #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MSB 12 #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK 0x1000 #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK) >> PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB) #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB) & PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK) #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB 0 #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MSB 11 #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK 0xfff #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK) >> PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB) #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB) & PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK) #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2_ADDRESS (0x4 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TIMING_CONTROLS_2_RSTMASK 0xffffffff #define PHY_BB_TIMING_CONTROLS_2_RESET 0x0 // 0x8 (PHY_BB_TIMING_CONTROLS_3) #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB 17 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MSB 31 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK 0xfffe0000 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK) >> PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB) #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB) & PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK) #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB 13 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MSB 16 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK 0x1e000 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK) >> PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB) #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB) & PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK) #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB 12 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MSB 12 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK 0x1000 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK) >> PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB) #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB) & PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK) #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB 11 #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MSB 11 #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK 0x800 #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK) >> PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB) #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB) & PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK) #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_RESET 0x1 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB 10 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MSB 10 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK 0x400 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK) >> PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB) #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB) & PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK) #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB 9 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MSB 9 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK 0x200 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK) >> PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB) #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB) & PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK) #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB 8 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MSB 8 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK 0x100 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK) >> PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB) #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB) & PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK) #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB 0 #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MSB 7 #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK 0xff #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK) >> PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB) #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB) & PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK) #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_3_ADDRESS (0x8 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TIMING_CONTROLS_3_RSTMASK 0xffffffff #define PHY_BB_TIMING_CONTROLS_3_RESET 0x800 // 0xc (PHY_BB_TIMING_CONTROL_4) #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB 31 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MSB 31 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK 0x80000000 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_GET(x) (((x) & PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK) >> PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB) #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB) & PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK) #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_RESET 0x0 #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB 29 #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MSB 29 #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK 0x20000000 #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_GET(x) (((x) & PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK) >> PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB) #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB) & PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK) #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_RESET 0x0 #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB 28 #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MSB 28 #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK 0x10000000 #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_GET(x) (((x) & PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK) >> PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB) #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB) & PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK) #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_RESET 0x0 #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB 21 #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MSB 27 #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK 0xfe00000 #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_GET(x) (((x) & PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK) >> PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB) #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB) & PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK) #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_RESET 0x0 #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB 17 #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MSB 20 #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK 0x1e0000 #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_GET(x) (((x) & PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK) >> PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB) #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB) & PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK) #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_RESET 0xe #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB 16 #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MSB 16 #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK 0x10000 #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_GET(x) (((x) & PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK) >> PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB) #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB) & PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK) #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_RESET 0x0 #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB 12 #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MSB 15 #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK 0xf000 #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_GET(x) (((x) & PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK) >> PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB) #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB) & PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK) #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_RESET 0x0 #define PHY_BB_TIMING_CONTROL_4_USE_DATA_AS_PILOT_DF_LSB 11 #define PHY_BB_TIMING_CONTROL_4_USE_DATA_AS_PILOT_DF_MSB 11 #define PHY_BB_TIMING_CONTROL_4_USE_DATA_AS_PILOT_DF_MASK 0x800 #define PHY_BB_TIMING_CONTROL_4_USE_DATA_AS_PILOT_DF_GET(x) (((x) & PHY_BB_TIMING_CONTROL_4_USE_DATA_AS_PILOT_DF_MASK) >> PHY_BB_TIMING_CONTROL_4_USE_DATA_AS_PILOT_DF_LSB) #define PHY_BB_TIMING_CONTROL_4_USE_DATA_AS_PILOT_DF_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_4_USE_DATA_AS_PILOT_DF_LSB) & PHY_BB_TIMING_CONTROL_4_USE_DATA_AS_PILOT_DF_MASK) #define PHY_BB_TIMING_CONTROL_4_USE_DATA_AS_PILOT_DF_RESET 0x0 #define PHY_BB_TIMING_CONTROL_4_ENABLE_MAGNITUDE_TRACK_11N_MIMO_LSB 1 #define PHY_BB_TIMING_CONTROL_4_ENABLE_MAGNITUDE_TRACK_11N_MIMO_MSB 1 #define PHY_BB_TIMING_CONTROL_4_ENABLE_MAGNITUDE_TRACK_11N_MIMO_MASK 0x2 #define PHY_BB_TIMING_CONTROL_4_ENABLE_MAGNITUDE_TRACK_11N_MIMO_GET(x) (((x) & PHY_BB_TIMING_CONTROL_4_ENABLE_MAGNITUDE_TRACK_11N_MIMO_MASK) >> PHY_BB_TIMING_CONTROL_4_ENABLE_MAGNITUDE_TRACK_11N_MIMO_LSB) #define PHY_BB_TIMING_CONTROL_4_ENABLE_MAGNITUDE_TRACK_11N_MIMO_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_4_ENABLE_MAGNITUDE_TRACK_11N_MIMO_LSB) & PHY_BB_TIMING_CONTROL_4_ENABLE_MAGNITUDE_TRACK_11N_MIMO_MASK) #define PHY_BB_TIMING_CONTROL_4_ENABLE_MAGNITUDE_TRACK_11N_MIMO_RESET 0x0 #define PHY_BB_TIMING_CONTROL_4_ENABLE_HT_FINE_PPM_LSB 0 #define PHY_BB_TIMING_CONTROL_4_ENABLE_HT_FINE_PPM_MSB 0 #define PHY_BB_TIMING_CONTROL_4_ENABLE_HT_FINE_PPM_MASK 0x1 #define PHY_BB_TIMING_CONTROL_4_ENABLE_HT_FINE_PPM_GET(x) (((x) & PHY_BB_TIMING_CONTROL_4_ENABLE_HT_FINE_PPM_MASK) >> PHY_BB_TIMING_CONTROL_4_ENABLE_HT_FINE_PPM_LSB) #define PHY_BB_TIMING_CONTROL_4_ENABLE_HT_FINE_PPM_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_4_ENABLE_HT_FINE_PPM_LSB) & PHY_BB_TIMING_CONTROL_4_ENABLE_HT_FINE_PPM_MASK) #define PHY_BB_TIMING_CONTROL_4_ENABLE_HT_FINE_PPM_RESET 0x1 #define PHY_BB_TIMING_CONTROL_4_ADDRESS (0xc + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TIMING_CONTROL_4_RSTMASK 0xbffff803 #define PHY_BB_TIMING_CONTROL_4_RESET 0x1c0001 // 0x10 (PHY_BB_TIMING_CONTROL_5) #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB 23 #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MSB 29 #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK 0x3f800000 #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_GET(x) (((x) & PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK) >> PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB) #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB) & PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK) #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_RESET 0x40 #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB 16 #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MSB 22 #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK 0x7f0000 #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_GET(x) (((x) & PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK) >> PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB) #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB) & PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK) #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_RESET 0x0 #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB 15 #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MSB 15 #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK 0x8000 #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_GET(x) (((x) & PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK) >> PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB) #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB) & PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK) #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_RESET 0x0 #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB 1 #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MSB 7 #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK 0xfe #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_GET(x) (((x) & PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK) >> PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB) #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB) & PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK) #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_RESET 0x0 #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB 0 #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MSB 0 #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK 0x1 #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_GET(x) (((x) & PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK) >> PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB) #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB) & PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK) #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_RESET 0x0 #define PHY_BB_TIMING_CONTROL_5_ADDRESS (0x10 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TIMING_CONTROL_5_RSTMASK 0x3fff80ff #define PHY_BB_TIMING_CONTROL_5_RESET 0x20000000 // 0x14 (PHY_BB_TIMING_CONTROL_6) #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW40_LSB 29 #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW40_MSB 29 #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW40_MASK 0x20000000 #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW40_GET(x) (((x) & PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW40_MASK) >> PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW40_LSB) #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW40_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW40_LSB) & PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW40_MASK) #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW40_RESET 0x0 #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW20_LSB 28 #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW20_MSB 28 #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW20_MASK 0x10000000 #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW20_GET(x) (((x) & PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW20_MASK) >> PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW20_LSB) #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW20_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW20_LSB) & PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW20_MASK) #define PHY_BB_TIMING_CONTROL_6_ADD_BACK_OFDM_DC_CCK_BW20_RESET 0x0 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB 21 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MSB 27 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK 0xfe00000 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_GET(x) (((x) & PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK) >> PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB) #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB) & PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK) #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_RESET 0x0 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB 15 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MSB 20 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK 0x1f8000 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_GET(x) (((x) & PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK) >> PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB) #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB) & PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK) #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_RESET 0x0 #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB 8 #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MSB 14 #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK 0x7f00 #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_GET(x) (((x) & PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK) >> PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB) #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB) & PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK) #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_RESET 0x0 #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB 0 #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MSB 7 #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK 0xff #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_GET(x) (((x) & PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK) >> PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB) #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB) & PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK) #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_RESET 0xa #define PHY_BB_TIMING_CONTROL_6_ADDRESS (0x14 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TIMING_CONTROL_6_RSTMASK 0x3fffffff #define PHY_BB_TIMING_CONTROL_6_RESET 0xa // 0x18 (PHY_BB_TIMING_CONTROL_11) #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB 31 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MSB 31 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK 0x80000000 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_GET(x) (((x) & PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK) >> PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB) #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB) & PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK) #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_RESET 0x0 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB 30 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MSB 30 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK 0x40000000 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_GET(x) (((x) & PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK) >> PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB) #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB) & PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK) #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_RESET 0x0 #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB 20 #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MSB 29 #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK 0x3ff00000 #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_GET(x) (((x) & PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK) >> PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB) #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB) & PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK) #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_RESET 0x0 #define PHY_BB_TIMING_CONTROL_11_ADDRESS (0x18 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TIMING_CONTROL_11_RSTMASK 0xfff00000 #define PHY_BB_TIMING_CONTROL_11_RESET 0x0 // 0x1c (PHY_BB_SPUR_MASK_CONTROLS) #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_NF_RSSI_SPUR_MIT_LSB 26 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_NF_RSSI_SPUR_MIT_MSB 26 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_NF_RSSI_SPUR_MIT_MASK 0x4000000 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_NF_RSSI_SPUR_MIT_GET(x) (((x) & PHY_BB_SPUR_MASK_CONTROLS_ENABLE_NF_RSSI_SPUR_MIT_MASK) >> PHY_BB_SPUR_MASK_CONTROLS_ENABLE_NF_RSSI_SPUR_MIT_LSB) #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_NF_RSSI_SPUR_MIT_SET(x) (((0 | (x)) << PHY_BB_SPUR_MASK_CONTROLS_ENABLE_NF_RSSI_SPUR_MIT_LSB) & PHY_BB_SPUR_MASK_CONTROLS_ENABLE_NF_RSSI_SPUR_MIT_MASK) #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_NF_RSSI_SPUR_MIT_RESET 0x0 #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB 18 #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MSB 25 #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK 0x3fc0000 #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_GET(x) (((x) & PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK) >> PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB) #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_SET(x) (((0 | (x)) << PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB) & PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK) #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_RESET 0x0 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB 17 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MSB 17 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK 0x20000 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_GET(x) (((x) & PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK) >> PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB) #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_SET(x) (((0 | (x)) << PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB) & PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK) #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_RESET 0x0 #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB 8 #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MSB 8 #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK 0x100 #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_GET(x) (((x) & PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK) >> PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB) #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_SET(x) (((0 | (x)) << PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB) & PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK) #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_RESET 0x0 #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB 0 #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MSB 7 #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK 0xff #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_GET(x) (((x) & PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK) >> PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB) #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_SET(x) (((0 | (x)) << PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB) & PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK) #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_RESET 0x0 #define PHY_BB_SPUR_MASK_CONTROLS_ADDRESS (0x1c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_MASK_CONTROLS_RSTMASK 0x7fe01ff #define PHY_BB_SPUR_MASK_CONTROLS_RESET 0x0 // 0x20 (PHY_BB_FIND_SIGNAL_LOW) #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB 24 #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MSB 30 #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK 0x7f000000 #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_GET(x) (((x) & PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK) >> PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB) #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_SET(x) (((0 | (x)) << PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB) & PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK) #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_RESET 0x18 #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB 20 #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MSB 23 #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK 0xf00000 #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_GET(x) (((x) & PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK) >> PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB) #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_SET(x) (((0 | (x)) << PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB) & PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK) #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_RESET 0x0 #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB 12 #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MSB 19 #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK 0xff000 #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_GET(x) (((x) & PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK) >> PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB) #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_SET(x) (((0 | (x)) << PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB) & PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK) #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_RESET 0x0 #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB 6 #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MSB 11 #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK 0xfc0 #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_GET(x) (((x) & PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK) >> PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB) #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_SET(x) (((0 | (x)) << PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB) & PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK) #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_RESET 0x0 #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB 0 #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MSB 5 #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK 0x3f #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_GET(x) (((x) & PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK) >> PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB) #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_SET(x) (((0 | (x)) << PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB) & PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK) #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_RESET 0x0 #define PHY_BB_FIND_SIGNAL_LOW_ADDRESS (0x20 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_FIND_SIGNAL_LOW_RSTMASK 0x7fffffff #define PHY_BB_FIND_SIGNAL_LOW_RESET 0x18000000 // 0x24 (PHY_BB_SFCORR) #define PHY_BB_SFCORR_M2_THRES_LSB 24 #define PHY_BB_SFCORR_M2_THRES_MSB 30 #define PHY_BB_SFCORR_M2_THRES_MASK 0x7f000000 #define PHY_BB_SFCORR_M2_THRES_GET(x) (((x) & PHY_BB_SFCORR_M2_THRES_MASK) >> PHY_BB_SFCORR_M2_THRES_LSB) #define PHY_BB_SFCORR_M2_THRES_SET(x) (((0 | (x)) << PHY_BB_SFCORR_M2_THRES_LSB) & PHY_BB_SFCORR_M2_THRES_MASK) #define PHY_BB_SFCORR_M2_THRES_RESET 0x0 #define PHY_BB_SFCORR_M1_THRES_LSB 17 #define PHY_BB_SFCORR_M1_THRES_MSB 23 #define PHY_BB_SFCORR_M1_THRES_MASK 0xfe0000 #define PHY_BB_SFCORR_M1_THRES_GET(x) (((x) & PHY_BB_SFCORR_M1_THRES_MASK) >> PHY_BB_SFCORR_M1_THRES_LSB) #define PHY_BB_SFCORR_M1_THRES_SET(x) (((0 | (x)) << PHY_BB_SFCORR_M1_THRES_LSB) & PHY_BB_SFCORR_M1_THRES_MASK) #define PHY_BB_SFCORR_M1_THRES_RESET 0x0 #define PHY_BB_SFCORR_M2COUNT_THR_LSB 0 #define PHY_BB_SFCORR_M2COUNT_THR_MSB 4 #define PHY_BB_SFCORR_M2COUNT_THR_MASK 0x1f #define PHY_BB_SFCORR_M2COUNT_THR_GET(x) (((x) & PHY_BB_SFCORR_M2COUNT_THR_MASK) >> PHY_BB_SFCORR_M2COUNT_THR_LSB) #define PHY_BB_SFCORR_M2COUNT_THR_SET(x) (((0 | (x)) << PHY_BB_SFCORR_M2COUNT_THR_LSB) & PHY_BB_SFCORR_M2COUNT_THR_MASK) #define PHY_BB_SFCORR_M2COUNT_THR_RESET 0x0 #define PHY_BB_SFCORR_ADDRESS (0x24 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_SFCORR_RSTMASK 0x7ffe001f #define PHY_BB_SFCORR_RESET 0x0 // 0x28 (PHY_BB_SELF_CORR_LOW) #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB 21 #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MSB 27 #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK 0xfe00000 #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_GET(x) (((x) & PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK) >> PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB) #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_SET(x) (((0 | (x)) << PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB) & PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK) #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_RESET 0x0 #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB 14 #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MSB 20 #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK 0x1fc000 #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_GET(x) (((x) & PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK) >> PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB) #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_SET(x) (((0 | (x)) << PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB) & PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK) #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_RESET 0x0 #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB 8 #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MSB 13 #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK 0x3f00 #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_GET(x) (((x) & PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK) >> PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB) #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_SET(x) (((0 | (x)) << PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB) & PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK) #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_RESET 0x0 #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB 1 #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MSB 7 #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK 0xfe #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_GET(x) (((x) & PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK) >> PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB) #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_SET(x) (((0 | (x)) << PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB) & PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK) #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_RESET 0x0 #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB 0 #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MSB 0 #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK 0x1 #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_GET(x) (((x) & PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK) >> PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB) #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_SET(x) (((0 | (x)) << PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB) & PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK) #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_RESET 0x0 #define PHY_BB_SELF_CORR_LOW_ADDRESS (0x28 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_SELF_CORR_LOW_RSTMASK 0xfffffff #define PHY_BB_SELF_CORR_LOW_RESET 0x0 // 0x30 (PHY_BB_TIMING_CONTROL_13) #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH2_LSB 23 #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH2_MSB 30 #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH2_MASK 0x7f800000 #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH2_GET(x) (((x) & PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH2_MASK) >> PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH2_LSB) #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH2_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH2_LSB) & PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH2_MASK) #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH2_RESET 0x1a #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH1_LSB 15 #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH1_MSB 22 #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH1_MASK 0x7f8000 #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH1_GET(x) (((x) & PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH1_MASK) >> PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH1_LSB) #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH1_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH1_LSB) & PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH1_MASK) #define PHY_BB_TIMING_CONTROL_13_TB_RSSI_TH1_RESET 0x10 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_HIGH_RSSI_LSB 10 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_HIGH_RSSI_MSB 14 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_HIGH_RSSI_MASK 0x7c00 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_HIGH_RSSI_GET(x) (((x) & PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_HIGH_RSSI_MASK) >> PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_HIGH_RSSI_LSB) #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_HIGH_RSSI_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_HIGH_RSSI_LSB) & PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_HIGH_RSSI_MASK) #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_HIGH_RSSI_RESET 0x1 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_MID_RSSI_LSB 5 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_MID_RSSI_MSB 9 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_MID_RSSI_MASK 0x3e0 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_MID_RSSI_GET(x) (((x) & PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_MID_RSSI_MASK) >> PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_MID_RSSI_LSB) #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_MID_RSSI_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_MID_RSSI_LSB) & PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_MID_RSSI_MASK) #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_MID_RSSI_RESET 0x2 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_LOW_RSSI_LSB 0 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_LOW_RSSI_MSB 4 #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_LOW_RSSI_MASK 0x1f #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_LOW_RSSI_GET(x) (((x) & PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_LOW_RSSI_MASK) >> PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_LOW_RSSI_LSB) #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_LOW_RSSI_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_LOW_RSSI_LSB) & PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_LOW_RSSI_MASK) #define PHY_BB_TIMING_CONTROL_13_TIMING_BACKOFF_LOW_RSSI_RESET 0x4 #define PHY_BB_TIMING_CONTROL_13_ADDRESS (0x30 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TIMING_CONTROL_13_RSTMASK 0x7fffffff #define PHY_BB_TIMING_CONTROL_13_RESET 0xd080444 // 0x34 (PHY_BB_RADAR_DETECTION) #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB 24 #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MSB 30 #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK 0x7f000000 #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_GET(x) (((x) & PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK) >> PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB) #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB) & PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK) #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_RESET 0x0 #define PHY_BB_RADAR_DETECTION_PULSE_DROP_THRESH_LSB 18 #define PHY_BB_RADAR_DETECTION_PULSE_DROP_THRESH_MSB 23 #define PHY_BB_RADAR_DETECTION_PULSE_DROP_THRESH_MASK 0xfc0000 #define PHY_BB_RADAR_DETECTION_PULSE_DROP_THRESH_GET(x) (((x) & PHY_BB_RADAR_DETECTION_PULSE_DROP_THRESH_MASK) >> PHY_BB_RADAR_DETECTION_PULSE_DROP_THRESH_LSB) #define PHY_BB_RADAR_DETECTION_PULSE_DROP_THRESH_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_PULSE_DROP_THRESH_LSB) & PHY_BB_RADAR_DETECTION_PULSE_DROP_THRESH_MASK) #define PHY_BB_RADAR_DETECTION_PULSE_DROP_THRESH_RESET 0x0 #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB 12 #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MSB 17 #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK 0x3f000 #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_GET(x) (((x) & PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK) >> PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB) #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB) & PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK) #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_RESET 0x0 #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB 6 #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MSB 11 #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK 0xfc0 #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_GET(x) (((x) & PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK) >> PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB) #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB) & PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK) #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_RESET 0x0 #define PHY_BB_RADAR_DETECTION_FFT_CHECK_COARSE_ENA_LSB 5 #define PHY_BB_RADAR_DETECTION_FFT_CHECK_COARSE_ENA_MSB 5 #define PHY_BB_RADAR_DETECTION_FFT_CHECK_COARSE_ENA_MASK 0x20 #define PHY_BB_RADAR_DETECTION_FFT_CHECK_COARSE_ENA_GET(x) (((x) & PHY_BB_RADAR_DETECTION_FFT_CHECK_COARSE_ENA_MASK) >> PHY_BB_RADAR_DETECTION_FFT_CHECK_COARSE_ENA_LSB) #define PHY_BB_RADAR_DETECTION_FFT_CHECK_COARSE_ENA_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_FFT_CHECK_COARSE_ENA_LSB) & PHY_BB_RADAR_DETECTION_FFT_CHECK_COARSE_ENA_MASK) #define PHY_BB_RADAR_DETECTION_FFT_CHECK_COARSE_ENA_RESET 0x0 #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_SEC_LSB 4 #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_SEC_MSB 4 #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_SEC_MASK 0x10 #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_SEC_GET(x) (((x) & PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_SEC_MASK) >> PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_SEC_LSB) #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_SEC_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_SEC_LSB) & PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_SEC_MASK) #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_SEC_RESET 0x0 #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_PRI_LSB 3 #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_PRI_MSB 3 #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_PRI_MASK 0x8 #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_PRI_GET(x) (((x) & PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_PRI_MASK) >> PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_PRI_LSB) #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_PRI_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_PRI_LSB) & PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_PRI_MASK) #define PHY_BB_RADAR_DETECTION_DFS_RESTART_ENA_PRI_RESET 0x0 #define PHY_BB_RADAR_DETECTION_DFS_SEC80_ENABLE_LSB 2 #define PHY_BB_RADAR_DETECTION_DFS_SEC80_ENABLE_MSB 2 #define PHY_BB_RADAR_DETECTION_DFS_SEC80_ENABLE_MASK 0x4 #define PHY_BB_RADAR_DETECTION_DFS_SEC80_ENABLE_GET(x) (((x) & PHY_BB_RADAR_DETECTION_DFS_SEC80_ENABLE_MASK) >> PHY_BB_RADAR_DETECTION_DFS_SEC80_ENABLE_LSB) #define PHY_BB_RADAR_DETECTION_DFS_SEC80_ENABLE_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_DFS_SEC80_ENABLE_LSB) & PHY_BB_RADAR_DETECTION_DFS_SEC80_ENABLE_MASK) #define PHY_BB_RADAR_DETECTION_DFS_SEC80_ENABLE_RESET 0x0 #define PHY_BB_RADAR_DETECTION_DFS_PRI80_ENABLE_LSB 1 #define PHY_BB_RADAR_DETECTION_DFS_PRI80_ENABLE_MSB 1 #define PHY_BB_RADAR_DETECTION_DFS_PRI80_ENABLE_MASK 0x2 #define PHY_BB_RADAR_DETECTION_DFS_PRI80_ENABLE_GET(x) (((x) & PHY_BB_RADAR_DETECTION_DFS_PRI80_ENABLE_MASK) >> PHY_BB_RADAR_DETECTION_DFS_PRI80_ENABLE_LSB) #define PHY_BB_RADAR_DETECTION_DFS_PRI80_ENABLE_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_DFS_PRI80_ENABLE_LSB) & PHY_BB_RADAR_DETECTION_DFS_PRI80_ENABLE_MASK) #define PHY_BB_RADAR_DETECTION_DFS_PRI80_ENABLE_RESET 0x0 #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB 0 #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MSB 0 #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK 0x1 #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_GET(x) (((x) & PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK) >> PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB) #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB) & PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK) #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_RESET 0x0 #define PHY_BB_RADAR_DETECTION_ADDRESS (0x34 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RADAR_DETECTION_RSTMASK 0x7fffffff #define PHY_BB_RADAR_DETECTION_RESET 0x0 // 0x38 (PHY_BB_RADAR_DETECTION_2) #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_DROP_CHECK_LSB 30 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_DROP_CHECK_MSB 30 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_DROP_CHECK_MASK 0x40000000 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_DROP_CHECK_GET(x) (((x) & PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_DROP_CHECK_MASK) >> PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_DROP_CHECK_LSB) #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_DROP_CHECK_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_DROP_CHECK_LSB) & PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_DROP_CHECK_MASK) #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_DROP_CHECK_RESET 0x0 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELPWR_CHECK_LSB 29 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELPWR_CHECK_MSB 29 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELPWR_CHECK_MASK 0x20000000 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELPWR_CHECK_GET(x) (((x) & PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELPWR_CHECK_MASK) >> PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELPWR_CHECK_LSB) #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELPWR_CHECK_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELPWR_CHECK_LSB) & PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELPWR_CHECK_MASK) #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELPWR_CHECK_RESET 0x0 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB 28 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MSB 28 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK 0x10000000 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_GET(x) (((x) & PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK) >> PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB) #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB) & PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK) #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_RESET 0x0 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB 27 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MSB 27 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK 0x8000000 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_GET(x) (((x) & PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK) >> PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB) #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB) & PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK) #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_RESET 0x0 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELPWR_THRESH_LSB 16 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELPWR_THRESH_MSB 20 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELPWR_THRESH_MASK 0x1f0000 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELPWR_THRESH_GET(x) (((x) & PHY_BB_RADAR_DETECTION_2_PULSE_RELPWR_THRESH_MASK) >> PHY_BB_RADAR_DETECTION_2_PULSE_RELPWR_THRESH_LSB) #define PHY_BB_RADAR_DETECTION_2_PULSE_RELPWR_THRESH_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_2_PULSE_RELPWR_THRESH_LSB) & PHY_BB_RADAR_DETECTION_2_PULSE_RELPWR_THRESH_MASK) #define PHY_BB_RADAR_DETECTION_2_PULSE_RELPWR_THRESH_RESET 0x0 #define PHY_BB_RADAR_DETECTION_2_DFS_CONT_80P80_LSB 13 #define PHY_BB_RADAR_DETECTION_2_DFS_CONT_80P80_MSB 13 #define PHY_BB_RADAR_DETECTION_2_DFS_CONT_80P80_MASK 0x2000 #define PHY_BB_RADAR_DETECTION_2_DFS_CONT_80P80_GET(x) (((x) & PHY_BB_RADAR_DETECTION_2_DFS_CONT_80P80_MASK) >> PHY_BB_RADAR_DETECTION_2_DFS_CONT_80P80_LSB) #define PHY_BB_RADAR_DETECTION_2_DFS_CONT_80P80_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_2_DFS_CONT_80P80_LSB) & PHY_BB_RADAR_DETECTION_2_DFS_CONT_80P80_MASK) #define PHY_BB_RADAR_DETECTION_2_DFS_CONT_80P80_RESET 0x0 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB 8 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MSB 12 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK 0x1f00 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_GET(x) (((x) & PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK) >> PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB) #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB) & PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK) #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_RESET 0x0 #define PHY_BB_RADAR_DETECTION_2_PULSE_WIDTH_MAX_LSB 0 #define PHY_BB_RADAR_DETECTION_2_PULSE_WIDTH_MAX_MSB 7 #define PHY_BB_RADAR_DETECTION_2_PULSE_WIDTH_MAX_MASK 0xff #define PHY_BB_RADAR_DETECTION_2_PULSE_WIDTH_MAX_GET(x) (((x) & PHY_BB_RADAR_DETECTION_2_PULSE_WIDTH_MAX_MASK) >> PHY_BB_RADAR_DETECTION_2_PULSE_WIDTH_MAX_LSB) #define PHY_BB_RADAR_DETECTION_2_PULSE_WIDTH_MAX_SET(x) (((0 | (x)) << PHY_BB_RADAR_DETECTION_2_PULSE_WIDTH_MAX_LSB) & PHY_BB_RADAR_DETECTION_2_PULSE_WIDTH_MAX_MASK) #define PHY_BB_RADAR_DETECTION_2_PULSE_WIDTH_MAX_RESET 0x0 #define PHY_BB_RADAR_DETECTION_2_ADDRESS (0x38 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RADAR_DETECTION_2_RSTMASK 0x781f3fff #define PHY_BB_RADAR_DETECTION_2_RESET 0x0 // 0x3c (PHY_BB_EXTENSION_RADAR) #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB 23 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MSB 31 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK 0xff800000 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_GET(x) (((x) & PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK) >> PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB) #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_SET(x) (((0 | (x)) << PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB) & PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK) #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_RESET 0x1ff #define PHY_BB_EXTENSION_RADAR_RADAR_FFT_DATAPATH_SEL_LSB 22 #define PHY_BB_EXTENSION_RADAR_RADAR_FFT_DATAPATH_SEL_MSB 22 #define PHY_BB_EXTENSION_RADAR_RADAR_FFT_DATAPATH_SEL_MASK 0x400000 #define PHY_BB_EXTENSION_RADAR_RADAR_FFT_DATAPATH_SEL_GET(x) (((x) & PHY_BB_EXTENSION_RADAR_RADAR_FFT_DATAPATH_SEL_MASK) >> PHY_BB_EXTENSION_RADAR_RADAR_FFT_DATAPATH_SEL_LSB) #define PHY_BB_EXTENSION_RADAR_RADAR_FFT_DATAPATH_SEL_SET(x) (((0 | (x)) << PHY_BB_EXTENSION_RADAR_RADAR_FFT_DATAPATH_SEL_LSB) & PHY_BB_EXTENSION_RADAR_RADAR_FFT_DATAPATH_SEL_MASK) #define PHY_BB_EXTENSION_RADAR_RADAR_FFT_DATAPATH_SEL_RESET 0x1 #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_NB_MASK_LSB 21 #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_NB_MASK_MSB 21 #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_NB_MASK_MASK 0x200000 #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_NB_MASK_GET(x) (((x) & PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_NB_MASK_MASK) >> PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_NB_MASK_LSB) #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_NB_MASK_SET(x) (((0 | (x)) << PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_NB_MASK_LSB) & PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_NB_MASK_MASK) #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_NB_MASK_RESET 0x1 #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_DC_MASK_LSB 20 #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_DC_MASK_MSB 20 #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_DC_MASK_MASK 0x100000 #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_DC_MASK_GET(x) (((x) & PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_DC_MASK_MASK) >> PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_DC_MASK_LSB) #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_DC_MASK_SET(x) (((0 | (x)) << PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_DC_MASK_LSB) & PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_DC_MASK_MASK) #define PHY_BB_EXTENSION_RADAR_LB_DC_CAP_PULSE_DC_MASK_RESET 0x1 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_FINE_LSB 8 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_FINE_MSB 16 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_FINE_MASK 0x1ff00 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_FINE_GET(x) (((x) & PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_FINE_MASK) >> PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_FINE_LSB) #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_FINE_SET(x) (((0 | (x)) << PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_FINE_LSB) & PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_FINE_MASK) #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_FINE_RESET 0x1ff #define PHY_BB_EXTENSION_RADAR_RADAR_PATH_SEL_LSB 6 #define PHY_BB_EXTENSION_RADAR_RADAR_PATH_SEL_MSB 7 #define PHY_BB_EXTENSION_RADAR_RADAR_PATH_SEL_MASK 0xc0 #define PHY_BB_EXTENSION_RADAR_RADAR_PATH_SEL_GET(x) (((x) & PHY_BB_EXTENSION_RADAR_RADAR_PATH_SEL_MASK) >> PHY_BB_EXTENSION_RADAR_RADAR_PATH_SEL_LSB) #define PHY_BB_EXTENSION_RADAR_RADAR_PATH_SEL_SET(x) (((0 | (x)) << PHY_BB_EXTENSION_RADAR_RADAR_PATH_SEL_LSB) & PHY_BB_EXTENSION_RADAR_RADAR_PATH_SEL_MASK) #define PHY_BB_EXTENSION_RADAR_RADAR_PATH_SEL_RESET 0x1 #define PHY_BB_EXTENSION_RADAR_RESTART_LGDFSPWR_DELTA_LSB 0 #define PHY_BB_EXTENSION_RADAR_RESTART_LGDFSPWR_DELTA_MSB 5 #define PHY_BB_EXTENSION_RADAR_RESTART_LGDFSPWR_DELTA_MASK 0x3f #define PHY_BB_EXTENSION_RADAR_RESTART_LGDFSPWR_DELTA_GET(x) (((x) & PHY_BB_EXTENSION_RADAR_RESTART_LGDFSPWR_DELTA_MASK) >> PHY_BB_EXTENSION_RADAR_RESTART_LGDFSPWR_DELTA_LSB) #define PHY_BB_EXTENSION_RADAR_RESTART_LGDFSPWR_DELTA_SET(x) (((0 | (x)) << PHY_BB_EXTENSION_RADAR_RESTART_LGDFSPWR_DELTA_LSB) & PHY_BB_EXTENSION_RADAR_RESTART_LGDFSPWR_DELTA_MASK) #define PHY_BB_EXTENSION_RADAR_RESTART_LGDFSPWR_DELTA_RESET 0xf #define PHY_BB_EXTENSION_RADAR_ADDRESS (0x3c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_EXTENSION_RADAR_RSTMASK 0xfff1ffff #define PHY_BB_EXTENSION_RADAR_RESET 0xfff1ff4f // 0x40 (PHY_BB_IBF_CTRL) #define PHY_BB_IBF_CTRL_CHN_PHASE_ALIGN_LSB 0 #define PHY_BB_IBF_CTRL_CHN_PHASE_ALIGN_MSB 3 #define PHY_BB_IBF_CTRL_CHN_PHASE_ALIGN_MASK 0xf #define PHY_BB_IBF_CTRL_CHN_PHASE_ALIGN_GET(x) (((x) & PHY_BB_IBF_CTRL_CHN_PHASE_ALIGN_MASK) >> PHY_BB_IBF_CTRL_CHN_PHASE_ALIGN_LSB) #define PHY_BB_IBF_CTRL_CHN_PHASE_ALIGN_SET(x) (((0 | (x)) << PHY_BB_IBF_CTRL_CHN_PHASE_ALIGN_LSB) & PHY_BB_IBF_CTRL_CHN_PHASE_ALIGN_MASK) #define PHY_BB_IBF_CTRL_CHN_PHASE_ALIGN_RESET 0x0 #define PHY_BB_IBF_CTRL_ADDRESS (0x40 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_IBF_CTRL_RSTMASK 0xf #define PHY_BB_IBF_CTRL_RESET 0x0 // 0x50 (PHY_BB_CHN_SPARE_01) #define PHY_BB_CHN_SPARE_01_CHN_ECO_CTRL_LSB 0 #define PHY_BB_CHN_SPARE_01_CHN_ECO_CTRL_MSB 31 #define PHY_BB_CHN_SPARE_01_CHN_ECO_CTRL_MASK 0xffffffff #define PHY_BB_CHN_SPARE_01_CHN_ECO_CTRL_GET(x) (((x) & PHY_BB_CHN_SPARE_01_CHN_ECO_CTRL_MASK) >> PHY_BB_CHN_SPARE_01_CHN_ECO_CTRL_LSB) #define PHY_BB_CHN_SPARE_01_CHN_ECO_CTRL_SET(x) (((0 | (x)) << PHY_BB_CHN_SPARE_01_CHN_ECO_CTRL_LSB) & PHY_BB_CHN_SPARE_01_CHN_ECO_CTRL_MASK) #define PHY_BB_CHN_SPARE_01_CHN_ECO_CTRL_RESET 0x0 #define PHY_BB_CHN_SPARE_01_ADDRESS (0x50 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHN_SPARE_01_RSTMASK 0xffffffff #define PHY_BB_CHN_SPARE_01_RESET 0x0 // 0x54 (PHY_BB_TIMING_CONTROLS_2A) #define PHY_BB_TIMING_CONTROLS_2A_COARSE_DC_DELAY_LSB 0 #define PHY_BB_TIMING_CONTROLS_2A_COARSE_DC_DELAY_MSB 4 #define PHY_BB_TIMING_CONTROLS_2A_COARSE_DC_DELAY_MASK 0x1f #define PHY_BB_TIMING_CONTROLS_2A_COARSE_DC_DELAY_GET(x) (((x) & PHY_BB_TIMING_CONTROLS_2A_COARSE_DC_DELAY_MASK) >> PHY_BB_TIMING_CONTROLS_2A_COARSE_DC_DELAY_LSB) #define PHY_BB_TIMING_CONTROLS_2A_COARSE_DC_DELAY_SET(x) (((0 | (x)) << PHY_BB_TIMING_CONTROLS_2A_COARSE_DC_DELAY_LSB) & PHY_BB_TIMING_CONTROLS_2A_COARSE_DC_DELAY_MASK) #define PHY_BB_TIMING_CONTROLS_2A_COARSE_DC_DELAY_RESET 0x0 #define PHY_BB_TIMING_CONTROLS_2A_ADDRESS (0x54 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TIMING_CONTROLS_2A_RSTMASK 0x1f #define PHY_BB_TIMING_CONTROLS_2A_RESET 0x0 // 0x58 (PHY_BB_RX_NOTCH_CNTL_2_PRI_B0) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_Q_PRI_B0_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_Q_PRI_B0_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_Q_PRI_B0_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_Q_PRI_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_Q_PRI_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_Q_PRI_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_Q_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_Q_PRI_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_Q_PRI_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_Q_PRI_B0_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_I_PRI_B0_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_I_PRI_B0_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_I_PRI_B0_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_I_PRI_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_I_PRI_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_I_PRI_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_I_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_I_PRI_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_I_PRI_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_NOTCH_CORR_SPUR1_I_PRI_B0_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_ADDRESS (0x58 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B0_RESET 0x400 // 0x5c (PHY_BB_RX_NOTCH_CNTL_3_PRI_B0) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_Q_PRI_B0_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_Q_PRI_B0_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_Q_PRI_B0_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_Q_PRI_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_Q_PRI_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_Q_PRI_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_Q_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_Q_PRI_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_Q_PRI_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_Q_PRI_B0_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_I_PRI_B0_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_I_PRI_B0_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_I_PRI_B0_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_I_PRI_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_I_PRI_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_I_PRI_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_I_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_I_PRI_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_I_PRI_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_NOTCH_CORR_SPUR2_I_PRI_B0_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_ADDRESS (0x5c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B0_RESET 0x400 // 0x60 (PHY_BB_RX_NOTCH_CNTL_4_PRI_B0) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_Q_PRI_B0_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_Q_PRI_B0_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_Q_PRI_B0_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_Q_PRI_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_Q_PRI_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_Q_PRI_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_Q_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_Q_PRI_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_Q_PRI_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_Q_PRI_B0_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_I_PRI_B0_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_I_PRI_B0_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_I_PRI_B0_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_I_PRI_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_I_PRI_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_I_PRI_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_I_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_I_PRI_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_I_PRI_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_NOTCH_CORR_DC_I_PRI_B0_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_ADDRESS (0x60 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B0_RESET 0x400 // 0x64 (PHY_BB_RX_NOTCH_CNTL_5_PRI_B0) #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_NOTCH_CORR_AGG_I_PRI_B0_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_NOTCH_CORR_AGG_I_PRI_B0_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_NOTCH_CORR_AGG_I_PRI_B0_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_NOTCH_CORR_AGG_I_PRI_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_NOTCH_CORR_AGG_I_PRI_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_NOTCH_CORR_AGG_I_PRI_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_NOTCH_CORR_AGG_I_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_NOTCH_CORR_AGG_I_PRI_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_NOTCH_CORR_AGG_I_PRI_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_NOTCH_CORR_AGG_I_PRI_B0_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_ADDRESS (0x64 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_RSTMASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B0_RESET 0x400 // 0x68 (PHY_BB_RX_NOTCH_CNTL_2_EXT_B0) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_Q_EXT_B0_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_Q_EXT_B0_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_Q_EXT_B0_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_Q_EXT_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_Q_EXT_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_Q_EXT_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_Q_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_Q_EXT_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_Q_EXT_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_Q_EXT_B0_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_I_EXT_B0_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_I_EXT_B0_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_I_EXT_B0_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_I_EXT_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_I_EXT_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_I_EXT_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_I_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_I_EXT_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_I_EXT_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_NOTCH_CORR_SPUR1_I_EXT_B0_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_ADDRESS (0x68 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B0_RESET 0x400 // 0x6c (PHY_BB_RX_NOTCH_CNTL_3_EXT_B0) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_Q_EXT_B0_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_Q_EXT_B0_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_Q_EXT_B0_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_Q_EXT_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_Q_EXT_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_Q_EXT_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_Q_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_Q_EXT_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_Q_EXT_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_Q_EXT_B0_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_I_EXT_B0_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_I_EXT_B0_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_I_EXT_B0_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_I_EXT_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_I_EXT_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_I_EXT_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_I_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_I_EXT_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_I_EXT_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_NOTCH_CORR_SPUR2_I_EXT_B0_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_ADDRESS (0x6c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B0_RESET 0x400 // 0x70 (PHY_BB_RX_NOTCH_CNTL_4_EXT_B0) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_Q_EXT_B0_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_Q_EXT_B0_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_Q_EXT_B0_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_Q_EXT_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_Q_EXT_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_Q_EXT_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_Q_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_Q_EXT_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_Q_EXT_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_Q_EXT_B0_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_I_EXT_B0_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_I_EXT_B0_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_I_EXT_B0_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_I_EXT_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_I_EXT_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_I_EXT_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_I_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_I_EXT_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_I_EXT_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_NOTCH_CORR_DC_I_EXT_B0_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_ADDRESS (0x70 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B0_RESET 0x400 // 0x74 (PHY_BB_RX_NOTCH_CNTL_5_EXT_B0) #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_NOTCH_CORR_AGG_I_EXT_B0_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_NOTCH_CORR_AGG_I_EXT_B0_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_NOTCH_CORR_AGG_I_EXT_B0_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_NOTCH_CORR_AGG_I_EXT_B0_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_NOTCH_CORR_AGG_I_EXT_B0_MASK) >> PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_NOTCH_CORR_AGG_I_EXT_B0_LSB) #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_NOTCH_CORR_AGG_I_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_NOTCH_CORR_AGG_I_EXT_B0_LSB) & PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_NOTCH_CORR_AGG_I_EXT_B0_MASK) #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_NOTCH_CORR_AGG_I_EXT_B0_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_ADDRESS (0x74 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_RSTMASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B0_RESET 0x400 // 0x80 (PHY_BB_MULTICHAIN_CONTROL) #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_DYN_DEWEIGHT_LSB 31 #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_DYN_DEWEIGHT_MSB 31 #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_DYN_DEWEIGHT_MASK 0x80000000 #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_DYN_DEWEIGHT_GET(x) (((x) & PHY_BB_MULTICHAIN_CONTROL_ENABLE_DYN_DEWEIGHT_MASK) >> PHY_BB_MULTICHAIN_CONTROL_ENABLE_DYN_DEWEIGHT_LSB) #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_DYN_DEWEIGHT_SET(x) (((0 | (x)) << PHY_BB_MULTICHAIN_CONTROL_ENABLE_DYN_DEWEIGHT_LSB) & PHY_BB_MULTICHAIN_CONTROL_ENABLE_DYN_DEWEIGHT_MASK) #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_DYN_DEWEIGHT_RESET 0x0 #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_STATIC_DEWEIGHT_LSB 30 #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_STATIC_DEWEIGHT_MSB 30 #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_STATIC_DEWEIGHT_MASK 0x40000000 #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_STATIC_DEWEIGHT_GET(x) (((x) & PHY_BB_MULTICHAIN_CONTROL_ENABLE_STATIC_DEWEIGHT_MASK) >> PHY_BB_MULTICHAIN_CONTROL_ENABLE_STATIC_DEWEIGHT_LSB) #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_STATIC_DEWEIGHT_SET(x) (((0 | (x)) << PHY_BB_MULTICHAIN_CONTROL_ENABLE_STATIC_DEWEIGHT_LSB) & PHY_BB_MULTICHAIN_CONTROL_ENABLE_STATIC_DEWEIGHT_MASK) #define PHY_BB_MULTICHAIN_CONTROL_ENABLE_STATIC_DEWEIGHT_RESET 0x0 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB 29 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MSB 29 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK 0x20000000 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_GET(x) (((x) & PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK) >> PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB) #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_SET(x) (((0 | (x)) << PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB) & PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK) #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_RESET 0x0 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB 22 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MSB 28 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK 0x1fc00000 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_GET(x) (((x) & PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK) >> PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB) #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_SET(x) (((0 | (x)) << PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB) & PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK) #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_RESET 0x0 #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB 10 #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MSB 20 #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK 0x1ffc00 #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_GET(x) (((x) & PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK) >> PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB) #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_SET(x) (((0 | (x)) << PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB) & PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK) #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_RESET 0x0 #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB 9 #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MSB 9 #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK 0x200 #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_GET(x) (((x) & PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK) >> PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB) #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_SET(x) (((0 | (x)) << PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB) & PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK) #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_RESET 0x0 #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB 8 #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MSB 8 #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK 0x100 #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_GET(x) (((x) & PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK) >> PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB) #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_SET(x) (((0 | (x)) << PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB) & PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK) #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_RESET 0x0 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB 1 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MSB 7 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK 0xfe #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_GET(x) (((x) & PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK) >> PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB) #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_SET(x) (((0 | (x)) << PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB) & PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK) #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_RESET 0x0 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB 0 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MSB 0 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK 0x1 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_GET(x) (((x) & PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK) >> PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB) #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_SET(x) (((0 | (x)) << PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB) & PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK) #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_RESET 0x0 #define PHY_BB_MULTICHAIN_CONTROL_ADDRESS (0x80 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_MULTICHAIN_CONTROL_RSTMASK 0xffdfffff #define PHY_BB_MULTICHAIN_CONTROL_RESET 0x0 // 0x84 (PHY_BB_PER_CHAIN_HT_CSD) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN3_4CHAINS_LSB 25 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN3_4CHAINS_MSB 29 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN3_4CHAINS_MASK 0x3e000000 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN3_4CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN3_4CHAINS_MASK) >> PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN3_4CHAINS_LSB) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN3_4CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN3_4CHAINS_LSB) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN3_4CHAINS_MASK) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN3_4CHAINS_RESET 0x6 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_4CHAINS_LSB 20 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_4CHAINS_MSB 24 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_4CHAINS_MASK 0x1f00000 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_4CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_4CHAINS_MASK) >> PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_4CHAINS_LSB) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_4CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_4CHAINS_LSB) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_4CHAINS_MASK) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_4CHAINS_RESET 0x4 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_4CHAINS_LSB 15 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_4CHAINS_MSB 19 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_4CHAINS_MASK 0xf8000 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_4CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_4CHAINS_MASK) >> PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_4CHAINS_LSB) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_4CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_4CHAINS_LSB) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_4CHAINS_MASK) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_4CHAINS_RESET 0x2 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_3CHAINS_LSB 10 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_3CHAINS_MSB 14 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_3CHAINS_MASK 0x7c00 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_3CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_3CHAINS_MASK) >> PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_3CHAINS_LSB) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_3CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_3CHAINS_LSB) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_3CHAINS_MASK) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN2_3CHAINS_RESET 0x4 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_3CHAINS_LSB 5 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_3CHAINS_MSB 9 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_3CHAINS_MASK 0x3e0 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_3CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_3CHAINS_MASK) >> PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_3CHAINS_LSB) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_3CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_3CHAINS_LSB) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_3CHAINS_MASK) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_3CHAINS_RESET 0x2 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_2CHAINS_LSB 0 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_2CHAINS_MSB 4 #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_2CHAINS_MASK 0x1f #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_2CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_2CHAINS_MASK) >> PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_2CHAINS_LSB) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_2CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_2CHAINS_LSB) & PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_2CHAINS_MASK) #define PHY_BB_PER_CHAIN_HT_CSD_HT_CSD_CHN1_2CHAINS_RESET 0x2 #define PHY_BB_PER_CHAIN_HT_CSD_ADDRESS (0x84 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PER_CHAIN_HT_CSD_RSTMASK 0x3fffffff #define PHY_BB_PER_CHAIN_HT_CSD_RESET 0xc411042 // 0x88 (PHY_BB_PRE_EMPHASIS_BW20_B0) #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_NEG_BW20_0_LSB 15 #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_NEG_BW20_0_MSB 29 #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_NEG_BW20_0_MASK 0x3fff8000 #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_NEG_BW20_0_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_NEG_BW20_0_MASK) >> PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_NEG_BW20_0_LSB) #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_NEG_BW20_0_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_NEG_BW20_0_LSB) & PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_NEG_BW20_0_MASK) #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_NEG_BW20_0_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_POS_BW20_0_LSB 0 #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_POS_BW20_0_MSB 14 #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_POS_BW20_0_MASK 0x7fff #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_POS_BW20_0_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_POS_BW20_0_MASK) >> PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_POS_BW20_0_LSB) #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_POS_BW20_0_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_POS_BW20_0_LSB) & PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_POS_BW20_0_MASK) #define PHY_BB_PRE_EMPHASIS_BW20_B0_PRE_EMP_DB_POS_BW20_0_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW20_B0_ADDRESS (0x88 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PRE_EMPHASIS_BW20_B0_RSTMASK 0x3fffffff #define PHY_BB_PRE_EMPHASIS_BW20_B0_RESET 0x0 // 0x8c (PHY_BB_PRE_EMPHASIS_BW40_B0) #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_NEG_BW40_0_LSB 15 #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_NEG_BW40_0_MSB 29 #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_NEG_BW40_0_MASK 0x3fff8000 #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_NEG_BW40_0_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_NEG_BW40_0_MASK) >> PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_NEG_BW40_0_LSB) #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_NEG_BW40_0_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_NEG_BW40_0_LSB) & PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_NEG_BW40_0_MASK) #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_NEG_BW40_0_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_POS_BW40_0_LSB 0 #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_POS_BW40_0_MSB 14 #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_POS_BW40_0_MASK 0x7fff #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_POS_BW40_0_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_POS_BW40_0_MASK) >> PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_POS_BW40_0_LSB) #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_POS_BW40_0_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_POS_BW40_0_LSB) & PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_POS_BW40_0_MASK) #define PHY_BB_PRE_EMPHASIS_BW40_B0_PRE_EMP_DB_POS_BW40_0_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW40_B0_ADDRESS (0x8c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PRE_EMPHASIS_BW40_B0_RSTMASK 0x3fffffff #define PHY_BB_PRE_EMPHASIS_BW40_B0_RESET 0x0 // 0x90 (PHY_BB_PRE_EMPHASIS_BW80_B0) #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_NEG_BW80_0_LSB 15 #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_NEG_BW80_0_MSB 29 #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_NEG_BW80_0_MASK 0x3fff8000 #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_NEG_BW80_0_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_NEG_BW80_0_MASK) >> PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_NEG_BW80_0_LSB) #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_NEG_BW80_0_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_NEG_BW80_0_LSB) & PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_NEG_BW80_0_MASK) #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_NEG_BW80_0_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_POS_BW80_0_LSB 0 #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_POS_BW80_0_MSB 14 #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_POS_BW80_0_MASK 0x7fff #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_POS_BW80_0_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_POS_BW80_0_MASK) >> PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_POS_BW80_0_LSB) #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_POS_BW80_0_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_POS_BW80_0_LSB) & PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_POS_BW80_0_MASK) #define PHY_BB_PRE_EMPHASIS_BW80_B0_PRE_EMP_DB_POS_BW80_0_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW80_B0_ADDRESS (0x90 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PRE_EMPHASIS_BW80_B0_RSTMASK 0x3fffffff #define PHY_BB_PRE_EMPHASIS_BW80_B0_RESET 0x0 // 0x94 (PHY_BB_CHN_TABLES_INTF_ADDR) #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_ADDR_AUTO_INCR_LSB 31 #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_ADDR_AUTO_INCR_MSB 31 #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_ADDR_AUTO_INCR_MASK 0x80000000 #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_ADDR_AUTO_INCR_GET(x) (((x) & PHY_BB_CHN_TABLES_INTF_ADDR_CHN_ADDR_AUTO_INCR_MASK) >> PHY_BB_CHN_TABLES_INTF_ADDR_CHN_ADDR_AUTO_INCR_LSB) #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_ADDR_AUTO_INCR_SET(x) (((0 | (x)) << PHY_BB_CHN_TABLES_INTF_ADDR_CHN_ADDR_AUTO_INCR_LSB) & PHY_BB_CHN_TABLES_INTF_ADDR_CHN_ADDR_AUTO_INCR_MASK) #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_ADDR_AUTO_INCR_RESET 0x0 #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_TABLES_ADDR_LSB 2 #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_TABLES_ADDR_MSB 17 #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_TABLES_ADDR_MASK 0x3fffc #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_TABLES_ADDR_GET(x) (((x) & PHY_BB_CHN_TABLES_INTF_ADDR_CHN_TABLES_ADDR_MASK) >> PHY_BB_CHN_TABLES_INTF_ADDR_CHN_TABLES_ADDR_LSB) #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_TABLES_ADDR_SET(x) (((0 | (x)) << PHY_BB_CHN_TABLES_INTF_ADDR_CHN_TABLES_ADDR_LSB) & PHY_BB_CHN_TABLES_INTF_ADDR_CHN_TABLES_ADDR_MASK) #define PHY_BB_CHN_TABLES_INTF_ADDR_CHN_TABLES_ADDR_RESET 0x0 #define PHY_BB_CHN_TABLES_INTF_ADDR_ADDRESS (0x94 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHN_TABLES_INTF_ADDR_RSTMASK 0x8003fffc #define PHY_BB_CHN_TABLES_INTF_ADDR_RESET 0x0 // 0x98 (PHY_BB_CHN_TABLES_INTF_DATA) #define PHY_BB_CHN_TABLES_INTF_DATA_CHN_TABLES_DATA_LSB 0 #define PHY_BB_CHN_TABLES_INTF_DATA_CHN_TABLES_DATA_MSB 31 #define PHY_BB_CHN_TABLES_INTF_DATA_CHN_TABLES_DATA_MASK 0xffffffff #define PHY_BB_CHN_TABLES_INTF_DATA_CHN_TABLES_DATA_GET(x) (((x) & PHY_BB_CHN_TABLES_INTF_DATA_CHN_TABLES_DATA_MASK) >> PHY_BB_CHN_TABLES_INTF_DATA_CHN_TABLES_DATA_LSB) #define PHY_BB_CHN_TABLES_INTF_DATA_CHN_TABLES_DATA_SET(x) (((0 | (x)) << PHY_BB_CHN_TABLES_INTF_DATA_CHN_TABLES_DATA_LSB) & PHY_BB_CHN_TABLES_INTF_DATA_CHN_TABLES_DATA_MASK) #define PHY_BB_CHN_TABLES_INTF_DATA_CHN_TABLES_DATA_RESET 0x0 #define PHY_BB_CHN_TABLES_INTF_DATA_ADDRESS (0x98 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHN_TABLES_INTF_DATA_RSTMASK 0xffffffff #define PHY_BB_CHN_TABLES_INTF_DATA_RESET 0x0 // 0x9c (PHY_BB_PHYDBG_CONTROL1) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_LSB 30 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_MSB 31 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_MASK 0xc0000000 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_MASK) >> PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_LSB) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_LSB) & PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_MASK) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_CHN_SEL_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_LSB 16 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_MSB 29 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_MASK 0x3fff0000 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_MASK) >> PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_LSB) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_LSB) & PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_MASK) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_COUNT_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_LSB 15 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_MSB 15 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_MASK 0x8000 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_MASK) >> PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_LSB) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_LSB) & PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_MASK) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_TRIG_MODE_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_LSB 14 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_MSB 14 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_MASK 0x4000 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_MASK) >> PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_LSB) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_LSB) & PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_MASK) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_PLYBCK_TRIG_MODE_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_LSB 0 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_MSB 13 #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_MASK 0x3fff #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_MASK) >> PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_LSB) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_LSB) & PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_MASK) #define PHY_BB_PHYDBG_CONTROL1_PHYDBG_CAP_PRE_STORE_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL1_ADDRESS (0x9c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PHYDBG_CONTROL1_RSTMASK 0xffffffff #define PHY_BB_PHYDBG_CONTROL1_RESET 0x0 // 0xa0 (PHY_BB_PHYDBG_CONTROL2) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_LSB 31 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_MSB 31 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_MASK 0x80000000 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_MASK) >> PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_LSB) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_LSB) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_MASK) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_EN_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_LSB 16 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_MSB 30 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_MASK 0x7fff0000 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_MASK) >> PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_LSB) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_LSB) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_MASK) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_ADDR_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_LSB 11 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_MSB 15 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_MASK 0xf800 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_MASK) >> PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_LSB) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_LSB) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_MASK) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_CAP_TRIG_SELECT_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_LSB 7 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_MSB 10 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_MASK 0x780 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_MASK) >> PHY_BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_LSB) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_LSB) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_MASK) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_FSMSTATE_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_LSB 5 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_MSB 6 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_MASK 0x60 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_MASK) >> PHY_BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_LSB) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_LSB) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_MASK) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_APB_AUTOINCR_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_LSB 4 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_MSB 4 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_MASK 0x10 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_MASK) >> PHY_BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_LSB) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_LSB) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_MASK) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_PLYBCK_EN_RESET 0x0 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_MODE_LSB 0 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_MODE_MSB 3 #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_MODE_MASK 0xf #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_MODE_GET(x) (((x) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_MODE_MASK) >> PHY_BB_PHYDBG_CONTROL2_PHYDBG_MODE_LSB) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_MODE_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_CONTROL2_PHYDBG_MODE_LSB) & PHY_BB_PHYDBG_CONTROL2_PHYDBG_MODE_MASK) #define PHY_BB_PHYDBG_CONTROL2_PHYDBG_MODE_RESET 0xf #define PHY_BB_PHYDBG_CONTROL2_ADDRESS (0xa0 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PHYDBG_CONTROL2_RSTMASK 0xffffffff #define PHY_BB_PHYDBG_CONTROL2_RESET 0xf // 0xa4 (PHY_BB_TSTDAC_CONSTANT) #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB 11 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MSB 21 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK 0x3ff800 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_GET(x) (((x) & PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK) >> PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB) #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_SET(x) (((0 | (x)) << PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB) & PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK) #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_RESET 0x0 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB 0 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MSB 10 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK 0x7ff #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_GET(x) (((x) & PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK) >> PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB) #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_SET(x) (((0 | (x)) << PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB) & PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK) #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_RESET 0x0 #define PHY_BB_TSTDAC_CONSTANT_ADDRESS (0xa4 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TSTDAC_CONSTANT_RSTMASK 0x3fffff #define PHY_BB_TSTDAC_CONSTANT_RESET 0x0 // 0xa8 (PHY_BB_SPUR_REPORT_B0) #define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB 16 #define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MSB 31 #define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK 0xffff0000 #define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_GET(x) (((x) & PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK) >> PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB) #define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_SET(x) (((0 | (x)) << PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB) & PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK) #define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_RESET 0x0 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB 8 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MSB 15 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK 0xff00 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_GET(x) (((x) & PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK) >> PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB) #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_SET(x) (((0 | (x)) << PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB) & PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK) #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_RESET 0x0 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB 0 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MSB 7 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK 0xff #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_GET(x) (((x) & PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK) >> PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB) #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_SET(x) (((0 | (x)) << PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB) & PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK) #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_RESET 0x0 #define PHY_BB_SPUR_REPORT_B0_ADDRESS (0xa8 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_REPORT_B0_RSTMASK 0xffffffff #define PHY_BB_SPUR_REPORT_B0_RESET 0x0 // 0xbc (PHY_BB_GREEN_TX_CONTROL_1) #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_CASES_LSB 1 #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_CASES_MSB 1 #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_CASES_MASK 0x2 #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_CASES_GET(x) (((x) & PHY_BB_GREEN_TX_CONTROL_1_GREEN_CASES_MASK) >> PHY_BB_GREEN_TX_CONTROL_1_GREEN_CASES_LSB) #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_CASES_SET(x) (((0 | (x)) << PHY_BB_GREEN_TX_CONTROL_1_GREEN_CASES_LSB) & PHY_BB_GREEN_TX_CONTROL_1_GREEN_CASES_MASK) #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_CASES_RESET 0x1 #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_TX_ENABLE_LSB 0 #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_TX_ENABLE_MSB 0 #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_TX_ENABLE_MASK 0x1 #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_TX_ENABLE_GET(x) (((x) & PHY_BB_GREEN_TX_CONTROL_1_GREEN_TX_ENABLE_MASK) >> PHY_BB_GREEN_TX_CONTROL_1_GREEN_TX_ENABLE_LSB) #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_TX_ENABLE_SET(x) (((0 | (x)) << PHY_BB_GREEN_TX_CONTROL_1_GREEN_TX_ENABLE_LSB) & PHY_BB_GREEN_TX_CONTROL_1_GREEN_TX_ENABLE_MASK) #define PHY_BB_GREEN_TX_CONTROL_1_GREEN_TX_ENABLE_RESET 0x0 #define PHY_BB_GREEN_TX_CONTROL_1_ADDRESS (0xbc + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_GREEN_TX_CONTROL_1_RSTMASK 0x3 #define PHY_BB_GREEN_TX_CONTROL_1_RESET 0x2 // 0xc0 (PHY_BB_IQ_ADC_MEAS_0_B0) #define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB 0 #define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MSB 31 #define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK) >> PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB) #define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB) & PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK) #define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_0_B0_ADDRESS (0xc0 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_0_B0_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_0_B0_RESET 0x0 // 0xc4 (PHY_BB_IQ_ADC_MEAS_1_B0) #define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB 0 #define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MSB 31 #define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK) >> PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB) #define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB) & PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK) #define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_1_B0_ADDRESS (0xc4 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_1_B0_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_1_B0_RESET 0x0 // 0xc8 (PHY_BB_IQ_ADC_MEAS_2_B0) #define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB 0 #define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MSB 31 #define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK) >> PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB) #define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB) & PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK) #define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_2_B0_ADDRESS (0xc8 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_2_B0_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_2_B0_RESET 0x0 // 0xcc (PHY_BB_IQ_ADC_MEAS_3_B0) #define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB 0 #define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MSB 31 #define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK) >> PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB) #define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB) & PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK) #define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_3_B0_ADDRESS (0xcc + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_3_B0_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_3_B0_RESET 0x0 // 0xd0 (PHY_BB_TX_PHASE_RAMP_B0) #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB 17 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MSB 24 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK 0x1fe0000 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK) >> PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB) #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB) & PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK) #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB 7 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MSB 16 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK 0x1ff80 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK) >> PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB) #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB) & PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK) #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB 1 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MSB 6 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK 0x7e #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK) >> PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB) #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB) & PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK) #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB 0 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MSB 0 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK 0x1 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK) >> PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB) #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB) & PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK) #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B0_ADDRESS (0xd0 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TX_PHASE_RAMP_B0_RSTMASK 0x1ffffff #define PHY_BB_TX_PHASE_RAMP_B0_RESET 0x0 // 0xd4 (PHY_BB_ADC_GAIN_CORR_B0) #define PHY_BB_ADC_GAIN_CORR_B0_ADC_FIXED_GAIN_LSB 20 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_FIXED_GAIN_MSB 28 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_FIXED_GAIN_MASK 0x1ff00000 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_FIXED_GAIN_GET(x) (((x) & PHY_BB_ADC_GAIN_CORR_B0_ADC_FIXED_GAIN_MASK) >> PHY_BB_ADC_GAIN_CORR_B0_ADC_FIXED_GAIN_LSB) #define PHY_BB_ADC_GAIN_CORR_B0_ADC_FIXED_GAIN_SET(x) (((0 | (x)) << PHY_BB_ADC_GAIN_CORR_B0_ADC_FIXED_GAIN_LSB) & PHY_BB_ADC_GAIN_CORR_B0_ADC_FIXED_GAIN_MASK) #define PHY_BB_ADC_GAIN_CORR_B0_ADC_FIXED_GAIN_RESET 0x100 #define PHY_BB_ADC_GAIN_CORR_B0_ENABLE_BW_MODE_SEL_FOR_TIADC_CORR_LSB 19 #define PHY_BB_ADC_GAIN_CORR_B0_ENABLE_BW_MODE_SEL_FOR_TIADC_CORR_MSB 19 #define PHY_BB_ADC_GAIN_CORR_B0_ENABLE_BW_MODE_SEL_FOR_TIADC_CORR_MASK 0x80000 #define PHY_BB_ADC_GAIN_CORR_B0_ENABLE_BW_MODE_SEL_FOR_TIADC_CORR_GET(x) (((x) & PHY_BB_ADC_GAIN_CORR_B0_ENABLE_BW_MODE_SEL_FOR_TIADC_CORR_MASK) >> PHY_BB_ADC_GAIN_CORR_B0_ENABLE_BW_MODE_SEL_FOR_TIADC_CORR_LSB) #define PHY_BB_ADC_GAIN_CORR_B0_ENABLE_BW_MODE_SEL_FOR_TIADC_CORR_SET(x) (((0 | (x)) << PHY_BB_ADC_GAIN_CORR_B0_ENABLE_BW_MODE_SEL_FOR_TIADC_CORR_LSB) & PHY_BB_ADC_GAIN_CORR_B0_ENABLE_BW_MODE_SEL_FOR_TIADC_CORR_MASK) #define PHY_BB_ADC_GAIN_CORR_B0_ENABLE_BW_MODE_SEL_FOR_TIADC_CORR_RESET 0x0 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB 18 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_ENABLE_MSB 18 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK 0x40000 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_ENABLE_GET(x) (((x) & PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK) >> PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB) #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_ENABLE_SET(x) (((0 | (x)) << PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB) & PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK) #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_ENABLE_RESET 0x0 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB 9 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MSB 17 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK 0x3fe00 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_GET(x) (((x) & PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK) >> PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB) #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_SET(x) (((0 | (x)) << PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB) & PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK) #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_RESET 0x20 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB 0 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MSB 8 #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK 0x1ff #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_GET(x) (((x) & PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK) >> PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB) #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_SET(x) (((0 | (x)) << PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB) & PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK) #define PHY_BB_ADC_GAIN_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_RESET 0x20 #define PHY_BB_ADC_GAIN_CORR_B0_ADDRESS (0xd4 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_ADC_GAIN_CORR_B0_RSTMASK 0x1fffffff #define PHY_BB_ADC_GAIN_CORR_B0_RESET 0x10004020 // 0xd8 (PHY_BB_ADC_DC_CORR_B0) #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB 18 #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_ENABLE_MSB 18 #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK 0x40000 #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_ENABLE_GET(x) (((x) & PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK) >> PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB) #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_ENABLE_SET(x) (((0 | (x)) << PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB) & PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK) #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_ENABLE_RESET 0x0 #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB 9 #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MSB 17 #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK 0x3fe00 #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_GET(x) (((x) & PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK) >> PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB) #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_SET(x) (((0 | (x)) << PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB) & PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK) #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_RESET 0x0 #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB 0 #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MSB 8 #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK 0x1ff #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_GET(x) (((x) & PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK) >> PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB) #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_SET(x) (((0 | (x)) << PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB) & PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK) #define PHY_BB_ADC_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_RESET 0x0 #define PHY_BB_ADC_DC_CORR_B0_ADDRESS (0xd8 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_ADC_DC_CORR_B0_RSTMASK 0x7ffff #define PHY_BB_ADC_DC_CORR_B0_RESET 0x0 // 0xdc (PHY_BB_RX_IQ_CORR_B0) #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_LB_LSB 3 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_LB_MSB 3 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_LB_MASK 0x8 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_LB_GET(x) (((x) & PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_LB_MASK) >> PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_LB_LSB) #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_LB_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_LB_LSB) & PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_LB_MASK) #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_LB_RESET 0x0 #define PHY_BB_RX_IQ_CORR_B0_RX_IQC_USE_ONETAP_LSB 2 #define PHY_BB_RX_IQ_CORR_B0_RX_IQC_USE_ONETAP_MSB 2 #define PHY_BB_RX_IQ_CORR_B0_RX_IQC_USE_ONETAP_MASK 0x4 #define PHY_BB_RX_IQ_CORR_B0_RX_IQC_USE_ONETAP_GET(x) (((x) & PHY_BB_RX_IQ_CORR_B0_RX_IQC_USE_ONETAP_MASK) >> PHY_BB_RX_IQ_CORR_B0_RX_IQC_USE_ONETAP_LSB) #define PHY_BB_RX_IQ_CORR_B0_RX_IQC_USE_ONETAP_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_B0_RX_IQC_USE_ONETAP_LSB) & PHY_BB_RX_IQ_CORR_B0_RX_IQC_USE_ONETAP_MASK) #define PHY_BB_RX_IQ_CORR_B0_RX_IQC_USE_ONETAP_RESET 0x0 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_IN_AGC_LSB 1 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_IN_AGC_MSB 1 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_IN_AGC_MASK 0x2 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_IN_AGC_GET(x) (((x) & PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_IN_AGC_MASK) >> PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_IN_AGC_LSB) #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_IN_AGC_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_IN_AGC_LSB) & PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_IN_AGC_MASK) #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_BYPASS_IN_AGC_RESET 0x0 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB 0 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MSB 0 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK 0x1 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_GET(x) (((x) & PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK) >> PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB) #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB) & PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK) #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_RESET 0x0 #define PHY_BB_RX_IQ_CORR_B0_ADDRESS (0xdc + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_IQ_CORR_B0_RSTMASK 0xf #define PHY_BB_RX_IQ_CORR_B0_RESET 0x0 // 0xe0 (PHY_BB_RX_IQ_CORR_LOOPBACK_B0) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_ENABLE_LSB 18 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_ENABLE_MSB 18 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_ENABLE_MASK 0x40000 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_ENABLE_GET(x) (((x) & PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_ENABLE_MASK) >> PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_ENABLE_LSB) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_ENABLE_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_ENABLE_LSB) & PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_ENABLE_MASK) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_ENABLE_RESET 0x0 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB 9 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MSB 17 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK 0x3fe00 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_I_COFF_0_GET(x) (((x) & PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK) >> PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_I_COFF_0_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB) & PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_I_COFF_0_RESET 0x0 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB 0 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MSB 8 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK 0x1ff #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_GET(x) (((x) & PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK) >> PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB) & PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_RESET 0x0 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_ADDRESS (0xe0 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_RSTMASK 0x7ffff #define PHY_BB_RX_IQ_CORR_LOOPBACK_B0_RESET 0x0 // 0xe4 (PHY_BB_PAPRD_AM2AM_MASK) #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB 0 #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MSB 30 #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK 0x7fffffff #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_GET(x) (((x) & PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK) >> PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB) #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_SET(x) (((0 | (x)) << PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB) & PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK) #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_RESET 0x0 #define PHY_BB_PAPRD_AM2AM_MASK_ADDRESS (0xe4 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_AM2AM_MASK_RSTMASK 0x7fffffff #define PHY_BB_PAPRD_AM2AM_MASK_RESET 0x0 // 0xe8 (PHY_BB_PAPRD_AM2PM_MASK) #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB 0 #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MSB 30 #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK 0x7fffffff #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_GET(x) (((x) & PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK) >> PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB) #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_SET(x) (((0 | (x)) << PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB) & PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK) #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_RESET 0x0 #define PHY_BB_PAPRD_AM2PM_MASK_ADDRESS (0xe8 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_AM2PM_MASK_RSTMASK 0x7fffffff #define PHY_BB_PAPRD_AM2PM_MASK_RESET 0x0 // 0xec (PHY_BB_PAPRD_HT40_MASK) #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB 0 #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MSB 30 #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK 0x7fffffff #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_GET(x) (((x) & PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK) >> PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB) #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_SET(x) (((0 | (x)) << PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB) & PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK) #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_RESET 0x0 #define PHY_BB_PAPRD_HT40_MASK_ADDRESS (0xec + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_HT40_MASK_RSTMASK 0x7fffffff #define PHY_BB_PAPRD_HT40_MASK_RESET 0x0 // 0xf0 (PHY_BB_PAPRD_CTRL0_B0) #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_VALID_GAIN_5_0_0_LSB 2 #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_VALID_GAIN_5_0_0_MSB 31 #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_VALID_GAIN_5_0_0_MASK 0xfffffffc #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_VALID_GAIN_5_0_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL0_B0_PAPRD_VALID_GAIN_5_0_0_MASK) >> PHY_BB_PAPRD_CTRL0_B0_PAPRD_VALID_GAIN_5_0_0_LSB) #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_VALID_GAIN_5_0_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL0_B0_PAPRD_VALID_GAIN_5_0_0_LSB) & PHY_BB_PAPRD_CTRL0_B0_PAPRD_VALID_GAIN_5_0_0_MASK) #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_VALID_GAIN_5_0_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_REG_CHAIN_INDEXED_LSB 1 #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_REG_CHAIN_INDEXED_MSB 1 #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_REG_CHAIN_INDEXED_MASK 0x2 #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_REG_CHAIN_INDEXED_GET(x) (((x) & PHY_BB_PAPRD_CTRL0_B0_PAPRD_REG_CHAIN_INDEXED_MASK) >> PHY_BB_PAPRD_CTRL0_B0_PAPRD_REG_CHAIN_INDEXED_LSB) #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_REG_CHAIN_INDEXED_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL0_B0_PAPRD_REG_CHAIN_INDEXED_LSB) & PHY_BB_PAPRD_CTRL0_B0_PAPRD_REG_CHAIN_INDEXED_MASK) #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_REG_CHAIN_INDEXED_RESET 0x1 #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_LSB 0 #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_MSB 0 #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_MASK 0x1 #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_MASK) >> PHY_BB_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_LSB) #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_LSB) & PHY_BB_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_MASK) #define PHY_BB_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL0_B0_ADDRESS (0xf0 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_CTRL0_B0_RSTMASK 0xffffffff #define PHY_BB_PAPRD_CTRL0_B0_RESET 0x2 // 0xf4 (PHY_BB_PAPRD_CTRL1_B0) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TRAINER_IANDQ_SEL_0_LSB 29 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TRAINER_IANDQ_SEL_0_MSB 29 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TRAINER_IANDQ_SEL_0_MASK 0x20000000 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TRAINER_IANDQ_SEL_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B0_PAPRD_TRAINER_IANDQ_SEL_0_MASK) >> PHY_BB_PAPRD_CTRL1_B0_PAPRD_TRAINER_IANDQ_SEL_0_LSB) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TRAINER_IANDQ_SEL_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B0_PAPRD_TRAINER_IANDQ_SEL_0_LSB) & PHY_BB_PAPRD_CTRL1_B0_PAPRD_TRAINER_IANDQ_SEL_0_MASK) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TRAINER_IANDQ_SEL_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MIN_0_LSB 8 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MIN_0_MSB 13 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MIN_0_MASK 0x3f00 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MIN_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MIN_0_MASK) >> PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MIN_0_LSB) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MIN_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MIN_0_LSB) & PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MIN_0_MASK) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MIN_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MAX_0_LSB 2 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MAX_0_MSB 7 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MAX_0_MASK 0xfc #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MAX_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MAX_0_MASK) >> PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MAX_0_LSB) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MAX_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MAX_0_LSB) & PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MAX_0_MASK) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_TARGET_PWR_MAX_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2PM_ENABLE_0_LSB 1 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2PM_ENABLE_0_MSB 1 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2PM_ENABLE_0_MASK 0x2 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2PM_ENABLE_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2PM_ENABLE_0_MASK) >> PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2PM_ENABLE_0_LSB) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2PM_ENABLE_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2PM_ENABLE_0_LSB) & PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2PM_ENABLE_0_MASK) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2PM_ENABLE_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2AM_ENABLE_0_LSB 0 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2AM_ENABLE_0_MSB 0 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2AM_ENABLE_0_MASK 0x1 #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2AM_ENABLE_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2AM_ENABLE_0_MASK) >> PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2AM_ENABLE_0_LSB) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2AM_ENABLE_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2AM_ENABLE_0_LSB) & PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2AM_ENABLE_0_MASK) #define PHY_BB_PAPRD_CTRL1_B0_PAPRD_ADAPTIVE_AM2AM_ENABLE_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B0_ADDRESS (0xf4 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_CTRL1_B0_RSTMASK 0x20003fff #define PHY_BB_PAPRD_CTRL1_B0_RESET 0x0 // 0xf8 (PHY_BB_PAPRD_CTRL2_B0) #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_MAG_THRSH_0_LSB 27 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_MAG_THRSH_0_MSB 31 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_MAG_THRSH_0_MASK 0xf8000000 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_MAG_THRSH_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B0_PAPRD_MAG_THRSH_0_MASK) >> PHY_BB_PAPRD_CTRL2_B0_PAPRD_MAG_THRSH_0_LSB) #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_MAG_THRSH_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B0_PAPRD_MAG_THRSH_0_LSB) & PHY_BB_PAPRD_CTRL2_B0_PAPRD_MAG_THRSH_0_MASK) #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_MAG_THRSH_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_TABLE_RFBMODE_0_LSB 24 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_TABLE_RFBMODE_0_MSB 26 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_TABLE_RFBMODE_0_MASK 0x7000000 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_TABLE_RFBMODE_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B0_PAPRD_TABLE_RFBMODE_0_MASK) >> PHY_BB_PAPRD_CTRL2_B0_PAPRD_TABLE_RFBMODE_0_LSB) #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_TABLE_RFBMODE_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B0_PAPRD_TABLE_RFBMODE_0_LSB) & PHY_BB_PAPRD_CTRL2_B0_PAPRD_TABLE_RFBMODE_0_MASK) #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_TABLE_RFBMODE_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_ADAPTIVE_TABLE_VALID_0_LSB 18 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_ADAPTIVE_TABLE_VALID_0_MSB 23 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_ADAPTIVE_TABLE_VALID_0_MASK 0xfc0000 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_ADAPTIVE_TABLE_VALID_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B0_PAPRD_ADAPTIVE_TABLE_VALID_0_MASK) >> PHY_BB_PAPRD_CTRL2_B0_PAPRD_ADAPTIVE_TABLE_VALID_0_LSB) #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_ADAPTIVE_TABLE_VALID_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B0_PAPRD_ADAPTIVE_TABLE_VALID_0_LSB) & PHY_BB_PAPRD_CTRL2_B0_PAPRD_ADAPTIVE_TABLE_VALID_0_MASK) #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_ADAPTIVE_TABLE_VALID_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_VALID_PA_SETTING_0_LSB 0 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_VALID_PA_SETTING_0_MSB 17 #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_VALID_PA_SETTING_0_MASK 0x3ffff #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_VALID_PA_SETTING_0_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B0_PAPRD_VALID_PA_SETTING_0_MASK) >> PHY_BB_PAPRD_CTRL2_B0_PAPRD_VALID_PA_SETTING_0_LSB) #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_VALID_PA_SETTING_0_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B0_PAPRD_VALID_PA_SETTING_0_LSB) & PHY_BB_PAPRD_CTRL2_B0_PAPRD_VALID_PA_SETTING_0_MASK) #define PHY_BB_PAPRD_CTRL2_B0_PAPRD_VALID_PA_SETTING_0_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B0_ADDRESS (0xf8 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_CTRL2_B0_RSTMASK 0xffffffff #define PHY_BB_PAPRD_CTRL2_B0_RESET 0x0 // 0xfc (PHY_BB_PAPRD_VHT80_MASK) #define PHY_BB_PAPRD_VHT80_MASK_PAPRD_VHT80_MASK_LSB 0 #define PHY_BB_PAPRD_VHT80_MASK_PAPRD_VHT80_MASK_MSB 30 #define PHY_BB_PAPRD_VHT80_MASK_PAPRD_VHT80_MASK_MASK 0x7fffffff #define PHY_BB_PAPRD_VHT80_MASK_PAPRD_VHT80_MASK_GET(x) (((x) & PHY_BB_PAPRD_VHT80_MASK_PAPRD_VHT80_MASK_MASK) >> PHY_BB_PAPRD_VHT80_MASK_PAPRD_VHT80_MASK_LSB) #define PHY_BB_PAPRD_VHT80_MASK_PAPRD_VHT80_MASK_SET(x) (((0 | (x)) << PHY_BB_PAPRD_VHT80_MASK_PAPRD_VHT80_MASK_LSB) & PHY_BB_PAPRD_VHT80_MASK_PAPRD_VHT80_MASK_MASK) #define PHY_BB_PAPRD_VHT80_MASK_PAPRD_VHT80_MASK_RESET 0x0 #define PHY_BB_PAPRD_VHT80_MASK_ADDRESS (0xfc + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_VHT80_MASK_RSTMASK 0x7fffffff #define PHY_BB_PAPRD_VHT80_MASK_RESET 0x0 // 0x100 (PHY_BB_PHYDBG_MEM_ADDR) #define PHY_BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_LSB 0 #define PHY_BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_MSB 14 #define PHY_BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_MASK 0x7fff #define PHY_BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_GET(x) (((x) & PHY_BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_MASK) >> PHY_BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_LSB) #define PHY_BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_LSB) & PHY_BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_MASK) #define PHY_BB_PHYDBG_MEM_ADDR_PHYDBG_MEM_ADDR_RESET 0x0 #define PHY_BB_PHYDBG_MEM_ADDR_ADDRESS (0x100 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PHYDBG_MEM_ADDR_RSTMASK 0x7fff #define PHY_BB_PHYDBG_MEM_ADDR_RESET 0x0 // 0x104 (PHY_BB_PHYDBG_MEM_DATA) #define PHY_BB_PHYDBG_MEM_DATA_PHYDBG_MEM_DATA_LSB 0 #define PHY_BB_PHYDBG_MEM_DATA_PHYDBG_MEM_DATA_MSB 31 #define PHY_BB_PHYDBG_MEM_DATA_PHYDBG_MEM_DATA_MASK 0xffffffff #define PHY_BB_PHYDBG_MEM_DATA_PHYDBG_MEM_DATA_GET(x) (((x) & PHY_BB_PHYDBG_MEM_DATA_PHYDBG_MEM_DATA_MASK) >> PHY_BB_PHYDBG_MEM_DATA_PHYDBG_MEM_DATA_LSB) #define PHY_BB_PHYDBG_MEM_DATA_PHYDBG_MEM_DATA_SET(x) (((0 | (x)) << PHY_BB_PHYDBG_MEM_DATA_PHYDBG_MEM_DATA_LSB) & PHY_BB_PHYDBG_MEM_DATA_PHYDBG_MEM_DATA_MASK) #define PHY_BB_PHYDBG_MEM_DATA_PHYDBG_MEM_DATA_RESET 0x0 #define PHY_BB_PHYDBG_MEM_DATA_ADDRESS (0x104 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PHYDBG_MEM_DATA_RSTMASK 0xffffffff #define PHY_BB_PHYDBG_MEM_DATA_RESET 0x0 // 0x108 (PHY_BB_BTCF_CONFIG) #define PHY_BB_BTCF_CONFIG_BTCF_FINETIM_CORR_EN_LSB 31 #define PHY_BB_BTCF_CONFIG_BTCF_FINETIM_CORR_EN_MSB 31 #define PHY_BB_BTCF_CONFIG_BTCF_FINETIM_CORR_EN_MASK 0x80000000 #define PHY_BB_BTCF_CONFIG_BTCF_FINETIM_CORR_EN_GET(x) (((x) & PHY_BB_BTCF_CONFIG_BTCF_FINETIM_CORR_EN_MASK) >> PHY_BB_BTCF_CONFIG_BTCF_FINETIM_CORR_EN_LSB) #define PHY_BB_BTCF_CONFIG_BTCF_FINETIM_CORR_EN_SET(x) (((0 | (x)) << PHY_BB_BTCF_CONFIG_BTCF_FINETIM_CORR_EN_LSB) & PHY_BB_BTCF_CONFIG_BTCF_FINETIM_CORR_EN_MASK) #define PHY_BB_BTCF_CONFIG_BTCF_FINETIM_CORR_EN_RESET 0x1 #define PHY_BB_BTCF_CONFIG_BTCF_EN_LSB 30 #define PHY_BB_BTCF_CONFIG_BTCF_EN_MSB 30 #define PHY_BB_BTCF_CONFIG_BTCF_EN_MASK 0x40000000 #define PHY_BB_BTCF_CONFIG_BTCF_EN_GET(x) (((x) & PHY_BB_BTCF_CONFIG_BTCF_EN_MASK) >> PHY_BB_BTCF_CONFIG_BTCF_EN_LSB) #define PHY_BB_BTCF_CONFIG_BTCF_EN_SET(x) (((0 | (x)) << PHY_BB_BTCF_CONFIG_BTCF_EN_LSB) & PHY_BB_BTCF_CONFIG_BTCF_EN_MASK) #define PHY_BB_BTCF_CONFIG_BTCF_EN_RESET 0x1 #define PHY_BB_BTCF_CONFIG_BTCF_LGFIRPWR_IDEAL_LSB 18 #define PHY_BB_BTCF_CONFIG_BTCF_LGFIRPWR_IDEAL_MSB 29 #define PHY_BB_BTCF_CONFIG_BTCF_LGFIRPWR_IDEAL_MASK 0x3ffc0000 #define PHY_BB_BTCF_CONFIG_BTCF_LGFIRPWR_IDEAL_GET(x) (((x) & PHY_BB_BTCF_CONFIG_BTCF_LGFIRPWR_IDEAL_MASK) >> PHY_BB_BTCF_CONFIG_BTCF_LGFIRPWR_IDEAL_LSB) #define PHY_BB_BTCF_CONFIG_BTCF_LGFIRPWR_IDEAL_SET(x) (((0 | (x)) << PHY_BB_BTCF_CONFIG_BTCF_LGFIRPWR_IDEAL_LSB) & PHY_BB_BTCF_CONFIG_BTCF_LGFIRPWR_IDEAL_MASK) #define PHY_BB_BTCF_CONFIG_BTCF_LGFIRPWR_IDEAL_RESET 0xe8b #define PHY_BB_BTCF_CONFIG_BTCF_DET_DSHIFT_LSB 15 #define PHY_BB_BTCF_CONFIG_BTCF_DET_DSHIFT_MSB 17 #define PHY_BB_BTCF_CONFIG_BTCF_DET_DSHIFT_MASK 0x38000 #define PHY_BB_BTCF_CONFIG_BTCF_DET_DSHIFT_GET(x) (((x) & PHY_BB_BTCF_CONFIG_BTCF_DET_DSHIFT_MASK) >> PHY_BB_BTCF_CONFIG_BTCF_DET_DSHIFT_LSB) #define PHY_BB_BTCF_CONFIG_BTCF_DET_DSHIFT_SET(x) (((0 | (x)) << PHY_BB_BTCF_CONFIG_BTCF_DET_DSHIFT_LSB) & PHY_BB_BTCF_CONFIG_BTCF_DET_DSHIFT_MASK) #define PHY_BB_BTCF_CONFIG_BTCF_DET_DSHIFT_RESET 0x3 #define PHY_BB_BTCF_CONFIG_BTCF_DET_RATIO_LSB 12 #define PHY_BB_BTCF_CONFIG_BTCF_DET_RATIO_MSB 14 #define PHY_BB_BTCF_CONFIG_BTCF_DET_RATIO_MASK 0x7000 #define PHY_BB_BTCF_CONFIG_BTCF_DET_RATIO_GET(x) (((x) & PHY_BB_BTCF_CONFIG_BTCF_DET_RATIO_MASK) >> PHY_BB_BTCF_CONFIG_BTCF_DET_RATIO_LSB) #define PHY_BB_BTCF_CONFIG_BTCF_DET_RATIO_SET(x) (((0 | (x)) << PHY_BB_BTCF_CONFIG_BTCF_DET_RATIO_LSB) & PHY_BB_BTCF_CONFIG_BTCF_DET_RATIO_MASK) #define PHY_BB_BTCF_CONFIG_BTCF_DET_RATIO_RESET 0x5 #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET256_LSB 8 #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET256_MSB 11 #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET256_MASK 0xf00 #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET256_GET(x) (((x) & PHY_BB_BTCF_CONFIG_FFT_TOFFSET256_MASK) >> PHY_BB_BTCF_CONFIG_FFT_TOFFSET256_LSB) #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET256_SET(x) (((0 | (x)) << PHY_BB_BTCF_CONFIG_FFT_TOFFSET256_LSB) & PHY_BB_BTCF_CONFIG_FFT_TOFFSET256_MASK) #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET256_RESET 0xe #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET128_LSB 4 #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET128_MSB 7 #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET128_MASK 0xf0 #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET128_GET(x) (((x) & PHY_BB_BTCF_CONFIG_FFT_TOFFSET128_MASK) >> PHY_BB_BTCF_CONFIG_FFT_TOFFSET128_LSB) #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET128_SET(x) (((0 | (x)) << PHY_BB_BTCF_CONFIG_FFT_TOFFSET128_LSB) & PHY_BB_BTCF_CONFIG_FFT_TOFFSET128_MASK) #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET128_RESET 0xd #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET64_LSB 0 #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET64_MSB 3 #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET64_MASK 0xf #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET64_GET(x) (((x) & PHY_BB_BTCF_CONFIG_FFT_TOFFSET64_MASK) >> PHY_BB_BTCF_CONFIG_FFT_TOFFSET64_LSB) #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET64_SET(x) (((0 | (x)) << PHY_BB_BTCF_CONFIG_FFT_TOFFSET64_LSB) & PHY_BB_BTCF_CONFIG_FFT_TOFFSET64_MASK) #define PHY_BB_BTCF_CONFIG_FFT_TOFFSET64_RESET 0xd #define PHY_BB_BTCF_CONFIG_ADDRESS (0x108 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BTCF_CONFIG_RSTMASK 0xffffffff #define PHY_BB_BTCF_CONFIG_RESET 0xfa2ddedd // 0x10c (PHY_BB_BTCF_TH_CONFIG) #define PHY_BB_BTCF_TH_CONFIG_BTCF_LOW_SNR_BRANCH_LSB 24 #define PHY_BB_BTCF_TH_CONFIG_BTCF_LOW_SNR_BRANCH_MSB 24 #define PHY_BB_BTCF_TH_CONFIG_BTCF_LOW_SNR_BRANCH_MASK 0x1000000 #define PHY_BB_BTCF_TH_CONFIG_BTCF_LOW_SNR_BRANCH_GET(x) (((x) & PHY_BB_BTCF_TH_CONFIG_BTCF_LOW_SNR_BRANCH_MASK) >> PHY_BB_BTCF_TH_CONFIG_BTCF_LOW_SNR_BRANCH_LSB) #define PHY_BB_BTCF_TH_CONFIG_BTCF_LOW_SNR_BRANCH_SET(x) (((0 | (x)) << PHY_BB_BTCF_TH_CONFIG_BTCF_LOW_SNR_BRANCH_LSB) & PHY_BB_BTCF_TH_CONFIG_BTCF_LOW_SNR_BRANCH_MASK) #define PHY_BB_BTCF_TH_CONFIG_BTCF_LOW_SNR_BRANCH_RESET 0x0 #define PHY_BB_BTCF_TH_CONFIG_BTCF_SNR_TH_DB_LSB 16 #define PHY_BB_BTCF_TH_CONFIG_BTCF_SNR_TH_DB_MSB 23 #define PHY_BB_BTCF_TH_CONFIG_BTCF_SNR_TH_DB_MASK 0xff0000 #define PHY_BB_BTCF_TH_CONFIG_BTCF_SNR_TH_DB_GET(x) (((x) & PHY_BB_BTCF_TH_CONFIG_BTCF_SNR_TH_DB_MASK) >> PHY_BB_BTCF_TH_CONFIG_BTCF_SNR_TH_DB_LSB) #define PHY_BB_BTCF_TH_CONFIG_BTCF_SNR_TH_DB_SET(x) (((0 | (x)) << PHY_BB_BTCF_TH_CONFIG_BTCF_SNR_TH_DB_LSB) & PHY_BB_BTCF_TH_CONFIG_BTCF_SNR_TH_DB_MASK) #define PHY_BB_BTCF_TH_CONFIG_BTCF_SNR_TH_DB_RESET 0xf #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH2_LSB 8 #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH2_MSB 15 #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH2_MASK 0xff00 #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH2_GET(x) (((x) & PHY_BB_BTCF_TH_CONFIG_BTCF_TH2_MASK) >> PHY_BB_BTCF_TH_CONFIG_BTCF_TH2_LSB) #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH2_SET(x) (((0 | (x)) << PHY_BB_BTCF_TH_CONFIG_BTCF_TH2_LSB) & PHY_BB_BTCF_TH_CONFIG_BTCF_TH2_MASK) #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH2_RESET 0x22 #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH1_LSB 0 #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH1_MSB 7 #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH1_MASK 0xff #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH1_GET(x) (((x) & PHY_BB_BTCF_TH_CONFIG_BTCF_TH1_MASK) >> PHY_BB_BTCF_TH_CONFIG_BTCF_TH1_LSB) #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH1_SET(x) (((0 | (x)) << PHY_BB_BTCF_TH_CONFIG_BTCF_TH1_LSB) & PHY_BB_BTCF_TH_CONFIG_BTCF_TH1_MASK) #define PHY_BB_BTCF_TH_CONFIG_BTCF_TH1_RESET 0x24 #define PHY_BB_BTCF_TH_CONFIG_ADDRESS (0x10c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BTCF_TH_CONFIG_RSTMASK 0x1ffffff #define PHY_BB_BTCF_TH_CONFIG_RESET 0xf2224 // 0x110 (PHY_BB_BTCF_DCN_CONFIG) #define PHY_BB_BTCF_DCN_CONFIG_DCN_BYPASS_LSB 31 #define PHY_BB_BTCF_DCN_CONFIG_DCN_BYPASS_MSB 31 #define PHY_BB_BTCF_DCN_CONFIG_DCN_BYPASS_MASK 0x80000000 #define PHY_BB_BTCF_DCN_CONFIG_DCN_BYPASS_GET(x) (((x) & PHY_BB_BTCF_DCN_CONFIG_DCN_BYPASS_MASK) >> PHY_BB_BTCF_DCN_CONFIG_DCN_BYPASS_LSB) #define PHY_BB_BTCF_DCN_CONFIG_DCN_BYPASS_SET(x) (((0 | (x)) << PHY_BB_BTCF_DCN_CONFIG_DCN_BYPASS_LSB) & PHY_BB_BTCF_DCN_CONFIG_DCN_BYPASS_MASK) #define PHY_BB_BTCF_DCN_CONFIG_DCN_BYPASS_RESET 0x0 #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA_SEL_LSB 30 #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA_SEL_MSB 30 #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA_SEL_MASK 0x40000000 #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA_SEL_GET(x) (((x) & PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA_SEL_MASK) >> PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA_SEL_LSB) #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA_SEL_SET(x) (((0 | (x)) << PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA_SEL_LSB) & PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA_SEL_MASK) #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA_SEL_RESET 0x0 #define PHY_BB_BTCF_DCN_CONFIG_BTCF_AGC_DLY_LSB 18 #define PHY_BB_BTCF_DCN_CONFIG_BTCF_AGC_DLY_MSB 26 #define PHY_BB_BTCF_DCN_CONFIG_BTCF_AGC_DLY_MASK 0x7fc0000 #define PHY_BB_BTCF_DCN_CONFIG_BTCF_AGC_DLY_GET(x) (((x) & PHY_BB_BTCF_DCN_CONFIG_BTCF_AGC_DLY_MASK) >> PHY_BB_BTCF_DCN_CONFIG_BTCF_AGC_DLY_LSB) #define PHY_BB_BTCF_DCN_CONFIG_BTCF_AGC_DLY_SET(x) (((0 | (x)) << PHY_BB_BTCF_DCN_CONFIG_BTCF_AGC_DLY_LSB) & PHY_BB_BTCF_DCN_CONFIG_BTCF_AGC_DLY_MASK) #define PHY_BB_BTCF_DCN_CONFIG_BTCF_AGC_DLY_RESET 0x140 #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA2_LSB 9 #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA2_MSB 17 #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA2_MASK 0x3fe00 #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA2_GET(x) (((x) & PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA2_MASK) >> PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA2_LSB) #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA2_SET(x) (((0 | (x)) << PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA2_LSB) & PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA2_MASK) #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA2_RESET 0x12c #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA1_LSB 0 #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA1_MSB 8 #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA1_MASK 0x1ff #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA1_GET(x) (((x) & PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA1_MASK) >> PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA1_LSB) #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA1_SET(x) (((0 | (x)) << PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA1_LSB) & PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA1_MASK) #define PHY_BB_BTCF_DCN_CONFIG_DCN_ALPHA1_RESET 0x12c #define PHY_BB_BTCF_DCN_CONFIG_ADDRESS (0x110 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BTCF_DCN_CONFIG_RSTMASK 0xc7ffffff #define PHY_BB_BTCF_DCN_CONFIG_RESET 0x502592c // 0x114 (PHY_BB_BTCF_TIM_CPATURE) #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_BTCF_LSB 18 #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_BTCF_MSB 25 #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_BTCF_MASK 0x3fc0000 #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_BTCF_GET(x) (((x) & PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_BTCF_MASK) >> PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_BTCF_LSB) #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_BTCF_SET(x) (((0 | (x)) << PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_BTCF_LSB) & PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_BTCF_MASK) #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_BTCF_RESET 0x0 #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_LSB 10 #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_MSB 17 #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_MASK 0x3fc00 #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_GET(x) (((x) & PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_MASK) >> PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_LSB) #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_SET(x) (((0 | (x)) << PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_LSB) & PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_MASK) #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_SKIP_RESET 0x0 #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_COARSE_SB_LSB 0 #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_COARSE_SB_MSB 9 #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_COARSE_SB_MASK 0x3ff #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_COARSE_SB_GET(x) (((x) & PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_COARSE_SB_MASK) >> PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_COARSE_SB_LSB) #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_COARSE_SB_SET(x) (((0 | (x)) << PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_COARSE_SB_LSB) & PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_COARSE_SB_MASK) #define PHY_BB_BTCF_TIM_CPATURE_BTCF_CAP_COARSE_SB_RESET 0x0 #define PHY_BB_BTCF_TIM_CPATURE_ADDRESS (0x114 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BTCF_TIM_CPATURE_RSTMASK 0x3ffffff #define PHY_BB_BTCF_TIM_CPATURE_RESET 0x0 // 0x118 (PHY_BB_BTCF_IDX_CPATURE) #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_PICKED_IDX_LSB 3 #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_PICKED_IDX_MSB 5 #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_PICKED_IDX_MASK 0x38 #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_PICKED_IDX_GET(x) (((x) & PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_PICKED_IDX_MASK) >> PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_PICKED_IDX_LSB) #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_PICKED_IDX_SET(x) (((0 | (x)) << PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_PICKED_IDX_LSB) & PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_PICKED_IDX_MASK) #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_PICKED_IDX_RESET 0x0 #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_MIN_IDX_LSB 0 #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_MIN_IDX_MSB 2 #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_MIN_IDX_MASK 0x7 #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_MIN_IDX_GET(x) (((x) & PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_MIN_IDX_MASK) >> PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_MIN_IDX_LSB) #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_MIN_IDX_SET(x) (((0 | (x)) << PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_MIN_IDX_LSB) & PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_MIN_IDX_MASK) #define PHY_BB_BTCF_IDX_CPATURE_BTCF_CAP_MIN_IDX_RESET 0x0 #define PHY_BB_BTCF_IDX_CPATURE_ADDRESS (0x118 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BTCF_IDX_CPATURE_RSTMASK 0x3f #define PHY_BB_BTCF_IDX_CPATURE_RESET 0x0 // 0x11c (PHY_BB_BTCF_FFTSTARTSTORE) #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_FREEZE_LSB 20 #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_FREEZE_MSB 20 #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_FREEZE_MASK 0x100000 #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_FREEZE_GET(x) (((x) & PHY_BB_BTCF_FFTSTARTSTORE_BTCF_FREEZE_MASK) >> PHY_BB_BTCF_FFTSTARTSTORE_BTCF_FREEZE_LSB) #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_FREEZE_SET(x) (((0 | (x)) << PHY_BB_BTCF_FFTSTARTSTORE_BTCF_FREEZE_LSB) & PHY_BB_BTCF_FFTSTARTSTORE_BTCF_FREEZE_MASK) #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_FREEZE_RESET 0x0 #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR2_FFTSTART_LSB 10 #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR2_FFTSTART_MSB 19 #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR2_FFTSTART_MASK 0xffc00 #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR2_FFTSTART_GET(x) (((x) & PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR2_FFTSTART_MASK) >> PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR2_FFTSTART_LSB) #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR2_FFTSTART_SET(x) (((0 | (x)) << PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR2_FFTSTART_LSB) & PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR2_FFTSTART_MASK) #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR2_FFTSTART_RESET 0x0 #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR1_FFTSTART_LSB 0 #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR1_FFTSTART_MSB 9 #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR1_FFTSTART_MASK 0x3ff #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR1_FFTSTART_GET(x) (((x) & PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR1_FFTSTART_MASK) >> PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR1_FFTSTART_LSB) #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR1_FFTSTART_SET(x) (((0 | (x)) << PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR1_FFTSTART_LSB) & PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR1_FFTSTART_MASK) #define PHY_BB_BTCF_FFTSTARTSTORE_BTCF_BR1_FFTSTART_RESET 0x0 #define PHY_BB_BTCF_FFTSTARTSTORE_ADDRESS (0x11c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BTCF_FFTSTARTSTORE_RSTMASK 0x1fffff #define PHY_BB_BTCF_FFTSTARTSTORE_RESET 0x0 // 0x128 (PHY_BB_BTCF_PWR_ATMIN_169) #define PHY_BB_BTCF_PWR_ATMIN_169_BTCF_PWR_ATMIN_D169_VALUE_LSB 0 #define PHY_BB_BTCF_PWR_ATMIN_169_BTCF_PWR_ATMIN_D169_VALUE_MSB 15 #define PHY_BB_BTCF_PWR_ATMIN_169_BTCF_PWR_ATMIN_D169_VALUE_MASK 0xffff #define PHY_BB_BTCF_PWR_ATMIN_169_BTCF_PWR_ATMIN_D169_VALUE_GET(x) (((x) & PHY_BB_BTCF_PWR_ATMIN_169_BTCF_PWR_ATMIN_D169_VALUE_MASK) >> PHY_BB_BTCF_PWR_ATMIN_169_BTCF_PWR_ATMIN_D169_VALUE_LSB) #define PHY_BB_BTCF_PWR_ATMIN_169_BTCF_PWR_ATMIN_D169_VALUE_SET(x) (((0 | (x)) << PHY_BB_BTCF_PWR_ATMIN_169_BTCF_PWR_ATMIN_D169_VALUE_LSB) & PHY_BB_BTCF_PWR_ATMIN_169_BTCF_PWR_ATMIN_D169_VALUE_MASK) #define PHY_BB_BTCF_PWR_ATMIN_169_BTCF_PWR_ATMIN_D169_VALUE_RESET 0x0 #define PHY_BB_BTCF_PWR_ATMIN_169_ADDRESS (0x128 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BTCF_PWR_ATMIN_169_RSTMASK 0xffff #define PHY_BB_BTCF_PWR_ATMIN_169_RESET 0x0 // 0x12c (PHY_BB_BCF_OFFSCNT_ATMIN_169) #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_NEG_LIM_LSB 17 #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_NEG_LIM_MSB 25 #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_NEG_LIM_MASK 0x3fe0000 #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_NEG_LIM_GET(x) (((x) & PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_NEG_LIM_MASK) >> PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_NEG_LIM_LSB) #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_NEG_LIM_SET(x) (((0 | (x)) << PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_NEG_LIM_LSB) & PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_NEG_LIM_MASK) #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_NEG_LIM_RESET 0x1f9 #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_POS_LIM_LSB 8 #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_POS_LIM_MSB 16 #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_POS_LIM_MASK 0x1ff00 #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_POS_LIM_GET(x) (((x) & PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_POS_LIM_MASK) >> PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_POS_LIM_LSB) #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_POS_LIM_SET(x) (((0 | (x)) << PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_POS_LIM_LSB) & PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_POS_LIM_MASK) #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_DELTA_POS_LIM_RESET 0x1f #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_OFFSCNT_ATMIN_D169_VALUE_LSB 0 #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_OFFSCNT_ATMIN_D169_VALUE_MSB 7 #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_OFFSCNT_ATMIN_D169_VALUE_MASK 0xff #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_OFFSCNT_ATMIN_D169_VALUE_GET(x) (((x) & PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_OFFSCNT_ATMIN_D169_VALUE_MASK) >> PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_OFFSCNT_ATMIN_D169_VALUE_LSB) #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_OFFSCNT_ATMIN_D169_VALUE_SET(x) (((0 | (x)) << PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_OFFSCNT_ATMIN_D169_VALUE_LSB) & PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_OFFSCNT_ATMIN_D169_VALUE_MASK) #define PHY_BB_BCF_OFFSCNT_ATMIN_169_BTCF_OFFSCNT_ATMIN_D169_VALUE_RESET 0x0 #define PHY_BB_BCF_OFFSCNT_ATMIN_169_ADDRESS (0x12c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BCF_OFFSCNT_ATMIN_169_RSTMASK 0x3ffffff #define PHY_BB_BCF_OFFSCNT_ATMIN_169_RESET 0x3f21f00 // 0x130 (PHY_BB_BTCF_ABORT_CNT) #define PHY_BB_BTCF_ABORT_CNT_BTCF_ABORT_COUNT_LSB 0 #define PHY_BB_BTCF_ABORT_CNT_BTCF_ABORT_COUNT_MSB 15 #define PHY_BB_BTCF_ABORT_CNT_BTCF_ABORT_COUNT_MASK 0xffff #define PHY_BB_BTCF_ABORT_CNT_BTCF_ABORT_COUNT_GET(x) (((x) & PHY_BB_BTCF_ABORT_CNT_BTCF_ABORT_COUNT_MASK) >> PHY_BB_BTCF_ABORT_CNT_BTCF_ABORT_COUNT_LSB) #define PHY_BB_BTCF_ABORT_CNT_BTCF_ABORT_COUNT_SET(x) (((0 | (x)) << PHY_BB_BTCF_ABORT_CNT_BTCF_ABORT_COUNT_LSB) & PHY_BB_BTCF_ABORT_CNT_BTCF_ABORT_COUNT_MASK) #define PHY_BB_BTCF_ABORT_CNT_BTCF_ABORT_COUNT_RESET 0x0 #define PHY_BB_BTCF_ABORT_CNT_ADDRESS (0x130 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BTCF_ABORT_CNT_RSTMASK 0xffff #define PHY_BB_BTCF_ABORT_CNT_RESET 0x0 // 0x138 (PHY_BB_BCF_MINSTORE_BR1) #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_VALUE_LSB 8 #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_VALUE_MSB 28 #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_VALUE_MASK 0x1fffff00 #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_VALUE_GET(x) (((x) & PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_VALUE_MASK) >> PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_VALUE_LSB) #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_VALUE_SET(x) (((0 | (x)) << PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_VALUE_LSB) & PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_VALUE_MASK) #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_VALUE_RESET 0x1fffff #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_POSTMININDX_LSB 3 #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_POSTMININDX_MSB 7 #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_POSTMININDX_MASK 0xf8 #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_POSTMININDX_GET(x) (((x) & PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_POSTMININDX_MASK) >> PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_POSTMININDX_LSB) #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_POSTMININDX_SET(x) (((0 | (x)) << PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_POSTMININDX_LSB) & PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_POSTMININDX_MASK) #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_POSTMININDX_RESET 0x0 #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_ID_LSB 0 #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_ID_MSB 2 #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_ID_MASK 0x7 #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_ID_GET(x) (((x) & PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_ID_MASK) >> PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_ID_LSB) #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_ID_SET(x) (((0 | (x)) << PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_ID_LSB) & PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_ID_MASK) #define PHY_BB_BCF_MINSTORE_BR1_BTCF_BR1_ID_RESET 0x0 #define PHY_BB_BCF_MINSTORE_BR1_ADDRESS (0x138 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BCF_MINSTORE_BR1_RSTMASK 0x1fffffff #define PHY_BB_BCF_MINSTORE_BR1_RESET 0x1fffff00 // 0x13c (PHY_BB_BCF_MINSTORE_BR2) #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_VALUE_LSB 8 #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_VALUE_MSB 28 #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_VALUE_MASK 0x1fffff00 #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_VALUE_GET(x) (((x) & PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_VALUE_MASK) >> PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_VALUE_LSB) #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_VALUE_SET(x) (((0 | (x)) << PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_VALUE_LSB) & PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_VALUE_MASK) #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_VALUE_RESET 0x1fffff #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_POSTMININDX_LSB 3 #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_POSTMININDX_MSB 7 #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_POSTMININDX_MASK 0xf8 #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_POSTMININDX_GET(x) (((x) & PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_POSTMININDX_MASK) >> PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_POSTMININDX_LSB) #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_POSTMININDX_SET(x) (((0 | (x)) << PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_POSTMININDX_LSB) & PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_POSTMININDX_MASK) #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_POSTMININDX_RESET 0x0 #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_ID_LSB 0 #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_ID_MSB 2 #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_ID_MASK 0x7 #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_ID_GET(x) (((x) & PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_ID_MASK) >> PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_ID_LSB) #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_ID_SET(x) (((0 | (x)) << PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_ID_LSB) & PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_ID_MASK) #define PHY_BB_BCF_MINSTORE_BR2_BTCF_BR2_ID_RESET 0x0 #define PHY_BB_BCF_MINSTORE_BR2_ADDRESS (0x13c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_BCF_MINSTORE_BR2_RSTMASK 0x1fffffff #define PHY_BB_BCF_MINSTORE_BR2_RESET 0x1fffff00 // 0x140 (PHY_BB_TX_OVERLAP_WINDOW) #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW80MHZ_LSB 8 #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW80MHZ_MSB 11 #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW80MHZ_MASK 0xf00 #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW80MHZ_GET(x) (((x) & PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW80MHZ_MASK) >> PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW80MHZ_LSB) #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW80MHZ_SET(x) (((0 | (x)) << PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW80MHZ_LSB) & PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW80MHZ_MASK) #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW80MHZ_RESET 0x0 #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW40MHZ_LSB 4 #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW40MHZ_MSB 7 #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW40MHZ_MASK 0xf0 #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW40MHZ_GET(x) (((x) & PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW40MHZ_MASK) >> PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW40MHZ_LSB) #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW40MHZ_SET(x) (((0 | (x)) << PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW40MHZ_LSB) & PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW40MHZ_MASK) #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW40MHZ_RESET 0x0 #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW20MHZ_LSB 0 #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW20MHZ_MSB 3 #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW20MHZ_MASK 0xf #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW20MHZ_GET(x) (((x) & PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW20MHZ_MASK) >> PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW20MHZ_LSB) #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW20MHZ_SET(x) (((0 | (x)) << PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW20MHZ_LSB) & PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW20MHZ_MASK) #define PHY_BB_TX_OVERLAP_WINDOW_OVERLAP_WINDOW_BW20MHZ_RESET 0x0 #define PHY_BB_TX_OVERLAP_WINDOW_ADDRESS (0x140 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_TX_OVERLAP_WINDOW_RSTMASK 0xfff #define PHY_BB_TX_OVERLAP_WINDOW_RESET 0x0 // 0x144 (PHY_BB_PER_CHAIN_LEGACY_CSD) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN3_4CHAINS_LSB 25 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN3_4CHAINS_MSB 29 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN3_4CHAINS_MASK 0x3e000000 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN3_4CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN3_4CHAINS_MASK) >> PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN3_4CHAINS_LSB) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN3_4CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN3_4CHAINS_LSB) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN3_4CHAINS_MASK) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN3_4CHAINS_RESET 0x6 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_4CHAINS_LSB 20 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_4CHAINS_MSB 24 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_4CHAINS_MASK 0x1f00000 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_4CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_4CHAINS_MASK) >> PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_4CHAINS_LSB) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_4CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_4CHAINS_LSB) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_4CHAINS_MASK) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_4CHAINS_RESET 0x4 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_4CHAINS_LSB 15 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_4CHAINS_MSB 19 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_4CHAINS_MASK 0xf8000 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_4CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_4CHAINS_MASK) >> PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_4CHAINS_LSB) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_4CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_4CHAINS_LSB) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_4CHAINS_MASK) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_4CHAINS_RESET 0x2 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_3CHAINS_LSB 10 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_3CHAINS_MSB 14 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_3CHAINS_MASK 0x7c00 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_3CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_3CHAINS_MASK) >> PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_3CHAINS_LSB) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_3CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_3CHAINS_LSB) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_3CHAINS_MASK) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN2_3CHAINS_RESET 0x8 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_3CHAINS_LSB 5 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_3CHAINS_MSB 9 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_3CHAINS_MASK 0x3e0 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_3CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_3CHAINS_MASK) >> PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_3CHAINS_LSB) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_3CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_3CHAINS_LSB) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_3CHAINS_MASK) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_3CHAINS_RESET 0x4 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_2CHAINS_LSB 0 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_2CHAINS_MSB 4 #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_2CHAINS_MASK 0x1f #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_2CHAINS_GET(x) (((x) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_2CHAINS_MASK) >> PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_2CHAINS_LSB) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_2CHAINS_SET(x) (((0 | (x)) << PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_2CHAINS_LSB) & PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_2CHAINS_MASK) #define PHY_BB_PER_CHAIN_LEGACY_CSD_LEG_CSD_CHN1_2CHAINS_RESET 0x8 #define PHY_BB_PER_CHAIN_LEGACY_CSD_ADDRESS (0x144 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PER_CHAIN_LEGACY_CSD_RSTMASK 0x3fffffff #define PHY_BB_PER_CHAIN_LEGACY_CSD_RESET 0xc412088 // 0x148 (PHY_BB_FDTG_CONTROL0) #define PHY_BB_FDTG_CONTROL0_FDTG_SUPPRESS_PREAMBLE_LSB 17 #define PHY_BB_FDTG_CONTROL0_FDTG_SUPPRESS_PREAMBLE_MSB 17 #define PHY_BB_FDTG_CONTROL0_FDTG_SUPPRESS_PREAMBLE_MASK 0x20000 #define PHY_BB_FDTG_CONTROL0_FDTG_SUPPRESS_PREAMBLE_GET(x) (((x) & PHY_BB_FDTG_CONTROL0_FDTG_SUPPRESS_PREAMBLE_MASK) >> PHY_BB_FDTG_CONTROL0_FDTG_SUPPRESS_PREAMBLE_LSB) #define PHY_BB_FDTG_CONTROL0_FDTG_SUPPRESS_PREAMBLE_SET(x) (((0 | (x)) << PHY_BB_FDTG_CONTROL0_FDTG_SUPPRESS_PREAMBLE_LSB) & PHY_BB_FDTG_CONTROL0_FDTG_SUPPRESS_PREAMBLE_MASK) #define PHY_BB_FDTG_CONTROL0_FDTG_SUPPRESS_PREAMBLE_RESET 0x1 #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_B_ADDR_LSB 9 #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_B_ADDR_MSB 16 #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_B_ADDR_MASK 0x1fe00 #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_B_ADDR_GET(x) (((x) & PHY_BB_FDTG_CONTROL0_FDTG_SS0_B_ADDR_MASK) >> PHY_BB_FDTG_CONTROL0_FDTG_SS0_B_ADDR_LSB) #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_B_ADDR_SET(x) (((0 | (x)) << PHY_BB_FDTG_CONTROL0_FDTG_SS0_B_ADDR_LSB) & PHY_BB_FDTG_CONTROL0_FDTG_SS0_B_ADDR_MASK) #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_B_ADDR_RESET 0x0 #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_A_ADDR_LSB 1 #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_A_ADDR_MSB 8 #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_A_ADDR_MASK 0x1fe #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_A_ADDR_GET(x) (((x) & PHY_BB_FDTG_CONTROL0_FDTG_SS0_A_ADDR_MASK) >> PHY_BB_FDTG_CONTROL0_FDTG_SS0_A_ADDR_LSB) #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_A_ADDR_SET(x) (((0 | (x)) << PHY_BB_FDTG_CONTROL0_FDTG_SS0_A_ADDR_LSB) & PHY_BB_FDTG_CONTROL0_FDTG_SS0_A_ADDR_MASK) #define PHY_BB_FDTG_CONTROL0_FDTG_SS0_A_ADDR_RESET 0x0 #define PHY_BB_FDTG_CONTROL0_FDTG_ENABLE_LSB 0 #define PHY_BB_FDTG_CONTROL0_FDTG_ENABLE_MSB 0 #define PHY_BB_FDTG_CONTROL0_FDTG_ENABLE_MASK 0x1 #define PHY_BB_FDTG_CONTROL0_FDTG_ENABLE_GET(x) (((x) & PHY_BB_FDTG_CONTROL0_FDTG_ENABLE_MASK) >> PHY_BB_FDTG_CONTROL0_FDTG_ENABLE_LSB) #define PHY_BB_FDTG_CONTROL0_FDTG_ENABLE_SET(x) (((0 | (x)) << PHY_BB_FDTG_CONTROL0_FDTG_ENABLE_LSB) & PHY_BB_FDTG_CONTROL0_FDTG_ENABLE_MASK) #define PHY_BB_FDTG_CONTROL0_FDTG_ENABLE_RESET 0x0 #define PHY_BB_FDTG_CONTROL0_ADDRESS (0x148 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_CONTROL0_RSTMASK 0x3ffff #define PHY_BB_FDTG_CONTROL0_RESET 0x20000 // 0x14c (PHY_BB_FDTG_CONTROL1) #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_B_ADDR_LSB 24 #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_B_ADDR_MSB 31 #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_B_ADDR_MASK 0xff000000 #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_B_ADDR_GET(x) (((x) & PHY_BB_FDTG_CONTROL1_FDTG_SS2_B_ADDR_MASK) >> PHY_BB_FDTG_CONTROL1_FDTG_SS2_B_ADDR_LSB) #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_B_ADDR_SET(x) (((0 | (x)) << PHY_BB_FDTG_CONTROL1_FDTG_SS2_B_ADDR_LSB) & PHY_BB_FDTG_CONTROL1_FDTG_SS2_B_ADDR_MASK) #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_B_ADDR_RESET 0x0 #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_A_ADDR_LSB 16 #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_A_ADDR_MSB 23 #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_A_ADDR_MASK 0xff0000 #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_A_ADDR_GET(x) (((x) & PHY_BB_FDTG_CONTROL1_FDTG_SS2_A_ADDR_MASK) >> PHY_BB_FDTG_CONTROL1_FDTG_SS2_A_ADDR_LSB) #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_A_ADDR_SET(x) (((0 | (x)) << PHY_BB_FDTG_CONTROL1_FDTG_SS2_A_ADDR_LSB) & PHY_BB_FDTG_CONTROL1_FDTG_SS2_A_ADDR_MASK) #define PHY_BB_FDTG_CONTROL1_FDTG_SS2_A_ADDR_RESET 0x0 #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_B_ADDR_LSB 8 #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_B_ADDR_MSB 15 #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_B_ADDR_MASK 0xff00 #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_B_ADDR_GET(x) (((x) & PHY_BB_FDTG_CONTROL1_FDTG_SS1_B_ADDR_MASK) >> PHY_BB_FDTG_CONTROL1_FDTG_SS1_B_ADDR_LSB) #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_B_ADDR_SET(x) (((0 | (x)) << PHY_BB_FDTG_CONTROL1_FDTG_SS1_B_ADDR_LSB) & PHY_BB_FDTG_CONTROL1_FDTG_SS1_B_ADDR_MASK) #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_B_ADDR_RESET 0x0 #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_A_ADDR_LSB 0 #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_A_ADDR_MSB 7 #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_A_ADDR_MASK 0xff #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_A_ADDR_GET(x) (((x) & PHY_BB_FDTG_CONTROL1_FDTG_SS1_A_ADDR_MASK) >> PHY_BB_FDTG_CONTROL1_FDTG_SS1_A_ADDR_LSB) #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_A_ADDR_SET(x) (((0 | (x)) << PHY_BB_FDTG_CONTROL1_FDTG_SS1_A_ADDR_LSB) & PHY_BB_FDTG_CONTROL1_FDTG_SS1_A_ADDR_MASK) #define PHY_BB_FDTG_CONTROL1_FDTG_SS1_A_ADDR_RESET 0x0 #define PHY_BB_FDTG_CONTROL1_ADDRESS (0x14c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_CONTROL1_RSTMASK 0xffffffff #define PHY_BB_FDTG_CONTROL1_RESET 0x0 // 0x150 (PHY_BB_FDTG_SS0_DATA_B0) #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_IM_0_LSB 24 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_IM_0_MSB 31 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_IM_0_MASK 0xff000000 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_IM_0_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_IM_0_MASK) >> PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_IM_0_LSB) #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_IM_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_IM_0_LSB) & PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_IM_0_MASK) #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_IM_0_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_RE_0_LSB 16 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_RE_0_MSB 23 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_RE_0_MASK 0xff0000 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_RE_0_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_RE_0_MASK) >> PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_RE_0_LSB) #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_RE_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_RE_0_LSB) & PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_RE_0_MASK) #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_B_DATA_RE_0_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_IM_0_LSB 8 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_IM_0_MSB 15 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_IM_0_MASK 0xff00 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_IM_0_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_IM_0_MASK) >> PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_IM_0_LSB) #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_IM_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_IM_0_LSB) & PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_IM_0_MASK) #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_IM_0_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_RE_0_LSB 0 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_RE_0_MSB 7 #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_RE_0_MASK 0xff #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_RE_0_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_RE_0_MASK) >> PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_RE_0_LSB) #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_RE_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_RE_0_LSB) & PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_RE_0_MASK) #define PHY_BB_FDTG_SS0_DATA_B0_FDTG_SS0_A_DATA_RE_0_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B0_ADDRESS (0x150 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS0_DATA_B0_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS0_DATA_B0_RESET 0x0 // 0x154 (PHY_BB_FDTG_SS1_DATA_B0) #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_IM_0_LSB 24 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_IM_0_MSB 31 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_IM_0_MASK 0xff000000 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_IM_0_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_IM_0_MASK) >> PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_IM_0_LSB) #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_IM_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_IM_0_LSB) & PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_IM_0_MASK) #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_IM_0_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_RE_0_LSB 16 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_RE_0_MSB 23 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_RE_0_MASK 0xff0000 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_RE_0_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_RE_0_MASK) >> PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_RE_0_LSB) #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_RE_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_RE_0_LSB) & PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_RE_0_MASK) #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_B_DATA_RE_0_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_IM_0_LSB 8 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_IM_0_MSB 15 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_IM_0_MASK 0xff00 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_IM_0_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_IM_0_MASK) >> PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_IM_0_LSB) #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_IM_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_IM_0_LSB) & PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_IM_0_MASK) #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_IM_0_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_RE_0_LSB 0 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_RE_0_MSB 7 #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_RE_0_MASK 0xff #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_RE_0_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_RE_0_MASK) >> PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_RE_0_LSB) #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_RE_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_RE_0_LSB) & PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_RE_0_MASK) #define PHY_BB_FDTG_SS1_DATA_B0_FDTG_SS1_A_DATA_RE_0_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B0_ADDRESS (0x154 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS1_DATA_B0_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS1_DATA_B0_RESET 0x0 // 0x158 (PHY_BB_FDTG_SS2_DATA_B0) #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_IM_0_LSB 24 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_IM_0_MSB 31 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_IM_0_MASK 0xff000000 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_IM_0_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_IM_0_MASK) >> PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_IM_0_LSB) #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_IM_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_IM_0_LSB) & PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_IM_0_MASK) #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_IM_0_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_RE_0_LSB 16 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_RE_0_MSB 23 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_RE_0_MASK 0xff0000 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_RE_0_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_RE_0_MASK) >> PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_RE_0_LSB) #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_RE_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_RE_0_LSB) & PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_RE_0_MASK) #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_B_DATA_RE_0_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_IM_0_LSB 8 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_IM_0_MSB 15 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_IM_0_MASK 0xff00 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_IM_0_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_IM_0_MASK) >> PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_IM_0_LSB) #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_IM_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_IM_0_LSB) & PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_IM_0_MASK) #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_IM_0_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_RE_0_LSB 0 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_RE_0_MSB 7 #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_RE_0_MASK 0xff #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_RE_0_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_RE_0_MASK) >> PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_RE_0_LSB) #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_RE_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_RE_0_LSB) & PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_RE_0_MASK) #define PHY_BB_FDTG_SS2_DATA_B0_FDTG_SS2_A_DATA_RE_0_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B0_ADDRESS (0x158 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS2_DATA_B0_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS2_DATA_B0_RESET 0x0 // 0x15c (PHY_BB_PAPRD_AM2AM_MASK2) #define PHY_BB_PAPRD_AM2AM_MASK2_PAPRD_AM2AM_MASK2_LSB 0 #define PHY_BB_PAPRD_AM2AM_MASK2_PAPRD_AM2AM_MASK2_MSB 9 #define PHY_BB_PAPRD_AM2AM_MASK2_PAPRD_AM2AM_MASK2_MASK 0x3ff #define PHY_BB_PAPRD_AM2AM_MASK2_PAPRD_AM2AM_MASK2_GET(x) (((x) & PHY_BB_PAPRD_AM2AM_MASK2_PAPRD_AM2AM_MASK2_MASK) >> PHY_BB_PAPRD_AM2AM_MASK2_PAPRD_AM2AM_MASK2_LSB) #define PHY_BB_PAPRD_AM2AM_MASK2_PAPRD_AM2AM_MASK2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_AM2AM_MASK2_PAPRD_AM2AM_MASK2_LSB) & PHY_BB_PAPRD_AM2AM_MASK2_PAPRD_AM2AM_MASK2_MASK) #define PHY_BB_PAPRD_AM2AM_MASK2_PAPRD_AM2AM_MASK2_RESET 0x0 #define PHY_BB_PAPRD_AM2AM_MASK2_ADDRESS (0x15c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_AM2AM_MASK2_RSTMASK 0x3ff #define PHY_BB_PAPRD_AM2AM_MASK2_RESET 0x0 // 0x160 (PHY_BB_PAPRD_AM2PM_MASK2) #define PHY_BB_PAPRD_AM2PM_MASK2_PAPRD_AM2PM_MASK2_LSB 0 #define PHY_BB_PAPRD_AM2PM_MASK2_PAPRD_AM2PM_MASK2_MSB 9 #define PHY_BB_PAPRD_AM2PM_MASK2_PAPRD_AM2PM_MASK2_MASK 0x3ff #define PHY_BB_PAPRD_AM2PM_MASK2_PAPRD_AM2PM_MASK2_GET(x) (((x) & PHY_BB_PAPRD_AM2PM_MASK2_PAPRD_AM2PM_MASK2_MASK) >> PHY_BB_PAPRD_AM2PM_MASK2_PAPRD_AM2PM_MASK2_LSB) #define PHY_BB_PAPRD_AM2PM_MASK2_PAPRD_AM2PM_MASK2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_AM2PM_MASK2_PAPRD_AM2PM_MASK2_LSB) & PHY_BB_PAPRD_AM2PM_MASK2_PAPRD_AM2PM_MASK2_MASK) #define PHY_BB_PAPRD_AM2PM_MASK2_PAPRD_AM2PM_MASK2_RESET 0x0 #define PHY_BB_PAPRD_AM2PM_MASK2_ADDRESS (0x160 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_AM2PM_MASK2_RSTMASK 0x3ff #define PHY_BB_PAPRD_AM2PM_MASK2_RESET 0x0 // 0x164 (PHY_BB_PAPRD_HT40_MASK2) #define PHY_BB_PAPRD_HT40_MASK2_PAPRD_HT40_MASK2_LSB 0 #define PHY_BB_PAPRD_HT40_MASK2_PAPRD_HT40_MASK2_MSB 9 #define PHY_BB_PAPRD_HT40_MASK2_PAPRD_HT40_MASK2_MASK 0x3ff #define PHY_BB_PAPRD_HT40_MASK2_PAPRD_HT40_MASK2_GET(x) (((x) & PHY_BB_PAPRD_HT40_MASK2_PAPRD_HT40_MASK2_MASK) >> PHY_BB_PAPRD_HT40_MASK2_PAPRD_HT40_MASK2_LSB) #define PHY_BB_PAPRD_HT40_MASK2_PAPRD_HT40_MASK2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_HT40_MASK2_PAPRD_HT40_MASK2_LSB) & PHY_BB_PAPRD_HT40_MASK2_PAPRD_HT40_MASK2_MASK) #define PHY_BB_PAPRD_HT40_MASK2_PAPRD_HT40_MASK2_RESET 0x0 #define PHY_BB_PAPRD_HT40_MASK2_ADDRESS (0x164 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_HT40_MASK2_RSTMASK 0x3ff #define PHY_BB_PAPRD_HT40_MASK2_RESET 0x0 // 0x168 (PHY_BB_PAPRD_VHT80_MASK2) #define PHY_BB_PAPRD_VHT80_MASK2_PAPRD_VHT80_MASK2_LSB 0 #define PHY_BB_PAPRD_VHT80_MASK2_PAPRD_VHT80_MASK2_MSB 9 #define PHY_BB_PAPRD_VHT80_MASK2_PAPRD_VHT80_MASK2_MASK 0x3ff #define PHY_BB_PAPRD_VHT80_MASK2_PAPRD_VHT80_MASK2_GET(x) (((x) & PHY_BB_PAPRD_VHT80_MASK2_PAPRD_VHT80_MASK2_MASK) >> PHY_BB_PAPRD_VHT80_MASK2_PAPRD_VHT80_MASK2_LSB) #define PHY_BB_PAPRD_VHT80_MASK2_PAPRD_VHT80_MASK2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_VHT80_MASK2_PAPRD_VHT80_MASK2_LSB) & PHY_BB_PAPRD_VHT80_MASK2_PAPRD_VHT80_MASK2_MASK) #define PHY_BB_PAPRD_VHT80_MASK2_PAPRD_VHT80_MASK2_RESET 0x0 #define PHY_BB_PAPRD_VHT80_MASK2_ADDRESS (0x168 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_VHT80_MASK2_RSTMASK 0x3ff #define PHY_BB_PAPRD_VHT80_MASK2_RESET 0x0 // 0x16c (PHY_BB_SPUR_CTRL1_PRI_B0) #define PHY_BB_SPUR_CTRL1_PRI_B0_ENABLE_SPUR_FILTER_PRI_B0_LSB 30 #define PHY_BB_SPUR_CTRL1_PRI_B0_ENABLE_SPUR_FILTER_PRI_B0_MSB 31 #define PHY_BB_SPUR_CTRL1_PRI_B0_ENABLE_SPUR_FILTER_PRI_B0_MASK 0xc0000000 #define PHY_BB_SPUR_CTRL1_PRI_B0_ENABLE_SPUR_FILTER_PRI_B0_GET(x) (((x) & PHY_BB_SPUR_CTRL1_PRI_B0_ENABLE_SPUR_FILTER_PRI_B0_MASK) >> PHY_BB_SPUR_CTRL1_PRI_B0_ENABLE_SPUR_FILTER_PRI_B0_LSB) #define PHY_BB_SPUR_CTRL1_PRI_B0_ENABLE_SPUR_FILTER_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_PRI_B0_ENABLE_SPUR_FILTER_PRI_B0_LSB) & PHY_BB_SPUR_CTRL1_PRI_B0_ENABLE_SPUR_FILTER_PRI_B0_MASK) #define PHY_BB_SPUR_CTRL1_PRI_B0_ENABLE_SPUR_FILTER_PRI_B0_RESET 0x0 #define PHY_BB_SPUR_CTRL1_PRI_B0_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B0_LSB 29 #define PHY_BB_SPUR_CTRL1_PRI_B0_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B0_MSB 29 #define PHY_BB_SPUR_CTRL1_PRI_B0_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B0_MASK 0x20000000 #define PHY_BB_SPUR_CTRL1_PRI_B0_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B0_GET(x) (((x) & PHY_BB_SPUR_CTRL1_PRI_B0_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B0_MASK) >> PHY_BB_SPUR_CTRL1_PRI_B0_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B0_LSB) #define PHY_BB_SPUR_CTRL1_PRI_B0_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_PRI_B0_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B0_LSB) & PHY_BB_SPUR_CTRL1_PRI_B0_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B0_MASK) #define PHY_BB_SPUR_CTRL1_PRI_B0_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B0_RESET 0x1 #define PHY_BB_SPUR_CTRL1_PRI_B0_SPUR_DELTA_PHASE_PRI_B0_LSB 0 #define PHY_BB_SPUR_CTRL1_PRI_B0_SPUR_DELTA_PHASE_PRI_B0_MSB 19 #define PHY_BB_SPUR_CTRL1_PRI_B0_SPUR_DELTA_PHASE_PRI_B0_MASK 0xfffff #define PHY_BB_SPUR_CTRL1_PRI_B0_SPUR_DELTA_PHASE_PRI_B0_GET(x) (((x) & PHY_BB_SPUR_CTRL1_PRI_B0_SPUR_DELTA_PHASE_PRI_B0_MASK) >> PHY_BB_SPUR_CTRL1_PRI_B0_SPUR_DELTA_PHASE_PRI_B0_LSB) #define PHY_BB_SPUR_CTRL1_PRI_B0_SPUR_DELTA_PHASE_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_PRI_B0_SPUR_DELTA_PHASE_PRI_B0_LSB) & PHY_BB_SPUR_CTRL1_PRI_B0_SPUR_DELTA_PHASE_PRI_B0_MASK) #define PHY_BB_SPUR_CTRL1_PRI_B0_SPUR_DELTA_PHASE_PRI_B0_RESET 0x0 #define PHY_BB_SPUR_CTRL1_PRI_B0_ADDRESS (0x16c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_CTRL1_PRI_B0_RSTMASK 0xe00fffff #define PHY_BB_SPUR_CTRL1_PRI_B0_RESET 0x20000000 // 0x170 (PHY_BB_SPUR_CTRL2_PRI_B0) #define PHY_BB_SPUR_CTRL2_PRI_B0_SPUR_DELTA_PHASE_2ND_PRI_B0_LSB 0 #define PHY_BB_SPUR_CTRL2_PRI_B0_SPUR_DELTA_PHASE_2ND_PRI_B0_MSB 19 #define PHY_BB_SPUR_CTRL2_PRI_B0_SPUR_DELTA_PHASE_2ND_PRI_B0_MASK 0xfffff #define PHY_BB_SPUR_CTRL2_PRI_B0_SPUR_DELTA_PHASE_2ND_PRI_B0_GET(x) (((x) & PHY_BB_SPUR_CTRL2_PRI_B0_SPUR_DELTA_PHASE_2ND_PRI_B0_MASK) >> PHY_BB_SPUR_CTRL2_PRI_B0_SPUR_DELTA_PHASE_2ND_PRI_B0_LSB) #define PHY_BB_SPUR_CTRL2_PRI_B0_SPUR_DELTA_PHASE_2ND_PRI_B0_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL2_PRI_B0_SPUR_DELTA_PHASE_2ND_PRI_B0_LSB) & PHY_BB_SPUR_CTRL2_PRI_B0_SPUR_DELTA_PHASE_2ND_PRI_B0_MASK) #define PHY_BB_SPUR_CTRL2_PRI_B0_SPUR_DELTA_PHASE_2ND_PRI_B0_RESET 0x0 #define PHY_BB_SPUR_CTRL2_PRI_B0_ADDRESS (0x170 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_CTRL2_PRI_B0_RSTMASK 0xfffff #define PHY_BB_SPUR_CTRL2_PRI_B0_RESET 0x0 // 0x174 (PHY_BB_SPUR_CTRL1_EXT_B0) #define PHY_BB_SPUR_CTRL1_EXT_B0_ENABLE_SPUR_FILTER_EXT_B0_LSB 30 #define PHY_BB_SPUR_CTRL1_EXT_B0_ENABLE_SPUR_FILTER_EXT_B0_MSB 31 #define PHY_BB_SPUR_CTRL1_EXT_B0_ENABLE_SPUR_FILTER_EXT_B0_MASK 0xc0000000 #define PHY_BB_SPUR_CTRL1_EXT_B0_ENABLE_SPUR_FILTER_EXT_B0_GET(x) (((x) & PHY_BB_SPUR_CTRL1_EXT_B0_ENABLE_SPUR_FILTER_EXT_B0_MASK) >> PHY_BB_SPUR_CTRL1_EXT_B0_ENABLE_SPUR_FILTER_EXT_B0_LSB) #define PHY_BB_SPUR_CTRL1_EXT_B0_ENABLE_SPUR_FILTER_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_EXT_B0_ENABLE_SPUR_FILTER_EXT_B0_LSB) & PHY_BB_SPUR_CTRL1_EXT_B0_ENABLE_SPUR_FILTER_EXT_B0_MASK) #define PHY_BB_SPUR_CTRL1_EXT_B0_ENABLE_SPUR_FILTER_EXT_B0_RESET 0x0 #define PHY_BB_SPUR_CTRL1_EXT_B0_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B0_LSB 29 #define PHY_BB_SPUR_CTRL1_EXT_B0_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B0_MSB 29 #define PHY_BB_SPUR_CTRL1_EXT_B0_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B0_MASK 0x20000000 #define PHY_BB_SPUR_CTRL1_EXT_B0_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B0_GET(x) (((x) & PHY_BB_SPUR_CTRL1_EXT_B0_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B0_MASK) >> PHY_BB_SPUR_CTRL1_EXT_B0_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B0_LSB) #define PHY_BB_SPUR_CTRL1_EXT_B0_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_EXT_B0_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B0_LSB) & PHY_BB_SPUR_CTRL1_EXT_B0_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B0_MASK) #define PHY_BB_SPUR_CTRL1_EXT_B0_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B0_RESET 0x1 #define PHY_BB_SPUR_CTRL1_EXT_B0_SPUR_DELTA_PHASE_EXT_B0_LSB 0 #define PHY_BB_SPUR_CTRL1_EXT_B0_SPUR_DELTA_PHASE_EXT_B0_MSB 19 #define PHY_BB_SPUR_CTRL1_EXT_B0_SPUR_DELTA_PHASE_EXT_B0_MASK 0xfffff #define PHY_BB_SPUR_CTRL1_EXT_B0_SPUR_DELTA_PHASE_EXT_B0_GET(x) (((x) & PHY_BB_SPUR_CTRL1_EXT_B0_SPUR_DELTA_PHASE_EXT_B0_MASK) >> PHY_BB_SPUR_CTRL1_EXT_B0_SPUR_DELTA_PHASE_EXT_B0_LSB) #define PHY_BB_SPUR_CTRL1_EXT_B0_SPUR_DELTA_PHASE_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_EXT_B0_SPUR_DELTA_PHASE_EXT_B0_LSB) & PHY_BB_SPUR_CTRL1_EXT_B0_SPUR_DELTA_PHASE_EXT_B0_MASK) #define PHY_BB_SPUR_CTRL1_EXT_B0_SPUR_DELTA_PHASE_EXT_B0_RESET 0x0 #define PHY_BB_SPUR_CTRL1_EXT_B0_ADDRESS (0x174 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_CTRL1_EXT_B0_RSTMASK 0xe00fffff #define PHY_BB_SPUR_CTRL1_EXT_B0_RESET 0x20000000 // 0x178 (PHY_BB_SPUR_CTRL2_EXT_B0) #define PHY_BB_SPUR_CTRL2_EXT_B0_SPUR_DELTA_PHASE_2ND_EXT_B0_LSB 0 #define PHY_BB_SPUR_CTRL2_EXT_B0_SPUR_DELTA_PHASE_2ND_EXT_B0_MSB 19 #define PHY_BB_SPUR_CTRL2_EXT_B0_SPUR_DELTA_PHASE_2ND_EXT_B0_MASK 0xfffff #define PHY_BB_SPUR_CTRL2_EXT_B0_SPUR_DELTA_PHASE_2ND_EXT_B0_GET(x) (((x) & PHY_BB_SPUR_CTRL2_EXT_B0_SPUR_DELTA_PHASE_2ND_EXT_B0_MASK) >> PHY_BB_SPUR_CTRL2_EXT_B0_SPUR_DELTA_PHASE_2ND_EXT_B0_LSB) #define PHY_BB_SPUR_CTRL2_EXT_B0_SPUR_DELTA_PHASE_2ND_EXT_B0_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL2_EXT_B0_SPUR_DELTA_PHASE_2ND_EXT_B0_LSB) & PHY_BB_SPUR_CTRL2_EXT_B0_SPUR_DELTA_PHASE_2ND_EXT_B0_MASK) #define PHY_BB_SPUR_CTRL2_EXT_B0_SPUR_DELTA_PHASE_2ND_EXT_B0_RESET 0x0 #define PHY_BB_SPUR_CTRL2_EXT_B0_ADDRESS (0x178 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_CTRL2_EXT_B0_RSTMASK 0xfffff #define PHY_BB_SPUR_CTRL2_EXT_B0_RESET 0x0 // 0x17c (PHY_BB_FDTG_SS3_DATA_B0) #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_IM_0_LSB 24 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_IM_0_MSB 31 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_IM_0_MASK 0xff000000 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_IM_0_GET(x) (((x) & PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_IM_0_MASK) >> PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_IM_0_LSB) #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_IM_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_IM_0_LSB) & PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_IM_0_MASK) #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_IM_0_RESET 0x0 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_RE_0_LSB 16 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_RE_0_MSB 23 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_RE_0_MASK 0xff0000 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_RE_0_GET(x) (((x) & PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_RE_0_MASK) >> PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_RE_0_LSB) #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_RE_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_RE_0_LSB) & PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_RE_0_MASK) #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_B_DATA_RE_0_RESET 0x0 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_IM_0_LSB 8 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_IM_0_MSB 15 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_IM_0_MASK 0xff00 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_IM_0_GET(x) (((x) & PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_IM_0_MASK) >> PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_IM_0_LSB) #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_IM_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_IM_0_LSB) & PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_IM_0_MASK) #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_IM_0_RESET 0x0 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_RE_0_LSB 0 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_RE_0_MSB 7 #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_RE_0_MASK 0xff #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_RE_0_GET(x) (((x) & PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_RE_0_MASK) >> PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_RE_0_LSB) #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_RE_0_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_RE_0_LSB) & PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_RE_0_MASK) #define PHY_BB_FDTG_SS3_DATA_B0_FDTG_SS3_A_DATA_RE_0_RESET 0x0 #define PHY_BB_FDTG_SS3_DATA_B0_ADDRESS (0x17c + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS3_DATA_B0_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS3_DATA_B0_RESET 0x0 // 0x180 (PHY_BB_FDTG_CONTROL2) #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_B_ADDR_LSB 8 #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_B_ADDR_MSB 15 #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_B_ADDR_MASK 0xff00 #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_B_ADDR_GET(x) (((x) & PHY_BB_FDTG_CONTROL2_FDTG_SS3_B_ADDR_MASK) >> PHY_BB_FDTG_CONTROL2_FDTG_SS3_B_ADDR_LSB) #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_B_ADDR_SET(x) (((0 | (x)) << PHY_BB_FDTG_CONTROL2_FDTG_SS3_B_ADDR_LSB) & PHY_BB_FDTG_CONTROL2_FDTG_SS3_B_ADDR_MASK) #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_B_ADDR_RESET 0x0 #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_A_ADDR_LSB 0 #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_A_ADDR_MSB 7 #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_A_ADDR_MASK 0xff #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_A_ADDR_GET(x) (((x) & PHY_BB_FDTG_CONTROL2_FDTG_SS3_A_ADDR_MASK) >> PHY_BB_FDTG_CONTROL2_FDTG_SS3_A_ADDR_LSB) #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_A_ADDR_SET(x) (((0 | (x)) << PHY_BB_FDTG_CONTROL2_FDTG_SS3_A_ADDR_LSB) & PHY_BB_FDTG_CONTROL2_FDTG_SS3_A_ADDR_MASK) #define PHY_BB_FDTG_CONTROL2_FDTG_SS3_A_ADDR_RESET 0x0 #define PHY_BB_FDTG_CONTROL2_ADDRESS (0x180 + __PHY_CHN_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_CONTROL2_RSTMASK 0xffff #define PHY_BB_FDTG_CONTROL2_RESET 0x0 #endif /* _PHY_CHN_REG_MAP_H_ */