// // ----------------------------------------------------------------------------- // Copyright (c) 2011-2014 Qualcomm Atheros, Inc. All rights reserved. // ----------------------------------------------------------------------------- // FILE : chn5_syn_reg_csr.h // DESCRIPTION : Software Header File for WiFi 2.5 // THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT // ----------------------------------------------------------------------------- // #ifndef _CHN5_SYN_REG_CSR_H_ #define _CHN5_SYN_REG_CSR_H_ #ifndef __CHN5_SYN_REG_CSR_BASE_ADDRESS #define __CHN5_SYN_REG_CSR_BASE_ADDRESS (0x47740) #endif // 0x0 (CHN5_SYN_N_REG) #define CHN5_SYN_N_REG_NBNA_LSB 24 #define CHN5_SYN_N_REG_NBNA_MSB 31 #define CHN5_SYN_N_REG_NBNA_MASK 0xff000000 #define CHN5_SYN_N_REG_NBNA_GET(x) (((x) & CHN5_SYN_N_REG_NBNA_MASK) >> CHN5_SYN_N_REG_NBNA_LSB) #define CHN5_SYN_N_REG_NBNA_SET(x) (((0 | (x)) << CHN5_SYN_N_REG_NBNA_LSB) & CHN5_SYN_N_REG_NBNA_MASK) #define CHN5_SYN_N_REG_NBNA_RESET 0x13 #define CHN5_SYN_N_REG_NF_LSB 1 #define CHN5_SYN_N_REG_NF_MSB 23 #define CHN5_SYN_N_REG_NF_MASK 0xfffffe #define CHN5_SYN_N_REG_NF_GET(x) (((x) & CHN5_SYN_N_REG_NF_MASK) >> CHN5_SYN_N_REG_NF_LSB) #define CHN5_SYN_N_REG_NF_SET(x) (((0 | (x)) << CHN5_SYN_N_REG_NF_LSB) & CHN5_SYN_N_REG_NF_MASK) #define CHN5_SYN_N_REG_NF_RESET 0xc7127 #define CHN5_SYN_N_REG_NF_LSB_LSB 0 #define CHN5_SYN_N_REG_NF_LSB_MSB 0 #define CHN5_SYN_N_REG_NF_LSB_MASK 0x1 #define CHN5_SYN_N_REG_NF_LSB_GET(x) (((x) & CHN5_SYN_N_REG_NF_LSB_MASK) >> CHN5_SYN_N_REG_NF_LSB_LSB) #define CHN5_SYN_N_REG_NF_LSB_SET(x) (((0 | (x)) << CHN5_SYN_N_REG_NF_LSB_LSB) & CHN5_SYN_N_REG_NF_LSB_MASK) #define CHN5_SYN_N_REG_NF_LSB_RESET 0x0 #define CHN5_SYN_N_REG_ADDRESS (0x0 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_N_REG_RSTMASK 0xffffffff #define CHN5_SYN_N_REG_RESET 0x1318e24e // 0x4 (CHN5_SYN_BS_0) #define CHN5_SYN_BS_0_BSSTART_LSB 31 #define CHN5_SYN_BS_0_BSSTART_MSB 31 #define CHN5_SYN_BS_0_BSSTART_MASK 0x80000000 #define CHN5_SYN_BS_0_BSSTART_GET(x) (((x) & CHN5_SYN_BS_0_BSSTART_MASK) >> CHN5_SYN_BS_0_BSSTART_LSB) #define CHN5_SYN_BS_0_BSSTART_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSSTART_LSB) & CHN5_SYN_BS_0_BSSTART_MASK) #define CHN5_SYN_BS_0_BSSTART_RESET 0x0 #define CHN5_SYN_BS_0_BSMODE_LSB 28 #define CHN5_SYN_BS_0_BSMODE_MSB 30 #define CHN5_SYN_BS_0_BSMODE_MASK 0x70000000 #define CHN5_SYN_BS_0_BSMODE_GET(x) (((x) & CHN5_SYN_BS_0_BSMODE_MASK) >> CHN5_SYN_BS_0_BSMODE_LSB) #define CHN5_SYN_BS_0_BSMODE_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSMODE_LSB) & CHN5_SYN_BS_0_BSMODE_MASK) #define CHN5_SYN_BS_0_BSMODE_RESET 0x0 #define CHN5_SYN_BS_0_BKSHFT_LSB 26 #define CHN5_SYN_BS_0_BKSHFT_MSB 27 #define CHN5_SYN_BS_0_BKSHFT_MASK 0xc000000 #define CHN5_SYN_BS_0_BKSHFT_GET(x) (((x) & CHN5_SYN_BS_0_BKSHFT_MASK) >> CHN5_SYN_BS_0_BKSHFT_LSB) #define CHN5_SYN_BS_0_BKSHFT_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BKSHFT_LSB) & CHN5_SYN_BS_0_BKSHFT_MASK) #define CHN5_SYN_BS_0_BKSHFT_RESET 0x0 #define CHN5_SYN_BS_0_BSWAIT_LSB 23 #define CHN5_SYN_BS_0_BSWAIT_MSB 25 #define CHN5_SYN_BS_0_BSWAIT_MASK 0x3800000 #define CHN5_SYN_BS_0_BSWAIT_GET(x) (((x) & CHN5_SYN_BS_0_BSWAIT_MASK) >> CHN5_SYN_BS_0_BSWAIT_LSB) #define CHN5_SYN_BS_0_BSWAIT_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSWAIT_LSB) & CHN5_SYN_BS_0_BSWAIT_MASK) #define CHN5_SYN_BS_0_BSWAIT_RESET 0x1 #define CHN5_SYN_BS_0_BSSAMPLE_LSB 20 #define CHN5_SYN_BS_0_BSSAMPLE_MSB 22 #define CHN5_SYN_BS_0_BSSAMPLE_MASK 0x700000 #define CHN5_SYN_BS_0_BSSAMPLE_GET(x) (((x) & CHN5_SYN_BS_0_BSSAMPLE_MASK) >> CHN5_SYN_BS_0_BSSAMPLE_LSB) #define CHN5_SYN_BS_0_BSSAMPLE_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSSAMPLE_LSB) & CHN5_SYN_BS_0_BSSAMPLE_MASK) #define CHN5_SYN_BS_0_BSSAMPLE_RESET 0x5 #define CHN5_SYN_BS_0_BSSETTIME_LSB 18 #define CHN5_SYN_BS_0_BSSETTIME_MSB 19 #define CHN5_SYN_BS_0_BSSETTIME_MASK 0xc0000 #define CHN5_SYN_BS_0_BSSETTIME_GET(x) (((x) & CHN5_SYN_BS_0_BSSETTIME_MASK) >> CHN5_SYN_BS_0_BSSETTIME_LSB) #define CHN5_SYN_BS_0_BSSETTIME_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSSETTIME_LSB) & CHN5_SYN_BS_0_BSSETTIME_MASK) #define CHN5_SYN_BS_0_BSSETTIME_RESET 0x1 #define CHN5_SYN_BS_0_BSFAST_MSB_0_LSB 16 #define CHN5_SYN_BS_0_BSFAST_MSB_0_MSB 17 #define CHN5_SYN_BS_0_BSFAST_MSB_0_MASK 0x30000 #define CHN5_SYN_BS_0_BSFAST_MSB_0_GET(x) (((x) & CHN5_SYN_BS_0_BSFAST_MSB_0_MASK) >> CHN5_SYN_BS_0_BSFAST_MSB_0_LSB) #define CHN5_SYN_BS_0_BSFAST_MSB_0_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSFAST_MSB_0_LSB) & CHN5_SYN_BS_0_BSFAST_MSB_0_MASK) #define CHN5_SYN_BS_0_BSFAST_MSB_0_RESET 0x1 #define CHN5_SYN_BS_0_BSFAST_MSB_1_LSB 14 #define CHN5_SYN_BS_0_BSFAST_MSB_1_MSB 15 #define CHN5_SYN_BS_0_BSFAST_MSB_1_MASK 0xc000 #define CHN5_SYN_BS_0_BSFAST_MSB_1_GET(x) (((x) & CHN5_SYN_BS_0_BSFAST_MSB_1_MASK) >> CHN5_SYN_BS_0_BSFAST_MSB_1_LSB) #define CHN5_SYN_BS_0_BSFAST_MSB_1_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSFAST_MSB_1_LSB) & CHN5_SYN_BS_0_BSFAST_MSB_1_MASK) #define CHN5_SYN_BS_0_BSFAST_MSB_1_RESET 0x1 #define CHN5_SYN_BS_0_BSFAST_MSB_2_LSB 12 #define CHN5_SYN_BS_0_BSFAST_MSB_2_MSB 13 #define CHN5_SYN_BS_0_BSFAST_MSB_2_MASK 0x3000 #define CHN5_SYN_BS_0_BSFAST_MSB_2_GET(x) (((x) & CHN5_SYN_BS_0_BSFAST_MSB_2_MASK) >> CHN5_SYN_BS_0_BSFAST_MSB_2_LSB) #define CHN5_SYN_BS_0_BSFAST_MSB_2_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSFAST_MSB_2_LSB) & CHN5_SYN_BS_0_BSFAST_MSB_2_MASK) #define CHN5_SYN_BS_0_BSFAST_MSB_2_RESET 0x2 #define CHN5_SYN_BS_0_BSFAST_LSB_LSB 10 #define CHN5_SYN_BS_0_BSFAST_LSB_MSB 11 #define CHN5_SYN_BS_0_BSFAST_LSB_MASK 0xc00 #define CHN5_SYN_BS_0_BSFAST_LSB_GET(x) (((x) & CHN5_SYN_BS_0_BSFAST_LSB_MASK) >> CHN5_SYN_BS_0_BSFAST_LSB_LSB) #define CHN5_SYN_BS_0_BSFAST_LSB_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSFAST_LSB_LSB) & CHN5_SYN_BS_0_BSFAST_LSB_MASK) #define CHN5_SYN_BS_0_BSFAST_LSB_RESET 0x2 #define CHN5_SYN_BS_0_BSFAST_EN_LSB 9 #define CHN5_SYN_BS_0_BSFAST_EN_MSB 9 #define CHN5_SYN_BS_0_BSFAST_EN_MASK 0x200 #define CHN5_SYN_BS_0_BSFAST_EN_GET(x) (((x) & CHN5_SYN_BS_0_BSFAST_EN_MASK) >> CHN5_SYN_BS_0_BSFAST_EN_LSB) #define CHN5_SYN_BS_0_BSFAST_EN_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSFAST_EN_LSB) & CHN5_SYN_BS_0_BSFAST_EN_MASK) #define CHN5_SYN_BS_0_BSFAST_EN_RESET 0x1 #define CHN5_SYN_BS_0_BSLUT_EN_LSB 8 #define CHN5_SYN_BS_0_BSLUT_EN_MSB 8 #define CHN5_SYN_BS_0_BSLUT_EN_MASK 0x100 #define CHN5_SYN_BS_0_BSLUT_EN_GET(x) (((x) & CHN5_SYN_BS_0_BSLUT_EN_MASK) >> CHN5_SYN_BS_0_BSLUT_EN_LSB) #define CHN5_SYN_BS_0_BSLUT_EN_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSLUT_EN_LSB) & CHN5_SYN_BS_0_BSLUT_EN_MASK) #define CHN5_SYN_BS_0_BSLUT_EN_RESET 0x0 #define CHN5_SYN_BS_0_BSLUT_SMPL_LSB 6 #define CHN5_SYN_BS_0_BSLUT_SMPL_MSB 7 #define CHN5_SYN_BS_0_BSLUT_SMPL_MASK 0xc0 #define CHN5_SYN_BS_0_BSLUT_SMPL_GET(x) (((x) & CHN5_SYN_BS_0_BSLUT_SMPL_MASK) >> CHN5_SYN_BS_0_BSLUT_SMPL_LSB) #define CHN5_SYN_BS_0_BSLUT_SMPL_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSLUT_SMPL_LSB) & CHN5_SYN_BS_0_BSLUT_SMPL_MASK) #define CHN5_SYN_BS_0_BSLUT_SMPL_RESET 0x3 #define CHN5_SYN_BS_0_BSLUT_START_LSB 5 #define CHN5_SYN_BS_0_BSLUT_START_MSB 5 #define CHN5_SYN_BS_0_BSLUT_START_MASK 0x20 #define CHN5_SYN_BS_0_BSLUT_START_GET(x) (((x) & CHN5_SYN_BS_0_BSLUT_START_MASK) >> CHN5_SYN_BS_0_BSLUT_START_LSB) #define CHN5_SYN_BS_0_BSLUT_START_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSLUT_START_LSB) & CHN5_SYN_BS_0_BSLUT_START_MASK) #define CHN5_SYN_BS_0_BSLUT_START_RESET 0x0 #define CHN5_SYN_BS_0_BSLUT_SEL_OVR_LSB 0 #define CHN5_SYN_BS_0_BSLUT_SEL_OVR_MSB 4 #define CHN5_SYN_BS_0_BSLUT_SEL_OVR_MASK 0x1f #define CHN5_SYN_BS_0_BSLUT_SEL_OVR_GET(x) (((x) & CHN5_SYN_BS_0_BSLUT_SEL_OVR_MASK) >> CHN5_SYN_BS_0_BSLUT_SEL_OVR_LSB) #define CHN5_SYN_BS_0_BSLUT_SEL_OVR_SET(x) (((0 | (x)) << CHN5_SYN_BS_0_BSLUT_SEL_OVR_LSB) & CHN5_SYN_BS_0_BSLUT_SEL_OVR_MASK) #define CHN5_SYN_BS_0_BSLUT_SEL_OVR_RESET 0x0 #define CHN5_SYN_BS_0_ADDRESS (0x4 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_BS_0_RSTMASK 0xffffffff #define CHN5_SYN_BS_0_RESET 0xd56ac0 // 0x8 (CHN5_SYN_BS_1) #define CHN5_SYN_BS_1_TSTCNT_LSB 16 #define CHN5_SYN_BS_1_TSTCNT_MSB 31 #define CHN5_SYN_BS_1_TSTCNT_MASK 0xffff0000 #define CHN5_SYN_BS_1_TSTCNT_GET(x) (((x) & CHN5_SYN_BS_1_TSTCNT_MASK) >> CHN5_SYN_BS_1_TSTCNT_LSB) #define CHN5_SYN_BS_1_TSTCNT_SET(x) (((0 | (x)) << CHN5_SYN_BS_1_TSTCNT_LSB) & CHN5_SYN_BS_1_TSTCNT_MASK) #define CHN5_SYN_BS_1_TSTCNT_RESET 0x0 #define CHN5_SYN_BS_1_BSTESTEN_LSB 15 #define CHN5_SYN_BS_1_BSTESTEN_MSB 15 #define CHN5_SYN_BS_1_BSTESTEN_MASK 0x8000 #define CHN5_SYN_BS_1_BSTESTEN_GET(x) (((x) & CHN5_SYN_BS_1_BSTESTEN_MASK) >> CHN5_SYN_BS_1_BSTESTEN_LSB) #define CHN5_SYN_BS_1_BSTESTEN_SET(x) (((0 | (x)) << CHN5_SYN_BS_1_BSTESTEN_LSB) & CHN5_SYN_BS_1_BSTESTEN_MASK) #define CHN5_SYN_BS_1_BSTESTEN_RESET 0x0 #define CHN5_SYN_BS_1_SDTESTEN_LSB 14 #define CHN5_SYN_BS_1_SDTESTEN_MSB 14 #define CHN5_SYN_BS_1_SDTESTEN_MASK 0x4000 #define CHN5_SYN_BS_1_SDTESTEN_GET(x) (((x) & CHN5_SYN_BS_1_SDTESTEN_MASK) >> CHN5_SYN_BS_1_SDTESTEN_LSB) #define CHN5_SYN_BS_1_SDTESTEN_SET(x) (((0 | (x)) << CHN5_SYN_BS_1_SDTESTEN_LSB) & CHN5_SYN_BS_1_SDTESTEN_MASK) #define CHN5_SYN_BS_1_SDTESTEN_RESET 0x0 #define CHN5_SYN_BS_1_SD_RESET_LSB 13 #define CHN5_SYN_BS_1_SD_RESET_MSB 13 #define CHN5_SYN_BS_1_SD_RESET_MASK 0x2000 #define CHN5_SYN_BS_1_SD_RESET_GET(x) (((x) & CHN5_SYN_BS_1_SD_RESET_MASK) >> CHN5_SYN_BS_1_SD_RESET_LSB) #define CHN5_SYN_BS_1_SD_RESET_SET(x) (((0 | (x)) << CHN5_SYN_BS_1_SD_RESET_LSB) & CHN5_SYN_BS_1_SD_RESET_MASK) #define CHN5_SYN_BS_1_SD_RESET_RESET 0x0 #define CHN5_SYN_BS_1_RESERVED_0_LSB 11 #define CHN5_SYN_BS_1_RESERVED_0_MSB 12 #define CHN5_SYN_BS_1_RESERVED_0_MASK 0x1800 #define CHN5_SYN_BS_1_RESERVED_0_GET(x) (((x) & CHN5_SYN_BS_1_RESERVED_0_MASK) >> CHN5_SYN_BS_1_RESERVED_0_LSB) #define CHN5_SYN_BS_1_RESERVED_0_SET(x) (((0 | (x)) << CHN5_SYN_BS_1_RESERVED_0_LSB) & CHN5_SYN_BS_1_RESERVED_0_MASK) #define CHN5_SYN_BS_1_RESERVED_0_RESET 0x0 #define CHN5_SYN_BS_1_IVCOBK_LSB 0 #define CHN5_SYN_BS_1_IVCOBK_MSB 10 #define CHN5_SYN_BS_1_IVCOBK_MASK 0x7ff #define CHN5_SYN_BS_1_IVCOBK_GET(x) (((x) & CHN5_SYN_BS_1_IVCOBK_MASK) >> CHN5_SYN_BS_1_IVCOBK_LSB) #define CHN5_SYN_BS_1_IVCOBK_SET(x) (((0 | (x)) << CHN5_SYN_BS_1_IVCOBK_LSB) & CHN5_SYN_BS_1_IVCOBK_MASK) #define CHN5_SYN_BS_1_IVCOBK_RESET 0x400 #define CHN5_SYN_BS_1_ADDRESS (0x8 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_BS_1_RSTMASK 0xffffffff #define CHN5_SYN_BS_1_RESET 0x400 // 0xc (CHN5_SYN_BS_2) #define CHN5_SYN_BS_2_BSCMP_POL_LSB 31 #define CHN5_SYN_BS_2_BSCMP_POL_MSB 31 #define CHN5_SYN_BS_2_BSCMP_POL_MASK 0x80000000 #define CHN5_SYN_BS_2_BSCMP_POL_GET(x) (((x) & CHN5_SYN_BS_2_BSCMP_POL_MASK) >> CHN5_SYN_BS_2_BSCMP_POL_LSB) #define CHN5_SYN_BS_2_BSCMP_POL_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_BSCMP_POL_LSB) & CHN5_SYN_BS_2_BSCMP_POL_MASK) #define CHN5_SYN_BS_2_BSCMP_POL_RESET 0x1 #define CHN5_SYN_BS_2_BSCMP_EQ_EN_LSB 30 #define CHN5_SYN_BS_2_BSCMP_EQ_EN_MSB 30 #define CHN5_SYN_BS_2_BSCMP_EQ_EN_MASK 0x40000000 #define CHN5_SYN_BS_2_BSCMP_EQ_EN_GET(x) (((x) & CHN5_SYN_BS_2_BSCMP_EQ_EN_MASK) >> CHN5_SYN_BS_2_BSCMP_EQ_EN_LSB) #define CHN5_SYN_BS_2_BSCMP_EQ_EN_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_BSCMP_EQ_EN_LSB) & CHN5_SYN_BS_2_BSCMP_EQ_EN_MASK) #define CHN5_SYN_BS_2_BSCMP_EQ_EN_RESET 0x0 #define CHN5_SYN_BS_2_RFCNTEN_DLY_DIS_LSB 29 #define CHN5_SYN_BS_2_RFCNTEN_DLY_DIS_MSB 29 #define CHN5_SYN_BS_2_RFCNTEN_DLY_DIS_MASK 0x20000000 #define CHN5_SYN_BS_2_RFCNTEN_DLY_DIS_GET(x) (((x) & CHN5_SYN_BS_2_RFCNTEN_DLY_DIS_MASK) >> CHN5_SYN_BS_2_RFCNTEN_DLY_DIS_LSB) #define CHN5_SYN_BS_2_RFCNTEN_DLY_DIS_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_RFCNTEN_DLY_DIS_LSB) & CHN5_SYN_BS_2_RFCNTEN_DLY_DIS_MASK) #define CHN5_SYN_BS_2_RFCNTEN_DLY_DIS_RESET 0x0 #define CHN5_SYN_BS_2_BS_CLBS_EN_LSB 28 #define CHN5_SYN_BS_2_BS_CLBS_EN_MSB 28 #define CHN5_SYN_BS_2_BS_CLBS_EN_MASK 0x10000000 #define CHN5_SYN_BS_2_BS_CLBS_EN_GET(x) (((x) & CHN5_SYN_BS_2_BS_CLBS_EN_MASK) >> CHN5_SYN_BS_2_BS_CLBS_EN_LSB) #define CHN5_SYN_BS_2_BS_CLBS_EN_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_BS_CLBS_EN_LSB) & CHN5_SYN_BS_2_BS_CLBS_EN_MASK) #define CHN5_SYN_BS_2_BS_CLBS_EN_RESET 0x0 #define CHN5_SYN_BS_2_SDM_SEL_LSB 26 #define CHN5_SYN_BS_2_SDM_SEL_MSB 27 #define CHN5_SYN_BS_2_SDM_SEL_MASK 0xc000000 #define CHN5_SYN_BS_2_SDM_SEL_GET(x) (((x) & CHN5_SYN_BS_2_SDM_SEL_MASK) >> CHN5_SYN_BS_2_SDM_SEL_LSB) #define CHN5_SYN_BS_2_SDM_SEL_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_SDM_SEL_LSB) & CHN5_SYN_BS_2_SDM_SEL_MASK) #define CHN5_SYN_BS_2_SDM_SEL_RESET 0x1 #define CHN5_SYN_BS_2_SDMOGAIN_LSB 24 #define CHN5_SYN_BS_2_SDMOGAIN_MSB 25 #define CHN5_SYN_BS_2_SDMOGAIN_MASK 0x3000000 #define CHN5_SYN_BS_2_SDMOGAIN_GET(x) (((x) & CHN5_SYN_BS_2_SDMOGAIN_MASK) >> CHN5_SYN_BS_2_SDMOGAIN_LSB) #define CHN5_SYN_BS_2_SDMOGAIN_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_SDMOGAIN_LSB) & CHN5_SYN_BS_2_SDMOGAIN_MASK) #define CHN5_SYN_BS_2_SDMOGAIN_RESET 0x0 #define CHN5_SYN_BS_2_RFCNT_SEL_BSC_LSB 21 #define CHN5_SYN_BS_2_RFCNT_SEL_BSC_MSB 23 #define CHN5_SYN_BS_2_RFCNT_SEL_BSC_MASK 0xe00000 #define CHN5_SYN_BS_2_RFCNT_SEL_BSC_GET(x) (((x) & CHN5_SYN_BS_2_RFCNT_SEL_BSC_MASK) >> CHN5_SYN_BS_2_RFCNT_SEL_BSC_LSB) #define CHN5_SYN_BS_2_RFCNT_SEL_BSC_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_RFCNT_SEL_BSC_LSB) & CHN5_SYN_BS_2_RFCNT_SEL_BSC_MASK) #define CHN5_SYN_BS_2_RFCNT_SEL_BSC_RESET 0x2 #define CHN5_SYN_BS_2_MULT_NDIVM1_LSB 18 #define CHN5_SYN_BS_2_MULT_NDIVM1_MSB 20 #define CHN5_SYN_BS_2_MULT_NDIVM1_MASK 0x1c0000 #define CHN5_SYN_BS_2_MULT_NDIVM1_GET(x) (((x) & CHN5_SYN_BS_2_MULT_NDIVM1_MASK) >> CHN5_SYN_BS_2_MULT_NDIVM1_LSB) #define CHN5_SYN_BS_2_MULT_NDIVM1_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_MULT_NDIVM1_LSB) & CHN5_SYN_BS_2_MULT_NDIVM1_MASK) #define CHN5_SYN_BS_2_MULT_NDIVM1_RESET 0x1 #define CHN5_SYN_BS_2_MONITOR_DLL_LSB 16 #define CHN5_SYN_BS_2_MONITOR_DLL_MSB 17 #define CHN5_SYN_BS_2_MONITOR_DLL_MASK 0x30000 #define CHN5_SYN_BS_2_MONITOR_DLL_GET(x) (((x) & CHN5_SYN_BS_2_MONITOR_DLL_MASK) >> CHN5_SYN_BS_2_MONITOR_DLL_LSB) #define CHN5_SYN_BS_2_MONITOR_DLL_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_MONITOR_DLL_LSB) & CHN5_SYN_BS_2_MONITOR_DLL_MASK) #define CHN5_SYN_BS_2_MONITOR_DLL_RESET 0x0 #define CHN5_SYN_BS_2_DTEST0_SEL_LSB 12 #define CHN5_SYN_BS_2_DTEST0_SEL_MSB 15 #define CHN5_SYN_BS_2_DTEST0_SEL_MASK 0xf000 #define CHN5_SYN_BS_2_DTEST0_SEL_GET(x) (((x) & CHN5_SYN_BS_2_DTEST0_SEL_MASK) >> CHN5_SYN_BS_2_DTEST0_SEL_LSB) #define CHN5_SYN_BS_2_DTEST0_SEL_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_DTEST0_SEL_LSB) & CHN5_SYN_BS_2_DTEST0_SEL_MASK) #define CHN5_SYN_BS_2_DTEST0_SEL_RESET 0x0 #define CHN5_SYN_BS_2_DTEST1_SEL_LSB 8 #define CHN5_SYN_BS_2_DTEST1_SEL_MSB 11 #define CHN5_SYN_BS_2_DTEST1_SEL_MASK 0xf00 #define CHN5_SYN_BS_2_DTEST1_SEL_GET(x) (((x) & CHN5_SYN_BS_2_DTEST1_SEL_MASK) >> CHN5_SYN_BS_2_DTEST1_SEL_LSB) #define CHN5_SYN_BS_2_DTEST1_SEL_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_DTEST1_SEL_LSB) & CHN5_SYN_BS_2_DTEST1_SEL_MASK) #define CHN5_SYN_BS_2_DTEST1_SEL_RESET 0x0 #define CHN5_SYN_BS_2_BIST_RO_SEL_LSB 4 #define CHN5_SYN_BS_2_BIST_RO_SEL_MSB 7 #define CHN5_SYN_BS_2_BIST_RO_SEL_MASK 0xf0 #define CHN5_SYN_BS_2_BIST_RO_SEL_GET(x) (((x) & CHN5_SYN_BS_2_BIST_RO_SEL_MASK) >> CHN5_SYN_BS_2_BIST_RO_SEL_LSB) #define CHN5_SYN_BS_2_BIST_RO_SEL_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_BIST_RO_SEL_LSB) & CHN5_SYN_BS_2_BIST_RO_SEL_MASK) #define CHN5_SYN_BS_2_BIST_RO_SEL_RESET 0x0 #define CHN5_SYN_BS_2_BS_RO_SEL_LSB 0 #define CHN5_SYN_BS_2_BS_RO_SEL_MSB 3 #define CHN5_SYN_BS_2_BS_RO_SEL_MASK 0xf #define CHN5_SYN_BS_2_BS_RO_SEL_GET(x) (((x) & CHN5_SYN_BS_2_BS_RO_SEL_MASK) >> CHN5_SYN_BS_2_BS_RO_SEL_LSB) #define CHN5_SYN_BS_2_BS_RO_SEL_SET(x) (((0 | (x)) << CHN5_SYN_BS_2_BS_RO_SEL_LSB) & CHN5_SYN_BS_2_BS_RO_SEL_MASK) #define CHN5_SYN_BS_2_BS_RO_SEL_RESET 0x0 #define CHN5_SYN_BS_2_ADDRESS (0xc + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_BS_2_RSTMASK 0xffffffff #define CHN5_SYN_BS_2_RESET 0x84440000 // 0x10 (CHN5_SYN_BS_READ) #define CHN5_SYN_BS_READ_VHT160_EN_3_LSB 28 #define CHN5_SYN_BS_READ_VHT160_EN_3_MSB 28 #define CHN5_SYN_BS_READ_VHT160_EN_3_MASK 0x10000000 #define CHN5_SYN_BS_READ_VHT160_EN_3_GET(x) (((x) & CHN5_SYN_BS_READ_VHT160_EN_3_MASK) >> CHN5_SYN_BS_READ_VHT160_EN_3_LSB) #define CHN5_SYN_BS_READ_VHT160_EN_3_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_VHT160_EN_3_LSB) & CHN5_SYN_BS_READ_VHT160_EN_3_MASK) #define CHN5_SYN_BS_READ_VHT160_EN_3_RESET 0x0 #define CHN5_SYN_BS_READ_VHT160_EN_2_LSB 27 #define CHN5_SYN_BS_READ_VHT160_EN_2_MSB 27 #define CHN5_SYN_BS_READ_VHT160_EN_2_MASK 0x8000000 #define CHN5_SYN_BS_READ_VHT160_EN_2_GET(x) (((x) & CHN5_SYN_BS_READ_VHT160_EN_2_MASK) >> CHN5_SYN_BS_READ_VHT160_EN_2_LSB) #define CHN5_SYN_BS_READ_VHT160_EN_2_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_VHT160_EN_2_LSB) & CHN5_SYN_BS_READ_VHT160_EN_2_MASK) #define CHN5_SYN_BS_READ_VHT160_EN_2_RESET 0x0 #define CHN5_SYN_BS_READ_VHT160_MODE_LSB 25 #define CHN5_SYN_BS_READ_VHT160_MODE_MSB 26 #define CHN5_SYN_BS_READ_VHT160_MODE_MASK 0x6000000 #define CHN5_SYN_BS_READ_VHT160_MODE_GET(x) (((x) & CHN5_SYN_BS_READ_VHT160_MODE_MASK) >> CHN5_SYN_BS_READ_VHT160_MODE_LSB) #define CHN5_SYN_BS_READ_VHT160_MODE_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_VHT160_MODE_LSB) & CHN5_SYN_BS_READ_VHT160_MODE_MASK) #define CHN5_SYN_BS_READ_VHT160_MODE_RESET 0x0 #define CHN5_SYN_BS_READ_TXON_MASK_LSB 24 #define CHN5_SYN_BS_READ_TXON_MASK_MSB 24 #define CHN5_SYN_BS_READ_TXON_MASK_MASK 0x1000000 #define CHN5_SYN_BS_READ_TXON_MASK_GET(x) (((x) & CHN5_SYN_BS_READ_TXON_MASK_MASK) >> CHN5_SYN_BS_READ_TXON_MASK_LSB) #define CHN5_SYN_BS_READ_TXON_MASK_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_TXON_MASK_LSB) & CHN5_SYN_BS_READ_TXON_MASK_MASK) #define CHN5_SYN_BS_READ_TXON_MASK_RESET 0x0 #define CHN5_SYN_BS_READ_CLBS_ON_LSB 23 #define CHN5_SYN_BS_READ_CLBS_ON_MSB 23 #define CHN5_SYN_BS_READ_CLBS_ON_MASK 0x800000 #define CHN5_SYN_BS_READ_CLBS_ON_GET(x) (((x) & CHN5_SYN_BS_READ_CLBS_ON_MASK) >> CHN5_SYN_BS_READ_CLBS_ON_LSB) #define CHN5_SYN_BS_READ_CLBS_ON_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_CLBS_ON_LSB) & CHN5_SYN_BS_READ_CLBS_ON_MASK) #define CHN5_SYN_BS_READ_CLBS_ON_RESET 0x0 #define CHN5_SYN_BS_READ_PAL_ON_LSB 22 #define CHN5_SYN_BS_READ_PAL_ON_MSB 22 #define CHN5_SYN_BS_READ_PAL_ON_MASK 0x400000 #define CHN5_SYN_BS_READ_PAL_ON_GET(x) (((x) & CHN5_SYN_BS_READ_PAL_ON_MASK) >> CHN5_SYN_BS_READ_PAL_ON_LSB) #define CHN5_SYN_BS_READ_PAL_ON_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_PAL_ON_LSB) & CHN5_SYN_BS_READ_PAL_ON_MASK) #define CHN5_SYN_BS_READ_PAL_ON_RESET 0x0 #define CHN5_SYN_BS_READ_VA_ON_LSB 21 #define CHN5_SYN_BS_READ_VA_ON_MSB 21 #define CHN5_SYN_BS_READ_VA_ON_MASK 0x200000 #define CHN5_SYN_BS_READ_VA_ON_GET(x) (((x) & CHN5_SYN_BS_READ_VA_ON_MASK) >> CHN5_SYN_BS_READ_VA_ON_LSB) #define CHN5_SYN_BS_READ_VA_ON_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_VA_ON_LSB) & CHN5_SYN_BS_READ_VA_ON_MASK) #define CHN5_SYN_BS_READ_VA_ON_RESET 0x0 #define CHN5_SYN_BS_READ_BS_ON_LSB 20 #define CHN5_SYN_BS_READ_BS_ON_MSB 20 #define CHN5_SYN_BS_READ_BS_ON_MASK 0x100000 #define CHN5_SYN_BS_READ_BS_ON_GET(x) (((x) & CHN5_SYN_BS_READ_BS_ON_MASK) >> CHN5_SYN_BS_READ_BS_ON_LSB) #define CHN5_SYN_BS_READ_BS_ON_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_BS_ON_LSB) & CHN5_SYN_BS_READ_BS_ON_MASK) #define CHN5_SYN_BS_READ_BS_ON_RESET 0x0 #define CHN5_SYN_BS_READ_BSLUT_ON_LSB 19 #define CHN5_SYN_BS_READ_BSLUT_ON_MSB 19 #define CHN5_SYN_BS_READ_BSLUT_ON_MASK 0x80000 #define CHN5_SYN_BS_READ_BSLUT_ON_GET(x) (((x) & CHN5_SYN_BS_READ_BSLUT_ON_MASK) >> CHN5_SYN_BS_READ_BSLUT_ON_LSB) #define CHN5_SYN_BS_READ_BSLUT_ON_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_BSLUT_ON_LSB) & CHN5_SYN_BS_READ_BSLUT_ON_MASK) #define CHN5_SYN_BS_READ_BSLUT_ON_RESET 0x0 #define CHN5_SYN_BS_READ_BIST_ON_LSB 18 #define CHN5_SYN_BS_READ_BIST_ON_MSB 18 #define CHN5_SYN_BS_READ_BIST_ON_MASK 0x40000 #define CHN5_SYN_BS_READ_BIST_ON_GET(x) (((x) & CHN5_SYN_BS_READ_BIST_ON_MASK) >> CHN5_SYN_BS_READ_BIST_ON_LSB) #define CHN5_SYN_BS_READ_BIST_ON_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_BIST_ON_LSB) & CHN5_SYN_BS_READ_BIST_ON_MASK) #define CHN5_SYN_BS_READ_BIST_ON_RESET 0x0 #define CHN5_SYN_BS_READ_RFCNT_BIST_PASS_LSB 17 #define CHN5_SYN_BS_READ_RFCNT_BIST_PASS_MSB 17 #define CHN5_SYN_BS_READ_RFCNT_BIST_PASS_MASK 0x20000 #define CHN5_SYN_BS_READ_RFCNT_BIST_PASS_GET(x) (((x) & CHN5_SYN_BS_READ_RFCNT_BIST_PASS_MASK) >> CHN5_SYN_BS_READ_RFCNT_BIST_PASS_LSB) #define CHN5_SYN_BS_READ_RFCNT_BIST_PASS_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_RFCNT_BIST_PASS_LSB) & CHN5_SYN_BS_READ_RFCNT_BIST_PASS_MASK) #define CHN5_SYN_BS_READ_RFCNT_BIST_PASS_RESET 0x0 #define CHN5_SYN_BS_READ_RFCNT_LATCH_TYPE_LSB 16 #define CHN5_SYN_BS_READ_RFCNT_LATCH_TYPE_MSB 16 #define CHN5_SYN_BS_READ_RFCNT_LATCH_TYPE_MASK 0x10000 #define CHN5_SYN_BS_READ_RFCNT_LATCH_TYPE_GET(x) (((x) & CHN5_SYN_BS_READ_RFCNT_LATCH_TYPE_MASK) >> CHN5_SYN_BS_READ_RFCNT_LATCH_TYPE_LSB) #define CHN5_SYN_BS_READ_RFCNT_LATCH_TYPE_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_RFCNT_LATCH_TYPE_LSB) & CHN5_SYN_BS_READ_RFCNT_LATCH_TYPE_MASK) #define CHN5_SYN_BS_READ_RFCNT_LATCH_TYPE_RESET 0x0 #define CHN5_SYN_BS_READ_BS_RO_LSB 0 #define CHN5_SYN_BS_READ_BS_RO_MSB 15 #define CHN5_SYN_BS_READ_BS_RO_MASK 0xffff #define CHN5_SYN_BS_READ_BS_RO_GET(x) (((x) & CHN5_SYN_BS_READ_BS_RO_MASK) >> CHN5_SYN_BS_READ_BS_RO_LSB) #define CHN5_SYN_BS_READ_BS_RO_SET(x) (((0 | (x)) << CHN5_SYN_BS_READ_BS_RO_LSB) & CHN5_SYN_BS_READ_BS_RO_MASK) #define CHN5_SYN_BS_READ_BS_RO_RESET 0x0 #define CHN5_SYN_BS_READ_ADDRESS (0x10 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_BS_READ_RSTMASK 0x1fffffff #define CHN5_SYN_BS_READ_RESET 0x0 // 0x14 (CHN5_SYN_PC_0) #define CHN5_SYN_PC_0_FASTCH_VCON_LSB 31 #define CHN5_SYN_PC_0_FASTCH_VCON_MSB 31 #define CHN5_SYN_PC_0_FASTCH_VCON_MASK 0x80000000 #define CHN5_SYN_PC_0_FASTCH_VCON_GET(x) (((x) & CHN5_SYN_PC_0_FASTCH_VCON_MASK) >> CHN5_SYN_PC_0_FASTCH_VCON_LSB) #define CHN5_SYN_PC_0_FASTCH_VCON_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_FASTCH_VCON_LSB) & CHN5_SYN_PC_0_FASTCH_VCON_MASK) #define CHN5_SYN_PC_0_FASTCH_VCON_RESET 0x0 #define CHN5_SYN_PC_0_FASTCH_TMR_LSB 28 #define CHN5_SYN_PC_0_FASTCH_TMR_MSB 30 #define CHN5_SYN_PC_0_FASTCH_TMR_MASK 0x70000000 #define CHN5_SYN_PC_0_FASTCH_TMR_GET(x) (((x) & CHN5_SYN_PC_0_FASTCH_TMR_MASK) >> CHN5_SYN_PC_0_FASTCH_TMR_LSB) #define CHN5_SYN_PC_0_FASTCH_TMR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_FASTCH_TMR_LSB) & CHN5_SYN_PC_0_FASTCH_TMR_MASK) #define CHN5_SYN_PC_0_FASTCH_TMR_RESET 0x3 #define CHN5_SYN_PC_0_VCO_FAST_CBNK11_OVR_LSB 26 #define CHN5_SYN_PC_0_VCO_FAST_CBNK11_OVR_MSB 27 #define CHN5_SYN_PC_0_VCO_FAST_CBNK11_OVR_MASK 0xc000000 #define CHN5_SYN_PC_0_VCO_FAST_CBNK11_OVR_GET(x) (((x) & CHN5_SYN_PC_0_VCO_FAST_CBNK11_OVR_MASK) >> CHN5_SYN_PC_0_VCO_FAST_CBNK11_OVR_LSB) #define CHN5_SYN_PC_0_VCO_FAST_CBNK11_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_VCO_FAST_CBNK11_OVR_LSB) & CHN5_SYN_PC_0_VCO_FAST_CBNK11_OVR_MASK) #define CHN5_SYN_PC_0_VCO_FAST_CBNK11_OVR_RESET 0x0 #define CHN5_SYN_PC_0_VCO_FAST_BIAS_OVR_LSB 24 #define CHN5_SYN_PC_0_VCO_FAST_BIAS_OVR_MSB 25 #define CHN5_SYN_PC_0_VCO_FAST_BIAS_OVR_MASK 0x3000000 #define CHN5_SYN_PC_0_VCO_FAST_BIAS_OVR_GET(x) (((x) & CHN5_SYN_PC_0_VCO_FAST_BIAS_OVR_MASK) >> CHN5_SYN_PC_0_VCO_FAST_BIAS_OVR_LSB) #define CHN5_SYN_PC_0_VCO_FAST_BIAS_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_VCO_FAST_BIAS_OVR_LSB) & CHN5_SYN_PC_0_VCO_FAST_BIAS_OVR_MASK) #define CHN5_SYN_PC_0_VCO_FAST_BIAS_OVR_RESET 0x0 #define CHN5_SYN_PC_0_BIAS_FAST_CH_OVR_LSB 22 #define CHN5_SYN_PC_0_BIAS_FAST_CH_OVR_MSB 23 #define CHN5_SYN_PC_0_BIAS_FAST_CH_OVR_MASK 0xc00000 #define CHN5_SYN_PC_0_BIAS_FAST_CH_OVR_GET(x) (((x) & CHN5_SYN_PC_0_BIAS_FAST_CH_OVR_MASK) >> CHN5_SYN_PC_0_BIAS_FAST_CH_OVR_LSB) #define CHN5_SYN_PC_0_BIAS_FAST_CH_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_BIAS_FAST_CH_OVR_LSB) & CHN5_SYN_PC_0_BIAS_FAST_CH_OVR_MASK) #define CHN5_SYN_PC_0_BIAS_FAST_CH_OVR_RESET 0x0 #define CHN5_SYN_PC_0_CP_FAST_CH_OVR_LSB 20 #define CHN5_SYN_PC_0_CP_FAST_CH_OVR_MSB 21 #define CHN5_SYN_PC_0_CP_FAST_CH_OVR_MASK 0x300000 #define CHN5_SYN_PC_0_CP_FAST_CH_OVR_GET(x) (((x) & CHN5_SYN_PC_0_CP_FAST_CH_OVR_MASK) >> CHN5_SYN_PC_0_CP_FAST_CH_OVR_LSB) #define CHN5_SYN_PC_0_CP_FAST_CH_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_CP_FAST_CH_OVR_LSB) & CHN5_SYN_PC_0_CP_FAST_CH_OVR_MASK) #define CHN5_SYN_PC_0_CP_FAST_CH_OVR_RESET 0x0 #define CHN5_SYN_PC_0_SDM_EN_LSB 18 #define CHN5_SYN_PC_0_SDM_EN_MSB 19 #define CHN5_SYN_PC_0_SDM_EN_MASK 0xc0000 #define CHN5_SYN_PC_0_SDM_EN_GET(x) (((x) & CHN5_SYN_PC_0_SDM_EN_MASK) >> CHN5_SYN_PC_0_SDM_EN_LSB) #define CHN5_SYN_PC_0_SDM_EN_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_SDM_EN_LSB) & CHN5_SYN_PC_0_SDM_EN_MASK) #define CHN5_SYN_PC_0_SDM_EN_RESET 0x0 #define CHN5_SYN_PC_0_BIAS_EN_OVR_LSB 16 #define CHN5_SYN_PC_0_BIAS_EN_OVR_MSB 17 #define CHN5_SYN_PC_0_BIAS_EN_OVR_MASK 0x30000 #define CHN5_SYN_PC_0_BIAS_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_0_BIAS_EN_OVR_MASK) >> CHN5_SYN_PC_0_BIAS_EN_OVR_LSB) #define CHN5_SYN_PC_0_BIAS_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_BIAS_EN_OVR_LSB) & CHN5_SYN_PC_0_BIAS_EN_OVR_MASK) #define CHN5_SYN_PC_0_BIAS_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_0_SYNON_OVR_LSB 14 #define CHN5_SYN_PC_0_SYNON_OVR_MSB 15 #define CHN5_SYN_PC_0_SYNON_OVR_MASK 0xc000 #define CHN5_SYN_PC_0_SYNON_OVR_GET(x) (((x) & CHN5_SYN_PC_0_SYNON_OVR_MASK) >> CHN5_SYN_PC_0_SYNON_OVR_LSB) #define CHN5_SYN_PC_0_SYNON_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_SYNON_OVR_LSB) & CHN5_SYN_PC_0_SYNON_OVR_MASK) #define CHN5_SYN_PC_0_SYNON_OVR_RESET 0x0 #define CHN5_SYN_PC_0_VCON_SW_OVR_LSB 12 #define CHN5_SYN_PC_0_VCON_SW_OVR_MSB 13 #define CHN5_SYN_PC_0_VCON_SW_OVR_MASK 0x3000 #define CHN5_SYN_PC_0_VCON_SW_OVR_GET(x) (((x) & CHN5_SYN_PC_0_VCON_SW_OVR_MASK) >> CHN5_SYN_PC_0_VCON_SW_OVR_LSB) #define CHN5_SYN_PC_0_VCON_SW_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_VCON_SW_OVR_LSB) & CHN5_SYN_PC_0_VCON_SW_OVR_MASK) #define CHN5_SYN_PC_0_VCON_SW_OVR_RESET 0x0 #define CHN5_SYN_PC_0_LPF_VMGEN_EN_OVR_LSB 10 #define CHN5_SYN_PC_0_LPF_VMGEN_EN_OVR_MSB 11 #define CHN5_SYN_PC_0_LPF_VMGEN_EN_OVR_MASK 0xc00 #define CHN5_SYN_PC_0_LPF_VMGEN_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_0_LPF_VMGEN_EN_OVR_MASK) >> CHN5_SYN_PC_0_LPF_VMGEN_EN_OVR_LSB) #define CHN5_SYN_PC_0_LPF_VMGEN_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_LPF_VMGEN_EN_OVR_LSB) & CHN5_SYN_PC_0_LPF_VMGEN_EN_OVR_MASK) #define CHN5_SYN_PC_0_LPF_VMGEN_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_0_VCO_EN_OVR_LSB 8 #define CHN5_SYN_PC_0_VCO_EN_OVR_MSB 9 #define CHN5_SYN_PC_0_VCO_EN_OVR_MASK 0x300 #define CHN5_SYN_PC_0_VCO_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_0_VCO_EN_OVR_MASK) >> CHN5_SYN_PC_0_VCO_EN_OVR_LSB) #define CHN5_SYN_PC_0_VCO_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_VCO_EN_OVR_LSB) & CHN5_SYN_PC_0_VCO_EN_OVR_MASK) #define CHN5_SYN_PC_0_VCO_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_0_CNTR_RESET_OVR_LSB 6 #define CHN5_SYN_PC_0_CNTR_RESET_OVR_MSB 7 #define CHN5_SYN_PC_0_CNTR_RESET_OVR_MASK 0xc0 #define CHN5_SYN_PC_0_CNTR_RESET_OVR_GET(x) (((x) & CHN5_SYN_PC_0_CNTR_RESET_OVR_MASK) >> CHN5_SYN_PC_0_CNTR_RESET_OVR_LSB) #define CHN5_SYN_PC_0_CNTR_RESET_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_CNTR_RESET_OVR_LSB) & CHN5_SYN_PC_0_CNTR_RESET_OVR_MASK) #define CHN5_SYN_PC_0_CNTR_RESET_OVR_RESET 0x0 #define CHN5_SYN_PC_0_CP_EN_OVR_LSB 4 #define CHN5_SYN_PC_0_CP_EN_OVR_MSB 5 #define CHN5_SYN_PC_0_CP_EN_OVR_MASK 0x30 #define CHN5_SYN_PC_0_CP_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_0_CP_EN_OVR_MASK) >> CHN5_SYN_PC_0_CP_EN_OVR_LSB) #define CHN5_SYN_PC_0_CP_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_CP_EN_OVR_LSB) & CHN5_SYN_PC_0_CP_EN_OVR_MASK) #define CHN5_SYN_PC_0_CP_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_0_PFD_RST_OVR_LSB 2 #define CHN5_SYN_PC_0_PFD_RST_OVR_MSB 3 #define CHN5_SYN_PC_0_PFD_RST_OVR_MASK 0xc #define CHN5_SYN_PC_0_PFD_RST_OVR_GET(x) (((x) & CHN5_SYN_PC_0_PFD_RST_OVR_MASK) >> CHN5_SYN_PC_0_PFD_RST_OVR_LSB) #define CHN5_SYN_PC_0_PFD_RST_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_PFD_RST_OVR_LSB) & CHN5_SYN_PC_0_PFD_RST_OVR_MASK) #define CHN5_SYN_PC_0_PFD_RST_OVR_RESET 0x0 #define CHN5_SYN_PC_0_LO_GM_EN_OVR_LSB 0 #define CHN5_SYN_PC_0_LO_GM_EN_OVR_MSB 1 #define CHN5_SYN_PC_0_LO_GM_EN_OVR_MASK 0x3 #define CHN5_SYN_PC_0_LO_GM_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_0_LO_GM_EN_OVR_MASK) >> CHN5_SYN_PC_0_LO_GM_EN_OVR_LSB) #define CHN5_SYN_PC_0_LO_GM_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_0_LO_GM_EN_OVR_LSB) & CHN5_SYN_PC_0_LO_GM_EN_OVR_MASK) #define CHN5_SYN_PC_0_LO_GM_EN_OVR_RESET 0x1 #define CHN5_SYN_PC_0_ADDRESS (0x14 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_PC_0_RSTMASK 0xffffffff #define CHN5_SYN_PC_0_RESET 0x30000001 // 0x18 (CHN5_SYN_PC_1) #define CHN5_SYN_PC_1_CP_REG25_EN_OVR_LSB 30 #define CHN5_SYN_PC_1_CP_REG25_EN_OVR_MSB 31 #define CHN5_SYN_PC_1_CP_REG25_EN_OVR_MASK 0xc0000000 #define CHN5_SYN_PC_1_CP_REG25_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_CP_REG25_EN_OVR_MASK) >> CHN5_SYN_PC_1_CP_REG25_EN_OVR_LSB) #define CHN5_SYN_PC_1_CP_REG25_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_CP_REG25_EN_OVR_LSB) & CHN5_SYN_PC_1_CP_REG25_EN_OVR_MASK) #define CHN5_SYN_PC_1_CP_REG25_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_CP_REG11_EN_OVR_LSB 28 #define CHN5_SYN_PC_1_CP_REG11_EN_OVR_MSB 29 #define CHN5_SYN_PC_1_CP_REG11_EN_OVR_MASK 0x30000000 #define CHN5_SYN_PC_1_CP_REG11_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_CP_REG11_EN_OVR_MASK) >> CHN5_SYN_PC_1_CP_REG11_EN_OVR_LSB) #define CHN5_SYN_PC_1_CP_REG11_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_CP_REG11_EN_OVR_LSB) & CHN5_SYN_PC_1_CP_REG11_EN_OVR_MASK) #define CHN5_SYN_PC_1_CP_REG11_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_VCO_REG25_EN_OVR_LSB 26 #define CHN5_SYN_PC_1_VCO_REG25_EN_OVR_MSB 27 #define CHN5_SYN_PC_1_VCO_REG25_EN_OVR_MASK 0xc000000 #define CHN5_SYN_PC_1_VCO_REG25_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_VCO_REG25_EN_OVR_MASK) >> CHN5_SYN_PC_1_VCO_REG25_EN_OVR_LSB) #define CHN5_SYN_PC_1_VCO_REG25_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_VCO_REG25_EN_OVR_LSB) & CHN5_SYN_PC_1_VCO_REG25_EN_OVR_MASK) #define CHN5_SYN_PC_1_VCO_REG25_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_VCO_REG11_EN_OVR_LSB 24 #define CHN5_SYN_PC_1_VCO_REG11_EN_OVR_MSB 25 #define CHN5_SYN_PC_1_VCO_REG11_EN_OVR_MASK 0x3000000 #define CHN5_SYN_PC_1_VCO_REG11_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_VCO_REG11_EN_OVR_MASK) >> CHN5_SYN_PC_1_VCO_REG11_EN_OVR_LSB) #define CHN5_SYN_PC_1_VCO_REG11_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_VCO_REG11_EN_OVR_LSB) & CHN5_SYN_PC_1_VCO_REG11_EN_OVR_MASK) #define CHN5_SYN_PC_1_VCO_REG11_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_CNTR_REG11_EN_OVR_LSB 22 #define CHN5_SYN_PC_1_CNTR_REG11_EN_OVR_MSB 23 #define CHN5_SYN_PC_1_CNTR_REG11_EN_OVR_MASK 0xc00000 #define CHN5_SYN_PC_1_CNTR_REG11_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_CNTR_REG11_EN_OVR_MASK) >> CHN5_SYN_PC_1_CNTR_REG11_EN_OVR_LSB) #define CHN5_SYN_PC_1_CNTR_REG11_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_CNTR_REG11_EN_OVR_LSB) & CHN5_SYN_PC_1_CNTR_REG11_EN_OVR_MASK) #define CHN5_SYN_PC_1_CNTR_REG11_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_LPF_PRECH_EN_OVR_LSB 20 #define CHN5_SYN_PC_1_LPF_PRECH_EN_OVR_MSB 21 #define CHN5_SYN_PC_1_LPF_PRECH_EN_OVR_MASK 0x300000 #define CHN5_SYN_PC_1_LPF_PRECH_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_LPF_PRECH_EN_OVR_MASK) >> CHN5_SYN_PC_1_LPF_PRECH_EN_OVR_LSB) #define CHN5_SYN_PC_1_LPF_PRECH_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_LPF_PRECH_EN_OVR_LSB) & CHN5_SYN_PC_1_LPF_PRECH_EN_OVR_MASK) #define CHN5_SYN_PC_1_LPF_PRECH_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_LPF_VHLGEN_EN_OVR_LSB 18 #define CHN5_SYN_PC_1_LPF_VHLGEN_EN_OVR_MSB 19 #define CHN5_SYN_PC_1_LPF_VHLGEN_EN_OVR_MASK 0xc0000 #define CHN5_SYN_PC_1_LPF_VHLGEN_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_LPF_VHLGEN_EN_OVR_MASK) >> CHN5_SYN_PC_1_LPF_VHLGEN_EN_OVR_LSB) #define CHN5_SYN_PC_1_LPF_VHLGEN_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_LPF_VHLGEN_EN_OVR_LSB) & CHN5_SYN_PC_1_LPF_VHLGEN_EN_OVR_MASK) #define CHN5_SYN_PC_1_LPF_VHLGEN_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_LPF_COMPH_EN_OVR_LSB 16 #define CHN5_SYN_PC_1_LPF_COMPH_EN_OVR_MSB 17 #define CHN5_SYN_PC_1_LPF_COMPH_EN_OVR_MASK 0x30000 #define CHN5_SYN_PC_1_LPF_COMPH_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_LPF_COMPH_EN_OVR_MASK) >> CHN5_SYN_PC_1_LPF_COMPH_EN_OVR_LSB) #define CHN5_SYN_PC_1_LPF_COMPH_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_LPF_COMPH_EN_OVR_LSB) & CHN5_SYN_PC_1_LPF_COMPH_EN_OVR_MASK) #define CHN5_SYN_PC_1_LPF_COMPH_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_LPF_COMPL_EN_OVR_LSB 14 #define CHN5_SYN_PC_1_LPF_COMPL_EN_OVR_MSB 15 #define CHN5_SYN_PC_1_LPF_COMPL_EN_OVR_MASK 0xc000 #define CHN5_SYN_PC_1_LPF_COMPL_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_LPF_COMPL_EN_OVR_MASK) >> CHN5_SYN_PC_1_LPF_COMPL_EN_OVR_LSB) #define CHN5_SYN_PC_1_LPF_COMPL_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_LPF_COMPL_EN_OVR_LSB) & CHN5_SYN_PC_1_LPF_COMPL_EN_OVR_MASK) #define CHN5_SYN_PC_1_LPF_COMPL_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_MULT_EN_OVR_LSB 12 #define CHN5_SYN_PC_1_MULT_EN_OVR_MSB 13 #define CHN5_SYN_PC_1_MULT_EN_OVR_MASK 0x3000 #define CHN5_SYN_PC_1_MULT_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_MULT_EN_OVR_MASK) >> CHN5_SYN_PC_1_MULT_EN_OVR_LSB) #define CHN5_SYN_PC_1_MULT_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_MULT_EN_OVR_LSB) & CHN5_SYN_PC_1_MULT_EN_OVR_MASK) #define CHN5_SYN_PC_1_MULT_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_RFCNT_BSCLK_EN_OVR_LSB 10 #define CHN5_SYN_PC_1_RFCNT_BSCLK_EN_OVR_MSB 11 #define CHN5_SYN_PC_1_RFCNT_BSCLK_EN_OVR_MASK 0xc00 #define CHN5_SYN_PC_1_RFCNT_BSCLK_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_RFCNT_BSCLK_EN_OVR_MASK) >> CHN5_SYN_PC_1_RFCNT_BSCLK_EN_OVR_LSB) #define CHN5_SYN_PC_1_RFCNT_BSCLK_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_RFCNT_BSCLK_EN_OVR_LSB) & CHN5_SYN_PC_1_RFCNT_BSCLK_EN_OVR_MASK) #define CHN5_SYN_PC_1_RFCNT_BSCLK_EN_OVR_RESET 0x0 #define CHN5_SYN_PC_1_VCO_EN_PEAKDET_OVR_LSB 8 #define CHN5_SYN_PC_1_VCO_EN_PEAKDET_OVR_MSB 9 #define CHN5_SYN_PC_1_VCO_EN_PEAKDET_OVR_MASK 0x300 #define CHN5_SYN_PC_1_VCO_EN_PEAKDET_OVR_GET(x) (((x) & CHN5_SYN_PC_1_VCO_EN_PEAKDET_OVR_MASK) >> CHN5_SYN_PC_1_VCO_EN_PEAKDET_OVR_LSB) #define CHN5_SYN_PC_1_VCO_EN_PEAKDET_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_VCO_EN_PEAKDET_OVR_LSB) & CHN5_SYN_PC_1_VCO_EN_PEAKDET_OVR_MASK) #define CHN5_SYN_PC_1_VCO_EN_PEAKDET_OVR_RESET 0x0 #define CHN5_SYN_PC_1_EN_DCLK_PLL_LSB 6 #define CHN5_SYN_PC_1_EN_DCLK_PLL_MSB 7 #define CHN5_SYN_PC_1_EN_DCLK_PLL_MASK 0xc0 #define CHN5_SYN_PC_1_EN_DCLK_PLL_GET(x) (((x) & CHN5_SYN_PC_1_EN_DCLK_PLL_MASK) >> CHN5_SYN_PC_1_EN_DCLK_PLL_LSB) #define CHN5_SYN_PC_1_EN_DCLK_PLL_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_EN_DCLK_PLL_LSB) & CHN5_SYN_PC_1_EN_DCLK_PLL_MASK) #define CHN5_SYN_PC_1_EN_DCLK_PLL_RESET 0x0 #define CHN5_SYN_PC_1_ISO_DIS_OVR_LSB 4 #define CHN5_SYN_PC_1_ISO_DIS_OVR_MSB 5 #define CHN5_SYN_PC_1_ISO_DIS_OVR_MASK 0x30 #define CHN5_SYN_PC_1_ISO_DIS_OVR_GET(x) (((x) & CHN5_SYN_PC_1_ISO_DIS_OVR_MASK) >> CHN5_SYN_PC_1_ISO_DIS_OVR_LSB) #define CHN5_SYN_PC_1_ISO_DIS_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_ISO_DIS_OVR_LSB) & CHN5_SYN_PC_1_ISO_DIS_OVR_MASK) #define CHN5_SYN_PC_1_ISO_DIS_OVR_RESET 0x0 #define CHN5_SYN_PC_1_SD_ISO_DIS_OVR_LSB 2 #define CHN5_SYN_PC_1_SD_ISO_DIS_OVR_MSB 3 #define CHN5_SYN_PC_1_SD_ISO_DIS_OVR_MASK 0xc #define CHN5_SYN_PC_1_SD_ISO_DIS_OVR_GET(x) (((x) & CHN5_SYN_PC_1_SD_ISO_DIS_OVR_MASK) >> CHN5_SYN_PC_1_SD_ISO_DIS_OVR_LSB) #define CHN5_SYN_PC_1_SD_ISO_DIS_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_SD_ISO_DIS_OVR_LSB) & CHN5_SYN_PC_1_SD_ISO_DIS_OVR_MASK) #define CHN5_SYN_PC_1_SD_ISO_DIS_OVR_RESET 0x0 #define CHN5_SYN_PC_1_LO_CHAIN_EN_OVR_LSB 0 #define CHN5_SYN_PC_1_LO_CHAIN_EN_OVR_MSB 1 #define CHN5_SYN_PC_1_LO_CHAIN_EN_OVR_MASK 0x3 #define CHN5_SYN_PC_1_LO_CHAIN_EN_OVR_GET(x) (((x) & CHN5_SYN_PC_1_LO_CHAIN_EN_OVR_MASK) >> CHN5_SYN_PC_1_LO_CHAIN_EN_OVR_LSB) #define CHN5_SYN_PC_1_LO_CHAIN_EN_OVR_SET(x) (((0 | (x)) << CHN5_SYN_PC_1_LO_CHAIN_EN_OVR_LSB) & CHN5_SYN_PC_1_LO_CHAIN_EN_OVR_MASK) #define CHN5_SYN_PC_1_LO_CHAIN_EN_OVR_RESET 0x1 #define CHN5_SYN_PC_1_ADDRESS (0x18 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_PC_1_RSTMASK 0xffffffff #define CHN5_SYN_PC_1_RESET 0x1 // 0x1c (CHN5_SYN_DLL_0) #define CHN5_SYN_DLL_0_MULT_VCOCUR_INIT_LSB 28 #define CHN5_SYN_DLL_0_MULT_VCOCUR_INIT_MSB 31 #define CHN5_SYN_DLL_0_MULT_VCOCUR_INIT_MASK 0xf0000000 #define CHN5_SYN_DLL_0_MULT_VCOCUR_INIT_GET(x) (((x) & CHN5_SYN_DLL_0_MULT_VCOCUR_INIT_MASK) >> CHN5_SYN_DLL_0_MULT_VCOCUR_INIT_LSB) #define CHN5_SYN_DLL_0_MULT_VCOCUR_INIT_SET(x) (((0 | (x)) << CHN5_SYN_DLL_0_MULT_VCOCUR_INIT_LSB) & CHN5_SYN_DLL_0_MULT_VCOCUR_INIT_MASK) #define CHN5_SYN_DLL_0_MULT_VCOCUR_INIT_RESET 0x5 #define CHN5_SYN_DLL_0_MULT_VCOCUR_MIN_LSB 24 #define CHN5_SYN_DLL_0_MULT_VCOCUR_MIN_MSB 27 #define CHN5_SYN_DLL_0_MULT_VCOCUR_MIN_MASK 0xf000000 #define CHN5_SYN_DLL_0_MULT_VCOCUR_MIN_GET(x) (((x) & CHN5_SYN_DLL_0_MULT_VCOCUR_MIN_MASK) >> CHN5_SYN_DLL_0_MULT_VCOCUR_MIN_LSB) #define CHN5_SYN_DLL_0_MULT_VCOCUR_MIN_SET(x) (((0 | (x)) << CHN5_SYN_DLL_0_MULT_VCOCUR_MIN_LSB) & CHN5_SYN_DLL_0_MULT_VCOCUR_MIN_MASK) #define CHN5_SYN_DLL_0_MULT_VCOCUR_MIN_RESET 0x0 #define CHN5_SYN_DLL_0_MULT_VCOCUR_MAX_LSB 20 #define CHN5_SYN_DLL_0_MULT_VCOCUR_MAX_MSB 23 #define CHN5_SYN_DLL_0_MULT_VCOCUR_MAX_MASK 0xf00000 #define CHN5_SYN_DLL_0_MULT_VCOCUR_MAX_GET(x) (((x) & CHN5_SYN_DLL_0_MULT_VCOCUR_MAX_MASK) >> CHN5_SYN_DLL_0_MULT_VCOCUR_MAX_LSB) #define CHN5_SYN_DLL_0_MULT_VCOCUR_MAX_SET(x) (((0 | (x)) << CHN5_SYN_DLL_0_MULT_VCOCUR_MAX_LSB) & CHN5_SYN_DLL_0_MULT_VCOCUR_MAX_MASK) #define CHN5_SYN_DLL_0_MULT_VCOCUR_MAX_RESET 0xf #define CHN5_SYN_DLL_0_MULT_VCOCAP_INIT_LSB 16 #define CHN5_SYN_DLL_0_MULT_VCOCAP_INIT_MSB 19 #define CHN5_SYN_DLL_0_MULT_VCOCAP_INIT_MASK 0xf0000 #define CHN5_SYN_DLL_0_MULT_VCOCAP_INIT_GET(x) (((x) & CHN5_SYN_DLL_0_MULT_VCOCAP_INIT_MASK) >> CHN5_SYN_DLL_0_MULT_VCOCAP_INIT_LSB) #define CHN5_SYN_DLL_0_MULT_VCOCAP_INIT_SET(x) (((0 | (x)) << CHN5_SYN_DLL_0_MULT_VCOCAP_INIT_LSB) & CHN5_SYN_DLL_0_MULT_VCOCAP_INIT_MASK) #define CHN5_SYN_DLL_0_MULT_VCOCAP_INIT_RESET 0x0 #define CHN5_SYN_DLL_0_MULT_VCOCAP_MIN_LSB 12 #define CHN5_SYN_DLL_0_MULT_VCOCAP_MIN_MSB 15 #define CHN5_SYN_DLL_0_MULT_VCOCAP_MIN_MASK 0xf000 #define CHN5_SYN_DLL_0_MULT_VCOCAP_MIN_GET(x) (((x) & CHN5_SYN_DLL_0_MULT_VCOCAP_MIN_MASK) >> CHN5_SYN_DLL_0_MULT_VCOCAP_MIN_LSB) #define CHN5_SYN_DLL_0_MULT_VCOCAP_MIN_SET(x) (((0 | (x)) << CHN5_SYN_DLL_0_MULT_VCOCAP_MIN_LSB) & CHN5_SYN_DLL_0_MULT_VCOCAP_MIN_MASK) #define CHN5_SYN_DLL_0_MULT_VCOCAP_MIN_RESET 0x0 #define CHN5_SYN_DLL_0_MULT_VCOCAP_MAX_LSB 8 #define CHN5_SYN_DLL_0_MULT_VCOCAP_MAX_MSB 11 #define CHN5_SYN_DLL_0_MULT_VCOCAP_MAX_MASK 0xf00 #define CHN5_SYN_DLL_0_MULT_VCOCAP_MAX_GET(x) (((x) & CHN5_SYN_DLL_0_MULT_VCOCAP_MAX_MASK) >> CHN5_SYN_DLL_0_MULT_VCOCAP_MAX_LSB) #define CHN5_SYN_DLL_0_MULT_VCOCAP_MAX_SET(x) (((0 | (x)) << CHN5_SYN_DLL_0_MULT_VCOCAP_MAX_LSB) & CHN5_SYN_DLL_0_MULT_VCOCAP_MAX_MASK) #define CHN5_SYN_DLL_0_MULT_VCOCAP_MAX_RESET 0xf #define CHN5_SYN_DLL_0_MULT_VCOCAP_LIN_LSB 7 #define CHN5_SYN_DLL_0_MULT_VCOCAP_LIN_MSB 7 #define CHN5_SYN_DLL_0_MULT_VCOCAP_LIN_MASK 0x80 #define CHN5_SYN_DLL_0_MULT_VCOCAP_LIN_GET(x) (((x) & CHN5_SYN_DLL_0_MULT_VCOCAP_LIN_MASK) >> CHN5_SYN_DLL_0_MULT_VCOCAP_LIN_LSB) #define CHN5_SYN_DLL_0_MULT_VCOCAP_LIN_SET(x) (((0 | (x)) << CHN5_SYN_DLL_0_MULT_VCOCAP_LIN_LSB) & CHN5_SYN_DLL_0_MULT_VCOCAP_LIN_MASK) #define CHN5_SYN_DLL_0_MULT_VCOCAP_LIN_RESET 0x0 #define CHN5_SYN_DLL_0_DLL_CHANGE_CAP_FIRST_LSB 6 #define CHN5_SYN_DLL_0_DLL_CHANGE_CAP_FIRST_MSB 6 #define CHN5_SYN_DLL_0_DLL_CHANGE_CAP_FIRST_MASK 0x40 #define CHN5_SYN_DLL_0_DLL_CHANGE_CAP_FIRST_GET(x) (((x) & CHN5_SYN_DLL_0_DLL_CHANGE_CAP_FIRST_MASK) >> CHN5_SYN_DLL_0_DLL_CHANGE_CAP_FIRST_LSB) #define CHN5_SYN_DLL_0_DLL_CHANGE_CAP_FIRST_SET(x) (((0 | (x)) << CHN5_SYN_DLL_0_DLL_CHANGE_CAP_FIRST_LSB) & CHN5_SYN_DLL_0_DLL_CHANGE_CAP_FIRST_MASK) #define CHN5_SYN_DLL_0_DLL_CHANGE_CAP_FIRST_RESET 0x0 #define CHN5_SYN_DLL_0_MULT_FORCE_CAPCUR_LSB 5 #define CHN5_SYN_DLL_0_MULT_FORCE_CAPCUR_MSB 5 #define CHN5_SYN_DLL_0_MULT_FORCE_CAPCUR_MASK 0x20 #define CHN5_SYN_DLL_0_MULT_FORCE_CAPCUR_GET(x) (((x) & CHN5_SYN_DLL_0_MULT_FORCE_CAPCUR_MASK) >> CHN5_SYN_DLL_0_MULT_FORCE_CAPCUR_LSB) #define CHN5_SYN_DLL_0_MULT_FORCE_CAPCUR_SET(x) (((0 | (x)) << CHN5_SYN_DLL_0_MULT_FORCE_CAPCUR_LSB) & CHN5_SYN_DLL_0_MULT_FORCE_CAPCUR_MASK) #define CHN5_SYN_DLL_0_MULT_FORCE_CAPCUR_RESET 0x0 #define CHN5_SYN_DLL_0_WAIT_DLLSM_LSB 0 #define CHN5_SYN_DLL_0_WAIT_DLLSM_MSB 4 #define CHN5_SYN_DLL_0_WAIT_DLLSM_MASK 0x1f #define CHN5_SYN_DLL_0_WAIT_DLLSM_GET(x) (((x) & CHN5_SYN_DLL_0_WAIT_DLLSM_MASK) >> CHN5_SYN_DLL_0_WAIT_DLLSM_LSB) #define CHN5_SYN_DLL_0_WAIT_DLLSM_SET(x) (((0 | (x)) << CHN5_SYN_DLL_0_WAIT_DLLSM_LSB) & CHN5_SYN_DLL_0_WAIT_DLLSM_MASK) #define CHN5_SYN_DLL_0_WAIT_DLLSM_RESET 0x3 #define CHN5_SYN_DLL_0_ADDRESS (0x1c + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_DLL_0_RSTMASK 0xffffffff #define CHN5_SYN_DLL_0_RESET 0x50f00f03 // 0x20 (CHN5_SYN_DLL_1) #define CHN5_SYN_DLL_1_DLL_VC_CHK_CNT_LSB 28 #define CHN5_SYN_DLL_1_DLL_VC_CHK_CNT_MSB 31 #define CHN5_SYN_DLL_1_DLL_VC_CHK_CNT_MASK 0xf0000000 #define CHN5_SYN_DLL_1_DLL_VC_CHK_CNT_GET(x) (((x) & CHN5_SYN_DLL_1_DLL_VC_CHK_CNT_MASK) >> CHN5_SYN_DLL_1_DLL_VC_CHK_CNT_LSB) #define CHN5_SYN_DLL_1_DLL_VC_CHK_CNT_SET(x) (((0 | (x)) << CHN5_SYN_DLL_1_DLL_VC_CHK_CNT_LSB) & CHN5_SYN_DLL_1_DLL_VC_CHK_CNT_MASK) #define CHN5_SYN_DLL_1_DLL_VC_CHK_CNT_RESET 0x4 #define CHN5_SYN_DLL_1_FORCE_DLL_IS_LOCKED_LSB 27 #define CHN5_SYN_DLL_1_FORCE_DLL_IS_LOCKED_MSB 27 #define CHN5_SYN_DLL_1_FORCE_DLL_IS_LOCKED_MASK 0x8000000 #define CHN5_SYN_DLL_1_FORCE_DLL_IS_LOCKED_GET(x) (((x) & CHN5_SYN_DLL_1_FORCE_DLL_IS_LOCKED_MASK) >> CHN5_SYN_DLL_1_FORCE_DLL_IS_LOCKED_LSB) #define CHN5_SYN_DLL_1_FORCE_DLL_IS_LOCKED_SET(x) (((0 | (x)) << CHN5_SYN_DLL_1_FORCE_DLL_IS_LOCKED_LSB) & CHN5_SYN_DLL_1_FORCE_DLL_IS_LOCKED_MASK) #define CHN5_SYN_DLL_1_FORCE_DLL_IS_LOCKED_RESET 0x0 #define CHN5_SYN_DLL_1_DLL_IS_LOCKED_OVR_LSB 26 #define CHN5_SYN_DLL_1_DLL_IS_LOCKED_OVR_MSB 26 #define CHN5_SYN_DLL_1_DLL_IS_LOCKED_OVR_MASK 0x4000000 #define CHN5_SYN_DLL_1_DLL_IS_LOCKED_OVR_GET(x) (((x) & CHN5_SYN_DLL_1_DLL_IS_LOCKED_OVR_MASK) >> CHN5_SYN_DLL_1_DLL_IS_LOCKED_OVR_LSB) #define CHN5_SYN_DLL_1_DLL_IS_LOCKED_OVR_SET(x) (((0 | (x)) << CHN5_SYN_DLL_1_DLL_IS_LOCKED_OVR_LSB) & CHN5_SYN_DLL_1_DLL_IS_LOCKED_OVR_MASK) #define CHN5_SYN_DLL_1_DLL_IS_LOCKED_OVR_RESET 0x0 #define CHN5_SYN_DLL_1_MULT_BUSY_SEL_LSB 25 #define CHN5_SYN_DLL_1_MULT_BUSY_SEL_MSB 25 #define CHN5_SYN_DLL_1_MULT_BUSY_SEL_MASK 0x2000000 #define CHN5_SYN_DLL_1_MULT_BUSY_SEL_GET(x) (((x) & CHN5_SYN_DLL_1_MULT_BUSY_SEL_MASK) >> CHN5_SYN_DLL_1_MULT_BUSY_SEL_LSB) #define CHN5_SYN_DLL_1_MULT_BUSY_SEL_SET(x) (((0 | (x)) << CHN5_SYN_DLL_1_MULT_BUSY_SEL_LSB) & CHN5_SYN_DLL_1_MULT_BUSY_SEL_MASK) #define CHN5_SYN_DLL_1_MULT_BUSY_SEL_RESET 0x0 #define CHN5_SYN_DLL_1_MULT_SM_RESET_LSB 24 #define CHN5_SYN_DLL_1_MULT_SM_RESET_MSB 24 #define CHN5_SYN_DLL_1_MULT_SM_RESET_MASK 0x1000000 #define CHN5_SYN_DLL_1_MULT_SM_RESET_GET(x) (((x) & CHN5_SYN_DLL_1_MULT_SM_RESET_MASK) >> CHN5_SYN_DLL_1_MULT_SM_RESET_LSB) #define CHN5_SYN_DLL_1_MULT_SM_RESET_SET(x) (((0 | (x)) << CHN5_SYN_DLL_1_MULT_SM_RESET_LSB) & CHN5_SYN_DLL_1_MULT_SM_RESET_MASK) #define CHN5_SYN_DLL_1_MULT_SM_RESET_RESET 0x0 #define CHN5_SYN_DLL_1_MULT_START_SEL_LSB 22 #define CHN5_SYN_DLL_1_MULT_START_SEL_MSB 23 #define CHN5_SYN_DLL_1_MULT_START_SEL_MASK 0xc00000 #define CHN5_SYN_DLL_1_MULT_START_SEL_GET(x) (((x) & CHN5_SYN_DLL_1_MULT_START_SEL_MASK) >> CHN5_SYN_DLL_1_MULT_START_SEL_LSB) #define CHN5_SYN_DLL_1_MULT_START_SEL_SET(x) (((0 | (x)) << CHN5_SYN_DLL_1_MULT_START_SEL_LSB) & CHN5_SYN_DLL_1_MULT_START_SEL_MASK) #define CHN5_SYN_DLL_1_MULT_START_SEL_RESET 0x0 #define CHN5_SYN_DLL_1_BS_IGNORE_MULT_LOCKED_LSB 21 #define CHN5_SYN_DLL_1_BS_IGNORE_MULT_LOCKED_MSB 21 #define CHN5_SYN_DLL_1_BS_IGNORE_MULT_LOCKED_MASK 0x200000 #define CHN5_SYN_DLL_1_BS_IGNORE_MULT_LOCKED_GET(x) (((x) & CHN5_SYN_DLL_1_BS_IGNORE_MULT_LOCKED_MASK) >> CHN5_SYN_DLL_1_BS_IGNORE_MULT_LOCKED_LSB) #define CHN5_SYN_DLL_1_BS_IGNORE_MULT_LOCKED_SET(x) (((0 | (x)) << CHN5_SYN_DLL_1_BS_IGNORE_MULT_LOCKED_LSB) & CHN5_SYN_DLL_1_BS_IGNORE_MULT_LOCKED_MASK) #define CHN5_SYN_DLL_1_BS_IGNORE_MULT_LOCKED_RESET 0x0 #define CHN5_SYN_DLL_1_RESERVED_0_LSB 0 #define CHN5_SYN_DLL_1_RESERVED_0_MSB 20 #define CHN5_SYN_DLL_1_RESERVED_0_MASK 0x1fffff #define CHN5_SYN_DLL_1_RESERVED_0_GET(x) (((x) & CHN5_SYN_DLL_1_RESERVED_0_MASK) >> CHN5_SYN_DLL_1_RESERVED_0_LSB) #define CHN5_SYN_DLL_1_RESERVED_0_SET(x) (((0 | (x)) << CHN5_SYN_DLL_1_RESERVED_0_LSB) & CHN5_SYN_DLL_1_RESERVED_0_MASK) #define CHN5_SYN_DLL_1_RESERVED_0_RESET 0x0 #define CHN5_SYN_DLL_1_ADDRESS (0x20 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_DLL_1_RSTMASK 0xffffffff #define CHN5_SYN_DLL_1_RESET 0x40000000 // 0x24 (CHN5_SYN_BIST) #define CHN5_SYN_BIST_BIST_START_LSB 31 #define CHN5_SYN_BIST_BIST_START_MSB 31 #define CHN5_SYN_BIST_BIST_START_MASK 0x80000000 #define CHN5_SYN_BIST_BIST_START_GET(x) (((x) & CHN5_SYN_BIST_BIST_START_MASK) >> CHN5_SYN_BIST_BIST_START_LSB) #define CHN5_SYN_BIST_BIST_START_SET(x) (((0 | (x)) << CHN5_SYN_BIST_BIST_START_LSB) & CHN5_SYN_BIST_BIST_START_MASK) #define CHN5_SYN_BIST_BIST_START_RESET 0x0 #define CHN5_SYN_BIST_BIST_MODE_LSB 28 #define CHN5_SYN_BIST_BIST_MODE_MSB 30 #define CHN5_SYN_BIST_BIST_MODE_MASK 0x70000000 #define CHN5_SYN_BIST_BIST_MODE_GET(x) (((x) & CHN5_SYN_BIST_BIST_MODE_MASK) >> CHN5_SYN_BIST_BIST_MODE_LSB) #define CHN5_SYN_BIST_BIST_MODE_SET(x) (((0 | (x)) << CHN5_SYN_BIST_BIST_MODE_LSB) & CHN5_SYN_BIST_BIST_MODE_MASK) #define CHN5_SYN_BIST_BIST_MODE_RESET 0x6 #define CHN5_SYN_BIST_BIST_TIME_LSB 26 #define CHN5_SYN_BIST_BIST_TIME_MSB 27 #define CHN5_SYN_BIST_BIST_TIME_MASK 0xc000000 #define CHN5_SYN_BIST_BIST_TIME_GET(x) (((x) & CHN5_SYN_BIST_BIST_TIME_MASK) >> CHN5_SYN_BIST_BIST_TIME_LSB) #define CHN5_SYN_BIST_BIST_TIME_SET(x) (((0 | (x)) << CHN5_SYN_BIST_BIST_TIME_LSB) & CHN5_SYN_BIST_BIST_TIME_MASK) #define CHN5_SYN_BIST_BIST_TIME_RESET 0x2 #define CHN5_SYN_BIST_BIST_WAIT_LSB 24 #define CHN5_SYN_BIST_BIST_WAIT_MSB 25 #define CHN5_SYN_BIST_BIST_WAIT_MASK 0x3000000 #define CHN5_SYN_BIST_BIST_WAIT_GET(x) (((x) & CHN5_SYN_BIST_BIST_WAIT_MASK) >> CHN5_SYN_BIST_BIST_WAIT_LSB) #define CHN5_SYN_BIST_BIST_WAIT_SET(x) (((0 | (x)) << CHN5_SYN_BIST_BIST_WAIT_LSB) & CHN5_SYN_BIST_BIST_WAIT_MASK) #define CHN5_SYN_BIST_BIST_WAIT_RESET 0x1 #define CHN5_SYN_BIST_NDIV_BIST_TIME_LSB 22 #define CHN5_SYN_BIST_NDIV_BIST_TIME_MSB 23 #define CHN5_SYN_BIST_NDIV_BIST_TIME_MASK 0xc00000 #define CHN5_SYN_BIST_NDIV_BIST_TIME_GET(x) (((x) & CHN5_SYN_BIST_NDIV_BIST_TIME_MASK) >> CHN5_SYN_BIST_NDIV_BIST_TIME_LSB) #define CHN5_SYN_BIST_NDIV_BIST_TIME_SET(x) (((0 | (x)) << CHN5_SYN_BIST_NDIV_BIST_TIME_LSB) & CHN5_SYN_BIST_NDIV_BIST_TIME_MASK) #define CHN5_SYN_BIST_NDIV_BIST_TIME_RESET 0x0 #define CHN5_SYN_BIST_EN_NDIV_BIST_LSB 21 #define CHN5_SYN_BIST_EN_NDIV_BIST_MSB 21 #define CHN5_SYN_BIST_EN_NDIV_BIST_MASK 0x200000 #define CHN5_SYN_BIST_EN_NDIV_BIST_GET(x) (((x) & CHN5_SYN_BIST_EN_NDIV_BIST_MASK) >> CHN5_SYN_BIST_EN_NDIV_BIST_LSB) #define CHN5_SYN_BIST_EN_NDIV_BIST_SET(x) (((0 | (x)) << CHN5_SYN_BIST_EN_NDIV_BIST_LSB) & CHN5_SYN_BIST_EN_NDIV_BIST_MASK) #define CHN5_SYN_BIST_EN_NDIV_BIST_RESET 0x0 #define CHN5_SYN_BIST_EN_RFCNT_BIST_LSB 20 #define CHN5_SYN_BIST_EN_RFCNT_BIST_MSB 20 #define CHN5_SYN_BIST_EN_RFCNT_BIST_MASK 0x100000 #define CHN5_SYN_BIST_EN_RFCNT_BIST_GET(x) (((x) & CHN5_SYN_BIST_EN_RFCNT_BIST_MASK) >> CHN5_SYN_BIST_EN_RFCNT_BIST_LSB) #define CHN5_SYN_BIST_EN_RFCNT_BIST_SET(x) (((0 | (x)) << CHN5_SYN_BIST_EN_RFCNT_BIST_LSB) & CHN5_SYN_BIST_EN_RFCNT_BIST_MASK) #define CHN5_SYN_BIST_EN_RFCNT_BIST_RESET 0x0 #define CHN5_SYN_BIST_RESERVED_0_LSB 19 #define CHN5_SYN_BIST_RESERVED_0_MSB 19 #define CHN5_SYN_BIST_RESERVED_0_MASK 0x80000 #define CHN5_SYN_BIST_RESERVED_0_GET(x) (((x) & CHN5_SYN_BIST_RESERVED_0_MASK) >> CHN5_SYN_BIST_RESERVED_0_LSB) #define CHN5_SYN_BIST_RESERVED_0_SET(x) (((0 | (x)) << CHN5_SYN_BIST_RESERVED_0_LSB) & CHN5_SYN_BIST_RESERVED_0_MASK) #define CHN5_SYN_BIST_RESERVED_0_RESET 0x0 #define CHN5_SYN_BIST_BIST_VMID_LSB 16 #define CHN5_SYN_BIST_BIST_VMID_MSB 18 #define CHN5_SYN_BIST_BIST_VMID_MASK 0x70000 #define CHN5_SYN_BIST_BIST_VMID_GET(x) (((x) & CHN5_SYN_BIST_BIST_VMID_MASK) >> CHN5_SYN_BIST_BIST_VMID_LSB) #define CHN5_SYN_BIST_BIST_VMID_SET(x) (((0 | (x)) << CHN5_SYN_BIST_BIST_VMID_LSB) & CHN5_SYN_BIST_BIST_VMID_MASK) #define CHN5_SYN_BIST_BIST_VMID_RESET 0x4 #define CHN5_SYN_BIST_RESERVED_1_LSB 15 #define CHN5_SYN_BIST_RESERVED_1_MSB 15 #define CHN5_SYN_BIST_RESERVED_1_MASK 0x8000 #define CHN5_SYN_BIST_RESERVED_1_GET(x) (((x) & CHN5_SYN_BIST_RESERVED_1_MASK) >> CHN5_SYN_BIST_RESERVED_1_LSB) #define CHN5_SYN_BIST_RESERVED_1_SET(x) (((0 | (x)) << CHN5_SYN_BIST_RESERVED_1_LSB) & CHN5_SYN_BIST_RESERVED_1_MASK) #define CHN5_SYN_BIST_RESERVED_1_RESET 0x0 #define CHN5_SYN_BIST_BIST_VMID_KVCOH_LSB 12 #define CHN5_SYN_BIST_BIST_VMID_KVCOH_MSB 14 #define CHN5_SYN_BIST_BIST_VMID_KVCOH_MASK 0x7000 #define CHN5_SYN_BIST_BIST_VMID_KVCOH_GET(x) (((x) & CHN5_SYN_BIST_BIST_VMID_KVCOH_MASK) >> CHN5_SYN_BIST_BIST_VMID_KVCOH_LSB) #define CHN5_SYN_BIST_BIST_VMID_KVCOH_SET(x) (((0 | (x)) << CHN5_SYN_BIST_BIST_VMID_KVCOH_LSB) & CHN5_SYN_BIST_BIST_VMID_KVCOH_MASK) #define CHN5_SYN_BIST_BIST_VMID_KVCOH_RESET 0x6 #define CHN5_SYN_BIST_RESERVED_2_LSB 11 #define CHN5_SYN_BIST_RESERVED_2_MSB 11 #define CHN5_SYN_BIST_RESERVED_2_MASK 0x800 #define CHN5_SYN_BIST_RESERVED_2_GET(x) (((x) & CHN5_SYN_BIST_RESERVED_2_MASK) >> CHN5_SYN_BIST_RESERVED_2_LSB) #define CHN5_SYN_BIST_RESERVED_2_SET(x) (((0 | (x)) << CHN5_SYN_BIST_RESERVED_2_LSB) & CHN5_SYN_BIST_RESERVED_2_MASK) #define CHN5_SYN_BIST_RESERVED_2_RESET 0x0 #define CHN5_SYN_BIST_BIST_VMID_KVCOL_LSB 8 #define CHN5_SYN_BIST_BIST_VMID_KVCOL_MSB 10 #define CHN5_SYN_BIST_BIST_VMID_KVCOL_MASK 0x700 #define CHN5_SYN_BIST_BIST_VMID_KVCOL_GET(x) (((x) & CHN5_SYN_BIST_BIST_VMID_KVCOL_MASK) >> CHN5_SYN_BIST_BIST_VMID_KVCOL_LSB) #define CHN5_SYN_BIST_BIST_VMID_KVCOL_SET(x) (((0 | (x)) << CHN5_SYN_BIST_BIST_VMID_KVCOL_LSB) & CHN5_SYN_BIST_BIST_VMID_KVCOL_MASK) #define CHN5_SYN_BIST_BIST_VMID_KVCOL_RESET 0x2 #define CHN5_SYN_BIST_RESERVED_3_LSB 0 #define CHN5_SYN_BIST_RESERVED_3_MSB 7 #define CHN5_SYN_BIST_RESERVED_3_MASK 0xff #define CHN5_SYN_BIST_RESERVED_3_GET(x) (((x) & CHN5_SYN_BIST_RESERVED_3_MASK) >> CHN5_SYN_BIST_RESERVED_3_LSB) #define CHN5_SYN_BIST_RESERVED_3_SET(x) (((0 | (x)) << CHN5_SYN_BIST_RESERVED_3_LSB) & CHN5_SYN_BIST_RESERVED_3_MASK) #define CHN5_SYN_BIST_RESERVED_3_RESET 0x0 #define CHN5_SYN_BIST_ADDRESS (0x24 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_BIST_RSTMASK 0xffffffff #define CHN5_SYN_BIST_RESET 0x69046200 // 0x28 (CHN5_SYN_AC_0) #define CHN5_SYN_AC_0_MULT_CP_LSB 28 #define CHN5_SYN_AC_0_MULT_CP_MSB 31 #define CHN5_SYN_AC_0_MULT_CP_MASK 0xf0000000 #define CHN5_SYN_AC_0_MULT_CP_GET(x) (((x) & CHN5_SYN_AC_0_MULT_CP_MASK) >> CHN5_SYN_AC_0_MULT_CP_LSB) #define CHN5_SYN_AC_0_MULT_CP_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_MULT_CP_LSB) & CHN5_SYN_AC_0_MULT_CP_MASK) #define CHN5_SYN_AC_0_MULT_CP_RESET 0xf #define CHN5_SYN_AC_0_MULT_VCL_LSB 26 #define CHN5_SYN_AC_0_MULT_VCL_MSB 27 #define CHN5_SYN_AC_0_MULT_VCL_MASK 0xc000000 #define CHN5_SYN_AC_0_MULT_VCL_GET(x) (((x) & CHN5_SYN_AC_0_MULT_VCL_MASK) >> CHN5_SYN_AC_0_MULT_VCL_LSB) #define CHN5_SYN_AC_0_MULT_VCL_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_MULT_VCL_LSB) & CHN5_SYN_AC_0_MULT_VCL_MASK) #define CHN5_SYN_AC_0_MULT_VCL_RESET 0x2 #define CHN5_SYN_AC_0_MULT_VCH_LSB 24 #define CHN5_SYN_AC_0_MULT_VCH_MSB 25 #define CHN5_SYN_AC_0_MULT_VCH_MASK 0x3000000 #define CHN5_SYN_AC_0_MULT_VCH_GET(x) (((x) & CHN5_SYN_AC_0_MULT_VCH_MASK) >> CHN5_SYN_AC_0_MULT_VCH_LSB) #define CHN5_SYN_AC_0_MULT_VCH_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_MULT_VCH_LSB) & CHN5_SYN_AC_0_MULT_VCH_MASK) #define CHN5_SYN_AC_0_MULT_VCH_RESET 0x2 #define CHN5_SYN_AC_0_MULT_CPCAL_LSB 22 #define CHN5_SYN_AC_0_MULT_CPCAL_MSB 23 #define CHN5_SYN_AC_0_MULT_CPCAL_MASK 0xc00000 #define CHN5_SYN_AC_0_MULT_CPCAL_GET(x) (((x) & CHN5_SYN_AC_0_MULT_CPCAL_MASK) >> CHN5_SYN_AC_0_MULT_CPCAL_LSB) #define CHN5_SYN_AC_0_MULT_CPCAL_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_MULT_CPCAL_LSB) & CHN5_SYN_AC_0_MULT_CPCAL_MASK) #define CHN5_SYN_AC_0_MULT_CPCAL_RESET 0x3 #define CHN5_SYN_AC_0_MULT_PDCAL_LSB 21 #define CHN5_SYN_AC_0_MULT_PDCAL_MSB 21 #define CHN5_SYN_AC_0_MULT_PDCAL_MASK 0x200000 #define CHN5_SYN_AC_0_MULT_PDCAL_GET(x) (((x) & CHN5_SYN_AC_0_MULT_PDCAL_MASK) >> CHN5_SYN_AC_0_MULT_PDCAL_LSB) #define CHN5_SYN_AC_0_MULT_PDCAL_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_MULT_PDCAL_LSB) & CHN5_SYN_AC_0_MULT_PDCAL_MASK) #define CHN5_SYN_AC_0_MULT_PDCAL_RESET 0x0 #define CHN5_SYN_AC_0_MULT_XOEDGESEL_LSB 20 #define CHN5_SYN_AC_0_MULT_XOEDGESEL_MSB 20 #define CHN5_SYN_AC_0_MULT_XOEDGESEL_MASK 0x100000 #define CHN5_SYN_AC_0_MULT_XOEDGESEL_GET(x) (((x) & CHN5_SYN_AC_0_MULT_XOEDGESEL_MASK) >> CHN5_SYN_AC_0_MULT_XOEDGESEL_LSB) #define CHN5_SYN_AC_0_MULT_XOEDGESEL_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_MULT_XOEDGESEL_LSB) & CHN5_SYN_AC_0_MULT_XOEDGESEL_MASK) #define CHN5_SYN_AC_0_MULT_XOEDGESEL_RESET 0x0 #define CHN5_SYN_AC_0_MULT_VREF25_LSB 17 #define CHN5_SYN_AC_0_MULT_VREF25_MSB 19 #define CHN5_SYN_AC_0_MULT_VREF25_MASK 0xe0000 #define CHN5_SYN_AC_0_MULT_VREF25_GET(x) (((x) & CHN5_SYN_AC_0_MULT_VREF25_MASK) >> CHN5_SYN_AC_0_MULT_VREF25_LSB) #define CHN5_SYN_AC_0_MULT_VREF25_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_MULT_VREF25_LSB) & CHN5_SYN_AC_0_MULT_VREF25_MASK) #define CHN5_SYN_AC_0_MULT_VREF25_RESET 0x3 #define CHN5_SYN_AC_0_MULT_VREF11_LSB 14 #define CHN5_SYN_AC_0_MULT_VREF11_MSB 16 #define CHN5_SYN_AC_0_MULT_VREF11_MASK 0x1c000 #define CHN5_SYN_AC_0_MULT_VREF11_GET(x) (((x) & CHN5_SYN_AC_0_MULT_VREF11_MASK) >> CHN5_SYN_AC_0_MULT_VREF11_LSB) #define CHN5_SYN_AC_0_MULT_VREF11_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_MULT_VREF11_LSB) & CHN5_SYN_AC_0_MULT_VREF11_MASK) #define CHN5_SYN_AC_0_MULT_VREF11_RESET 0x3 #define CHN5_SYN_AC_0_CP_VREF25_LSB 11 #define CHN5_SYN_AC_0_CP_VREF25_MSB 13 #define CHN5_SYN_AC_0_CP_VREF25_MASK 0x3800 #define CHN5_SYN_AC_0_CP_VREF25_GET(x) (((x) & CHN5_SYN_AC_0_CP_VREF25_MASK) >> CHN5_SYN_AC_0_CP_VREF25_LSB) #define CHN5_SYN_AC_0_CP_VREF25_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_CP_VREF25_LSB) & CHN5_SYN_AC_0_CP_VREF25_MASK) #define CHN5_SYN_AC_0_CP_VREF25_RESET 0x3 #define CHN5_SYN_AC_0_CP_VREF11_LSB 8 #define CHN5_SYN_AC_0_CP_VREF11_MSB 10 #define CHN5_SYN_AC_0_CP_VREF11_MASK 0x700 #define CHN5_SYN_AC_0_CP_VREF11_GET(x) (((x) & CHN5_SYN_AC_0_CP_VREF11_MASK) >> CHN5_SYN_AC_0_CP_VREF11_LSB) #define CHN5_SYN_AC_0_CP_VREF11_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_CP_VREF11_LSB) & CHN5_SYN_AC_0_CP_VREF11_MASK) #define CHN5_SYN_AC_0_CP_VREF11_RESET 0x3 #define CHN5_SYN_AC_0_VCO_VREF25_LSB 5 #define CHN5_SYN_AC_0_VCO_VREF25_MSB 7 #define CHN5_SYN_AC_0_VCO_VREF25_MASK 0xe0 #define CHN5_SYN_AC_0_VCO_VREF25_GET(x) (((x) & CHN5_SYN_AC_0_VCO_VREF25_MASK) >> CHN5_SYN_AC_0_VCO_VREF25_LSB) #define CHN5_SYN_AC_0_VCO_VREF25_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_VCO_VREF25_LSB) & CHN5_SYN_AC_0_VCO_VREF25_MASK) #define CHN5_SYN_AC_0_VCO_VREF25_RESET 0x3 #define CHN5_SYN_AC_0_VCO_VREF11_LSB 2 #define CHN5_SYN_AC_0_VCO_VREF11_MSB 4 #define CHN5_SYN_AC_0_VCO_VREF11_MASK 0x1c #define CHN5_SYN_AC_0_VCO_VREF11_GET(x) (((x) & CHN5_SYN_AC_0_VCO_VREF11_MASK) >> CHN5_SYN_AC_0_VCO_VREF11_LSB) #define CHN5_SYN_AC_0_VCO_VREF11_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_VCO_VREF11_LSB) & CHN5_SYN_AC_0_VCO_VREF11_MASK) #define CHN5_SYN_AC_0_VCO_VREF11_RESET 0x3 #define CHN5_SYN_AC_0_CP_REG25_LEAKER_LSB 1 #define CHN5_SYN_AC_0_CP_REG25_LEAKER_MSB 1 #define CHN5_SYN_AC_0_CP_REG25_LEAKER_MASK 0x2 #define CHN5_SYN_AC_0_CP_REG25_LEAKER_GET(x) (((x) & CHN5_SYN_AC_0_CP_REG25_LEAKER_MASK) >> CHN5_SYN_AC_0_CP_REG25_LEAKER_LSB) #define CHN5_SYN_AC_0_CP_REG25_LEAKER_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_CP_REG25_LEAKER_LSB) & CHN5_SYN_AC_0_CP_REG25_LEAKER_MASK) #define CHN5_SYN_AC_0_CP_REG25_LEAKER_RESET 0x0 #define CHN5_SYN_AC_0_CNTR_REG11_LEAKER_LSB 0 #define CHN5_SYN_AC_0_CNTR_REG11_LEAKER_MSB 0 #define CHN5_SYN_AC_0_CNTR_REG11_LEAKER_MASK 0x1 #define CHN5_SYN_AC_0_CNTR_REG11_LEAKER_GET(x) (((x) & CHN5_SYN_AC_0_CNTR_REG11_LEAKER_MASK) >> CHN5_SYN_AC_0_CNTR_REG11_LEAKER_LSB) #define CHN5_SYN_AC_0_CNTR_REG11_LEAKER_SET(x) (((0 | (x)) << CHN5_SYN_AC_0_CNTR_REG11_LEAKER_LSB) & CHN5_SYN_AC_0_CNTR_REG11_LEAKER_MASK) #define CHN5_SYN_AC_0_CNTR_REG11_LEAKER_RESET 0x0 #define CHN5_SYN_AC_0_ADDRESS (0x28 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_AC_0_RSTMASK 0xffffffff #define CHN5_SYN_AC_0_RESET 0xfac6db6c // 0x2c (CHN5_SYN_AC_1) #define CHN5_SYN_AC_1_CNTR_VREF11_LSB 29 #define CHN5_SYN_AC_1_CNTR_VREF11_MSB 31 #define CHN5_SYN_AC_1_CNTR_VREF11_MASK 0xe0000000 #define CHN5_SYN_AC_1_CNTR_VREF11_GET(x) (((x) & CHN5_SYN_AC_1_CNTR_VREF11_MASK) >> CHN5_SYN_AC_1_CNTR_VREF11_LSB) #define CHN5_SYN_AC_1_CNTR_VREF11_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_CNTR_VREF11_LSB) & CHN5_SYN_AC_1_CNTR_VREF11_MASK) #define CHN5_SYN_AC_1_CNTR_VREF11_RESET 0x3 #define CHN5_SYN_AC_1_CP_REG25_BYP_LSB 28 #define CHN5_SYN_AC_1_CP_REG25_BYP_MSB 28 #define CHN5_SYN_AC_1_CP_REG25_BYP_MASK 0x10000000 #define CHN5_SYN_AC_1_CP_REG25_BYP_GET(x) (((x) & CHN5_SYN_AC_1_CP_REG25_BYP_MASK) >> CHN5_SYN_AC_1_CP_REG25_BYP_LSB) #define CHN5_SYN_AC_1_CP_REG25_BYP_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_CP_REG25_BYP_LSB) & CHN5_SYN_AC_1_CP_REG25_BYP_MASK) #define CHN5_SYN_AC_1_CP_REG25_BYP_RESET 0x0 #define CHN5_SYN_AC_1_VCO_REG25_BYP_LSB 27 #define CHN5_SYN_AC_1_VCO_REG25_BYP_MSB 27 #define CHN5_SYN_AC_1_VCO_REG25_BYP_MASK 0x8000000 #define CHN5_SYN_AC_1_VCO_REG25_BYP_GET(x) (((x) & CHN5_SYN_AC_1_VCO_REG25_BYP_MASK) >> CHN5_SYN_AC_1_VCO_REG25_BYP_LSB) #define CHN5_SYN_AC_1_VCO_REG25_BYP_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_VCO_REG25_BYP_LSB) & CHN5_SYN_AC_1_VCO_REG25_BYP_MASK) #define CHN5_SYN_AC_1_VCO_REG25_BYP_RESET 0x0 #define CHN5_SYN_AC_1_VCO_REG11_BYP_LSB 26 #define CHN5_SYN_AC_1_VCO_REG11_BYP_MSB 26 #define CHN5_SYN_AC_1_VCO_REG11_BYP_MASK 0x4000000 #define CHN5_SYN_AC_1_VCO_REG11_BYP_GET(x) (((x) & CHN5_SYN_AC_1_VCO_REG11_BYP_MASK) >> CHN5_SYN_AC_1_VCO_REG11_BYP_LSB) #define CHN5_SYN_AC_1_VCO_REG11_BYP_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_VCO_REG11_BYP_LSB) & CHN5_SYN_AC_1_VCO_REG11_BYP_MASK) #define CHN5_SYN_AC_1_VCO_REG11_BYP_RESET 0x0 #define CHN5_SYN_AC_1_CNTR_REG11_BYP_LSB 25 #define CHN5_SYN_AC_1_CNTR_REG11_BYP_MSB 25 #define CHN5_SYN_AC_1_CNTR_REG11_BYP_MASK 0x2000000 #define CHN5_SYN_AC_1_CNTR_REG11_BYP_GET(x) (((x) & CHN5_SYN_AC_1_CNTR_REG11_BYP_MASK) >> CHN5_SYN_AC_1_CNTR_REG11_BYP_LSB) #define CHN5_SYN_AC_1_CNTR_REG11_BYP_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_CNTR_REG11_BYP_LSB) & CHN5_SYN_AC_1_CNTR_REG11_BYP_MASK) #define CHN5_SYN_AC_1_CNTR_REG11_BYP_RESET 0x0 #define CHN5_SYN_AC_1_CNTR_PWIDTH_LSB 23 #define CHN5_SYN_AC_1_CNTR_PWIDTH_MSB 24 #define CHN5_SYN_AC_1_CNTR_PWIDTH_MASK 0x1800000 #define CHN5_SYN_AC_1_CNTR_PWIDTH_GET(x) (((x) & CHN5_SYN_AC_1_CNTR_PWIDTH_MASK) >> CHN5_SYN_AC_1_CNTR_PWIDTH_LSB) #define CHN5_SYN_AC_1_CNTR_PWIDTH_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_CNTR_PWIDTH_LSB) & CHN5_SYN_AC_1_CNTR_PWIDTH_MASK) #define CHN5_SYN_AC_1_CNTR_PWIDTH_RESET 0x0 #define CHN5_SYN_AC_1_LO_VMODE_EN_LSB 22 #define CHN5_SYN_AC_1_LO_VMODE_EN_MSB 22 #define CHN5_SYN_AC_1_LO_VMODE_EN_MASK 0x400000 #define CHN5_SYN_AC_1_LO_VMODE_EN_GET(x) (((x) & CHN5_SYN_AC_1_LO_VMODE_EN_MASK) >> CHN5_SYN_AC_1_LO_VMODE_EN_LSB) #define CHN5_SYN_AC_1_LO_VMODE_EN_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_LO_VMODE_EN_LSB) & CHN5_SYN_AC_1_LO_VMODE_EN_MASK) #define CHN5_SYN_AC_1_LO_VMODE_EN_RESET 0x0 #define CHN5_SYN_AC_1_VCO_VMODE_EN_LSB 21 #define CHN5_SYN_AC_1_VCO_VMODE_EN_MSB 21 #define CHN5_SYN_AC_1_VCO_VMODE_EN_MASK 0x200000 #define CHN5_SYN_AC_1_VCO_VMODE_EN_GET(x) (((x) & CHN5_SYN_AC_1_VCO_VMODE_EN_MASK) >> CHN5_SYN_AC_1_VCO_VMODE_EN_LSB) #define CHN5_SYN_AC_1_VCO_VMODE_EN_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_VCO_VMODE_EN_LSB) & CHN5_SYN_AC_1_VCO_VMODE_EN_MASK) #define CHN5_SYN_AC_1_VCO_VMODE_EN_RESET 0x0 #define CHN5_SYN_AC_1_VCO_CBNK11_LSB 18 #define CHN5_SYN_AC_1_VCO_CBNK11_MSB 20 #define CHN5_SYN_AC_1_VCO_CBNK11_MASK 0x1c0000 #define CHN5_SYN_AC_1_VCO_CBNK11_GET(x) (((x) & CHN5_SYN_AC_1_VCO_CBNK11_MASK) >> CHN5_SYN_AC_1_VCO_CBNK11_LSB) #define CHN5_SYN_AC_1_VCO_CBNK11_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_VCO_CBNK11_LSB) & CHN5_SYN_AC_1_VCO_CBNK11_MASK) #define CHN5_SYN_AC_1_VCO_CBNK11_RESET 0x5 #define CHN5_SYN_AC_1_VCO_VMONITOR_LSB 15 #define CHN5_SYN_AC_1_VCO_VMONITOR_MSB 17 #define CHN5_SYN_AC_1_VCO_VMONITOR_MASK 0x38000 #define CHN5_SYN_AC_1_VCO_VMONITOR_GET(x) (((x) & CHN5_SYN_AC_1_VCO_VMONITOR_MASK) >> CHN5_SYN_AC_1_VCO_VMONITOR_LSB) #define CHN5_SYN_AC_1_VCO_VMONITOR_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_VCO_VMONITOR_LSB) & CHN5_SYN_AC_1_VCO_VMONITOR_MASK) #define CHN5_SYN_AC_1_VCO_VMONITOR_RESET 0x3 #define CHN5_SYN_AC_1_VCO_KVCO_LSB 12 #define CHN5_SYN_AC_1_VCO_KVCO_MSB 14 #define CHN5_SYN_AC_1_VCO_KVCO_MASK 0x7000 #define CHN5_SYN_AC_1_VCO_KVCO_GET(x) (((x) & CHN5_SYN_AC_1_VCO_KVCO_MASK) >> CHN5_SYN_AC_1_VCO_KVCO_LSB) #define CHN5_SYN_AC_1_VCO_KVCO_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_VCO_KVCO_LSB) & CHN5_SYN_AC_1_VCO_KVCO_MASK) #define CHN5_SYN_AC_1_VCO_KVCO_RESET 0x2 #define CHN5_SYN_AC_1_VCO_BIAS_LSB 7 #define CHN5_SYN_AC_1_VCO_BIAS_MSB 11 #define CHN5_SYN_AC_1_VCO_BIAS_MASK 0xf80 #define CHN5_SYN_AC_1_VCO_BIAS_GET(x) (((x) & CHN5_SYN_AC_1_VCO_BIAS_MASK) >> CHN5_SYN_AC_1_VCO_BIAS_LSB) #define CHN5_SYN_AC_1_VCO_BIAS_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_VCO_BIAS_LSB) & CHN5_SYN_AC_1_VCO_BIAS_MASK) #define CHN5_SYN_AC_1_VCO_BIAS_RESET 0x14 #define CHN5_SYN_AC_1_BIAS_ICP_LSB 5 #define CHN5_SYN_AC_1_BIAS_ICP_MSB 6 #define CHN5_SYN_AC_1_BIAS_ICP_MASK 0x60 #define CHN5_SYN_AC_1_BIAS_ICP_GET(x) (((x) & CHN5_SYN_AC_1_BIAS_ICP_MASK) >> CHN5_SYN_AC_1_BIAS_ICP_LSB) #define CHN5_SYN_AC_1_BIAS_ICP_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_BIAS_ICP_LSB) & CHN5_SYN_AC_1_BIAS_ICP_MASK) #define CHN5_SYN_AC_1_BIAS_ICP_RESET 0x2 #define CHN5_SYN_AC_1_RESERVED_0_LSB 0 #define CHN5_SYN_AC_1_RESERVED_0_MSB 4 #define CHN5_SYN_AC_1_RESERVED_0_MASK 0x1f #define CHN5_SYN_AC_1_RESERVED_0_GET(x) (((x) & CHN5_SYN_AC_1_RESERVED_0_MASK) >> CHN5_SYN_AC_1_RESERVED_0_LSB) #define CHN5_SYN_AC_1_RESERVED_0_SET(x) (((0 | (x)) << CHN5_SYN_AC_1_RESERVED_0_LSB) & CHN5_SYN_AC_1_RESERVED_0_MASK) #define CHN5_SYN_AC_1_RESERVED_0_RESET 0x0 #define CHN5_SYN_AC_1_ADDRESS (0x2c + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_AC_1_RSTMASK 0xffffffff #define CHN5_SYN_AC_1_RESET 0x6015aa40 // 0x30 (CHN5_SYN_AC_2) #define CHN5_SYN_AC_2_CP_PINVC_LSB 31 #define CHN5_SYN_AC_2_CP_PINVC_MSB 31 #define CHN5_SYN_AC_2_CP_PINVC_MASK 0x80000000 #define CHN5_SYN_AC_2_CP_PINVC_GET(x) (((x) & CHN5_SYN_AC_2_CP_PINVC_MASK) >> CHN5_SYN_AC_2_CP_PINVC_LSB) #define CHN5_SYN_AC_2_CP_PINVC_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_CP_PINVC_LSB) & CHN5_SYN_AC_2_CP_PINVC_MASK) #define CHN5_SYN_AC_2_CP_PINVC_RESET 0x0 #define CHN5_SYN_AC_2_CP_ICP_LSB 24 #define CHN5_SYN_AC_2_CP_ICP_MSB 30 #define CHN5_SYN_AC_2_CP_ICP_MASK 0x7f000000 #define CHN5_SYN_AC_2_CP_ICP_GET(x) (((x) & CHN5_SYN_AC_2_CP_ICP_MASK) >> CHN5_SYN_AC_2_CP_ICP_LSB) #define CHN5_SYN_AC_2_CP_ICP_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_CP_ICP_LSB) & CHN5_SYN_AC_2_CP_ICP_MASK) #define CHN5_SYN_AC_2_CP_ICP_RESET 0x33 #define CHN5_SYN_AC_2_CP_ILK_LSB 20 #define CHN5_SYN_AC_2_CP_ILK_MSB 23 #define CHN5_SYN_AC_2_CP_ILK_MASK 0xf00000 #define CHN5_SYN_AC_2_CP_ILK_GET(x) (((x) & CHN5_SYN_AC_2_CP_ILK_MASK) >> CHN5_SYN_AC_2_CP_ILK_LSB) #define CHN5_SYN_AC_2_CP_ILK_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_CP_ILK_LSB) & CHN5_SYN_AC_2_CP_ILK_MASK) #define CHN5_SYN_AC_2_CP_ILK_RESET 0x6 #define CHN5_SYN_AC_2_CP_MON_FB_LSB 19 #define CHN5_SYN_AC_2_CP_MON_FB_MSB 19 #define CHN5_SYN_AC_2_CP_MON_FB_MASK 0x80000 #define CHN5_SYN_AC_2_CP_MON_FB_GET(x) (((x) & CHN5_SYN_AC_2_CP_MON_FB_MASK) >> CHN5_SYN_AC_2_CP_MON_FB_LSB) #define CHN5_SYN_AC_2_CP_MON_FB_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_CP_MON_FB_LSB) & CHN5_SYN_AC_2_CP_MON_FB_MASK) #define CHN5_SYN_AC_2_CP_MON_FB_RESET 0x0 #define CHN5_SYN_AC_2_CP_MON_REF_LSB 18 #define CHN5_SYN_AC_2_CP_MON_REF_MSB 18 #define CHN5_SYN_AC_2_CP_MON_REF_MASK 0x40000 #define CHN5_SYN_AC_2_CP_MON_REF_GET(x) (((x) & CHN5_SYN_AC_2_CP_MON_REF_MASK) >> CHN5_SYN_AC_2_CP_MON_REF_LSB) #define CHN5_SYN_AC_2_CP_MON_REF_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_CP_MON_REF_LSB) & CHN5_SYN_AC_2_CP_MON_REF_MASK) #define CHN5_SYN_AC_2_CP_MON_REF_RESET 0x0 #define CHN5_SYN_AC_2_CP_HIZ_UP_LSB 17 #define CHN5_SYN_AC_2_CP_HIZ_UP_MSB 17 #define CHN5_SYN_AC_2_CP_HIZ_UP_MASK 0x20000 #define CHN5_SYN_AC_2_CP_HIZ_UP_GET(x) (((x) & CHN5_SYN_AC_2_CP_HIZ_UP_MASK) >> CHN5_SYN_AC_2_CP_HIZ_UP_LSB) #define CHN5_SYN_AC_2_CP_HIZ_UP_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_CP_HIZ_UP_LSB) & CHN5_SYN_AC_2_CP_HIZ_UP_MASK) #define CHN5_SYN_AC_2_CP_HIZ_UP_RESET 0x0 #define CHN5_SYN_AC_2_CP_HIZ_DN_LSB 16 #define CHN5_SYN_AC_2_CP_HIZ_DN_MSB 16 #define CHN5_SYN_AC_2_CP_HIZ_DN_MASK 0x10000 #define CHN5_SYN_AC_2_CP_HIZ_DN_GET(x) (((x) & CHN5_SYN_AC_2_CP_HIZ_DN_MASK) >> CHN5_SYN_AC_2_CP_HIZ_DN_LSB) #define CHN5_SYN_AC_2_CP_HIZ_DN_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_CP_HIZ_DN_LSB) & CHN5_SYN_AC_2_CP_HIZ_DN_MASK) #define CHN5_SYN_AC_2_CP_HIZ_DN_RESET 0x0 #define CHN5_SYN_AC_2_CP_FORCE_DN_LSB 15 #define CHN5_SYN_AC_2_CP_FORCE_DN_MSB 15 #define CHN5_SYN_AC_2_CP_FORCE_DN_MASK 0x8000 #define CHN5_SYN_AC_2_CP_FORCE_DN_GET(x) (((x) & CHN5_SYN_AC_2_CP_FORCE_DN_MASK) >> CHN5_SYN_AC_2_CP_FORCE_DN_LSB) #define CHN5_SYN_AC_2_CP_FORCE_DN_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_CP_FORCE_DN_LSB) & CHN5_SYN_AC_2_CP_FORCE_DN_MASK) #define CHN5_SYN_AC_2_CP_FORCE_DN_RESET 0x0 #define CHN5_SYN_AC_2_CP_LOW_NBIAS_LSB 14 #define CHN5_SYN_AC_2_CP_LOW_NBIAS_MSB 14 #define CHN5_SYN_AC_2_CP_LOW_NBIAS_MASK 0x4000 #define CHN5_SYN_AC_2_CP_LOW_NBIAS_GET(x) (((x) & CHN5_SYN_AC_2_CP_LOW_NBIAS_MASK) >> CHN5_SYN_AC_2_CP_LOW_NBIAS_LSB) #define CHN5_SYN_AC_2_CP_LOW_NBIAS_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_CP_LOW_NBIAS_LSB) & CHN5_SYN_AC_2_CP_LOW_NBIAS_MASK) #define CHN5_SYN_AC_2_CP_LOW_NBIAS_RESET 0x1 #define CHN5_SYN_AC_2_RESERVED_0_LSB 13 #define CHN5_SYN_AC_2_RESERVED_0_MSB 13 #define CHN5_SYN_AC_2_RESERVED_0_MASK 0x2000 #define CHN5_SYN_AC_2_RESERVED_0_GET(x) (((x) & CHN5_SYN_AC_2_RESERVED_0_MASK) >> CHN5_SYN_AC_2_RESERVED_0_LSB) #define CHN5_SYN_AC_2_RESERVED_0_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_RESERVED_0_LSB) & CHN5_SYN_AC_2_RESERVED_0_MASK) #define CHN5_SYN_AC_2_RESERVED_0_RESET 0x0 #define CHN5_SYN_AC_2_SYN_ABUS_SEL_LSB 8 #define CHN5_SYN_AC_2_SYN_ABUS_SEL_MSB 12 #define CHN5_SYN_AC_2_SYN_ABUS_SEL_MASK 0x1f00 #define CHN5_SYN_AC_2_SYN_ABUS_SEL_GET(x) (((x) & CHN5_SYN_AC_2_SYN_ABUS_SEL_MASK) >> CHN5_SYN_AC_2_SYN_ABUS_SEL_LSB) #define CHN5_SYN_AC_2_SYN_ABUS_SEL_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_SYN_ABUS_SEL_LSB) & CHN5_SYN_AC_2_SYN_ABUS_SEL_MASK) #define CHN5_SYN_AC_2_SYN_ABUS_SEL_RESET 0x0 #define CHN5_SYN_AC_2_SYN_ABUSH_SEL_LSB 3 #define CHN5_SYN_AC_2_SYN_ABUSH_SEL_MSB 7 #define CHN5_SYN_AC_2_SYN_ABUSH_SEL_MASK 0xf8 #define CHN5_SYN_AC_2_SYN_ABUSH_SEL_GET(x) (((x) & CHN5_SYN_AC_2_SYN_ABUSH_SEL_MASK) >> CHN5_SYN_AC_2_SYN_ABUSH_SEL_LSB) #define CHN5_SYN_AC_2_SYN_ABUSH_SEL_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_SYN_ABUSH_SEL_LSB) & CHN5_SYN_AC_2_SYN_ABUSH_SEL_MASK) #define CHN5_SYN_AC_2_SYN_ABUSH_SEL_RESET 0x0 #define CHN5_SYN_AC_2_RFBUS_EN_VCO_LSB 2 #define CHN5_SYN_AC_2_RFBUS_EN_VCO_MSB 2 #define CHN5_SYN_AC_2_RFBUS_EN_VCO_MASK 0x4 #define CHN5_SYN_AC_2_RFBUS_EN_VCO_GET(x) (((x) & CHN5_SYN_AC_2_RFBUS_EN_VCO_MASK) >> CHN5_SYN_AC_2_RFBUS_EN_VCO_LSB) #define CHN5_SYN_AC_2_RFBUS_EN_VCO_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_RFBUS_EN_VCO_LSB) & CHN5_SYN_AC_2_RFBUS_EN_VCO_MASK) #define CHN5_SYN_AC_2_RFBUS_EN_VCO_RESET 0x0 #define CHN5_SYN_AC_2_RFBUS_EN_MULT_LSB 1 #define CHN5_SYN_AC_2_RFBUS_EN_MULT_MSB 1 #define CHN5_SYN_AC_2_RFBUS_EN_MULT_MASK 0x2 #define CHN5_SYN_AC_2_RFBUS_EN_MULT_GET(x) (((x) & CHN5_SYN_AC_2_RFBUS_EN_MULT_MASK) >> CHN5_SYN_AC_2_RFBUS_EN_MULT_LSB) #define CHN5_SYN_AC_2_RFBUS_EN_MULT_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_RFBUS_EN_MULT_LSB) & CHN5_SYN_AC_2_RFBUS_EN_MULT_MASK) #define CHN5_SYN_AC_2_RFBUS_EN_MULT_RESET 0x0 #define CHN5_SYN_AC_2_LPF_VHMLGEN_BYP_LSB 0 #define CHN5_SYN_AC_2_LPF_VHMLGEN_BYP_MSB 0 #define CHN5_SYN_AC_2_LPF_VHMLGEN_BYP_MASK 0x1 #define CHN5_SYN_AC_2_LPF_VHMLGEN_BYP_GET(x) (((x) & CHN5_SYN_AC_2_LPF_VHMLGEN_BYP_MASK) >> CHN5_SYN_AC_2_LPF_VHMLGEN_BYP_LSB) #define CHN5_SYN_AC_2_LPF_VHMLGEN_BYP_SET(x) (((0 | (x)) << CHN5_SYN_AC_2_LPF_VHMLGEN_BYP_LSB) & CHN5_SYN_AC_2_LPF_VHMLGEN_BYP_MASK) #define CHN5_SYN_AC_2_LPF_VHMLGEN_BYP_RESET 0x0 #define CHN5_SYN_AC_2_ADDRESS (0x30 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_AC_2_RSTMASK 0xffffffff #define CHN5_SYN_AC_2_RESET 0x33604000 // 0x34 (CHN5_SYN_AC_3) #define CHN5_SYN_AC_3_LPF_R1_LSB 28 #define CHN5_SYN_AC_3_LPF_R1_MSB 31 #define CHN5_SYN_AC_3_LPF_R1_MASK 0xf0000000 #define CHN5_SYN_AC_3_LPF_R1_GET(x) (((x) & CHN5_SYN_AC_3_LPF_R1_MASK) >> CHN5_SYN_AC_3_LPF_R1_LSB) #define CHN5_SYN_AC_3_LPF_R1_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_LPF_R1_LSB) & CHN5_SYN_AC_3_LPF_R1_MASK) #define CHN5_SYN_AC_3_LPF_R1_RESET 0x7 #define CHN5_SYN_AC_3_LPF_R2_LSB 24 #define CHN5_SYN_AC_3_LPF_R2_MSB 27 #define CHN5_SYN_AC_3_LPF_R2_MASK 0xf000000 #define CHN5_SYN_AC_3_LPF_R2_GET(x) (((x) & CHN5_SYN_AC_3_LPF_R2_MASK) >> CHN5_SYN_AC_3_LPF_R2_LSB) #define CHN5_SYN_AC_3_LPF_R2_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_LPF_R2_LSB) & CHN5_SYN_AC_3_LPF_R2_MASK) #define CHN5_SYN_AC_3_LPF_R2_RESET 0x5 #define CHN5_SYN_AC_3_RESERVED_0_LSB 22 #define CHN5_SYN_AC_3_RESERVED_0_MSB 23 #define CHN5_SYN_AC_3_RESERVED_0_MASK 0xc00000 #define CHN5_SYN_AC_3_RESERVED_0_GET(x) (((x) & CHN5_SYN_AC_3_RESERVED_0_MASK) >> CHN5_SYN_AC_3_RESERVED_0_LSB) #define CHN5_SYN_AC_3_RESERVED_0_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_RESERVED_0_LSB) & CHN5_SYN_AC_3_RESERVED_0_MASK) #define CHN5_SYN_AC_3_RESERVED_0_RESET 0x0 #define CHN5_SYN_AC_3_LPF_C1_LSB 20 #define CHN5_SYN_AC_3_LPF_C1_MSB 21 #define CHN5_SYN_AC_3_LPF_C1_MASK 0x300000 #define CHN5_SYN_AC_3_LPF_C1_GET(x) (((x) & CHN5_SYN_AC_3_LPF_C1_MASK) >> CHN5_SYN_AC_3_LPF_C1_LSB) #define CHN5_SYN_AC_3_LPF_C1_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_LPF_C1_LSB) & CHN5_SYN_AC_3_LPF_C1_MASK) #define CHN5_SYN_AC_3_LPF_C1_RESET 0x1 #define CHN5_SYN_AC_3_LPF_C2_LSB 16 #define CHN5_SYN_AC_3_LPF_C2_MSB 19 #define CHN5_SYN_AC_3_LPF_C2_MASK 0xf0000 #define CHN5_SYN_AC_3_LPF_C2_GET(x) (((x) & CHN5_SYN_AC_3_LPF_C2_MASK) >> CHN5_SYN_AC_3_LPF_C2_LSB) #define CHN5_SYN_AC_3_LPF_C2_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_LPF_C2_LSB) & CHN5_SYN_AC_3_LPF_C2_MASK) #define CHN5_SYN_AC_3_LPF_C2_RESET 0x5 #define CHN5_SYN_AC_3_LPF_C3_LSB 12 #define CHN5_SYN_AC_3_LPF_C3_MSB 15 #define CHN5_SYN_AC_3_LPF_C3_MASK 0xf000 #define CHN5_SYN_AC_3_LPF_C3_GET(x) (((x) & CHN5_SYN_AC_3_LPF_C3_MASK) >> CHN5_SYN_AC_3_LPF_C3_LSB) #define CHN5_SYN_AC_3_LPF_C3_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_LPF_C3_LSB) & CHN5_SYN_AC_3_LPF_C3_MASK) #define CHN5_SYN_AC_3_LPF_C3_RESET 0x5 #define CHN5_SYN_AC_3_RESERVED_1_LSB 11 #define CHN5_SYN_AC_3_RESERVED_1_MSB 11 #define CHN5_SYN_AC_3_RESERVED_1_MASK 0x800 #define CHN5_SYN_AC_3_RESERVED_1_GET(x) (((x) & CHN5_SYN_AC_3_RESERVED_1_MASK) >> CHN5_SYN_AC_3_RESERVED_1_LSB) #define CHN5_SYN_AC_3_RESERVED_1_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_RESERVED_1_LSB) & CHN5_SYN_AC_3_RESERVED_1_MASK) #define CHN5_SYN_AC_3_RESERVED_1_RESET 0x0 #define CHN5_SYN_AC_3_LPF_VH_LSB 8 #define CHN5_SYN_AC_3_LPF_VH_MSB 10 #define CHN5_SYN_AC_3_LPF_VH_MASK 0x700 #define CHN5_SYN_AC_3_LPF_VH_GET(x) (((x) & CHN5_SYN_AC_3_LPF_VH_MASK) >> CHN5_SYN_AC_3_LPF_VH_LSB) #define CHN5_SYN_AC_3_LPF_VH_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_LPF_VH_LSB) & CHN5_SYN_AC_3_LPF_VH_MASK) #define CHN5_SYN_AC_3_LPF_VH_RESET 0x2 #define CHN5_SYN_AC_3_RESERVED_2_LSB 7 #define CHN5_SYN_AC_3_RESERVED_2_MSB 7 #define CHN5_SYN_AC_3_RESERVED_2_MASK 0x80 #define CHN5_SYN_AC_3_RESERVED_2_GET(x) (((x) & CHN5_SYN_AC_3_RESERVED_2_MASK) >> CHN5_SYN_AC_3_RESERVED_2_LSB) #define CHN5_SYN_AC_3_RESERVED_2_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_RESERVED_2_LSB) & CHN5_SYN_AC_3_RESERVED_2_MASK) #define CHN5_SYN_AC_3_RESERVED_2_RESET 0x0 #define CHN5_SYN_AC_3_LPF_VM_LSB 4 #define CHN5_SYN_AC_3_LPF_VM_MSB 6 #define CHN5_SYN_AC_3_LPF_VM_MASK 0x70 #define CHN5_SYN_AC_3_LPF_VM_GET(x) (((x) & CHN5_SYN_AC_3_LPF_VM_MASK) >> CHN5_SYN_AC_3_LPF_VM_LSB) #define CHN5_SYN_AC_3_LPF_VM_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_LPF_VM_LSB) & CHN5_SYN_AC_3_LPF_VM_MASK) #define CHN5_SYN_AC_3_LPF_VM_RESET 0x4 #define CHN5_SYN_AC_3_RESERVED_3_LSB 3 #define CHN5_SYN_AC_3_RESERVED_3_MSB 3 #define CHN5_SYN_AC_3_RESERVED_3_MASK 0x8 #define CHN5_SYN_AC_3_RESERVED_3_GET(x) (((x) & CHN5_SYN_AC_3_RESERVED_3_MASK) >> CHN5_SYN_AC_3_RESERVED_3_LSB) #define CHN5_SYN_AC_3_RESERVED_3_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_RESERVED_3_LSB) & CHN5_SYN_AC_3_RESERVED_3_MASK) #define CHN5_SYN_AC_3_RESERVED_3_RESET 0x0 #define CHN5_SYN_AC_3_LPF_VL_LSB 0 #define CHN5_SYN_AC_3_LPF_VL_MSB 2 #define CHN5_SYN_AC_3_LPF_VL_MASK 0x7 #define CHN5_SYN_AC_3_LPF_VL_GET(x) (((x) & CHN5_SYN_AC_3_LPF_VL_MASK) >> CHN5_SYN_AC_3_LPF_VL_LSB) #define CHN5_SYN_AC_3_LPF_VL_SET(x) (((0 | (x)) << CHN5_SYN_AC_3_LPF_VL_LSB) & CHN5_SYN_AC_3_LPF_VL_MASK) #define CHN5_SYN_AC_3_LPF_VL_RESET 0x6 #define CHN5_SYN_AC_3_ADDRESS (0x34 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_AC_3_RSTMASK 0xffffffff #define CHN5_SYN_AC_3_RESET 0x75155246 // 0x38 (CHN5_SYN_PAL_READ) #define CHN5_SYN_PAL_READ_PAL_FLIP_MDIV_LSB 28 #define CHN5_SYN_PAL_READ_PAL_FLIP_MDIV_MSB 31 #define CHN5_SYN_PAL_READ_PAL_FLIP_MDIV_MASK 0xf0000000 #define CHN5_SYN_PAL_READ_PAL_FLIP_MDIV_GET(x) (((x) & CHN5_SYN_PAL_READ_PAL_FLIP_MDIV_MASK) >> CHN5_SYN_PAL_READ_PAL_FLIP_MDIV_LSB) #define CHN5_SYN_PAL_READ_PAL_FLIP_MDIV_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PAL_FLIP_MDIV_LSB) & CHN5_SYN_PAL_READ_PAL_FLIP_MDIV_MASK) #define CHN5_SYN_PAL_READ_PAL_FLIP_MDIV_RESET 0x0 #define CHN5_SYN_PAL_READ_PAL_FLIP_RXDIV_LSB 24 #define CHN5_SYN_PAL_READ_PAL_FLIP_RXDIV_MSB 27 #define CHN5_SYN_PAL_READ_PAL_FLIP_RXDIV_MASK 0xf000000 #define CHN5_SYN_PAL_READ_PAL_FLIP_RXDIV_GET(x) (((x) & CHN5_SYN_PAL_READ_PAL_FLIP_RXDIV_MASK) >> CHN5_SYN_PAL_READ_PAL_FLIP_RXDIV_LSB) #define CHN5_SYN_PAL_READ_PAL_FLIP_RXDIV_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PAL_FLIP_RXDIV_LSB) & CHN5_SYN_PAL_READ_PAL_FLIP_RXDIV_MASK) #define CHN5_SYN_PAL_READ_PAL_FLIP_RXDIV_RESET 0x0 #define CHN5_SYN_PAL_READ_PAL_FLIP_TXDIV_LSB 20 #define CHN5_SYN_PAL_READ_PAL_FLIP_TXDIV_MSB 23 #define CHN5_SYN_PAL_READ_PAL_FLIP_TXDIV_MASK 0xf00000 #define CHN5_SYN_PAL_READ_PAL_FLIP_TXDIV_GET(x) (((x) & CHN5_SYN_PAL_READ_PAL_FLIP_TXDIV_MASK) >> CHN5_SYN_PAL_READ_PAL_FLIP_TXDIV_LSB) #define CHN5_SYN_PAL_READ_PAL_FLIP_TXDIV_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PAL_FLIP_TXDIV_LSB) & CHN5_SYN_PAL_READ_PAL_FLIP_TXDIV_MASK) #define CHN5_SYN_PAL_READ_PAL_FLIP_TXDIV_RESET 0x0 #define CHN5_SYN_PAL_READ_PAL_INVERT_MDIV_LSB 17 #define CHN5_SYN_PAL_READ_PAL_INVERT_MDIV_MSB 19 #define CHN5_SYN_PAL_READ_PAL_INVERT_MDIV_MASK 0xe0000 #define CHN5_SYN_PAL_READ_PAL_INVERT_MDIV_GET(x) (((x) & CHN5_SYN_PAL_READ_PAL_INVERT_MDIV_MASK) >> CHN5_SYN_PAL_READ_PAL_INVERT_MDIV_LSB) #define CHN5_SYN_PAL_READ_PAL_INVERT_MDIV_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PAL_INVERT_MDIV_LSB) & CHN5_SYN_PAL_READ_PAL_INVERT_MDIV_MASK) #define CHN5_SYN_PAL_READ_PAL_INVERT_MDIV_RESET 0x0 #define CHN5_SYN_PAL_READ_PAL_INVERT_RXDIV_LSB 14 #define CHN5_SYN_PAL_READ_PAL_INVERT_RXDIV_MSB 16 #define CHN5_SYN_PAL_READ_PAL_INVERT_RXDIV_MASK 0x1c000 #define CHN5_SYN_PAL_READ_PAL_INVERT_RXDIV_GET(x) (((x) & CHN5_SYN_PAL_READ_PAL_INVERT_RXDIV_MASK) >> CHN5_SYN_PAL_READ_PAL_INVERT_RXDIV_LSB) #define CHN5_SYN_PAL_READ_PAL_INVERT_RXDIV_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PAL_INVERT_RXDIV_LSB) & CHN5_SYN_PAL_READ_PAL_INVERT_RXDIV_MASK) #define CHN5_SYN_PAL_READ_PAL_INVERT_RXDIV_RESET 0x0 #define CHN5_SYN_PAL_READ_PAL_INVERT_TXDIV_LSB 11 #define CHN5_SYN_PAL_READ_PAL_INVERT_TXDIV_MSB 13 #define CHN5_SYN_PAL_READ_PAL_INVERT_TXDIV_MASK 0x3800 #define CHN5_SYN_PAL_READ_PAL_INVERT_TXDIV_GET(x) (((x) & CHN5_SYN_PAL_READ_PAL_INVERT_TXDIV_MASK) >> CHN5_SYN_PAL_READ_PAL_INVERT_TXDIV_LSB) #define CHN5_SYN_PAL_READ_PAL_INVERT_TXDIV_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PAL_INVERT_TXDIV_LSB) & CHN5_SYN_PAL_READ_PAL_INVERT_TXDIV_MASK) #define CHN5_SYN_PAL_READ_PAL_INVERT_TXDIV_RESET 0x0 #define CHN5_SYN_PAL_READ_PAL_RESULT_MDIV_LSB 8 #define CHN5_SYN_PAL_READ_PAL_RESULT_MDIV_MSB 10 #define CHN5_SYN_PAL_READ_PAL_RESULT_MDIV_MASK 0x700 #define CHN5_SYN_PAL_READ_PAL_RESULT_MDIV_GET(x) (((x) & CHN5_SYN_PAL_READ_PAL_RESULT_MDIV_MASK) >> CHN5_SYN_PAL_READ_PAL_RESULT_MDIV_LSB) #define CHN5_SYN_PAL_READ_PAL_RESULT_MDIV_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PAL_RESULT_MDIV_LSB) & CHN5_SYN_PAL_READ_PAL_RESULT_MDIV_MASK) #define CHN5_SYN_PAL_READ_PAL_RESULT_MDIV_RESET 0x0 #define CHN5_SYN_PAL_READ_PAL_RESULT_RXDIV_LSB 5 #define CHN5_SYN_PAL_READ_PAL_RESULT_RXDIV_MSB 7 #define CHN5_SYN_PAL_READ_PAL_RESULT_RXDIV_MASK 0xe0 #define CHN5_SYN_PAL_READ_PAL_RESULT_RXDIV_GET(x) (((x) & CHN5_SYN_PAL_READ_PAL_RESULT_RXDIV_MASK) >> CHN5_SYN_PAL_READ_PAL_RESULT_RXDIV_LSB) #define CHN5_SYN_PAL_READ_PAL_RESULT_RXDIV_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PAL_RESULT_RXDIV_LSB) & CHN5_SYN_PAL_READ_PAL_RESULT_RXDIV_MASK) #define CHN5_SYN_PAL_READ_PAL_RESULT_RXDIV_RESET 0x0 #define CHN5_SYN_PAL_READ_PAL_RESULT_TXDIV_LSB 2 #define CHN5_SYN_PAL_READ_PAL_RESULT_TXDIV_MSB 4 #define CHN5_SYN_PAL_READ_PAL_RESULT_TXDIV_MASK 0x1c #define CHN5_SYN_PAL_READ_PAL_RESULT_TXDIV_GET(x) (((x) & CHN5_SYN_PAL_READ_PAL_RESULT_TXDIV_MASK) >> CHN5_SYN_PAL_READ_PAL_RESULT_TXDIV_LSB) #define CHN5_SYN_PAL_READ_PAL_RESULT_TXDIV_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PAL_RESULT_TXDIV_LSB) & CHN5_SYN_PAL_READ_PAL_RESULT_TXDIV_MASK) #define CHN5_SYN_PAL_READ_PAL_RESULT_TXDIV_RESET 0x0 #define CHN5_SYN_PAL_READ_PAL_BIST_FAIL_LSB 1 #define CHN5_SYN_PAL_READ_PAL_BIST_FAIL_MSB 1 #define CHN5_SYN_PAL_READ_PAL_BIST_FAIL_MASK 0x2 #define CHN5_SYN_PAL_READ_PAL_BIST_FAIL_GET(x) (((x) & CHN5_SYN_PAL_READ_PAL_BIST_FAIL_MASK) >> CHN5_SYN_PAL_READ_PAL_BIST_FAIL_LSB) #define CHN5_SYN_PAL_READ_PAL_BIST_FAIL_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PAL_BIST_FAIL_LSB) & CHN5_SYN_PAL_READ_PAL_BIST_FAIL_MASK) #define CHN5_SYN_PAL_READ_PAL_BIST_FAIL_RESET 0x0 #define CHN5_SYN_PAL_READ_PP_PAL_BIST_FAIL_LSB 0 #define CHN5_SYN_PAL_READ_PP_PAL_BIST_FAIL_MSB 0 #define CHN5_SYN_PAL_READ_PP_PAL_BIST_FAIL_MASK 0x1 #define CHN5_SYN_PAL_READ_PP_PAL_BIST_FAIL_GET(x) (((x) & CHN5_SYN_PAL_READ_PP_PAL_BIST_FAIL_MASK) >> CHN5_SYN_PAL_READ_PP_PAL_BIST_FAIL_LSB) #define CHN5_SYN_PAL_READ_PP_PAL_BIST_FAIL_SET(x) (((0 | (x)) << CHN5_SYN_PAL_READ_PP_PAL_BIST_FAIL_LSB) & CHN5_SYN_PAL_READ_PP_PAL_BIST_FAIL_MASK) #define CHN5_SYN_PAL_READ_PP_PAL_BIST_FAIL_RESET 0x0 #define CHN5_SYN_PAL_READ_ADDRESS (0x38 + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_PAL_READ_RSTMASK 0xffffffff #define CHN5_SYN_PAL_READ_RESET 0x0 // 0x3c (CHN5_SYN_READ) #define CHN5_SYN_READ_MULT_VCOCAP_LSB 28 #define CHN5_SYN_READ_MULT_VCOCAP_MSB 31 #define CHN5_SYN_READ_MULT_VCOCAP_MASK 0xf0000000 #define CHN5_SYN_READ_MULT_VCOCAP_GET(x) (((x) & CHN5_SYN_READ_MULT_VCOCAP_MASK) >> CHN5_SYN_READ_MULT_VCOCAP_LSB) #define CHN5_SYN_READ_MULT_VCOCAP_SET(x) (((0 | (x)) << CHN5_SYN_READ_MULT_VCOCAP_LSB) & CHN5_SYN_READ_MULT_VCOCAP_MASK) #define CHN5_SYN_READ_MULT_VCOCAP_RESET 0x0 #define CHN5_SYN_READ_MULT_VCOCUR_LSB 24 #define CHN5_SYN_READ_MULT_VCOCUR_MSB 27 #define CHN5_SYN_READ_MULT_VCOCUR_MASK 0xf000000 #define CHN5_SYN_READ_MULT_VCOCUR_GET(x) (((x) & CHN5_SYN_READ_MULT_VCOCUR_MASK) >> CHN5_SYN_READ_MULT_VCOCUR_LSB) #define CHN5_SYN_READ_MULT_VCOCUR_SET(x) (((0 | (x)) << CHN5_SYN_READ_MULT_VCOCUR_LSB) & CHN5_SYN_READ_MULT_VCOCUR_MASK) #define CHN5_SYN_READ_MULT_VCOCUR_RESET 0x0 #define CHN5_SYN_READ_MULT_SM_STATE_LSB 22 #define CHN5_SYN_READ_MULT_SM_STATE_MSB 23 #define CHN5_SYN_READ_MULT_SM_STATE_MASK 0xc00000 #define CHN5_SYN_READ_MULT_SM_STATE_GET(x) (((x) & CHN5_SYN_READ_MULT_SM_STATE_MASK) >> CHN5_SYN_READ_MULT_SM_STATE_LSB) #define CHN5_SYN_READ_MULT_SM_STATE_SET(x) (((0 | (x)) << CHN5_SYN_READ_MULT_SM_STATE_LSB) & CHN5_SYN_READ_MULT_SM_STATE_MASK) #define CHN5_SYN_READ_MULT_SM_STATE_RESET 0x0 #define CHN5_SYN_READ_MULT_IS_LOCKED_LSB 21 #define CHN5_SYN_READ_MULT_IS_LOCKED_MSB 21 #define CHN5_SYN_READ_MULT_IS_LOCKED_MASK 0x200000 #define CHN5_SYN_READ_MULT_IS_LOCKED_GET(x) (((x) & CHN5_SYN_READ_MULT_IS_LOCKED_MASK) >> CHN5_SYN_READ_MULT_IS_LOCKED_LSB) #define CHN5_SYN_READ_MULT_IS_LOCKED_SET(x) (((0 | (x)) << CHN5_SYN_READ_MULT_IS_LOCKED_LSB) & CHN5_SYN_READ_MULT_IS_LOCKED_MASK) #define CHN5_SYN_READ_MULT_IS_LOCKED_RESET 0x0 #define CHN5_SYN_READ_MULT_CAPCUR_EXHAUSTED_LSB 20 #define CHN5_SYN_READ_MULT_CAPCUR_EXHAUSTED_MSB 20 #define CHN5_SYN_READ_MULT_CAPCUR_EXHAUSTED_MASK 0x100000 #define CHN5_SYN_READ_MULT_CAPCUR_EXHAUSTED_GET(x) (((x) & CHN5_SYN_READ_MULT_CAPCUR_EXHAUSTED_MASK) >> CHN5_SYN_READ_MULT_CAPCUR_EXHAUSTED_LSB) #define CHN5_SYN_READ_MULT_CAPCUR_EXHAUSTED_SET(x) (((0 | (x)) << CHN5_SYN_READ_MULT_CAPCUR_EXHAUSTED_LSB) & CHN5_SYN_READ_MULT_CAPCUR_EXHAUSTED_MASK) #define CHN5_SYN_READ_MULT_CAPCUR_EXHAUSTED_RESET 0x0 #define CHN5_SYN_READ_MULT_VC2HI_LSB 19 #define CHN5_SYN_READ_MULT_VC2HI_MSB 19 #define CHN5_SYN_READ_MULT_VC2HI_MASK 0x80000 #define CHN5_SYN_READ_MULT_VC2HI_GET(x) (((x) & CHN5_SYN_READ_MULT_VC2HI_MASK) >> CHN5_SYN_READ_MULT_VC2HI_LSB) #define CHN5_SYN_READ_MULT_VC2HI_SET(x) (((0 | (x)) << CHN5_SYN_READ_MULT_VC2HI_LSB) & CHN5_SYN_READ_MULT_VC2HI_MASK) #define CHN5_SYN_READ_MULT_VC2HI_RESET 0x0 #define CHN5_SYN_READ_MULT_VC2LO_LSB 18 #define CHN5_SYN_READ_MULT_VC2LO_MSB 18 #define CHN5_SYN_READ_MULT_VC2LO_MASK 0x40000 #define CHN5_SYN_READ_MULT_VC2LO_GET(x) (((x) & CHN5_SYN_READ_MULT_VC2LO_MASK) >> CHN5_SYN_READ_MULT_VC2LO_LSB) #define CHN5_SYN_READ_MULT_VC2LO_SET(x) (((0 | (x)) << CHN5_SYN_READ_MULT_VC2LO_LSB) & CHN5_SYN_READ_MULT_VC2LO_MASK) #define CHN5_SYN_READ_MULT_VC2LO_RESET 0x0 #define CHN5_SYN_READ_LPF_VHIGH_LSB 17 #define CHN5_SYN_READ_LPF_VHIGH_MSB 17 #define CHN5_SYN_READ_LPF_VHIGH_MASK 0x20000 #define CHN5_SYN_READ_LPF_VHIGH_GET(x) (((x) & CHN5_SYN_READ_LPF_VHIGH_MASK) >> CHN5_SYN_READ_LPF_VHIGH_LSB) #define CHN5_SYN_READ_LPF_VHIGH_SET(x) (((0 | (x)) << CHN5_SYN_READ_LPF_VHIGH_LSB) & CHN5_SYN_READ_LPF_VHIGH_MASK) #define CHN5_SYN_READ_LPF_VHIGH_RESET 0x0 #define CHN5_SYN_READ_LPF_VLOW_LSB 16 #define CHN5_SYN_READ_LPF_VLOW_MSB 16 #define CHN5_SYN_READ_LPF_VLOW_MASK 0x10000 #define CHN5_SYN_READ_LPF_VLOW_GET(x) (((x) & CHN5_SYN_READ_LPF_VLOW_MASK) >> CHN5_SYN_READ_LPF_VLOW_LSB) #define CHN5_SYN_READ_LPF_VLOW_SET(x) (((0 | (x)) << CHN5_SYN_READ_LPF_VLOW_LSB) & CHN5_SYN_READ_LPF_VLOW_MASK) #define CHN5_SYN_READ_LPF_VLOW_RESET 0x0 #define CHN5_SYN_READ_PLL_IS_LOCKED_LSB 15 #define CHN5_SYN_READ_PLL_IS_LOCKED_MSB 15 #define CHN5_SYN_READ_PLL_IS_LOCKED_MASK 0x8000 #define CHN5_SYN_READ_PLL_IS_LOCKED_GET(x) (((x) & CHN5_SYN_READ_PLL_IS_LOCKED_MASK) >> CHN5_SYN_READ_PLL_IS_LOCKED_LSB) #define CHN5_SYN_READ_PLL_IS_LOCKED_SET(x) (((0 | (x)) << CHN5_SYN_READ_PLL_IS_LOCKED_LSB) & CHN5_SYN_READ_PLL_IS_LOCKED_MASK) #define CHN5_SYN_READ_PLL_IS_LOCKED_RESET 0x0 #define CHN5_SYN_READ_VCO_AMP_COMP_O_LSB 14 #define CHN5_SYN_READ_VCO_AMP_COMP_O_MSB 14 #define CHN5_SYN_READ_VCO_AMP_COMP_O_MASK 0x4000 #define CHN5_SYN_READ_VCO_AMP_COMP_O_GET(x) (((x) & CHN5_SYN_READ_VCO_AMP_COMP_O_MASK) >> CHN5_SYN_READ_VCO_AMP_COMP_O_LSB) #define CHN5_SYN_READ_VCO_AMP_COMP_O_SET(x) (((0 | (x)) << CHN5_SYN_READ_VCO_AMP_COMP_O_LSB) & CHN5_SYN_READ_VCO_AMP_COMP_O_MASK) #define CHN5_SYN_READ_VCO_AMP_COMP_O_RESET 0x0 #define CHN5_SYN_READ_LO_DIST_ENCAP_LSB 11 #define CHN5_SYN_READ_LO_DIST_ENCAP_MSB 13 #define CHN5_SYN_READ_LO_DIST_ENCAP_MASK 0x3800 #define CHN5_SYN_READ_LO_DIST_ENCAP_GET(x) (((x) & CHN5_SYN_READ_LO_DIST_ENCAP_MASK) >> CHN5_SYN_READ_LO_DIST_ENCAP_LSB) #define CHN5_SYN_READ_LO_DIST_ENCAP_SET(x) (((0 | (x)) << CHN5_SYN_READ_LO_DIST_ENCAP_LSB) & CHN5_SYN_READ_LO_DIST_ENCAP_MASK) #define CHN5_SYN_READ_LO_DIST_ENCAP_RESET 0x0 #define CHN5_SYN_READ_LO_GEN_ENCAP_LSB 8 #define CHN5_SYN_READ_LO_GEN_ENCAP_MSB 10 #define CHN5_SYN_READ_LO_GEN_ENCAP_MASK 0x700 #define CHN5_SYN_READ_LO_GEN_ENCAP_GET(x) (((x) & CHN5_SYN_READ_LO_GEN_ENCAP_MASK) >> CHN5_SYN_READ_LO_GEN_ENCAP_LSB) #define CHN5_SYN_READ_LO_GEN_ENCAP_SET(x) (((0 | (x)) << CHN5_SYN_READ_LO_GEN_ENCAP_LSB) & CHN5_SYN_READ_LO_GEN_ENCAP_MASK) #define CHN5_SYN_READ_LO_GEN_ENCAP_RESET 0x0 #define CHN5_SYN_READ_PAL_RST23_CHK_FAIL_LSB 7 #define CHN5_SYN_READ_PAL_RST23_CHK_FAIL_MSB 7 #define CHN5_SYN_READ_PAL_RST23_CHK_FAIL_MASK 0x80 #define CHN5_SYN_READ_PAL_RST23_CHK_FAIL_GET(x) (((x) & CHN5_SYN_READ_PAL_RST23_CHK_FAIL_MASK) >> CHN5_SYN_READ_PAL_RST23_CHK_FAIL_LSB) #define CHN5_SYN_READ_PAL_RST23_CHK_FAIL_SET(x) (((0 | (x)) << CHN5_SYN_READ_PAL_RST23_CHK_FAIL_LSB) & CHN5_SYN_READ_PAL_RST23_CHK_FAIL_MASK) #define CHN5_SYN_READ_PAL_RST23_CHK_FAIL_RESET 0x0 #define CHN5_SYN_READ_PAL_FLIP_MDIV_CHK_FAIL_LSB 6 #define CHN5_SYN_READ_PAL_FLIP_MDIV_CHK_FAIL_MSB 6 #define CHN5_SYN_READ_PAL_FLIP_MDIV_CHK_FAIL_MASK 0x40 #define CHN5_SYN_READ_PAL_FLIP_MDIV_CHK_FAIL_GET(x) (((x) & CHN5_SYN_READ_PAL_FLIP_MDIV_CHK_FAIL_MASK) >> CHN5_SYN_READ_PAL_FLIP_MDIV_CHK_FAIL_LSB) #define CHN5_SYN_READ_PAL_FLIP_MDIV_CHK_FAIL_SET(x) (((0 | (x)) << CHN5_SYN_READ_PAL_FLIP_MDIV_CHK_FAIL_LSB) & CHN5_SYN_READ_PAL_FLIP_MDIV_CHK_FAIL_MASK) #define CHN5_SYN_READ_PAL_FLIP_MDIV_CHK_FAIL_RESET 0x0 #define CHN5_SYN_READ_PAL_RST2_CHK_FAIL_LSB 5 #define CHN5_SYN_READ_PAL_RST2_CHK_FAIL_MSB 5 #define CHN5_SYN_READ_PAL_RST2_CHK_FAIL_MASK 0x20 #define CHN5_SYN_READ_PAL_RST2_CHK_FAIL_GET(x) (((x) & CHN5_SYN_READ_PAL_RST2_CHK_FAIL_MASK) >> CHN5_SYN_READ_PAL_RST2_CHK_FAIL_LSB) #define CHN5_SYN_READ_PAL_RST2_CHK_FAIL_SET(x) (((0 | (x)) << CHN5_SYN_READ_PAL_RST2_CHK_FAIL_LSB) & CHN5_SYN_READ_PAL_RST2_CHK_FAIL_MASK) #define CHN5_SYN_READ_PAL_RST2_CHK_FAIL_RESET 0x0 #define CHN5_SYN_READ_PAL_FLIP_RTXDIV_CHK_FAIL_LSB 4 #define CHN5_SYN_READ_PAL_FLIP_RTXDIV_CHK_FAIL_MSB 4 #define CHN5_SYN_READ_PAL_FLIP_RTXDIV_CHK_FAIL_MASK 0x10 #define CHN5_SYN_READ_PAL_FLIP_RTXDIV_CHK_FAIL_GET(x) (((x) & CHN5_SYN_READ_PAL_FLIP_RTXDIV_CHK_FAIL_MASK) >> CHN5_SYN_READ_PAL_FLIP_RTXDIV_CHK_FAIL_LSB) #define CHN5_SYN_READ_PAL_FLIP_RTXDIV_CHK_FAIL_SET(x) (((0 | (x)) << CHN5_SYN_READ_PAL_FLIP_RTXDIV_CHK_FAIL_LSB) & CHN5_SYN_READ_PAL_FLIP_RTXDIV_CHK_FAIL_MASK) #define CHN5_SYN_READ_PAL_FLIP_RTXDIV_CHK_FAIL_RESET 0x0 #define CHN5_SYN_READ_ADDRESS (0x3c + __CHN5_SYN_REG_CSR_BASE_ADDRESS) #define CHN5_SYN_READ_RSTMASK 0xfffffff0 #define CHN5_SYN_READ_RESET 0x0 #endif /* _CHN5_SYN_REG_CSR_H_ */