// // ----------------------------------------------------------------------------- // Copyright (c) 2011-2014 Qualcomm Atheros, Inc. All rights reserved. // ----------------------------------------------------------------------------- // FILE : chn1_reg_map.h // DESCRIPTION : Software Header File for WiFi 2.5 // THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT // ----------------------------------------------------------------------------- // #ifndef _PHY_CHN1_REG_MAP_H_ #define _PHY_CHN1_REG_MAP_H_ #ifndef __PHY_CHN1_REG_MAP_BASE_ADDRESS #define __PHY_CHN1_REG_MAP_BASE_ADDRESS (0x11400) #endif // 0x58 (PHY_BB_RX_NOTCH_CNTL_2_PRI_B1) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_Q_PRI_B1_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_Q_PRI_B1_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_Q_PRI_B1_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_Q_PRI_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_Q_PRI_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_Q_PRI_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_Q_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_Q_PRI_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_Q_PRI_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_Q_PRI_B1_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_I_PRI_B1_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_I_PRI_B1_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_I_PRI_B1_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_I_PRI_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_I_PRI_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_I_PRI_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_I_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_I_PRI_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_I_PRI_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_NOTCH_CORR_SPUR1_I_PRI_B1_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_ADDRESS (0x58 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_2_PRI_B1_RESET 0x400 // 0x5c (PHY_BB_RX_NOTCH_CNTL_3_PRI_B1) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_Q_PRI_B1_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_Q_PRI_B1_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_Q_PRI_B1_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_Q_PRI_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_Q_PRI_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_Q_PRI_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_Q_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_Q_PRI_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_Q_PRI_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_Q_PRI_B1_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_I_PRI_B1_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_I_PRI_B1_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_I_PRI_B1_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_I_PRI_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_I_PRI_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_I_PRI_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_I_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_I_PRI_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_I_PRI_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_NOTCH_CORR_SPUR2_I_PRI_B1_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_ADDRESS (0x5c + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_3_PRI_B1_RESET 0x400 // 0x60 (PHY_BB_RX_NOTCH_CNTL_4_PRI_B1) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_Q_PRI_B1_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_Q_PRI_B1_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_Q_PRI_B1_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_Q_PRI_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_Q_PRI_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_Q_PRI_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_Q_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_Q_PRI_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_Q_PRI_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_Q_PRI_B1_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_I_PRI_B1_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_I_PRI_B1_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_I_PRI_B1_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_I_PRI_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_I_PRI_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_I_PRI_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_I_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_I_PRI_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_I_PRI_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_NOTCH_CORR_DC_I_PRI_B1_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_ADDRESS (0x60 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_4_PRI_B1_RESET 0x400 // 0x64 (PHY_BB_RX_NOTCH_CNTL_5_PRI_B1) #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_NOTCH_CORR_AGG_I_PRI_B1_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_NOTCH_CORR_AGG_I_PRI_B1_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_NOTCH_CORR_AGG_I_PRI_B1_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_NOTCH_CORR_AGG_I_PRI_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_NOTCH_CORR_AGG_I_PRI_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_NOTCH_CORR_AGG_I_PRI_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_NOTCH_CORR_AGG_I_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_NOTCH_CORR_AGG_I_PRI_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_NOTCH_CORR_AGG_I_PRI_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_NOTCH_CORR_AGG_I_PRI_B1_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_ADDRESS (0x64 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_RSTMASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_5_PRI_B1_RESET 0x400 // 0x68 (PHY_BB_RX_NOTCH_CNTL_2_EXT_B1) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_Q_EXT_B1_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_Q_EXT_B1_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_Q_EXT_B1_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_Q_EXT_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_Q_EXT_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_Q_EXT_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_Q_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_Q_EXT_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_Q_EXT_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_Q_EXT_B1_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_I_EXT_B1_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_I_EXT_B1_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_I_EXT_B1_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_I_EXT_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_I_EXT_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_I_EXT_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_I_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_I_EXT_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_I_EXT_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_NOTCH_CORR_SPUR1_I_EXT_B1_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_ADDRESS (0x68 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_2_EXT_B1_RESET 0x400 // 0x6c (PHY_BB_RX_NOTCH_CNTL_3_EXT_B1) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_Q_EXT_B1_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_Q_EXT_B1_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_Q_EXT_B1_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_Q_EXT_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_Q_EXT_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_Q_EXT_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_Q_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_Q_EXT_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_Q_EXT_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_Q_EXT_B1_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_I_EXT_B1_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_I_EXT_B1_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_I_EXT_B1_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_I_EXT_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_I_EXT_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_I_EXT_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_I_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_I_EXT_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_I_EXT_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_NOTCH_CORR_SPUR2_I_EXT_B1_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_ADDRESS (0x6c + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_3_EXT_B1_RESET 0x400 // 0x70 (PHY_BB_RX_NOTCH_CNTL_4_EXT_B1) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_Q_EXT_B1_LSB 16 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_Q_EXT_B1_MSB 27 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_Q_EXT_B1_MASK 0xfff0000 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_Q_EXT_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_Q_EXT_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_Q_EXT_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_Q_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_Q_EXT_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_Q_EXT_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_Q_EXT_B1_RESET 0x0 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_I_EXT_B1_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_I_EXT_B1_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_I_EXT_B1_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_I_EXT_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_I_EXT_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_I_EXT_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_I_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_I_EXT_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_I_EXT_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_NOTCH_CORR_DC_I_EXT_B1_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_ADDRESS (0x70 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_RSTMASK 0xfff0fff #define PHY_BB_RX_NOTCH_CNTL_4_EXT_B1_RESET 0x400 // 0x74 (PHY_BB_RX_NOTCH_CNTL_5_EXT_B1) #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_NOTCH_CORR_AGG_I_EXT_B1_LSB 0 #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_NOTCH_CORR_AGG_I_EXT_B1_MSB 11 #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_NOTCH_CORR_AGG_I_EXT_B1_MASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_NOTCH_CORR_AGG_I_EXT_B1_GET(x) (((x) & PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_NOTCH_CORR_AGG_I_EXT_B1_MASK) >> PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_NOTCH_CORR_AGG_I_EXT_B1_LSB) #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_NOTCH_CORR_AGG_I_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_NOTCH_CORR_AGG_I_EXT_B1_LSB) & PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_NOTCH_CORR_AGG_I_EXT_B1_MASK) #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_NOTCH_CORR_AGG_I_EXT_B1_RESET 0x400 #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_ADDRESS (0x74 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_RSTMASK 0xfff #define PHY_BB_RX_NOTCH_CNTL_5_EXT_B1_RESET 0x400 // 0x88 (PHY_BB_PRE_EMPHASIS_BW20_B1) #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_NEG_BW20_1_LSB 15 #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_NEG_BW20_1_MSB 29 #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_NEG_BW20_1_MASK 0x3fff8000 #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_NEG_BW20_1_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_NEG_BW20_1_MASK) >> PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_NEG_BW20_1_LSB) #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_NEG_BW20_1_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_NEG_BW20_1_LSB) & PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_NEG_BW20_1_MASK) #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_NEG_BW20_1_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_POS_BW20_1_LSB 0 #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_POS_BW20_1_MSB 14 #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_POS_BW20_1_MASK 0x7fff #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_POS_BW20_1_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_POS_BW20_1_MASK) >> PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_POS_BW20_1_LSB) #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_POS_BW20_1_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_POS_BW20_1_LSB) & PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_POS_BW20_1_MASK) #define PHY_BB_PRE_EMPHASIS_BW20_B1_PRE_EMP_DB_POS_BW20_1_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW20_B1_ADDRESS (0x88 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_PRE_EMPHASIS_BW20_B1_RSTMASK 0x3fffffff #define PHY_BB_PRE_EMPHASIS_BW20_B1_RESET 0x0 // 0x8c (PHY_BB_PRE_EMPHASIS_BW40_B1) #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_NEG_BW40_1_LSB 15 #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_NEG_BW40_1_MSB 29 #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_NEG_BW40_1_MASK 0x3fff8000 #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_NEG_BW40_1_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_NEG_BW40_1_MASK) >> PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_NEG_BW40_1_LSB) #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_NEG_BW40_1_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_NEG_BW40_1_LSB) & PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_NEG_BW40_1_MASK) #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_NEG_BW40_1_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_POS_BW40_1_LSB 0 #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_POS_BW40_1_MSB 14 #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_POS_BW40_1_MASK 0x7fff #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_POS_BW40_1_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_POS_BW40_1_MASK) >> PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_POS_BW40_1_LSB) #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_POS_BW40_1_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_POS_BW40_1_LSB) & PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_POS_BW40_1_MASK) #define PHY_BB_PRE_EMPHASIS_BW40_B1_PRE_EMP_DB_POS_BW40_1_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW40_B1_ADDRESS (0x8c + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_PRE_EMPHASIS_BW40_B1_RSTMASK 0x3fffffff #define PHY_BB_PRE_EMPHASIS_BW40_B1_RESET 0x0 // 0x90 (PHY_BB_PRE_EMPHASIS_BW80_B1) #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_NEG_BW80_1_LSB 15 #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_NEG_BW80_1_MSB 29 #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_NEG_BW80_1_MASK 0x3fff8000 #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_NEG_BW80_1_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_NEG_BW80_1_MASK) >> PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_NEG_BW80_1_LSB) #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_NEG_BW80_1_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_NEG_BW80_1_LSB) & PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_NEG_BW80_1_MASK) #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_NEG_BW80_1_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_POS_BW80_1_LSB 0 #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_POS_BW80_1_MSB 14 #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_POS_BW80_1_MASK 0x7fff #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_POS_BW80_1_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_POS_BW80_1_MASK) >> PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_POS_BW80_1_LSB) #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_POS_BW80_1_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_POS_BW80_1_LSB) & PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_POS_BW80_1_MASK) #define PHY_BB_PRE_EMPHASIS_BW80_B1_PRE_EMP_DB_POS_BW80_1_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW80_B1_ADDRESS (0x90 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_PRE_EMPHASIS_BW80_B1_RSTMASK 0x3fffffff #define PHY_BB_PRE_EMPHASIS_BW80_B1_RESET 0x0 // 0x94 (PHY_BB_CHN1_TABLES_INTF_ADDR) #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_ADDR_AUTO_INCR_LSB 31 #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_ADDR_AUTO_INCR_MSB 31 #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_ADDR_AUTO_INCR_MASK 0x80000000 #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_ADDR_AUTO_INCR_GET(x) (((x) & PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_ADDR_AUTO_INCR_MASK) >> PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_ADDR_AUTO_INCR_LSB) #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_ADDR_AUTO_INCR_SET(x) (((0 | (x)) << PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_ADDR_AUTO_INCR_LSB) & PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_ADDR_AUTO_INCR_MASK) #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_ADDR_AUTO_INCR_RESET 0x0 #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_TABLES_ADDR_LSB 2 #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_TABLES_ADDR_MSB 17 #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_TABLES_ADDR_MASK 0x3fffc #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_TABLES_ADDR_GET(x) (((x) & PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_TABLES_ADDR_MASK) >> PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_TABLES_ADDR_LSB) #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_TABLES_ADDR_SET(x) (((0 | (x)) << PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_TABLES_ADDR_LSB) & PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_TABLES_ADDR_MASK) #define PHY_BB_CHN1_TABLES_INTF_ADDR_CHN1_TABLES_ADDR_RESET 0x0 #define PHY_BB_CHN1_TABLES_INTF_ADDR_ADDRESS (0x94 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHN1_TABLES_INTF_ADDR_RSTMASK 0x8003fffc #define PHY_BB_CHN1_TABLES_INTF_ADDR_RESET 0x0 // 0x98 (PHY_BB_CHN1_TABLES_INTF_DATA) #define PHY_BB_CHN1_TABLES_INTF_DATA_CHN1_TABLES_DATA_LSB 0 #define PHY_BB_CHN1_TABLES_INTF_DATA_CHN1_TABLES_DATA_MSB 31 #define PHY_BB_CHN1_TABLES_INTF_DATA_CHN1_TABLES_DATA_MASK 0xffffffff #define PHY_BB_CHN1_TABLES_INTF_DATA_CHN1_TABLES_DATA_GET(x) (((x) & PHY_BB_CHN1_TABLES_INTF_DATA_CHN1_TABLES_DATA_MASK) >> PHY_BB_CHN1_TABLES_INTF_DATA_CHN1_TABLES_DATA_LSB) #define PHY_BB_CHN1_TABLES_INTF_DATA_CHN1_TABLES_DATA_SET(x) (((0 | (x)) << PHY_BB_CHN1_TABLES_INTF_DATA_CHN1_TABLES_DATA_LSB) & PHY_BB_CHN1_TABLES_INTF_DATA_CHN1_TABLES_DATA_MASK) #define PHY_BB_CHN1_TABLES_INTF_DATA_CHN1_TABLES_DATA_RESET 0x0 #define PHY_BB_CHN1_TABLES_INTF_DATA_ADDRESS (0x98 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHN1_TABLES_INTF_DATA_RSTMASK 0xffffffff #define PHY_BB_CHN1_TABLES_INTF_DATA_RESET 0x0 // 0xa8 (PHY_BB_SPUR_REPORT_B1) #define PHY_BB_SPUR_REPORT_B1_POWER_WITH_SPUR_REMOVED_1_LSB 16 #define PHY_BB_SPUR_REPORT_B1_POWER_WITH_SPUR_REMOVED_1_MSB 31 #define PHY_BB_SPUR_REPORT_B1_POWER_WITH_SPUR_REMOVED_1_MASK 0xffff0000 #define PHY_BB_SPUR_REPORT_B1_POWER_WITH_SPUR_REMOVED_1_GET(x) (((x) & PHY_BB_SPUR_REPORT_B1_POWER_WITH_SPUR_REMOVED_1_MASK) >> PHY_BB_SPUR_REPORT_B1_POWER_WITH_SPUR_REMOVED_1_LSB) #define PHY_BB_SPUR_REPORT_B1_POWER_WITH_SPUR_REMOVED_1_SET(x) (((0 | (x)) << PHY_BB_SPUR_REPORT_B1_POWER_WITH_SPUR_REMOVED_1_LSB) & PHY_BB_SPUR_REPORT_B1_POWER_WITH_SPUR_REMOVED_1_MASK) #define PHY_BB_SPUR_REPORT_B1_POWER_WITH_SPUR_REMOVED_1_RESET 0x0 #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_Q_1_LSB 8 #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_Q_1_MSB 15 #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_Q_1_MASK 0xff00 #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_Q_1_GET(x) (((x) & PHY_BB_SPUR_REPORT_B1_SPUR_EST_Q_1_MASK) >> PHY_BB_SPUR_REPORT_B1_SPUR_EST_Q_1_LSB) #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_Q_1_SET(x) (((0 | (x)) << PHY_BB_SPUR_REPORT_B1_SPUR_EST_Q_1_LSB) & PHY_BB_SPUR_REPORT_B1_SPUR_EST_Q_1_MASK) #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_Q_1_RESET 0x0 #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_I_1_LSB 0 #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_I_1_MSB 7 #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_I_1_MASK 0xff #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_I_1_GET(x) (((x) & PHY_BB_SPUR_REPORT_B1_SPUR_EST_I_1_MASK) >> PHY_BB_SPUR_REPORT_B1_SPUR_EST_I_1_LSB) #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_I_1_SET(x) (((0 | (x)) << PHY_BB_SPUR_REPORT_B1_SPUR_EST_I_1_LSB) & PHY_BB_SPUR_REPORT_B1_SPUR_EST_I_1_MASK) #define PHY_BB_SPUR_REPORT_B1_SPUR_EST_I_1_RESET 0x0 #define PHY_BB_SPUR_REPORT_B1_ADDRESS (0xa8 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_REPORT_B1_RSTMASK 0xffffffff #define PHY_BB_SPUR_REPORT_B1_RESET 0x0 // 0xc0 (PHY_BB_IQ_ADC_MEAS_0_B1) #define PHY_BB_IQ_ADC_MEAS_0_B1_GAIN_DC_IQ_CAL_MEAS_0_1_LSB 0 #define PHY_BB_IQ_ADC_MEAS_0_B1_GAIN_DC_IQ_CAL_MEAS_0_1_MSB 31 #define PHY_BB_IQ_ADC_MEAS_0_B1_GAIN_DC_IQ_CAL_MEAS_0_1_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_0_B1_GAIN_DC_IQ_CAL_MEAS_0_1_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_0_B1_GAIN_DC_IQ_CAL_MEAS_0_1_MASK) >> PHY_BB_IQ_ADC_MEAS_0_B1_GAIN_DC_IQ_CAL_MEAS_0_1_LSB) #define PHY_BB_IQ_ADC_MEAS_0_B1_GAIN_DC_IQ_CAL_MEAS_0_1_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_0_B1_GAIN_DC_IQ_CAL_MEAS_0_1_LSB) & PHY_BB_IQ_ADC_MEAS_0_B1_GAIN_DC_IQ_CAL_MEAS_0_1_MASK) #define PHY_BB_IQ_ADC_MEAS_0_B1_GAIN_DC_IQ_CAL_MEAS_0_1_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_0_B1_ADDRESS (0xc0 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_0_B1_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_0_B1_RESET 0x0 // 0xc4 (PHY_BB_IQ_ADC_MEAS_1_B1) #define PHY_BB_IQ_ADC_MEAS_1_B1_GAIN_DC_IQ_CAL_MEAS_1_1_LSB 0 #define PHY_BB_IQ_ADC_MEAS_1_B1_GAIN_DC_IQ_CAL_MEAS_1_1_MSB 31 #define PHY_BB_IQ_ADC_MEAS_1_B1_GAIN_DC_IQ_CAL_MEAS_1_1_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_1_B1_GAIN_DC_IQ_CAL_MEAS_1_1_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_1_B1_GAIN_DC_IQ_CAL_MEAS_1_1_MASK) >> PHY_BB_IQ_ADC_MEAS_1_B1_GAIN_DC_IQ_CAL_MEAS_1_1_LSB) #define PHY_BB_IQ_ADC_MEAS_1_B1_GAIN_DC_IQ_CAL_MEAS_1_1_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_1_B1_GAIN_DC_IQ_CAL_MEAS_1_1_LSB) & PHY_BB_IQ_ADC_MEAS_1_B1_GAIN_DC_IQ_CAL_MEAS_1_1_MASK) #define PHY_BB_IQ_ADC_MEAS_1_B1_GAIN_DC_IQ_CAL_MEAS_1_1_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_1_B1_ADDRESS (0xc4 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_1_B1_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_1_B1_RESET 0x0 // 0xc8 (PHY_BB_IQ_ADC_MEAS_2_B1) #define PHY_BB_IQ_ADC_MEAS_2_B1_GAIN_DC_IQ_CAL_MEAS_2_1_LSB 0 #define PHY_BB_IQ_ADC_MEAS_2_B1_GAIN_DC_IQ_CAL_MEAS_2_1_MSB 31 #define PHY_BB_IQ_ADC_MEAS_2_B1_GAIN_DC_IQ_CAL_MEAS_2_1_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_2_B1_GAIN_DC_IQ_CAL_MEAS_2_1_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_2_B1_GAIN_DC_IQ_CAL_MEAS_2_1_MASK) >> PHY_BB_IQ_ADC_MEAS_2_B1_GAIN_DC_IQ_CAL_MEAS_2_1_LSB) #define PHY_BB_IQ_ADC_MEAS_2_B1_GAIN_DC_IQ_CAL_MEAS_2_1_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_2_B1_GAIN_DC_IQ_CAL_MEAS_2_1_LSB) & PHY_BB_IQ_ADC_MEAS_2_B1_GAIN_DC_IQ_CAL_MEAS_2_1_MASK) #define PHY_BB_IQ_ADC_MEAS_2_B1_GAIN_DC_IQ_CAL_MEAS_2_1_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_2_B1_ADDRESS (0xc8 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_2_B1_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_2_B1_RESET 0x0 // 0xcc (PHY_BB_IQ_ADC_MEAS_3_B1) #define PHY_BB_IQ_ADC_MEAS_3_B1_GAIN_DC_IQ_CAL_MEAS_3_1_LSB 0 #define PHY_BB_IQ_ADC_MEAS_3_B1_GAIN_DC_IQ_CAL_MEAS_3_1_MSB 31 #define PHY_BB_IQ_ADC_MEAS_3_B1_GAIN_DC_IQ_CAL_MEAS_3_1_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_3_B1_GAIN_DC_IQ_CAL_MEAS_3_1_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_3_B1_GAIN_DC_IQ_CAL_MEAS_3_1_MASK) >> PHY_BB_IQ_ADC_MEAS_3_B1_GAIN_DC_IQ_CAL_MEAS_3_1_LSB) #define PHY_BB_IQ_ADC_MEAS_3_B1_GAIN_DC_IQ_CAL_MEAS_3_1_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_3_B1_GAIN_DC_IQ_CAL_MEAS_3_1_LSB) & PHY_BB_IQ_ADC_MEAS_3_B1_GAIN_DC_IQ_CAL_MEAS_3_1_MASK) #define PHY_BB_IQ_ADC_MEAS_3_B1_GAIN_DC_IQ_CAL_MEAS_3_1_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_3_B1_ADDRESS (0xcc + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_3_B1_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_3_B1_RESET 0x0 // 0xd0 (PHY_BB_TX_PHASE_RAMP_B1) #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ALPHA_1_LSB 17 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ALPHA_1_MSB 24 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ALPHA_1_MASK 0x1fe0000 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ALPHA_1_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ALPHA_1_MASK) >> PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ALPHA_1_LSB) #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ALPHA_1_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ALPHA_1_LSB) & PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ALPHA_1_MASK) #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ALPHA_1_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_INIT_1_LSB 7 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_INIT_1_MSB 16 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_INIT_1_MASK 0x1ff80 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_INIT_1_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_INIT_1_MASK) >> PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_INIT_1_LSB) #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_INIT_1_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_INIT_1_LSB) & PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_INIT_1_MASK) #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_INIT_1_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_BIAS_1_LSB 1 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_BIAS_1_MSB 6 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_BIAS_1_MASK 0x7e #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_BIAS_1_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_BIAS_1_MASK) >> PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_BIAS_1_LSB) #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_BIAS_1_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_BIAS_1_LSB) & PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_BIAS_1_MASK) #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_BIAS_1_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ENABLE_1_LSB 0 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ENABLE_1_MSB 0 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ENABLE_1_MASK 0x1 #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ENABLE_1_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ENABLE_1_MASK) >> PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ENABLE_1_LSB) #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ENABLE_1_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ENABLE_1_LSB) & PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ENABLE_1_MASK) #define PHY_BB_TX_PHASE_RAMP_B1_CF_PHASE_RAMP_ENABLE_1_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B1_ADDRESS (0xd0 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_TX_PHASE_RAMP_B1_RSTMASK 0x1ffffff #define PHY_BB_TX_PHASE_RAMP_B1_RESET 0x0 // 0xd4 (PHY_BB_ADC_GAIN_CORR_B1) #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_I_COEFF_1_LSB 9 #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_I_COEFF_1_MSB 17 #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_I_COEFF_1_MASK 0x3fe00 #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_I_COEFF_1_GET(x) (((x) & PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_I_COEFF_1_MASK) >> PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_I_COEFF_1_LSB) #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_I_COEFF_1_SET(x) (((0 | (x)) << PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_I_COEFF_1_LSB) & PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_I_COEFF_1_MASK) #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_I_COEFF_1_RESET 0x20 #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_Q_COEFF_1_LSB 0 #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_Q_COEFF_1_MSB 8 #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_Q_COEFF_1_MASK 0x1ff #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_Q_COEFF_1_GET(x) (((x) & PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_Q_COEFF_1_MASK) >> PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_Q_COEFF_1_LSB) #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_Q_COEFF_1_SET(x) (((0 | (x)) << PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_Q_COEFF_1_LSB) & PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_Q_COEFF_1_MASK) #define PHY_BB_ADC_GAIN_CORR_B1_ADC_GAIN_CORR_Q_COEFF_1_RESET 0x20 #define PHY_BB_ADC_GAIN_CORR_B1_ADDRESS (0xd4 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_ADC_GAIN_CORR_B1_RSTMASK 0x3ffff #define PHY_BB_ADC_GAIN_CORR_B1_RESET 0x4020 // 0xd8 (PHY_BB_ADC_DC_CORR_B1) #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_I_COEFF_1_LSB 9 #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_I_COEFF_1_MSB 17 #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_I_COEFF_1_MASK 0x3fe00 #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_I_COEFF_1_GET(x) (((x) & PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_I_COEFF_1_MASK) >> PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_I_COEFF_1_LSB) #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_I_COEFF_1_SET(x) (((0 | (x)) << PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_I_COEFF_1_LSB) & PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_I_COEFF_1_MASK) #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_I_COEFF_1_RESET 0x0 #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_Q_COEFF_1_LSB 0 #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_Q_COEFF_1_MSB 8 #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_Q_COEFF_1_MASK 0x1ff #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_Q_COEFF_1_GET(x) (((x) & PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_Q_COEFF_1_MASK) >> PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_Q_COEFF_1_LSB) #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_Q_COEFF_1_SET(x) (((0 | (x)) << PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_Q_COEFF_1_LSB) & PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_Q_COEFF_1_MASK) #define PHY_BB_ADC_DC_CORR_B1_ADC_DC_CORR_Q_COEFF_1_RESET 0x0 #define PHY_BB_ADC_DC_CORR_B1_ADDRESS (0xd8 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_ADC_DC_CORR_B1_RSTMASK 0x3ffff #define PHY_BB_ADC_DC_CORR_B1_RESET 0x0 // 0xe0 (PHY_BB_RX_IQ_CORR_LOOPBACK_B1) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_I_COFF_1_LSB 9 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_I_COFF_1_MSB 17 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_I_COFF_1_MASK 0x3fe00 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_I_COFF_1_GET(x) (((x) & PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_I_COFF_1_MASK) >> PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_I_COFF_1_LSB) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_I_COFF_1_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_I_COFF_1_LSB) & PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_I_COFF_1_MASK) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_I_COFF_1_RESET 0x0 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_Q_COFF_1_LSB 0 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_Q_COFF_1_MSB 8 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_Q_COFF_1_MASK 0x1ff #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_Q_COFF_1_GET(x) (((x) & PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_Q_COFF_1_MASK) >> PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_Q_COFF_1_LSB) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_Q_COFF_1_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_Q_COFF_1_LSB) & PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_Q_COFF_1_MASK) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_LOOPBACK_IQCORR_Q_Q_COFF_1_RESET 0x0 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_ADDRESS (0xe0 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_RSTMASK 0x3ffff #define PHY_BB_RX_IQ_CORR_LOOPBACK_B1_RESET 0x0 // 0xf0 (PHY_BB_PAPRD_CTRL0_B1) #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_VALID_GAIN_5_0_1_LSB 2 #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_VALID_GAIN_5_0_1_MSB 31 #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_VALID_GAIN_5_0_1_MASK 0xfffffffc #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_VALID_GAIN_5_0_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL0_B1_PAPRD_VALID_GAIN_5_0_1_MASK) >> PHY_BB_PAPRD_CTRL0_B1_PAPRD_VALID_GAIN_5_0_1_LSB) #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_VALID_GAIN_5_0_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL0_B1_PAPRD_VALID_GAIN_5_0_1_LSB) & PHY_BB_PAPRD_CTRL0_B1_PAPRD_VALID_GAIN_5_0_1_MASK) #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_VALID_GAIN_5_0_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_LSB 0 #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_MSB 0 #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_MASK 0x1 #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_MASK) >> PHY_BB_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_LSB) #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_LSB) & PHY_BB_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_MASK) #define PHY_BB_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL0_B1_ADDRESS (0xf0 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_CTRL0_B1_RSTMASK 0xfffffffd #define PHY_BB_PAPRD_CTRL0_B1_RESET 0x0 // 0xf4 (PHY_BB_PAPRD_CTRL1_B1) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TRAINER_IANDQ_SEL_1_LSB 29 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TRAINER_IANDQ_SEL_1_MSB 29 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TRAINER_IANDQ_SEL_1_MASK 0x20000000 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TRAINER_IANDQ_SEL_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B1_PAPRD_TRAINER_IANDQ_SEL_1_MASK) >> PHY_BB_PAPRD_CTRL1_B1_PAPRD_TRAINER_IANDQ_SEL_1_LSB) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TRAINER_IANDQ_SEL_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B1_PAPRD_TRAINER_IANDQ_SEL_1_LSB) & PHY_BB_PAPRD_CTRL1_B1_PAPRD_TRAINER_IANDQ_SEL_1_MASK) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TRAINER_IANDQ_SEL_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MIN_1_LSB 8 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MIN_1_MSB 13 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MIN_1_MASK 0x3f00 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MIN_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MIN_1_MASK) >> PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MIN_1_LSB) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MIN_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MIN_1_LSB) & PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MIN_1_MASK) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MIN_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MAX_1_LSB 2 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MAX_1_MSB 7 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MAX_1_MASK 0xfc #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MAX_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MAX_1_MASK) >> PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MAX_1_LSB) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MAX_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MAX_1_LSB) & PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MAX_1_MASK) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_TARGET_PWR_MAX_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2PM_ENABLE_1_LSB 1 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2PM_ENABLE_1_MSB 1 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2PM_ENABLE_1_MASK 0x2 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2PM_ENABLE_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2PM_ENABLE_1_MASK) >> PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2PM_ENABLE_1_LSB) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2PM_ENABLE_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2PM_ENABLE_1_LSB) & PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2PM_ENABLE_1_MASK) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2PM_ENABLE_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2AM_ENABLE_1_LSB 0 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2AM_ENABLE_1_MSB 0 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2AM_ENABLE_1_MASK 0x1 #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2AM_ENABLE_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2AM_ENABLE_1_MASK) >> PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2AM_ENABLE_1_LSB) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2AM_ENABLE_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2AM_ENABLE_1_LSB) & PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2AM_ENABLE_1_MASK) #define PHY_BB_PAPRD_CTRL1_B1_PAPRD_ADAPTIVE_AM2AM_ENABLE_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B1_ADDRESS (0xf4 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_CTRL1_B1_RSTMASK 0x20003fff #define PHY_BB_PAPRD_CTRL1_B1_RESET 0x0 // 0xf8 (PHY_BB_PAPRD_CTRL2_B1) #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_MAG_THRSH_1_LSB 27 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_MAG_THRSH_1_MSB 31 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_MAG_THRSH_1_MASK 0xf8000000 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_MAG_THRSH_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B1_PAPRD_MAG_THRSH_1_MASK) >> PHY_BB_PAPRD_CTRL2_B1_PAPRD_MAG_THRSH_1_LSB) #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_MAG_THRSH_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B1_PAPRD_MAG_THRSH_1_LSB) & PHY_BB_PAPRD_CTRL2_B1_PAPRD_MAG_THRSH_1_MASK) #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_MAG_THRSH_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_TABLE_RFBMODE_1_LSB 24 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_TABLE_RFBMODE_1_MSB 26 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_TABLE_RFBMODE_1_MASK 0x7000000 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_TABLE_RFBMODE_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B1_PAPRD_TABLE_RFBMODE_1_MASK) >> PHY_BB_PAPRD_CTRL2_B1_PAPRD_TABLE_RFBMODE_1_LSB) #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_TABLE_RFBMODE_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B1_PAPRD_TABLE_RFBMODE_1_LSB) & PHY_BB_PAPRD_CTRL2_B1_PAPRD_TABLE_RFBMODE_1_MASK) #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_TABLE_RFBMODE_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_ADAPTIVE_TABLE_VALID_1_LSB 18 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_ADAPTIVE_TABLE_VALID_1_MSB 23 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_ADAPTIVE_TABLE_VALID_1_MASK 0xfc0000 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_ADAPTIVE_TABLE_VALID_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B1_PAPRD_ADAPTIVE_TABLE_VALID_1_MASK) >> PHY_BB_PAPRD_CTRL2_B1_PAPRD_ADAPTIVE_TABLE_VALID_1_LSB) #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_ADAPTIVE_TABLE_VALID_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B1_PAPRD_ADAPTIVE_TABLE_VALID_1_LSB) & PHY_BB_PAPRD_CTRL2_B1_PAPRD_ADAPTIVE_TABLE_VALID_1_MASK) #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_ADAPTIVE_TABLE_VALID_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_VALID_PA_SETTING_1_LSB 0 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_VALID_PA_SETTING_1_MSB 17 #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_VALID_PA_SETTING_1_MASK 0x3ffff #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_VALID_PA_SETTING_1_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B1_PAPRD_VALID_PA_SETTING_1_MASK) >> PHY_BB_PAPRD_CTRL2_B1_PAPRD_VALID_PA_SETTING_1_LSB) #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_VALID_PA_SETTING_1_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B1_PAPRD_VALID_PA_SETTING_1_LSB) & PHY_BB_PAPRD_CTRL2_B1_PAPRD_VALID_PA_SETTING_1_MASK) #define PHY_BB_PAPRD_CTRL2_B1_PAPRD_VALID_PA_SETTING_1_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B1_ADDRESS (0xf8 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_CTRL2_B1_RSTMASK 0xffffffff #define PHY_BB_PAPRD_CTRL2_B1_RESET 0x0 // 0x150 (PHY_BB_FDTG_SS0_DATA_B1) #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_IM_1_LSB 24 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_IM_1_MSB 31 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_IM_1_MASK 0xff000000 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_IM_1_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_IM_1_MASK) >> PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_IM_1_LSB) #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_IM_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_IM_1_LSB) & PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_IM_1_MASK) #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_IM_1_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_RE_1_LSB 16 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_RE_1_MSB 23 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_RE_1_MASK 0xff0000 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_RE_1_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_RE_1_MASK) >> PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_RE_1_LSB) #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_RE_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_RE_1_LSB) & PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_RE_1_MASK) #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_B_DATA_RE_1_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_IM_1_LSB 8 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_IM_1_MSB 15 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_IM_1_MASK 0xff00 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_IM_1_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_IM_1_MASK) >> PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_IM_1_LSB) #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_IM_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_IM_1_LSB) & PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_IM_1_MASK) #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_IM_1_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_RE_1_LSB 0 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_RE_1_MSB 7 #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_RE_1_MASK 0xff #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_RE_1_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_RE_1_MASK) >> PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_RE_1_LSB) #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_RE_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_RE_1_LSB) & PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_RE_1_MASK) #define PHY_BB_FDTG_SS0_DATA_B1_FDTG_SS0_A_DATA_RE_1_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B1_ADDRESS (0x150 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS0_DATA_B1_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS0_DATA_B1_RESET 0x0 // 0x154 (PHY_BB_FDTG_SS1_DATA_B1) #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_IM_1_LSB 24 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_IM_1_MSB 31 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_IM_1_MASK 0xff000000 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_IM_1_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_IM_1_MASK) >> PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_IM_1_LSB) #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_IM_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_IM_1_LSB) & PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_IM_1_MASK) #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_IM_1_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_RE_1_LSB 16 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_RE_1_MSB 23 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_RE_1_MASK 0xff0000 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_RE_1_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_RE_1_MASK) >> PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_RE_1_LSB) #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_RE_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_RE_1_LSB) & PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_RE_1_MASK) #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_B_DATA_RE_1_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_IM_1_LSB 8 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_IM_1_MSB 15 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_IM_1_MASK 0xff00 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_IM_1_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_IM_1_MASK) >> PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_IM_1_LSB) #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_IM_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_IM_1_LSB) & PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_IM_1_MASK) #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_IM_1_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_RE_1_LSB 0 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_RE_1_MSB 7 #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_RE_1_MASK 0xff #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_RE_1_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_RE_1_MASK) >> PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_RE_1_LSB) #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_RE_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_RE_1_LSB) & PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_RE_1_MASK) #define PHY_BB_FDTG_SS1_DATA_B1_FDTG_SS1_A_DATA_RE_1_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B1_ADDRESS (0x154 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS1_DATA_B1_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS1_DATA_B1_RESET 0x0 // 0x158 (PHY_BB_FDTG_SS2_DATA_B1) #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_IM_1_LSB 24 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_IM_1_MSB 31 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_IM_1_MASK 0xff000000 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_IM_1_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_IM_1_MASK) >> PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_IM_1_LSB) #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_IM_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_IM_1_LSB) & PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_IM_1_MASK) #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_IM_1_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_RE_1_LSB 16 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_RE_1_MSB 23 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_RE_1_MASK 0xff0000 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_RE_1_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_RE_1_MASK) >> PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_RE_1_LSB) #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_RE_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_RE_1_LSB) & PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_RE_1_MASK) #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_B_DATA_RE_1_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_IM_1_LSB 8 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_IM_1_MSB 15 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_IM_1_MASK 0xff00 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_IM_1_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_IM_1_MASK) >> PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_IM_1_LSB) #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_IM_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_IM_1_LSB) & PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_IM_1_MASK) #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_IM_1_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_RE_1_LSB 0 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_RE_1_MSB 7 #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_RE_1_MASK 0xff #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_RE_1_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_RE_1_MASK) >> PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_RE_1_LSB) #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_RE_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_RE_1_LSB) & PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_RE_1_MASK) #define PHY_BB_FDTG_SS2_DATA_B1_FDTG_SS2_A_DATA_RE_1_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B1_ADDRESS (0x158 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS2_DATA_B1_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS2_DATA_B1_RESET 0x0 // 0x16c (PHY_BB_SPUR_CTRL1_PRI_B1) #define PHY_BB_SPUR_CTRL1_PRI_B1_ENABLE_SPUR_FILTER_PRI_B1_LSB 30 #define PHY_BB_SPUR_CTRL1_PRI_B1_ENABLE_SPUR_FILTER_PRI_B1_MSB 31 #define PHY_BB_SPUR_CTRL1_PRI_B1_ENABLE_SPUR_FILTER_PRI_B1_MASK 0xc0000000 #define PHY_BB_SPUR_CTRL1_PRI_B1_ENABLE_SPUR_FILTER_PRI_B1_GET(x) (((x) & PHY_BB_SPUR_CTRL1_PRI_B1_ENABLE_SPUR_FILTER_PRI_B1_MASK) >> PHY_BB_SPUR_CTRL1_PRI_B1_ENABLE_SPUR_FILTER_PRI_B1_LSB) #define PHY_BB_SPUR_CTRL1_PRI_B1_ENABLE_SPUR_FILTER_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_PRI_B1_ENABLE_SPUR_FILTER_PRI_B1_LSB) & PHY_BB_SPUR_CTRL1_PRI_B1_ENABLE_SPUR_FILTER_PRI_B1_MASK) #define PHY_BB_SPUR_CTRL1_PRI_B1_ENABLE_SPUR_FILTER_PRI_B1_RESET 0x0 #define PHY_BB_SPUR_CTRL1_PRI_B1_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B1_LSB 29 #define PHY_BB_SPUR_CTRL1_PRI_B1_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B1_MSB 29 #define PHY_BB_SPUR_CTRL1_PRI_B1_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B1_MASK 0x20000000 #define PHY_BB_SPUR_CTRL1_PRI_B1_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B1_GET(x) (((x) & PHY_BB_SPUR_CTRL1_PRI_B1_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B1_MASK) >> PHY_BB_SPUR_CTRL1_PRI_B1_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B1_LSB) #define PHY_BB_SPUR_CTRL1_PRI_B1_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_PRI_B1_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B1_LSB) & PHY_BB_SPUR_CTRL1_PRI_B1_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B1_MASK) #define PHY_BB_SPUR_CTRL1_PRI_B1_AGC_HT_STF_SPUR_FILTER_ENA_PRI_B1_RESET 0x1 #define PHY_BB_SPUR_CTRL1_PRI_B1_SPUR_DELTA_PHASE_PRI_B1_LSB 0 #define PHY_BB_SPUR_CTRL1_PRI_B1_SPUR_DELTA_PHASE_PRI_B1_MSB 19 #define PHY_BB_SPUR_CTRL1_PRI_B1_SPUR_DELTA_PHASE_PRI_B1_MASK 0xfffff #define PHY_BB_SPUR_CTRL1_PRI_B1_SPUR_DELTA_PHASE_PRI_B1_GET(x) (((x) & PHY_BB_SPUR_CTRL1_PRI_B1_SPUR_DELTA_PHASE_PRI_B1_MASK) >> PHY_BB_SPUR_CTRL1_PRI_B1_SPUR_DELTA_PHASE_PRI_B1_LSB) #define PHY_BB_SPUR_CTRL1_PRI_B1_SPUR_DELTA_PHASE_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_PRI_B1_SPUR_DELTA_PHASE_PRI_B1_LSB) & PHY_BB_SPUR_CTRL1_PRI_B1_SPUR_DELTA_PHASE_PRI_B1_MASK) #define PHY_BB_SPUR_CTRL1_PRI_B1_SPUR_DELTA_PHASE_PRI_B1_RESET 0x0 #define PHY_BB_SPUR_CTRL1_PRI_B1_ADDRESS (0x16c + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_CTRL1_PRI_B1_RSTMASK 0xe00fffff #define PHY_BB_SPUR_CTRL1_PRI_B1_RESET 0x20000000 // 0x170 (PHY_BB_SPUR_CTRL2_PRI_B1) #define PHY_BB_SPUR_CTRL2_PRI_B1_SPUR_DELTA_PHASE_2ND_PRI_B1_LSB 0 #define PHY_BB_SPUR_CTRL2_PRI_B1_SPUR_DELTA_PHASE_2ND_PRI_B1_MSB 19 #define PHY_BB_SPUR_CTRL2_PRI_B1_SPUR_DELTA_PHASE_2ND_PRI_B1_MASK 0xfffff #define PHY_BB_SPUR_CTRL2_PRI_B1_SPUR_DELTA_PHASE_2ND_PRI_B1_GET(x) (((x) & PHY_BB_SPUR_CTRL2_PRI_B1_SPUR_DELTA_PHASE_2ND_PRI_B1_MASK) >> PHY_BB_SPUR_CTRL2_PRI_B1_SPUR_DELTA_PHASE_2ND_PRI_B1_LSB) #define PHY_BB_SPUR_CTRL2_PRI_B1_SPUR_DELTA_PHASE_2ND_PRI_B1_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL2_PRI_B1_SPUR_DELTA_PHASE_2ND_PRI_B1_LSB) & PHY_BB_SPUR_CTRL2_PRI_B1_SPUR_DELTA_PHASE_2ND_PRI_B1_MASK) #define PHY_BB_SPUR_CTRL2_PRI_B1_SPUR_DELTA_PHASE_2ND_PRI_B1_RESET 0x0 #define PHY_BB_SPUR_CTRL2_PRI_B1_ADDRESS (0x170 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_CTRL2_PRI_B1_RSTMASK 0xfffff #define PHY_BB_SPUR_CTRL2_PRI_B1_RESET 0x0 // 0x174 (PHY_BB_SPUR_CTRL1_EXT_B1) #define PHY_BB_SPUR_CTRL1_EXT_B1_ENABLE_SPUR_FILTER_EXT_B1_LSB 30 #define PHY_BB_SPUR_CTRL1_EXT_B1_ENABLE_SPUR_FILTER_EXT_B1_MSB 31 #define PHY_BB_SPUR_CTRL1_EXT_B1_ENABLE_SPUR_FILTER_EXT_B1_MASK 0xc0000000 #define PHY_BB_SPUR_CTRL1_EXT_B1_ENABLE_SPUR_FILTER_EXT_B1_GET(x) (((x) & PHY_BB_SPUR_CTRL1_EXT_B1_ENABLE_SPUR_FILTER_EXT_B1_MASK) >> PHY_BB_SPUR_CTRL1_EXT_B1_ENABLE_SPUR_FILTER_EXT_B1_LSB) #define PHY_BB_SPUR_CTRL1_EXT_B1_ENABLE_SPUR_FILTER_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_EXT_B1_ENABLE_SPUR_FILTER_EXT_B1_LSB) & PHY_BB_SPUR_CTRL1_EXT_B1_ENABLE_SPUR_FILTER_EXT_B1_MASK) #define PHY_BB_SPUR_CTRL1_EXT_B1_ENABLE_SPUR_FILTER_EXT_B1_RESET 0x0 #define PHY_BB_SPUR_CTRL1_EXT_B1_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B1_LSB 29 #define PHY_BB_SPUR_CTRL1_EXT_B1_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B1_MSB 29 #define PHY_BB_SPUR_CTRL1_EXT_B1_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B1_MASK 0x20000000 #define PHY_BB_SPUR_CTRL1_EXT_B1_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B1_GET(x) (((x) & PHY_BB_SPUR_CTRL1_EXT_B1_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B1_MASK) >> PHY_BB_SPUR_CTRL1_EXT_B1_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B1_LSB) #define PHY_BB_SPUR_CTRL1_EXT_B1_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_EXT_B1_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B1_LSB) & PHY_BB_SPUR_CTRL1_EXT_B1_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B1_MASK) #define PHY_BB_SPUR_CTRL1_EXT_B1_AGC_HT_STF_SPUR_FILTER_ENA_EXT_B1_RESET 0x1 #define PHY_BB_SPUR_CTRL1_EXT_B1_SPUR_DELTA_PHASE_EXT_B1_LSB 0 #define PHY_BB_SPUR_CTRL1_EXT_B1_SPUR_DELTA_PHASE_EXT_B1_MSB 19 #define PHY_BB_SPUR_CTRL1_EXT_B1_SPUR_DELTA_PHASE_EXT_B1_MASK 0xfffff #define PHY_BB_SPUR_CTRL1_EXT_B1_SPUR_DELTA_PHASE_EXT_B1_GET(x) (((x) & PHY_BB_SPUR_CTRL1_EXT_B1_SPUR_DELTA_PHASE_EXT_B1_MASK) >> PHY_BB_SPUR_CTRL1_EXT_B1_SPUR_DELTA_PHASE_EXT_B1_LSB) #define PHY_BB_SPUR_CTRL1_EXT_B1_SPUR_DELTA_PHASE_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL1_EXT_B1_SPUR_DELTA_PHASE_EXT_B1_LSB) & PHY_BB_SPUR_CTRL1_EXT_B1_SPUR_DELTA_PHASE_EXT_B1_MASK) #define PHY_BB_SPUR_CTRL1_EXT_B1_SPUR_DELTA_PHASE_EXT_B1_RESET 0x0 #define PHY_BB_SPUR_CTRL1_EXT_B1_ADDRESS (0x174 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_CTRL1_EXT_B1_RSTMASK 0xe00fffff #define PHY_BB_SPUR_CTRL1_EXT_B1_RESET 0x20000000 // 0x178 (PHY_BB_SPUR_CTRL2_EXT_B1) #define PHY_BB_SPUR_CTRL2_EXT_B1_SPUR_DELTA_PHASE_2ND_EXT_B1_LSB 0 #define PHY_BB_SPUR_CTRL2_EXT_B1_SPUR_DELTA_PHASE_2ND_EXT_B1_MSB 19 #define PHY_BB_SPUR_CTRL2_EXT_B1_SPUR_DELTA_PHASE_2ND_EXT_B1_MASK 0xfffff #define PHY_BB_SPUR_CTRL2_EXT_B1_SPUR_DELTA_PHASE_2ND_EXT_B1_GET(x) (((x) & PHY_BB_SPUR_CTRL2_EXT_B1_SPUR_DELTA_PHASE_2ND_EXT_B1_MASK) >> PHY_BB_SPUR_CTRL2_EXT_B1_SPUR_DELTA_PHASE_2ND_EXT_B1_LSB) #define PHY_BB_SPUR_CTRL2_EXT_B1_SPUR_DELTA_PHASE_2ND_EXT_B1_SET(x) (((0 | (x)) << PHY_BB_SPUR_CTRL2_EXT_B1_SPUR_DELTA_PHASE_2ND_EXT_B1_LSB) & PHY_BB_SPUR_CTRL2_EXT_B1_SPUR_DELTA_PHASE_2ND_EXT_B1_MASK) #define PHY_BB_SPUR_CTRL2_EXT_B1_SPUR_DELTA_PHASE_2ND_EXT_B1_RESET 0x0 #define PHY_BB_SPUR_CTRL2_EXT_B1_ADDRESS (0x178 + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_CTRL2_EXT_B1_RSTMASK 0xfffff #define PHY_BB_SPUR_CTRL2_EXT_B1_RESET 0x0 // 0x17c (PHY_BB_FDTG_SS3_DATA_B1) #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_IM_1_LSB 24 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_IM_1_MSB 31 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_IM_1_MASK 0xff000000 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_IM_1_GET(x) (((x) & PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_IM_1_MASK) >> PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_IM_1_LSB) #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_IM_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_IM_1_LSB) & PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_IM_1_MASK) #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_IM_1_RESET 0x0 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_RE_1_LSB 16 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_RE_1_MSB 23 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_RE_1_MASK 0xff0000 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_RE_1_GET(x) (((x) & PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_RE_1_MASK) >> PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_RE_1_LSB) #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_RE_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_RE_1_LSB) & PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_RE_1_MASK) #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_B_DATA_RE_1_RESET 0x0 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_IM_1_LSB 8 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_IM_1_MSB 15 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_IM_1_MASK 0xff00 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_IM_1_GET(x) (((x) & PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_IM_1_MASK) >> PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_IM_1_LSB) #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_IM_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_IM_1_LSB) & PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_IM_1_MASK) #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_IM_1_RESET 0x0 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_RE_1_LSB 0 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_RE_1_MSB 7 #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_RE_1_MASK 0xff #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_RE_1_GET(x) (((x) & PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_RE_1_MASK) >> PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_RE_1_LSB) #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_RE_1_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_RE_1_LSB) & PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_RE_1_MASK) #define PHY_BB_FDTG_SS3_DATA_B1_FDTG_SS3_A_DATA_RE_1_RESET 0x0 #define PHY_BB_FDTG_SS3_DATA_B1_ADDRESS (0x17c + __PHY_CHN1_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS3_DATA_B1_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS3_DATA_B1_RESET 0x0 #endif /* _PHY_CHN1_REG_MAP_H_ */