// Copyright (c) 2014 Qualcomm Atheros, Inc. All rights reserved. // $ATH_LICENSE_HW_HDR_C$ // // DO NOT EDIT! This file is automatically generated // These definitions are tied to a particular hardware layout #ifndef _PPDU_TX_PHY_DESC_H_ #define _PPDU_TX_PHY_DESC_H_ #if !defined(__ASSEMBLER__) #endif // ################ START SUMMARY ################# // // Dword Fields // 0-1 struct pre_tx_phy_desc pre_tx_phy_desc_bw20; // 2-3 struct pre_tx_phy_desc pre_tx_phy_desc_bw40; // 4-5 struct pre_tx_phy_desc pre_tx_phy_desc_bw80; // 6-7 struct pre_tx_phy_desc pre_tx_phy_desc_bw160; // 8 ppdu_tx_antenna_sector_ctrl_20[23:0], pdg_sifs_response_valid[24], pdg_sifs_response_bw[26:25], reserved_9[31:27] // 9 ppdu_tx_antenna_sector_ctrl_40[23:0], reserved_10[31:24] // 10 ppdu_tx_antenna_sector_ctrl_80[23:0], reserved_11[31:24] // 11 ppdu_tx_antenna_sector_ctrl_160[23:0], reserved_12[31:24] // // ################ END SUMMARY ################# #define NUM_OF_DWORDS_PPDU_TX_PHY_DESC 12 struct ppdu_tx_phy_desc { struct pre_tx_phy_desc pre_tx_phy_desc_bw20; struct pre_tx_phy_desc pre_tx_phy_desc_bw40; struct pre_tx_phy_desc pre_tx_phy_desc_bw80; struct pre_tx_phy_desc pre_tx_phy_desc_bw160; volatile uint32_t ppdu_tx_antenna_sector_ctrl_20 : 24, //[23:0] pdg_sifs_response_valid : 1, //[24] pdg_sifs_response_bw : 2, //[26:25] reserved_9 : 5; //[31:27] volatile uint32_t ppdu_tx_antenna_sector_ctrl_40 : 24, //[23:0] reserved_10 : 8; //[31:24] volatile uint32_t ppdu_tx_antenna_sector_ctrl_80 : 24, //[23:0] reserved_11 : 8; //[31:24] volatile uint32_t ppdu_tx_antenna_sector_ctrl_160 : 24, //[23:0] reserved_12 : 8; //[31:24] }; /* struct pre_tx_phy_desc pre_tx_phy_desc_bw20 Field only valid in case 20MH PPDU transmission is allowed (ppdu_allow_bw20 is set) See structure description of: PRE_TX_PHY_DESC struct pre_tx_phy_desc pre_tx_phy_desc_bw40 Field only valid in case 40MH PPDU transmission is allowed (ppdu_allow_bw40 is set) See structure description of: PRE_TX_PHY_DESC struct pre_tx_phy_desc pre_tx_phy_desc_bw80 Field only valid in case 80MH PPDU transmission is allowed (ppdu_allow_bw80 is set) See structure description of: PRE_TX_PHY_DESC struct pre_tx_phy_desc pre_tx_phy_desc_bw160 Field only valid in case 160MH PPDU transmission is allowed (ppdu_allow_bw160 is set) See structure description of: PRE_TX_PHY_DESC ppdu_tx_antenna_sector_ctrl_20 Sectored transmit antenna control for the medium protection frame when transmitted at 20 MHz. pdg_sifs_response_valid When set, this TLV is generated by the PDG as a result of receiving the PDG_RESPONSE TLV pdg_sifs_response_bw Only valid when pdg_sifs_response_valid is set. Only the pre_tx_phy_desc_bw20 contains valid info Only the pre_tx_phy_desc_bw40 contains valid info Only the pre_tx_phy_desc_bw80 contains valid info Only the pre_tx_phy_desc_bw80 contains valid info reserved_9 ppdu_tx_antenna_sector_ctrl_40 Sectored transmit antenna control for the medium protection frame when transmitted at 40 MHz. reserved_10 ppdu_tx_antenna_sector_ctrl_80 Sectored transmit antenna control for the medium protection frame when transmitted at 80 MHz. reserved_11 ppdu_tx_antenna_sector_ctrl_160 Sectored transmit antenna control for the medium protection frame when transmitted at 160 MHz. reserved_12 */ #define PPDU_TX_PHY_DESC_0_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW20_OFFSET 0x00000000 #define PPDU_TX_PHY_DESC_0_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW20_LSB 24 #define PPDU_TX_PHY_DESC_0_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW20_MASK 0xffffffff #define PPDU_TX_PHY_DESC_1_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW20_OFFSET 0x00000004 #define PPDU_TX_PHY_DESC_1_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW20_LSB 24 #define PPDU_TX_PHY_DESC_1_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW20_MASK 0xffffffff #define PPDU_TX_PHY_DESC_2_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW40_OFFSET 0x00000008 #define PPDU_TX_PHY_DESC_2_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW40_LSB 24 #define PPDU_TX_PHY_DESC_2_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW40_MASK 0xffffffff #define PPDU_TX_PHY_DESC_3_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW40_OFFSET 0x0000000c #define PPDU_TX_PHY_DESC_3_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW40_LSB 24 #define PPDU_TX_PHY_DESC_3_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW40_MASK 0xffffffff #define PPDU_TX_PHY_DESC_4_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW80_OFFSET 0x00000010 #define PPDU_TX_PHY_DESC_4_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW80_LSB 24 #define PPDU_TX_PHY_DESC_4_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW80_MASK 0xffffffff #define PPDU_TX_PHY_DESC_5_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW80_OFFSET 0x00000014 #define PPDU_TX_PHY_DESC_5_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW80_LSB 24 #define PPDU_TX_PHY_DESC_5_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW80_MASK 0xffffffff #define PPDU_TX_PHY_DESC_6_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW160_OFFSET 0x00000018 #define PPDU_TX_PHY_DESC_6_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW160_LSB 24 #define PPDU_TX_PHY_DESC_6_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW160_MASK 0xffffffff #define PPDU_TX_PHY_DESC_7_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW160_OFFSET 0x0000001c #define PPDU_TX_PHY_DESC_7_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW160_LSB 24 #define PPDU_TX_PHY_DESC_7_PRE_TX_PHY_DESC_PRE_TX_PHY_DESC_BW160_MASK 0xffffffff /* Description PPDU_TX_PHY_DESC_8_PPDU_TX_ANTENNA_SECTOR_CTRL_20 Sectored transmit antenna control for the medium protection frame when transmitted at 20 MHz. */ #define PPDU_TX_PHY_DESC_8_PPDU_TX_ANTENNA_SECTOR_CTRL_20_OFFSET 0x00000020 #define PPDU_TX_PHY_DESC_8_PPDU_TX_ANTENNA_SECTOR_CTRL_20_LSB 0 #define PPDU_TX_PHY_DESC_8_PPDU_TX_ANTENNA_SECTOR_CTRL_20_MASK 0x00ffffff /* Description PPDU_TX_PHY_DESC_8_PDG_SIFS_RESPONSE_VALID When set, this TLV is generated by the PDG as a result of receiving the PDG_RESPONSE TLV */ #define PPDU_TX_PHY_DESC_8_PDG_SIFS_RESPONSE_VALID_OFFSET 0x00000020 #define PPDU_TX_PHY_DESC_8_PDG_SIFS_RESPONSE_VALID_LSB 24 #define PPDU_TX_PHY_DESC_8_PDG_SIFS_RESPONSE_VALID_MASK 0x01000000 /* Description PPDU_TX_PHY_DESC_8_PDG_SIFS_RESPONSE_BW Only valid when pdg_sifs_response_valid is set. Only the pre_tx_phy_desc_bw20 contains valid info Only the pre_tx_phy_desc_bw40 contains valid info Only the pre_tx_phy_desc_bw80 contains valid info Only the pre_tx_phy_desc_bw80 contains valid info */ #define PPDU_TX_PHY_DESC_8_PDG_SIFS_RESPONSE_BW_OFFSET 0x00000020 #define PPDU_TX_PHY_DESC_8_PDG_SIFS_RESPONSE_BW_LSB 25 #define PPDU_TX_PHY_DESC_8_PDG_SIFS_RESPONSE_BW_MASK 0x06000000 /* Description PPDU_TX_PHY_DESC_8_RESERVED_9 */ #define PPDU_TX_PHY_DESC_8_RESERVED_9_OFFSET 0x00000020 #define PPDU_TX_PHY_DESC_8_RESERVED_9_LSB 27 #define PPDU_TX_PHY_DESC_8_RESERVED_9_MASK 0xf8000000 /* Description PPDU_TX_PHY_DESC_9_PPDU_TX_ANTENNA_SECTOR_CTRL_40 Sectored transmit antenna control for the medium protection frame when transmitted at 40 MHz. */ #define PPDU_TX_PHY_DESC_9_PPDU_TX_ANTENNA_SECTOR_CTRL_40_OFFSET 0x00000024 #define PPDU_TX_PHY_DESC_9_PPDU_TX_ANTENNA_SECTOR_CTRL_40_LSB 0 #define PPDU_TX_PHY_DESC_9_PPDU_TX_ANTENNA_SECTOR_CTRL_40_MASK 0x00ffffff /* Description PPDU_TX_PHY_DESC_9_RESERVED_10 */ #define PPDU_TX_PHY_DESC_9_RESERVED_10_OFFSET 0x00000024 #define PPDU_TX_PHY_DESC_9_RESERVED_10_LSB 24 #define PPDU_TX_PHY_DESC_9_RESERVED_10_MASK 0xff000000 /* Description PPDU_TX_PHY_DESC_10_PPDU_TX_ANTENNA_SECTOR_CTRL_80 Sectored transmit antenna control for the medium protection frame when transmitted at 80 MHz. */ #define PPDU_TX_PHY_DESC_10_PPDU_TX_ANTENNA_SECTOR_CTRL_80_OFFSET 0x00000028 #define PPDU_TX_PHY_DESC_10_PPDU_TX_ANTENNA_SECTOR_CTRL_80_LSB 0 #define PPDU_TX_PHY_DESC_10_PPDU_TX_ANTENNA_SECTOR_CTRL_80_MASK 0x00ffffff /* Description PPDU_TX_PHY_DESC_10_RESERVED_11 */ #define PPDU_TX_PHY_DESC_10_RESERVED_11_OFFSET 0x00000028 #define PPDU_TX_PHY_DESC_10_RESERVED_11_LSB 24 #define PPDU_TX_PHY_DESC_10_RESERVED_11_MASK 0xff000000 /* Description PPDU_TX_PHY_DESC_11_PPDU_TX_ANTENNA_SECTOR_CTRL_160 Sectored transmit antenna control for the medium protection frame when transmitted at 160 MHz. */ #define PPDU_TX_PHY_DESC_11_PPDU_TX_ANTENNA_SECTOR_CTRL_160_OFFSET 0x0000002c #define PPDU_TX_PHY_DESC_11_PPDU_TX_ANTENNA_SECTOR_CTRL_160_LSB 0 #define PPDU_TX_PHY_DESC_11_PPDU_TX_ANTENNA_SECTOR_CTRL_160_MASK 0x00ffffff /* Description PPDU_TX_PHY_DESC_11_RESERVED_12 */ #define PPDU_TX_PHY_DESC_11_RESERVED_12_OFFSET 0x0000002c #define PPDU_TX_PHY_DESC_11_RESERVED_12_LSB 24 #define PPDU_TX_PHY_DESC_11_RESERVED_12_MASK 0xff000000 #endif // _PPDU_TX_PHY_DESC_H_