// Copyright (c) 2014 Qualcomm Atheros, Inc. All rights reserved. // $ATH_LICENSE_HW_HDR_C$ // // DO NOT EDIT! This file is automatically generated // These definitions are tied to a particular hardware layout #ifndef _RX_PHY_PPDU_END_H_ #define _RX_PHY_PPDU_END_H_ #if !defined(__ASSEMBLER__) #endif // ################ START SUMMARY ################# // // Dword Fields // 0 reserved_0a[1:0], error_radar[2], error_rx_abort[3], error_rx_nap[4], error_ofdm_timing[5], error_ofdm_signal_parity[6], error_ofdm_rate_illegal[7], error_ofdm_length_illegal[8], error_ppdu_ofdm_restart[9], error_ofdm_service[10], error_ppdu_ofdm_power_drop[11], error_cck_blocker[12], error_cck_timing[13], error_cck_header_crc[14], error_cck_rate_illegal[15], error_cck_length_illegal[16], error_ppdu_cck_restart[17], error_cck_service[18], error_ppdu_cck_power_drop[19], error_ht_crc_err[20], error_ht_length_illegal[21], error_ht_rate_illegal[22], error_ht_zlf[23], error_false_radar_ext[24], error_green_field[25], error_spectral_scan[26], error_rx_bw_gt_dyn_bw[27], error_leg_ht_mismatch[28], error_vht_crc_error[29], error_vht_siga_unsupported[30], error_vht_lsig_len_invalid[31] // 1 error_vht_ndp_or_zlf[0], error_vht_nsym_lt_zero[1], error_vht_rx_extra_symbol_mismatch[2], error_vht_rx_skip_group_id0[3], error_vht_rx_skip_group_id1to62[4], error_vht_rx_skip_group_id63[5], error_ofdm_ldpc_decoder_disabled[6], error_defer_nap[7], error_fdomain_timeout[8], error_lsig_rel_check[9], error_bt_collision[10], error_unsupported_mu_feedback[11], error_ppdu_tx_interrupt_rx[12], error_rx_unsupported_cbf[13], reserved_1[31:14] // // ################ END SUMMARY ################# #define NUM_OF_DWORDS_RX_PHY_PPDU_END 2 struct rx_phy_ppdu_end { volatile uint32_t reserved_0a : 2, //[1:0] error_radar : 1, //[2] error_rx_abort : 1, //[3] error_rx_nap : 1, //[4] error_ofdm_timing : 1, //[5] error_ofdm_signal_parity : 1, //[6] error_ofdm_rate_illegal : 1, //[7] error_ofdm_length_illegal : 1, //[8] error_ppdu_ofdm_restart : 1, //[9] error_ofdm_service : 1, //[10] error_ppdu_ofdm_power_drop : 1, //[11] error_cck_blocker : 1, //[12] error_cck_timing : 1, //[13] error_cck_header_crc : 1, //[14] error_cck_rate_illegal : 1, //[15] error_cck_length_illegal : 1, //[16] error_ppdu_cck_restart : 1, //[17] error_cck_service : 1, //[18] error_ppdu_cck_power_drop : 1, //[19] error_ht_crc_err : 1, //[20] error_ht_length_illegal : 1, //[21] error_ht_rate_illegal : 1, //[22] error_ht_zlf : 1, //[23] error_false_radar_ext : 1, //[24] error_green_field : 1, //[25] error_spectral_scan : 1, //[26] error_rx_bw_gt_dyn_bw : 1, //[27] error_leg_ht_mismatch : 1, //[28] error_vht_crc_error : 1, //[29] error_vht_siga_unsupported : 1, //[30] error_vht_lsig_len_invalid : 1; //[31] volatile uint32_t error_vht_ndp_or_zlf : 1, //[0] error_vht_nsym_lt_zero : 1, //[1] error_vht_rx_extra_symbol_mismatch: 1, //[2] error_vht_rx_skip_group_id0 : 1, //[3] error_vht_rx_skip_group_id1to62 : 1, //[4] error_vht_rx_skip_group_id63 : 1, //[5] error_ofdm_ldpc_decoder_disabled: 1, //[6] error_defer_nap : 1, //[7] error_fdomain_timeout : 1, //[8] error_lsig_rel_check : 1, //[9] error_bt_collision : 1, //[10] error_unsupported_mu_feedback : 1, //[11] error_ppdu_tx_interrupt_rx : 1, //[12] error_rx_unsupported_cbf : 1, //[13] reserved_1 : 18; //[31:14] }; /* reserved_0a error_radar error_rx_abort PSDU terminated due to PHY_OFF message error_rx_nap Not used in Cascade Note that if MAC sends RX_PHY_NAP to PHY, error_defer_nap is set. Also, If Nsts is 0 for MU TxBF packet, PHY will report error_defer_nap as well. error_ofdm_timing error_ofdm_signal_parity error_ofdm_rate_illegal error_ofdm_length_illegal error_ppdu_ofdm_restart error_ofdm_service error_ppdu_ofdm_power_drop error_cck_blocker error_cck_timing error_cck_header_crc error_cck_rate_illegal error_cck_length_illegal error_ppdu_cck_restart error_cck_service error_ppdu_cck_power_drop error_ht_crc_err error_ht_length_illegal error_ht_rate_illegal error_ht_zlf error_false_radar_ext error_green_field error_spectral_scan error_rx_bw_gt_dyn_bw error_leg_ht_mismatch error_vht_crc_error error_vht_siga_unsupported error_vht_lsig_len_invalid error_vht_ndp_or_zlf Is this needed??? This should be an error anymore error_vht_nsym_lt_zero error_vht_rx_extra_symbol_mismatch error_vht_rx_skip_group_id0 error_vht_rx_skip_group_id1to62 error_vht_rx_skip_group_id63 error_ofdm_ldpc_decoder_disabled error_defer_nap error_fdomain_timeout error_lsig_rel_check error_bt_collision PHY will also set this field to 0. This error is added by the MAC. error_unsupported_mu_feedback error_ppdu_tx_interrupt_rx error_rx_unsupported_cbf reserved_1 */ /* Description RX_PHY_PPDU_END_0_RESERVED_0A */ #define RX_PHY_PPDU_END_0_RESERVED_0A_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_RESERVED_0A_LSB 0 #define RX_PHY_PPDU_END_0_RESERVED_0A_MASK 0x00000003 /* Description RX_PHY_PPDU_END_0_ERROR_RADAR */ #define RX_PHY_PPDU_END_0_ERROR_RADAR_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_RADAR_LSB 2 #define RX_PHY_PPDU_END_0_ERROR_RADAR_MASK 0x00000004 /* Description RX_PHY_PPDU_END_0_ERROR_RX_ABORT PSDU terminated due to PHY_OFF message */ #define RX_PHY_PPDU_END_0_ERROR_RX_ABORT_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_RX_ABORT_LSB 3 #define RX_PHY_PPDU_END_0_ERROR_RX_ABORT_MASK 0x00000008 /* Description RX_PHY_PPDU_END_0_ERROR_RX_NAP Not used in Cascade Note that if MAC sends RX_PHY_NAP to PHY, error_defer_nap is set. Also, If Nsts is 0 for MU TxBF packet, PHY will report error_defer_nap as well. */ #define RX_PHY_PPDU_END_0_ERROR_RX_NAP_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_RX_NAP_LSB 4 #define RX_PHY_PPDU_END_0_ERROR_RX_NAP_MASK 0x00000010 /* Description RX_PHY_PPDU_END_0_ERROR_OFDM_TIMING */ #define RX_PHY_PPDU_END_0_ERROR_OFDM_TIMING_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_OFDM_TIMING_LSB 5 #define RX_PHY_PPDU_END_0_ERROR_OFDM_TIMING_MASK 0x00000020 /* Description RX_PHY_PPDU_END_0_ERROR_OFDM_SIGNAL_PARITY */ #define RX_PHY_PPDU_END_0_ERROR_OFDM_SIGNAL_PARITY_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_OFDM_SIGNAL_PARITY_LSB 6 #define RX_PHY_PPDU_END_0_ERROR_OFDM_SIGNAL_PARITY_MASK 0x00000040 /* Description RX_PHY_PPDU_END_0_ERROR_OFDM_RATE_ILLEGAL */ #define RX_PHY_PPDU_END_0_ERROR_OFDM_RATE_ILLEGAL_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_OFDM_RATE_ILLEGAL_LSB 7 #define RX_PHY_PPDU_END_0_ERROR_OFDM_RATE_ILLEGAL_MASK 0x00000080 /* Description RX_PHY_PPDU_END_0_ERROR_OFDM_LENGTH_ILLEGAL */ #define RX_PHY_PPDU_END_0_ERROR_OFDM_LENGTH_ILLEGAL_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_OFDM_LENGTH_ILLEGAL_LSB 8 #define RX_PHY_PPDU_END_0_ERROR_OFDM_LENGTH_ILLEGAL_MASK 0x00000100 /* Description RX_PHY_PPDU_END_0_ERROR_PPDU_OFDM_RESTART */ #define RX_PHY_PPDU_END_0_ERROR_PPDU_OFDM_RESTART_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_PPDU_OFDM_RESTART_LSB 9 #define RX_PHY_PPDU_END_0_ERROR_PPDU_OFDM_RESTART_MASK 0x00000200 /* Description RX_PHY_PPDU_END_0_ERROR_OFDM_SERVICE */ #define RX_PHY_PPDU_END_0_ERROR_OFDM_SERVICE_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_OFDM_SERVICE_LSB 10 #define RX_PHY_PPDU_END_0_ERROR_OFDM_SERVICE_MASK 0x00000400 /* Description RX_PHY_PPDU_END_0_ERROR_PPDU_OFDM_POWER_DROP */ #define RX_PHY_PPDU_END_0_ERROR_PPDU_OFDM_POWER_DROP_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_PPDU_OFDM_POWER_DROP_LSB 11 #define RX_PHY_PPDU_END_0_ERROR_PPDU_OFDM_POWER_DROP_MASK 0x00000800 /* Description RX_PHY_PPDU_END_0_ERROR_CCK_BLOCKER */ #define RX_PHY_PPDU_END_0_ERROR_CCK_BLOCKER_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_CCK_BLOCKER_LSB 12 #define RX_PHY_PPDU_END_0_ERROR_CCK_BLOCKER_MASK 0x00001000 /* Description RX_PHY_PPDU_END_0_ERROR_CCK_TIMING */ #define RX_PHY_PPDU_END_0_ERROR_CCK_TIMING_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_CCK_TIMING_LSB 13 #define RX_PHY_PPDU_END_0_ERROR_CCK_TIMING_MASK 0x00002000 /* Description RX_PHY_PPDU_END_0_ERROR_CCK_HEADER_CRC */ #define RX_PHY_PPDU_END_0_ERROR_CCK_HEADER_CRC_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_CCK_HEADER_CRC_LSB 14 #define RX_PHY_PPDU_END_0_ERROR_CCK_HEADER_CRC_MASK 0x00004000 /* Description RX_PHY_PPDU_END_0_ERROR_CCK_RATE_ILLEGAL */ #define RX_PHY_PPDU_END_0_ERROR_CCK_RATE_ILLEGAL_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_CCK_RATE_ILLEGAL_LSB 15 #define RX_PHY_PPDU_END_0_ERROR_CCK_RATE_ILLEGAL_MASK 0x00008000 /* Description RX_PHY_PPDU_END_0_ERROR_CCK_LENGTH_ILLEGAL */ #define RX_PHY_PPDU_END_0_ERROR_CCK_LENGTH_ILLEGAL_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_CCK_LENGTH_ILLEGAL_LSB 16 #define RX_PHY_PPDU_END_0_ERROR_CCK_LENGTH_ILLEGAL_MASK 0x00010000 /* Description RX_PHY_PPDU_END_0_ERROR_PPDU_CCK_RESTART */ #define RX_PHY_PPDU_END_0_ERROR_PPDU_CCK_RESTART_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_PPDU_CCK_RESTART_LSB 17 #define RX_PHY_PPDU_END_0_ERROR_PPDU_CCK_RESTART_MASK 0x00020000 /* Description RX_PHY_PPDU_END_0_ERROR_CCK_SERVICE */ #define RX_PHY_PPDU_END_0_ERROR_CCK_SERVICE_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_CCK_SERVICE_LSB 18 #define RX_PHY_PPDU_END_0_ERROR_CCK_SERVICE_MASK 0x00040000 /* Description RX_PHY_PPDU_END_0_ERROR_PPDU_CCK_POWER_DROP */ #define RX_PHY_PPDU_END_0_ERROR_PPDU_CCK_POWER_DROP_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_PPDU_CCK_POWER_DROP_LSB 19 #define RX_PHY_PPDU_END_0_ERROR_PPDU_CCK_POWER_DROP_MASK 0x00080000 /* Description RX_PHY_PPDU_END_0_ERROR_HT_CRC_ERR */ #define RX_PHY_PPDU_END_0_ERROR_HT_CRC_ERR_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_HT_CRC_ERR_LSB 20 #define RX_PHY_PPDU_END_0_ERROR_HT_CRC_ERR_MASK 0x00100000 /* Description RX_PHY_PPDU_END_0_ERROR_HT_LENGTH_ILLEGAL */ #define RX_PHY_PPDU_END_0_ERROR_HT_LENGTH_ILLEGAL_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_HT_LENGTH_ILLEGAL_LSB 21 #define RX_PHY_PPDU_END_0_ERROR_HT_LENGTH_ILLEGAL_MASK 0x00200000 /* Description RX_PHY_PPDU_END_0_ERROR_HT_RATE_ILLEGAL */ #define RX_PHY_PPDU_END_0_ERROR_HT_RATE_ILLEGAL_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_HT_RATE_ILLEGAL_LSB 22 #define RX_PHY_PPDU_END_0_ERROR_HT_RATE_ILLEGAL_MASK 0x00400000 /* Description RX_PHY_PPDU_END_0_ERROR_HT_ZLF */ #define RX_PHY_PPDU_END_0_ERROR_HT_ZLF_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_HT_ZLF_LSB 23 #define RX_PHY_PPDU_END_0_ERROR_HT_ZLF_MASK 0x00800000 /* Description RX_PHY_PPDU_END_0_ERROR_FALSE_RADAR_EXT */ #define RX_PHY_PPDU_END_0_ERROR_FALSE_RADAR_EXT_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_FALSE_RADAR_EXT_LSB 24 #define RX_PHY_PPDU_END_0_ERROR_FALSE_RADAR_EXT_MASK 0x01000000 /* Description RX_PHY_PPDU_END_0_ERROR_GREEN_FIELD */ #define RX_PHY_PPDU_END_0_ERROR_GREEN_FIELD_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_GREEN_FIELD_LSB 25 #define RX_PHY_PPDU_END_0_ERROR_GREEN_FIELD_MASK 0x02000000 /* Description RX_PHY_PPDU_END_0_ERROR_SPECTRAL_SCAN */ #define RX_PHY_PPDU_END_0_ERROR_SPECTRAL_SCAN_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_SPECTRAL_SCAN_LSB 26 #define RX_PHY_PPDU_END_0_ERROR_SPECTRAL_SCAN_MASK 0x04000000 /* Description RX_PHY_PPDU_END_0_ERROR_RX_BW_GT_DYN_BW */ #define RX_PHY_PPDU_END_0_ERROR_RX_BW_GT_DYN_BW_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_RX_BW_GT_DYN_BW_LSB 27 #define RX_PHY_PPDU_END_0_ERROR_RX_BW_GT_DYN_BW_MASK 0x08000000 /* Description RX_PHY_PPDU_END_0_ERROR_LEG_HT_MISMATCH */ #define RX_PHY_PPDU_END_0_ERROR_LEG_HT_MISMATCH_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_LEG_HT_MISMATCH_LSB 28 #define RX_PHY_PPDU_END_0_ERROR_LEG_HT_MISMATCH_MASK 0x10000000 /* Description RX_PHY_PPDU_END_0_ERROR_VHT_CRC_ERROR */ #define RX_PHY_PPDU_END_0_ERROR_VHT_CRC_ERROR_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_VHT_CRC_ERROR_LSB 29 #define RX_PHY_PPDU_END_0_ERROR_VHT_CRC_ERROR_MASK 0x20000000 /* Description RX_PHY_PPDU_END_0_ERROR_VHT_SIGA_UNSUPPORTED */ #define RX_PHY_PPDU_END_0_ERROR_VHT_SIGA_UNSUPPORTED_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_VHT_SIGA_UNSUPPORTED_LSB 30 #define RX_PHY_PPDU_END_0_ERROR_VHT_SIGA_UNSUPPORTED_MASK 0x40000000 /* Description RX_PHY_PPDU_END_0_ERROR_VHT_LSIG_LEN_INVALID */ #define RX_PHY_PPDU_END_0_ERROR_VHT_LSIG_LEN_INVALID_OFFSET 0x00000000 #define RX_PHY_PPDU_END_0_ERROR_VHT_LSIG_LEN_INVALID_LSB 31 #define RX_PHY_PPDU_END_0_ERROR_VHT_LSIG_LEN_INVALID_MASK 0x80000000 /* Description RX_PHY_PPDU_END_1_ERROR_VHT_NDP_OR_ZLF Is this needed??? This should be an error anymore */ #define RX_PHY_PPDU_END_1_ERROR_VHT_NDP_OR_ZLF_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_VHT_NDP_OR_ZLF_LSB 0 #define RX_PHY_PPDU_END_1_ERROR_VHT_NDP_OR_ZLF_MASK 0x00000001 /* Description RX_PHY_PPDU_END_1_ERROR_VHT_NSYM_LT_ZERO */ #define RX_PHY_PPDU_END_1_ERROR_VHT_NSYM_LT_ZERO_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_VHT_NSYM_LT_ZERO_LSB 1 #define RX_PHY_PPDU_END_1_ERROR_VHT_NSYM_LT_ZERO_MASK 0x00000002 /* Description RX_PHY_PPDU_END_1_ERROR_VHT_RX_EXTRA_SYMBOL_MISMATCH */ #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_EXTRA_SYMBOL_MISMATCH_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_EXTRA_SYMBOL_MISMATCH_LSB 2 #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_EXTRA_SYMBOL_MISMATCH_MASK 0x00000004 /* Description RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID0 */ #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID0_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID0_LSB 3 #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID0_MASK 0x00000008 /* Description RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID1TO62 */ #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID1TO62_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID1TO62_LSB 4 #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID1TO62_MASK 0x00000010 /* Description RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID63 */ #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID63_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID63_LSB 5 #define RX_PHY_PPDU_END_1_ERROR_VHT_RX_SKIP_GROUP_ID63_MASK 0x00000020 /* Description RX_PHY_PPDU_END_1_ERROR_OFDM_LDPC_DECODER_DISABLED */ #define RX_PHY_PPDU_END_1_ERROR_OFDM_LDPC_DECODER_DISABLED_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_OFDM_LDPC_DECODER_DISABLED_LSB 6 #define RX_PHY_PPDU_END_1_ERROR_OFDM_LDPC_DECODER_DISABLED_MASK 0x00000040 /* Description RX_PHY_PPDU_END_1_ERROR_DEFER_NAP */ #define RX_PHY_PPDU_END_1_ERROR_DEFER_NAP_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_DEFER_NAP_LSB 7 #define RX_PHY_PPDU_END_1_ERROR_DEFER_NAP_MASK 0x00000080 /* Description RX_PHY_PPDU_END_1_ERROR_FDOMAIN_TIMEOUT */ #define RX_PHY_PPDU_END_1_ERROR_FDOMAIN_TIMEOUT_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_FDOMAIN_TIMEOUT_LSB 8 #define RX_PHY_PPDU_END_1_ERROR_FDOMAIN_TIMEOUT_MASK 0x00000100 /* Description RX_PHY_PPDU_END_1_ERROR_LSIG_REL_CHECK */ #define RX_PHY_PPDU_END_1_ERROR_LSIG_REL_CHECK_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_LSIG_REL_CHECK_LSB 9 #define RX_PHY_PPDU_END_1_ERROR_LSIG_REL_CHECK_MASK 0x00000200 /* Description RX_PHY_PPDU_END_1_ERROR_BT_COLLISION PHY will also set this field to 0. This error is added by the MAC. */ #define RX_PHY_PPDU_END_1_ERROR_BT_COLLISION_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_BT_COLLISION_LSB 10 #define RX_PHY_PPDU_END_1_ERROR_BT_COLLISION_MASK 0x00000400 /* Description RX_PHY_PPDU_END_1_ERROR_UNSUPPORTED_MU_FEEDBACK */ #define RX_PHY_PPDU_END_1_ERROR_UNSUPPORTED_MU_FEEDBACK_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_UNSUPPORTED_MU_FEEDBACK_LSB 11 #define RX_PHY_PPDU_END_1_ERROR_UNSUPPORTED_MU_FEEDBACK_MASK 0x00000800 /* Description RX_PHY_PPDU_END_1_ERROR_PPDU_TX_INTERRUPT_RX */ #define RX_PHY_PPDU_END_1_ERROR_PPDU_TX_INTERRUPT_RX_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_PPDU_TX_INTERRUPT_RX_LSB 12 #define RX_PHY_PPDU_END_1_ERROR_PPDU_TX_INTERRUPT_RX_MASK 0x00001000 /* Description RX_PHY_PPDU_END_1_ERROR_RX_UNSUPPORTED_CBF */ #define RX_PHY_PPDU_END_1_ERROR_RX_UNSUPPORTED_CBF_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_ERROR_RX_UNSUPPORTED_CBF_LSB 13 #define RX_PHY_PPDU_END_1_ERROR_RX_UNSUPPORTED_CBF_MASK 0x00002000 /* Description RX_PHY_PPDU_END_1_RESERVED_1 */ #define RX_PHY_PPDU_END_1_RESERVED_1_OFFSET 0x00000004 #define RX_PHY_PPDU_END_1_RESERVED_1_LSB 14 #define RX_PHY_PPDU_END_1_RESERVED_1_MASK 0xffffc000 #endif // _RX_PHY_PPDU_END_H_