/* * Copyright (c) 2015 Qualcomm Atheros, Inc. * All Rights Reserved. * Qualcomm Atheros Confidential and Proprietary. */ package RegAccess; use strict; use Class::Struct; use constant regMapStruct => { ################################################################### ## pcie_local_reg Register/Field definitions ################################################################### "RTC_STATE" => { type => "reg", addr => 0x0, width => 32, athEmulAttr => 0, acc => "RO" }, "RTC_STATE.COLD_RESET" => { type => "field", addr => 0x0, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RTC_STATE.XTAL_COUNT" => { type => "field", addr => 0x0, width => 10, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RTC_STATE.V" => { type => "field", addr => 0x0, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PCIE_SOC_WAKE" => { type => "reg", addr => 0x4, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_SOC_WAKE.V" => { type => "field", addr => 0x4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "SOC_GLOBAL_RESET" => { type => "reg", addr => 0x8, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_GLOBAL_RESET.MASK_SOC_RST_TO_PCIE_BRIDGE" => { type => "field", addr => 0x8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "SOC_GLOBAL_RESET.V" => { type => "field", addr => 0x8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_LOCAL_CTRL_OBS_MUX" => { type => "reg", addr => 0x10, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_LOCAL_CTRL_OBS_MUX.SEL" => { type => "field", addr => 0x10, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_DEBUG_LOCAL" => { type => "reg", addr => 0x14, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_DEBUG_LOCAL.V" => { type => "field", addr => 0x14, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PCIE_BAR_VALID" => { type => "reg", addr => 0x18, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_BAR_VALID.DBG" => { type => "field", addr => 0x18, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_SOC_RDY_STATUS" => { type => "reg", addr => 0x1c, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_SOC_RDY_STATUS.VAL" => { type => "field", addr => 0x1c, width => 31, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PCIE_SOC_RDY_STATUS.BAR" => { type => "field", addr => 0x1c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, ################################################################### ## bb_reg_map Register/Field definitions ################################################################### ################################################################### ## bb_reg_map.bb_agc_reg_map Register/Field definitions ################################################################### "BB_settling_time" => { type => "reg", addr => 0x10000, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_settling_time.lbreset_advance" => { type => "field", addr => 0x10000, width => 4, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_settling_time.switch_settling" => { type => "field", addr => 0x10000, width => 7, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_settling_time.agc_settling" => { type => "field", addr => 0x10000, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b0" => { type => "reg", addr => 0x10004, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_gain_force_max_gains_b0.xatten2_hyst_margin_0" => { type => "field", addr => 0x10004, width => 7, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b0.xatten1_hyst_margin_0" => { type => "field", addr => 0x10004, width => 7, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b0.xatten2_sw_f_0" => { type => "field", addr => 0x10004, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b0.xatten1_sw_f_0" => { type => "field", addr => 0x10004, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b0.mb_gain_f_0" => { type => "field", addr => 0x10004, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b0.rf_gain_f_0" => { type => "field", addr => 0x10004, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gains_min_offsets" => { type => "reg", addr => 0x10008, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_gains_min_offsets.enable_ant_fast_gc_ctrl" => { type => "field", addr => 0x10008, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gains_min_offsets.use_fixed_gain" => { type => "field", addr => 0x10008, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gains_min_offsets.enable_srch_start_gain" => { type => "field", addr => 0x10008, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gains_min_offsets.cf_agc_hist_phy_err" => { type => "field", addr => 0x10008, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gains_min_offsets.cf_agc_hist_voting" => { type => "field", addr => 0x10008, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gains_min_offsets.cf_agc_hist_gc" => { type => "field", addr => 0x10008, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gains_min_offsets.cf_agc_hist_enable" => { type => "field", addr => 0x10008, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gains_min_offsets.gain_force" => { type => "field", addr => 0x10008, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gains_min_offsets.offsetC3" => { type => "field", addr => 0x10008, width => 5, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gains_min_offsets.offsetC2" => { type => "field", addr => 0x10008, width => 5, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gains_min_offsets.offsetC1" => { type => "field", addr => 0x10008, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_desired_sigsize" => { type => "reg", addr => 0x1000c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_desired_sigsize.ena_init_gain" => { type => "field", addr => 0x1000c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_desired_sigsize.reduce_init_gc_count" => { type => "field", addr => 0x1000c, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_desired_sigsize.init_gc_count_max" => { type => "field", addr => 0x1000c, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_desired_sigsize.total_desired" => { type => "field", addr => 0x1000c, width => 8, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_desired_sigsize.disable_fine_rfsat" => { type => "field", addr => 0x1000c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_desired_sigsize.adc_desired_size" => { type => "field", addr => 0x1000c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_find_signal" => { type => "reg", addr => 0x10010, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_find_signal.m1count_max" => { type => "field", addr => 0x10010, width => 6, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x1f }, "BB_find_signal.firpwr" => { type => "field", addr => 0x10010, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0xb2 }, "BB_find_signal.firstep" => { type => "field", addr => 0x10010, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x04 }, "BB_find_signal.relstep" => { type => "field", addr => 0x10010, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x2e }, "BB_agc" => { type => "reg", addr => 0x10014, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc.rssi_out_select" => { type => "field", addr => 0x10014, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_agc.pwrlow_gain_thr" => { type => "field", addr => 0x10014, width => 8, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 40 }, "BB_agc.coarse_high" => { type => "field", addr => 0x10014, width => 7, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_agc.coarse_low" => { type => "field", addr => 0x10014, width => 8, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_agc.coarsepwr_const" => { type => "field", addr => 0x10014, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_atten_switch_ctl_b0" => { type => "reg", addr => 0x10018, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ext_atten_switch_ctl_b0.xlna_gain_db_0" => { type => "field", addr => 0x10018, width => 5, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_atten_switch_ctl_b0.xatten2_margin_0" => { type => "field", addr => 0x10018, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_atten_switch_ctl_b0.xatten1_margin_0" => { type => "field", addr => 0x10018, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 50 }, "BB_ext_atten_switch_ctl_b0.xatten2_db_0" => { type => "field", addr => 0x10018, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_atten_switch_ctl_b0.xatten1_db_0" => { type => "field", addr => 0x10018, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cca_b0" => { type => "reg", addr => 0x1001c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cca_b0.minCCApwr_0" => { type => "field", addr => 0x1001c, width => 9, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cca_b0.thr_cca" => { type => "field", addr => 0x1001c, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 28 }, "BB_cca_b0.cf_cca_count_maxC" => { type => "field", addr => 0x1001c, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "BB_cca_b0.cf_maxCCApwr_0" => { type => "field", addr => 0x1001c, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1a6 }, "BB_cca_ctrl_2_b0" => { type => "reg", addr => 0x10020, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cca_ctrl_2_b0.minCCA_same_per_segment" => { type => "field", addr => 0x10020, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cca_ctrl_2_b0.minCCA_firpwr_thr" => { type => "field", addr => 0x10020, width => 8, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0xa6 }, "BB_cca_ctrl_2_b0.cca_avg_ena" => { type => "field", addr => 0x10020, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_cca_ctrl_2_b0.thr_cca_mode" => { type => "field", addr => 0x10020, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cca_ctrl_2_b0.NF_gain_comp_0" => { type => "field", addr => 0x10020, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cca_ctrl_2_b0.enable_minCCApwr_thr" => { type => "field", addr => 0x10020, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cca_ctrl_2_b0.minCCApwr_thr_0" => { type => "field", addr => 0x10020, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_restart" => { type => "reg", addr => 0x10024, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_restart.dfs_restart_mode" => { type => "field", addr => 0x10024, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_restart.dfs_restart_ena" => { type => "field", addr => 0x10024, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_restart.enable_pwr_drop_err_cck" => { type => "field", addr => 0x10024, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_restart.weak_rssi_vote_thr" => { type => "field", addr => 0x10024, width => 7, bitOffset => 22, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_restart.enable_ant_fast_div_m2flag" => { type => "field", addr => 0x10024, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_restart.ant_fast_div_gc_limit" => { type => "field", addr => 0x10024, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_restart.ofdm_cck_rssi_bias" => { type => "field", addr => 0x10024, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_restart.pwrdrop_lgfirpwr_delta" => { type => "field", addr => 0x10024, width => 5, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_restart.enable_pwr_drop_err" => { type => "field", addr => 0x10024, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_restart.restart_lgfirpwr_delta" => { type => "field", addr => 0x10024, width => 5, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_restart.enable_restart" => { type => "field", addr => 0x10024, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_multichain_gain_ctrl" => { type => "reg", addr => 0x10028, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_multichain_gain_ctrl.ant_div_sw_com_lock" => { type => "field", addr => 0x10028, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_gain_ctrl.ant_div_main_gaintb" => { type => "field", addr => 0x10028, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_gain_ctrl.ant_div_alt_gaintb" => { type => "field", addr => 0x10028, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_gain_ctrl.ant_div_main_lnaconf" => { type => "field", addr => 0x10028, width => 2, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_multichain_gain_ctrl.ant_div_alt_lnaconf" => { type => "field", addr => 0x10028, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_multichain_gain_ctrl.enable_ant_div_lnadiv" => { type => "field", addr => 0x10028, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_gain_ctrl.enable_ant_sw_rx_prot" => { type => "field", addr => 0x10028, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_gain_ctrl.quant_noise_floor_ena" => { type => "field", addr => 0x10028, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_gain_ctrl.quant_noise_floor_db" => { type => "field", addr => 0x10028, width => 6, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_gain_ctrl.ant_fast_div_bias" => { type => "field", addr => 0x10028, width => 6, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_gain_ctrl.enable_check_strong_ant" => { type => "field", addr => 0x10028, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_chan_pwr_thr_1" => { type => "reg", addr => 0x1002c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ext_chan_pwr_thr_1.ant_div_alt_ant_deltaNF" => { type => "field", addr => 0x1002c, width => 6, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_chan_pwr_thr_1.ant_div_alt_ant_deltaGainIdx" => { type => "field", addr => 0x1002c, width => 5, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_chan_pwr_thr_1.ant_div_alt_ant_minGainIdx" => { type => "field", addr => 0x1002c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_chan_pwr_thr_1.thr_cca_ext40" => { type => "field", addr => 0x1002c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_bw_pwr_thr" => { type => "reg", addr => 0x10030, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ext_bw_pwr_thr.minCCA_relpwr_thr" => { type => "field", addr => 0x10030, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0xe0 }, "BB_ext_bw_pwr_thr.bw_det_ext40_max_delta_db" => { type => "field", addr => 0x10030, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_ext_bw_pwr_thr.bw_det_ext20_max_delta_db" => { type => "field", addr => 0x10030, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_ext_bw_pwr_thr.bw_det_pri20_min_rssi_db" => { type => "field", addr => 0x10030, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_ext_bw_pwr_thr_2" => { type => "reg", addr => 0x10034, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ext_bw_pwr_thr_2.thr_cca_ext80" => { type => "field", addr => 0x10034, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_bw_pwr_thr_2.bw_det_ext40_min_rssi_db" => { type => "field", addr => 0x10034, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_ext_bw_pwr_thr_2.bw_det_ext20_min_rssi_db" => { type => "field", addr => 0x10034, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_rifs_srch" => { type => "reg", addr => 0x10038, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rifs_srch.rifs_disable_cck_det" => { type => "field", addr => 0x10038, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_rifs_srch.rifs_disable_pwrlow_gc" => { type => "field", addr => 0x10038, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_rifs_srch.rifs_init_delay" => { type => "field", addr => 0x10038, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 400 }, "BB_rifs_srch.init_gain_dB_offset" => { type => "field", addr => 0x10038, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_peak_det_ctrl_1" => { type => "reg", addr => 0x1003c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_peak_det_ctrl_1.pwd_pkdet_during_rx" => { type => "field", addr => 0x1003c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_peak_det_ctrl_1.pwd_pkdet_during_cal" => { type => "field", addr => 0x1003c, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_peak_det_ctrl_1.peak_det_settling" => { type => "field", addr => 0x1003c, width => 7, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_peak_det_ctrl_1.peak_det_tally_thr_high_0" => { type => "field", addr => 0x1003c, width => 5, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_peak_det_ctrl_1.peak_det_tally_thr_med_0" => { type => "field", addr => 0x1003c, width => 5, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_peak_det_ctrl_1.peak_det_tally_thr_low_0" => { type => "field", addr => 0x1003c, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_peak_det_ctrl_1.peak_det_win_len" => { type => "field", addr => 0x1003c, width => 6, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 16 }, "BB_peak_det_ctrl_1.use_peak_det" => { type => "field", addr => 0x1003c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_peak_det_ctrl_1.use_oc_gain_table" => { type => "field", addr => 0x1003c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_peak_det_ctrl_2" => { type => "reg", addr => 0x10040, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_peak_det_ctrl_2.enable_rfsat_strong" => { type => "field", addr => 0x10040, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_peak_det_ctrl_2.enable_rfsat_restart" => { type => "field", addr => 0x10040, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_peak_det_ctrl_2.rf_gain_drop_db_non_0" => { type => "field", addr => 0x10040, width => 5, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_peak_det_ctrl_2.rf_gain_drop_db_high_0" => { type => "field", addr => 0x10040, width => 5, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 28 }, "BB_peak_det_ctrl_2.rf_gain_drop_db_med_0" => { type => "field", addr => 0x10040, width => 5, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_peak_det_ctrl_2.rf_gain_drop_db_low_0" => { type => "field", addr => 0x10040, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_rx_gain_bounds_1" => { type => "reg", addr => 0x10044, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_gain_bounds_1.rf_mb_gain_delta_max_db" => { type => "field", addr => 0x10044, width => 6, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 63 }, "BB_rx_gain_bounds_1.rx_ocgain_sel_5G" => { type => "field", addr => 0x10044, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_gain_bounds_1.rx_ocgain_sel_2G" => { type => "field", addr => 0x10044, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_gain_bounds_1.rx_max_rf_gain" => { type => "field", addr => 0x10044, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 46 }, "BB_rx_gain_bounds_1.rx_max_rf_gain_ref" => { type => "field", addr => 0x10044, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 40 }, "BB_rx_gain_bounds_1.rx_max_mb_gain" => { type => "field", addr => 0x10044, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 39 }, "BB_rx_gain_bounds_2" => { type => "reg", addr => 0x10048, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_gain_bounds_2.rf_gain_div_base_addr" => { type => "field", addr => 0x10048, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 80 }, "BB_rx_gain_bounds_2.rf_gain_base_addr" => { type => "field", addr => 0x10048, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 48 }, "BB_rx_gain_bounds_2.rf_gain_ref_base_addr" => { type => "field", addr => 0x10048, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 32 }, "BB_rx_gain_bounds_2.gc_rssi_low_db" => { type => "field", addr => 0x10048, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_peak_det_cal_ctrl" => { type => "reg", addr => 0x1004c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_peak_det_cal_ctrl.pkdet_cal_meas_time_sel" => { type => "field", addr => 0x1004c, width => 2, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_peak_det_cal_ctrl.pkdet_cal_bias" => { type => "field", addr => 0x1004c, width => 6, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_peak_det_cal_ctrl.pkdet_cal_win_thr" => { type => "field", addr => 0x1004c, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_agc_dig_dc_ctrl" => { type => "reg", addr => 0x10050, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc_dig_dc_ctrl.dig_dc_switch_cck" => { type => "field", addr => 0x10050, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_agc_dig_dc_ctrl.use_dig_dc" => { type => "field", addr => 0x10050, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_bt_coex_1" => { type => "reg", addr => 0x10054, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bt_coex_1.bt_rx_disable_NF_cal" => { type => "field", addr => 0x10054, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_1.bt_tx_disable_NF_cal" => { type => "field", addr => 0x10054, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_1.rf_gain_drop_db_high_1" => { type => "field", addr => 0x10054, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_1.rf_gain_drop_db_med_1" => { type => "field", addr => 0x10054, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_1.rf_gain_drop_db_low_1" => { type => "field", addr => 0x10054, width => 5, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_1.peak_det_tally_thr_high_1" => { type => "field", addr => 0x10054, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_1.peak_det_tally_thr_med_1" => { type => "field", addr => 0x10054, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_1.peak_det_tally_thr_low_1" => { type => "field", addr => 0x10054, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_2" => { type => "reg", addr => 0x10058, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bt_coex_2.rfsat_rx_rx" => { type => "field", addr => 0x10058, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_2.rf_gain_drop_db_high_2" => { type => "field", addr => 0x10058, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_2.rf_gain_drop_db_med_2" => { type => "field", addr => 0x10058, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_2.rf_gain_drop_db_low_2" => { type => "field", addr => 0x10058, width => 5, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_2.peak_det_tally_thr_high_2" => { type => "field", addr => 0x10058, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_2.peak_det_tally_thr_med_2" => { type => "field", addr => 0x10058, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_2.peak_det_tally_thr_low_2" => { type => "field", addr => 0x10058, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3" => { type => "reg", addr => 0x1005c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bt_coex_3.bt_rx_firpwr_incr" => { type => "field", addr => 0x1005c, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rf_gain_drop_db_non_2" => { type => "field", addr => 0x1005c, width => 5, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rf_gain_drop_db_non_1" => { type => "field", addr => 0x1005c, width => 5, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rfsat_eq_srch_rx" => { type => "field", addr => 0x1005c, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rfsat_eq_rx_srch" => { type => "field", addr => 0x1005c, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rfsat_eq_srch_srch" => { type => "field", addr => 0x1005c, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rfsat_wlan_srch_rx" => { type => "field", addr => 0x1005c, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rfsat_wlan_rx_srch" => { type => "field", addr => 0x1005c, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rfsat_wlan_srch_srch" => { type => "field", addr => 0x1005c, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rfsat_bt_srch_rx" => { type => "field", addr => 0x1005c, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rfsat_bt_rx_srch" => { type => "field", addr => 0x1005c, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_3.rfsat_bt_srch_srch" => { type => "field", addr => 0x1005c, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_4" => { type => "reg", addr => 0x10060, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bt_coex_4.rfgain_eqv_lna_3" => { type => "field", addr => 0x10060, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_4.rfgain_eqv_lna_2" => { type => "field", addr => 0x10060, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_4.rfgain_eqv_lna_1" => { type => "field", addr => 0x10060, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_4.rfgain_eqv_lna_0" => { type => "field", addr => 0x10060, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_5" => { type => "reg", addr => 0x10064, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bt_coex_5.rfgain_eqv_lna_7" => { type => "field", addr => 0x10064, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_5.rfgain_eqv_lna_6" => { type => "field", addr => 0x10064, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_5.rfgain_eqv_lna_5" => { type => "field", addr => 0x10064, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bt_coex_5.rfgain_eqv_lna_4" => { type => "field", addr => 0x10064, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dyn_adc_size_ctrl" => { type => "reg", addr => 0x10068, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dyn_adc_size_ctrl.adc_size_desired_min_db2" => { type => "field", addr => 0x10068, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0xB6 }, "BB_dyn_adc_size_ctrl.adc_size_desired_max_db2" => { type => "field", addr => 0x10068, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0xe2 }, "BB_dyn_adc_size_ctrl.rssi_pri_high_thr" => { type => "field", addr => 0x10068, width => 7, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 37 }, "BB_dyn_adc_size_ctrl.alpha_adc_size_relpwr" => { type => "field", addr => 0x10068, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dyn_adc_size_ctrl.alpha_adc_size_rssi" => { type => "field", addr => 0x10068, width => 2, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_dyn_adc_size_ctrl.enable_dynamic_adc_sizing" => { type => "field", addr => 0x10068, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_lo_dccal_ctrl" => { type => "reg", addr => 0x1006c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_lo_dccal_ctrl.calnum_txlb" => { type => "field", addr => 0x1006c, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "BB_rx_lo_dccal_ctrl.calnum_rx" => { type => "field", addr => 0x1006c, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "BB_adc_capture" => { type => "reg", addr => 0x10070, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_adc_capture.adc_capture_chn_idx" => { type => "field", addr => 0x10070, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_adc_capture.adc_capture_length" => { type => "field", addr => 0x10070, width => 14, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 2048 }, "BB_adc_capture.adc_capture_scale" => { type => "field", addr => 0x10070, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_adc_capture.adc_capture_gc_ena" => { type => "field", addr => 0x10070, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_adc_capture.adc_capture_format" => { type => "field", addr => 0x10070, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_adc_capture.adc_capture_overrun_flag" => { type => "field", addr => 0x10070, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_adc_capture.adc_capture_sat_flag" => { type => "field", addr => 0x10070, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_adc_capture.adc_capture_error_flag" => { type => "field", addr => 0x10070, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_adc_capture.adc_capture_active" => { type => "field", addr => 0x10070, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_find_signal_2" => { type => "reg", addr => 0x10074, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_find_signal_2.rssi_thr1b" => { type => "field", addr => 0x10074, width => 7, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_find_signal_2.enable_rssi_thr1b" => { type => "field", addr => 0x10074, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_find_signal_2.agcsm_skip_cal_after_reset" => { type => "field", addr => 0x10074, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_find_signal_2.disable_pwr_drop_last_two_sym_vht" => { type => "field", addr => 0x10074, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_find_signal_2.found_low" => { type => "field", addr => 0x10074, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0xc4 }, "BB_find_signal_2.found_low_ena" => { type => "field", addr => 0x10074, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_find_signal_2.relpwr_weak_db" => { type => "field", addr => 0x10074, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x2c }, "BB_peak_det_ctrl_3" => { type => "reg", addr => 0x10078, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_peak_det_ctrl_3.first_rfsat_gain_increase" => { type => "field", addr => 0x10078, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_peak_det_ctrl_3.xrf_gain_drop_db" => { type => "field", addr => 0x10078, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_peak_det_ctrl_3.xrf_gain_drop_ena" => { type => "field", addr => 0x10078, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_peak_det_ctrl_3.use_common_rf_gain_drop" => { type => "field", addr => 0x10078, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_peak_det_ctrl_3.peak_det_4win_thr" => { type => "field", addr => 0x10078, width => 2, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_peak_det_ctrl_3.peak_det_4win_ena" => { type => "field", addr => 0x10078, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_peak_det_ctrl_3.rfsat_2_add_rfgain_del" => { type => "field", addr => 0x10078, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 32 }, "BB_peak_det_ctrl_3.agc_dbdac_reg_setting" => { type => "field", addr => 0x10078, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_find_signal2" => { type => "reg", addr => 0x1007c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_find_signal2.relpwr" => { type => "field", addr => 0x1007c, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x24 }, "BB_srch_fft_ctrl_1" => { type => "reg", addr => 0x10080, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_srch_fft_ctrl_1.pulse_check_srch_fft" => { type => "field", addr => 0x10080, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_srch_fft_ctrl_1.spectral_scan_dBm_adj" => { type => "field", addr => 0x10080, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_srch_fft_ctrl_1.radar_fft_dBm_adj" => { type => "field", addr => 0x10080, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_srch_fft_ctrl_1.fft_check_fine_ena" => { type => "field", addr => 0x10080, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_srch_fft_ctrl_1.radar_fft_long_period" => { type => "field", addr => 0x10080, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_srch_fft_ctrl_1.srch_fft_scale_vec" => { type => "field", addr => 0x10080, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0xfff }, "BB_srch_fft_ctrl_1.spectral_scan_bin_scale" => { type => "field", addr => 0x10080, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_srch_fft_ctrl_1.radar_fft_bin_scale" => { type => "field", addr => 0x10080, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_srch_fft_ctrl_1.spectral_scan_rpt_mode" => { type => "field", addr => 0x10080, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_srch_fft_ctrl_1.radar_fft_rpt_mode" => { type => "field", addr => 0x10080, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_srch_fft_ctrl_1.spectral_scan_pwr_format" => { type => "field", addr => 0x10080, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_srch_fft_ctrl_1.radar_fft_pwr_format" => { type => "field", addr => 0x10080, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_srch_fft_ctrl_1.fft_check_radar_ena" => { type => "field", addr => 0x10080, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_srch_fft_ctrl_1.fft_check_wlan_ena" => { type => "field", addr => 0x10080, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_srch_fft_ctrl_2" => { type => "reg", addr => 0x10084, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_srch_fft_ctrl_2.str_bin_thr_radar" => { type => "field", addr => 0x10084, width => 6, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_srch_fft_ctrl_2.str_bin_thr_wlan" => { type => "field", addr => 0x10084, width => 6, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_srch_fft_ctrl_2.radar_fft_bw_priority" => { type => "field", addr => 0x10084, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_srch_fft_ctrl_2.srch_fft_ib_thr" => { type => "field", addr => 0x10084, width => 7, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_srch_fft_ctrl_2.srch_fft_sb_freq" => { type => "field", addr => 0x10084, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 931 }, "BB_srch_fft_ctrl_3" => { type => "reg", addr => 0x10088, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_srch_fft_ctrl_3.nb_tone_thr_radar_blk" => { type => "field", addr => 0x10088, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 20 }, "BB_srch_fft_ctrl_3.nb_tone_thr_radar_fine" => { type => "field", addr => 0x10088, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_srch_fft_ctrl_3.nb_tone_thr_radar_coarse" => { type => "field", addr => 0x10088, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_srch_fft_ctrl_3.nb_tone_thr_wlan" => { type => "field", addr => 0x10088, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 20 }, "BB_srch_fft_ctrl_4" => { type => "reg", addr => 0x1008c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_srch_fft_ctrl_4.radar_fft_short_rpt_sel" => { type => "field", addr => 0x1008c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_srch_fft_ctrl_4.srch_fft_dc_scale_inband" => { type => "field", addr => 0x1008c, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_srch_fft_ctrl_4.srch_fft_pwr_drop_ratio" => { type => "field", addr => 0x1008c, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_srch_fft_ctrl_4.srch_fft_pwr_low_cap" => { type => "field", addr => 0x1008c, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 25 }, "BB_srch_fft_ctrl_4.srch_fft_rfsat_peakmag_thr" => { type => "field", addr => 0x1008c, width => 10, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 255 }, "BB_srch_fft_ctrl_4.spectral_scan_chn_mask" => { type => "field", addr => 0x1008c, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_srch_fft_ctrl_4.radar_fft_chn_mask" => { type => "field", addr => 0x1008c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_radar_chirp_detect" => { type => "reg", addr => 0x10090, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_radar_chirp_detect.chirp_fft_bw_check_ena" => { type => "field", addr => 0x10090, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_radar_chirp_detect.nonlin_vel_check_ena" => { type => "field", addr => 0x10090, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_radar_chirp_detect.chirp_max_num_fft_rpt" => { type => "field", addr => 0x10090, width => 5, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_radar_chirp_detect.srch_fft_str_rssi_thresh" => { type => "field", addr => 0x10090, width => 6, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_radar_chirp_detect.chirp_max_delta_diff" => { type => "field", addr => 0x10090, width => 4, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_radar_chirp_detect.chirp_max_delta_bin" => { type => "field", addr => 0x10090, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 11 }, "BB_radar_chirp_detect.chirp_min_delta_bin" => { type => "field", addr => 0x10090, width => 5, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_radar_chirp_detect.chirp_max_num_diff" => { type => "field", addr => 0x10090, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_spectral_scan_2" => { type => "reg", addr => 0x10098, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spectral_scan_2.spectral_scan_rssi_rpt_mode" => { type => "field", addr => 0x10098, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_spectral_scan_2.spectral_scan_wb_rpt_mode" => { type => "field", addr => 0x10098, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_spectral_scan_2.spectral_scan_str_bin_thr" => { type => "field", addr => 0x10098, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_spectral_scan_2.spectral_scan_nb_tone_thr" => { type => "field", addr => 0x10098, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_spectral_scan_2.spectral_scan_init_delay" => { type => "field", addr => 0x10098, width => 7, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 80 }, "BB_spectral_scan_2.spectral_scan_noise_floor_ref" => { type => "field", addr => 0x10098, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xa0 }, "BB_spectral_scan_3" => { type => "reg", addr => 0x1009c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spectral_scan_3.spectral_scan_rssi_thr" => { type => "field", addr => 0x1009c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "BB_agc_timeout_1" => { type => "reg", addr => 0x100a0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc_timeout_1.agc_ht_stf_sm_timeout" => { type => "field", addr => 0x100a0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "BB_agc_timeout_1.sscan_sm_timeout" => { type => "field", addr => 0x100a0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "BB_agc_timeout_1.radar_sm_timeout" => { type => "field", addr => 0x100a0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "BB_adcsat_ctrl_1" => { type => "reg", addr => 0x100a4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_adcsat_ctrl_1.adcsat_cnt_thr" => { type => "field", addr => 0x100a4, width => 5, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_adcsat_ctrl_1.adcsat_win_len" => { type => "field", addr => 0x100a4, width => 5, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 16 }, "BB_adcsat_ctrl_1.adcsat_clip_found_thr" => { type => "field", addr => 0x100a4, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 247 }, "BB_adcsat_ctrl_1.adcsat_clip_coarse_thr" => { type => "field", addr => 0x100a4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 145 }, "BB_adcsat_ctrl_2" => { type => "reg", addr => 0x100a8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_adcsat_ctrl_2.use_rf_gain_for_xatten_control" => { type => "field", addr => 0x100a8, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_adcsat_ctrl_2.rf_reduce_only_gcmode1_recent_rfsat" => { type => "field", addr => 0x100a8, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_adcsat_ctrl_2.quickdrop_other" => { type => "field", addr => 0x100a8, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0xec }, "BB_adcsat_ctrl_2.quickdrop_found" => { type => "field", addr => 0x100a8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0xd8 }, "BB_adcsat_ctrl_2.quickdrop_coarse" => { type => "field", addr => 0x100a8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xd8 }, "BB_agc_spare_01" => { type => "reg", addr => 0x100ac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc_spare_01.agc_eco_ctrl" => { type => "field", addr => 0x100ac, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_agc_ht_stf_ctrl_1" => { type => "reg", addr => 0x100b0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc_ht_stf_ctrl_1.agc_ht_stf_min_adc_pwr" => { type => "field", addr => 0x100b0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0xe2 }, "BB_agc_ht_stf_ctrl_1.agc_ht_stf_min_lstf_pwr" => { type => "field", addr => 0x100b0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0xd8 }, "BB_agc_ht_stf_ctrl_1.agc_ht_stf_weak_size_desired" => { type => "field", addr => 0x100b0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0xc4 }, "BB_agc_ht_stf_ctrl_1.agc_ht_stf_pwr_delay" => { type => "field", addr => 0x100b0, width => 6, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 35 }, "BB_agc_ht_stf_ctrl_1.agc_ht_stf_allow_gain_incr" => { type => "field", addr => 0x100b0, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_agc_ht_stf_ctrl_1.agc_ht_stf_ena" => { type => "field", addr => 0x100b0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_agc_ht_stf_ctrl_2" => { type => "reg", addr => 0x100b4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc_ht_stf_ctrl_2.agc_ht_stf_settling" => { type => "field", addr => 0x100b4, width => 7, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 22 }, "BB_agc_ht_stf_ctrl_2.agc_ht_stf_allow_rf" => { type => "field", addr => 0x100b4, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_ht_stf_ctrl_2.agc_ht_stf_dc_est_win_sel" => { type => "field", addr => 0x100b4, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_agc_ht_stf_ctrl_2.agc_ht_stf_dc_est_ena" => { type => "field", addr => 0x100b4, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_agc_ht_stf_ctrl_2.vht_sym_det_num_bins" => { type => "field", addr => 0x100b4, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 11 }, "BB_agc_ht_stf_ctrl_2.agc_ht_stf_pwr_low_gc_thr" => { type => "field", addr => 0x100b4, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_agc_ht_stf_ctrl_2.agc_ht_stf_pwr_high_gc_thr" => { type => "field", addr => 0x100b4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_agc_ht_stf_ctrl_3" => { type => "reg", addr => 0x100b8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc_ht_stf_ctrl_3.agc_ht_stf_lsig_len_min" => { type => "field", addr => 0x100b8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_radar_lb_control" => { type => "reg", addr => 0x100bc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_radar_lb_control.force_adc_lb_bypass" => { type => "field", addr => 0x100bc, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_radar_lb_control.force_pwr_lb_bypass" => { type => "field", addr => 0x100bc, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_radar_lb_control.chirp_over_dc_interval" => { type => "field", addr => 0x100bc, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 20 }, "BB_radar_lb_control.chirp_over_dc_skip_ena" => { type => "field", addr => 0x100bc, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_lb_control.radar_lb_adapt_cmp_thr" => { type => "field", addr => 0x100bc, width => 5, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_radar_lb_control.radar_lb_conv_factor" => { type => "field", addr => 0x100bc, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 100 }, "BB_radar_lb_control.radar_lb_dc_cap_at_dc" => { type => "field", addr => 0x100bc, width => 9, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 20 }, "BB_radar_lb_control.radar_lb_mode" => { type => "field", addr => 0x100bc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_radar_pulse_thres1" => { type => "reg", addr => 0x100c0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_radar_pulse_thres1.radar_1st_fft_delay" => { type => "field", addr => 0x100c0, width => 6, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_pulse_thres1.pursue_ext80_radar" => { type => "field", addr => 0x100c0, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_pulse_thres1.radar_fft_80p80_rel_thrsh" => { type => "field", addr => 0x100c0, width => 6, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_pulse_thres1.pulse_at_dc_rssi_thresh" => { type => "field", addr => 0x100c0, width => 6, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_radar_pulse_thres1.long_pulse_rssi_thresh" => { type => "field", addr => 0x100c0, width => 6, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_radar_pulse_thres1.long_pulse_at_dc_rssi_thresh" => { type => "field", addr => 0x100c0, width => 6, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_radar_pulse_thres1.long_pulse_rssi_check_ena" => { type => "field", addr => 0x100c0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_radar_pulse_thres2" => { type => "reg", addr => 0x100c4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_radar_pulse_thres2.srch_fft_adcsat_peakmag_thr" => { type => "field", addr => 0x100c4, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 100 }, "BB_radar_pulse_thres2.nb_tone_thres_radar_chirp" => { type => "field", addr => 0x100c4, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_radar_pulse_thres2.str_bin_thr_radar_chirp" => { type => "field", addr => 0x100c4, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_radar_pulse_thres2.str_bin_thr_radar_fine" => { type => "field", addr => 0x100c4, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_ss_gain_ctrl_1" => { type => "reg", addr => 0x100c8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ss_gain_ctrl_1.ss_copy_target_power" => { type => "field", addr => 0x100c8, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ss_gain_ctrl_1.ss_gain_copy_reduce_db2" => { type => "field", addr => 0x100c8, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ss_gain_ctrl_1.ss_settle_time" => { type => "field", addr => 0x100c8, width => 7, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_ss_gain_ctrl_1.second_agc_use_16" => { type => "field", addr => 0x100c8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ss_gain_ctrl_1.ss_gain_copy_ena" => { type => "field", addr => 0x100c8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_agc_rtt_ctrl" => { type => "reg", addr => 0x100d0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc_rtt_ctrl.fixed_str_chain_rtt_en" => { type => "field", addr => 0x100d0, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_rtt_ctrl.fixed_str_chain_rtt" => { type => "field", addr => 0x100d0, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_rtt_ctrl.rtt_chain_sel_th_4" => { type => "field", addr => 0x100d0, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_gain_nf_en" => { type => "reg", addr => 0x10170, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_gain_nf_en.capture_nf_gain" => { type => "field", addr => 0x10170, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rssi_b0" => { type => "reg", addr => 0x10180, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rssi_b0.rssi_ext80_0" => { type => "field", addr => 0x10180, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rssi_b0.rssi_ext40_0" => { type => "field", addr => 0x10180, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rssi_b0.rssi_ext20_0" => { type => "field", addr => 0x10180, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rssi_b0.rssi_pri20_0" => { type => "field", addr => 0x10180, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_agc_dig_dc_status_b0" => { type => "reg", addr => 0x10188, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc_dig_dc_status_b0.dc_cal_residual_dc_q_0" => { type => "field", addr => 0x10188, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_agc_dig_dc_status_b0.dc_cal_residual_dc_i_0" => { type => "field", addr => 0x10188, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dc_cal_status_b0" => { type => "reg", addr => 0x101a0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_dc_cal_status_b0.offsetC2Q_0" => { type => "field", addr => 0x101a0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_b0.offsetC2I_0" => { type => "field", addr => 0x101a0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_b0.offsetC1Q_0" => { type => "field", addr => 0x101a0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_b0.offsetC1I_0" => { type => "field", addr => 0x101a0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_2_b0" => { type => "reg", addr => 0x101a4, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_dc_cal_status_2_b0.offsetC4Q_0" => { type => "field", addr => 0x101a4, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_2_b0.offsetC4I_0" => { type => "field", addr => 0x101a4, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_2_b0.offsetC3Q_0" => { type => "field", addr => 0x101a4, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_2_b0.offsetC3I_0" => { type => "field", addr => 0x101a4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_3_b0" => { type => "reg", addr => 0x101a8, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_dc_cal_status_3_b0.offsetC6Q_0" => { type => "field", addr => 0x101a8, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_dc_cal_status_3_b0.offsetC6I_0" => { type => "field", addr => 0x101a8, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_dc_cal_status_3_b0.offsetC5Q_0" => { type => "field", addr => 0x101a8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_dc_cal_status_3_b0.offsetC5I_0" => { type => "field", addr => 0x101a8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_dc_cal_status_4_b0" => { type => "reg", addr => 0x101ac, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_dc_cal_status_4_b0.offsetC7Q_0" => { type => "field", addr => 0x101ac, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_dc_cal_status_4_b0.offsetC7I_0" => { type => "field", addr => 0x101ac, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rx_gain_nf_b0" => { type => "reg", addr => 0x101b0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rx_gain_nf_b0.gain_val_after_nf_0" => { type => "field", addr => 0x101b0, width => 17, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_bbb_sig_detect" => { type => "reg", addr => 0x101c0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bbb_sig_detect.disable_str_chain_sel_cck" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.ena_dc_est_bcorr" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.delay_start_dcoff_cck" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.delay_start_spur_cck" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.start_dcoff_priority_cck" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.use_dc_est_during_srch" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bbb_sig_detect.delay_start_sync_cck" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.enable_fine_dc_cck" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.cyc256_fine_dc_est_cck" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.enable_coarse_dc_cck" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.cyc64_coarse_dc_est_cck" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.cyc32_coarse_dc_est_cck" => { type => "field", addr => 0x101c0, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_sig_detect.ant_switch_time" => { type => "field", addr => 0x101c0, width => 7, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bbb_sig_detect.agcreg_channel_freq" => { type => "field", addr => 0x101c0, width => 13, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_dagc_ctrl" => { type => "reg", addr => 0x101c4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bbb_dagc_ctrl.bk_in_scale_coarse" => { type => "field", addr => 0x101c4, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_dagc_ctrl.rxb_det_strong_chn_default" => { type => "field", addr => 0x101c4, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_dagc_ctrl.firstep_count_lgmax" => { type => "field", addr => 0x101c4, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bbb_dagc_ctrl.firstep_2" => { type => "field", addr => 0x101c4, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_bbb_dagc_ctrl.enable_firstep_sel" => { type => "field", addr => 0x101c4, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_bbb_dagc_ctrl.barker_rssi_thr" => { type => "field", addr => 0x101c4, width => 7, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_dagc_ctrl.enable_barker_rssi_thr" => { type => "field", addr => 0x101c4, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_dagc_ctrl.dagc_target_pwr_cck" => { type => "field", addr => 0x101c4, width => 8, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_dagc_ctrl.enable_dagc_cck" => { type => "field", addr => 0x101c4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_iqcorr_ctrl_cck" => { type => "reg", addr => 0x101c8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_iqcorr_ctrl_cck.cf_clc_init_rfgain" => { type => "field", addr => 0x101c8, width => 5, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_iqcorr_ctrl_cck.clcal_meas_time_sel" => { type => "field", addr => 0x101c8, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_iqcorr_ctrl_cck.rxcal_meas_time_sel" => { type => "field", addr => 0x101c8, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_cck_spur_mit" => { type => "reg", addr => 0x101cc, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_cck_spur_mit.spur_filter_type" => { type => "field", addr => 0x101cc, width => 2, bitOffset => 29, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_spur_mit.cck_spur_freq" => { type => "field", addr => 0x101cc, width => 20, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_spur_mit.spur_rssi_thr" => { type => "field", addr => 0x101cc, width => 8, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_spur_mit.use_cck_spur_mit" => { type => "field", addr => 0x101cc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_mrc_cck_ctrl" => { type => "reg", addr => 0x101d0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_mrc_cck_ctrl.agcreg_th_d0_b_tf_est" => { type => "field", addr => 0x101d0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_mrc_cck_ctrl.agcreg_th_d0_b" => { type => "field", addr => 0x101d0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_mrc_cck_ctrl.agcreg_c11bp" => { type => "field", addr => 0x101d0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_mrc_cck_ctrl.agcreg_c11b" => { type => "field", addr => 0x101d0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_blocker_det" => { type => "reg", addr => 0x101d4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cck_blocker_det.cck_det_ramp_thr" => { type => "field", addr => 0x101d4, width => 5, bitOffset => 27, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_blocker_det.skip_ramp_enable" => { type => "field", addr => 0x101d4, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_cck_blocker_det.cck_blocker_monitor_time" => { type => "field", addr => 0x101d4, width => 6, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_blocker_det.cck_blocker_det_delay_thr" => { type => "field", addr => 0x101d4, width => 6, bitOffset => 14, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_blocker_det.cck_blocker_det_thr" => { type => "field", addr => 0x101d4, width => 5, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_blocker_det.bk_valid_delay" => { type => "field", addr => 0x101d4, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_blocker_det.cck_blocker_det_bksum_num" => { type => "field", addr => 0x101d4, width => 4, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_blocker_det.cck_blocker_det_restart_weak_sig" => { type => "field", addr => 0x101d4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_blocker_det.cck_freq_shift_blocker_detection" => { type => "field", addr => 0x101d4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bk_corr_settings" => { type => "reg", addr => 0x101d8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bk_corr_settings.bk_in_scale_tf" => { type => "field", addr => 0x101d8, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_bk_corr_settings.bk_in_backoff" => { type => "field", addr => 0x101d8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0xba }, "BB_bk_corr_settings.bk_in_min_backoff" => { type => "field", addr => 0x101d8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xa6 }, "BB_cck_blocker_det2" => { type => "reg", addr => 0x101e0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cck_blocker_det2.disable_m1ok_11b" => { type => "field", addr => 0x101e0, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_blocker_det2.cckpdp_valid_thr" => { type => "field", addr => 0x101e0, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cck_blocker_det2.firpwr_str" => { type => "field", addr => 0x101e0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xa6 }, "BB_detection_mask_cntl" => { type => "reg", addr => 0x101e4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_detection_mask_cntl.rssi_comb_dm_apply" => { type => "field", addr => 0x101e4, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_detection_mask_cntl.flag_firpwr_dm_apply" => { type => "field", addr => 0x101e4, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_detection_mask_cntl.flag_relpwr_dm_apply" => { type => "field", addr => 0x101e4, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_detection_mask_cntl.m2flag_dm_apply" => { type => "field", addr => 0x101e4, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_detection_mask_cntl.in_range_dm_apply" => { type => "field", addr => 0x101e4, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_detection_mask_cntl.gain_dropped_dm_apply" => { type => "field", addr => 0x101e4, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_detection_mask_cntl.rfsat_dm_apply" => { type => "field", addr => 0x101e4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_detection_mask_cntl.adcsat_dm_apply" => { type => "field", addr => 0x101e4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_ocgain" => { type => "reg", addr => 0x10200, width => 32, athEmulAttr => 0, acc => "RW", depth => 128, incr => 4 }, "BB_rx_ocgain.gain_entry" => { type => "field", addr => 0x10200, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, ################################################################### ## bb_reg_map.bb_chn_reg_map Register/Field definitions ################################################################### "BB_timing_controls_1" => { type => "reg", addr => 0x10400, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_timing_controls_1.fft_scaling" => { type => "field", addr => 0x10400, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.coarse_ppm_select" => { type => "field", addr => 0x10400, width => 2, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.timing_leak_enable" => { type => "field", addr => 0x10400, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.enable_long_rescale" => { type => "field", addr => 0x10400, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.false_alarm" => { type => "field", addr => 0x10400, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.enable_channel_filter" => { type => "field", addr => 0x10400, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.enable_rx_stbc" => { type => "field", addr => 0x10400, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.enable_long_chanfil" => { type => "field", addr => 0x10400, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.ht_fine_ppm_qam" => { type => "field", addr => 0x10400, width => 2, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.ht_fine_ppm_stream" => { type => "field", addr => 0x10400, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.ste_to_long1" => { type => "field", addr => 0x10400, width => 6, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_1.ste_thr" => { type => "field", addr => 0x10400, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2" => { type => "reg", addr => 0x10404, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_timing_controls_2.enable_ht_fine_timing" => { type => "field", addr => 0x10404, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.traceback128" => { type => "field", addr => 0x10404, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.enable_weighting" => { type => "field", addr => 0x10404, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.enable_dc_offset_track" => { type => "field", addr => 0x10404, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.enable_dc_offset" => { type => "field", addr => 0x10404, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.dc_off_tim_const" => { type => "field", addr => 0x10404, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.enable_pilot_interpolation" => { type => "field", addr => 0x10404, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.dc_off_deltaf_thres" => { type => "field", addr => 0x10404, width => 7, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 20 }, "BB_timing_controls_2.enable_offset_filter" => { type => "field", addr => 0x10404, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.enable_magnitude_track_mimo" => { type => "field", addr => 0x10404, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.enable_magnitude_track" => { type => "field", addr => 0x10404, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.force_delta_phi_symbol" => { type => "field", addr => 0x10404, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2.forced_delta_phi_symbol" => { type => "field", addr => 0x10404, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_3" => { type => "reg", addr => 0x10408, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_timing_controls_3.delta_slope_coef_man" => { type => "field", addr => 0x10408, width => 15, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_3.delta_slope_coef_exp" => { type => "field", addr => 0x10408, width => 4, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_3.enable_df_chanest" => { type => "field", addr => 0x10408, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_3.continuous_ppm_rescue" => { type => "field", addr => 0x10408, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_timing_controls_3.enable_fine_interp" => { type => "field", addr => 0x10408, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_3.enable_fine_ppm" => { type => "field", addr => 0x10408, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_3.enable_ppm_rescue" => { type => "field", addr => 0x10408, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_3.ppm_rescue_interval" => { type => "field", addr => 0x10408, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_4" => { type => "reg", addr => 0x1040c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_timing_control_4.enable_spur_rssi" => { type => "field", addr => 0x1040c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_4.enable_chan_mask" => { type => "field", addr => 0x1040c, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_4.enable_pilot_mask" => { type => "field", addr => 0x1040c, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_4.early_trigger_thr" => { type => "field", addr => 0x1040c, width => 7, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_4.use_pilot_track_df" => { type => "field", addr => 0x1040c, width => 4, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0xe }, "BB_timing_control_4.do_gain_dc_iq_cal" => { type => "field", addr => 0x1040c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_timing_control_4.cal_lg_count_max" => { type => "field", addr => 0x1040c, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_4.use_data_as_pilot_df" => { type => "field", addr => 0x1040c, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_timing_control_4.enable_magnitude_track_11n_mimo" => { type => "field", addr => 0x1040c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_4.enable_ht_fine_ppm" => { type => "field", addr => 0x1040c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_timing_control_5" => { type => "reg", addr => 0x10410, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_timing_control_5.long_sc_thresh_hi_rssi" => { type => "field", addr => 0x10410, width => 7, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 64 }, "BB_timing_control_5.rssi_thr1a" => { type => "field", addr => 0x10410, width => 7, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_5.enable_rssi_thr1a" => { type => "field", addr => 0x10410, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_5.cycpwr_thr1" => { type => "field", addr => 0x10410, width => 7, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_5.enable_cycpwr_thr1" => { type => "field", addr => 0x10410, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_6" => { type => "reg", addr => 0x10414, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_timing_control_6.add_back_ofdm_dc_cck_bw40" => { type => "field", addr => 0x10414, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_timing_control_6.add_back_ofdm_dc_cck_bw20" => { type => "field", addr => 0x10414, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_timing_control_6.ofdm_xcorr_thresh_hi_rssi" => { type => "field", addr => 0x10414, width => 7, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_6.ofdm_xcorr_thresh" => { type => "field", addr => 0x10414, width => 6, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_6.early_trigger_thr_hi_rssi" => { type => "field", addr => 0x10414, width => 7, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_6.hi_rssi_thresh" => { type => "field", addr => 0x10414, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_timing_control_11" => { type => "reg", addr => 0x10418, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_timing_control_11.use_spur_filter_in_selfcor" => { type => "field", addr => 0x10418, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_11.use_spur_filter_in_agc" => { type => "field", addr => 0x10418, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_control_11.spur_freq_sd" => { type => "field", addr => 0x10418, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_mask_controls" => { type => "reg", addr => 0x1041c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spur_mask_controls.enable_nf_rssi_spur_mit" => { type => "field", addr => 0x1041c, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_mask_controls.mask_rate_cntl" => { type => "field", addr => 0x1041c, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_mask_controls.enable_mask_ppm" => { type => "field", addr => 0x1041c, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_mask_controls.en_vit_spur_rssi" => { type => "field", addr => 0x1041c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_mask_controls.spur_rssi_thresh" => { type => "field", addr => 0x1041c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_find_signal_low" => { type => "reg", addr => 0x10420, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_find_signal_low.long_sc_thresh" => { type => "field", addr => 0x10420, width => 7, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 24 }, "BB_find_signal_low.ycok_max_low" => { type => "field", addr => 0x10420, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_find_signal_low.firpwr_low" => { type => "field", addr => 0x10420, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_find_signal_low.firstep_low" => { type => "field", addr => 0x10420, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_find_signal_low.relstep_low" => { type => "field", addr => 0x10420, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sfcorr" => { type => "reg", addr => 0x10424, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sfcorr.m2_thres" => { type => "field", addr => 0x10424, width => 7, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_sfcorr.m1_thres" => { type => "field", addr => 0x10424, width => 7, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_sfcorr.m2count_thr" => { type => "field", addr => 0x10424, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_self_corr_low" => { type => "reg", addr => 0x10428, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_self_corr_low.m2_thresh_low" => { type => "field", addr => 0x10428, width => 7, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_self_corr_low.m1_thresh_low" => { type => "field", addr => 0x10428, width => 7, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_self_corr_low.m2count_thr_low" => { type => "field", addr => 0x10428, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_self_corr_low.m1count_max_low" => { type => "field", addr => 0x10428, width => 7, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_self_corr_low.use_self_corr_low" => { type => "field", addr => 0x10428, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_timing_control_13" => { type => "reg", addr => 0x10430, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_timing_control_13.tb_rssi_th2" => { type => "field", addr => 0x10430, width => 8, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 26 }, "BB_timing_control_13.tb_rssi_th1" => { type => "field", addr => 0x10430, width => 8, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 16 }, "BB_timing_control_13.timing_backoff_high_rssi" => { type => "field", addr => 0x10430, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_timing_control_13.timing_backoff_mid_rssi" => { type => "field", addr => 0x10430, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_timing_control_13.timing_backoff_low_rssi" => { type => "field", addr => 0x10430, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_radar_detection" => { type => "reg", addr => 0x10434, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_radar_detection.radar_firpwr_thresh" => { type => "field", addr => 0x10434, width => 7, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection.pulse_drop_thresh" => { type => "field", addr => 0x10434, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection.pulse_height_thresh" => { type => "field", addr => 0x10434, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection.pulse_rssi_thresh" => { type => "field", addr => 0x10434, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection.fft_check_coarse_ena" => { type => "field", addr => 0x10434, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_radar_detection.dfs_restart_ena_sec" => { type => "field", addr => 0x10434, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_radar_detection.dfs_restart_ena_pri" => { type => "field", addr => 0x10434, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_radar_detection.dfs_sec80_enable" => { type => "field", addr => 0x10434, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection.dfs_pri80_enable" => { type => "field", addr => 0x10434, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection.pulse_detect_enable" => { type => "field", addr => 0x10434, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection_2" => { type => "reg", addr => 0x10438, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_radar_detection_2.enable_pulse_drop_check" => { type => "field", addr => 0x10438, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection_2.enable_pulse_relpwr_check" => { type => "field", addr => 0x10438, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection_2.enable_pulse_relstep_check" => { type => "field", addr => 0x10438, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection_2.enable_pulse_gc_count_check" => { type => "field", addr => 0x10438, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection_2.pulse_relpwr_thresh" => { type => "field", addr => 0x10438, width => 5, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection_2.dfs_cont_80p80" => { type => "field", addr => 0x10438, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection_2.pulse_relstep_thresh" => { type => "field", addr => 0x10438, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_radar_detection_2.pulse_width_max" => { type => "field", addr => 0x10438, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_extension_radar" => { type => "reg", addr => 0x1043c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_extension_radar.radar_lb_dc_cap" => { type => "field", addr => 0x1043c, width => 9, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x1ff }, "BB_extension_radar.radar_fft_datapath_sel" => { type => "field", addr => 0x1043c, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_extension_radar.lb_dc_cap_pulse_nb_mask" => { type => "field", addr => 0x1043c, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_extension_radar.lb_dc_cap_pulse_dc_mask" => { type => "field", addr => 0x1043c, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_extension_radar.radar_lb_dc_cap_fine" => { type => "field", addr => 0x1043c, width => 9, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1ff }, "BB_extension_radar.radar_path_sel" => { type => "field", addr => 0x1043c, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_extension_radar.restart_lgdfspwr_delta" => { type => "field", addr => 0x1043c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_ibf_ctrl" => { type => "reg", addr => 0x10440, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibf_ctrl.chn_phase_align" => { type => "field", addr => 0x10440, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chn_spare_01" => { type => "reg", addr => 0x10450, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chn_spare_01.chn_eco_ctrl" => { type => "field", addr => 0x10450, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_timing_controls_2a" => { type => "reg", addr => 0x10454, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_timing_controls_2a.coarse_dc_delay" => { type => "field", addr => 0x10454, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rx_notch_cntl_2_pri_b0" => { type => "reg", addr => 0x10458, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_2_pri_b0.notch_corr_spur1_q_pri_b0" => { type => "field", addr => 0x10458, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_2_pri_b0.notch_corr_spur1_i_pri_b0" => { type => "field", addr => 0x10458, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_3_pri_b0" => { type => "reg", addr => 0x1045c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_3_pri_b0.notch_corr_spur2_q_pri_b0" => { type => "field", addr => 0x1045c, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_3_pri_b0.notch_corr_spur2_i_pri_b0" => { type => "field", addr => 0x1045c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_4_pri_b0" => { type => "reg", addr => 0x10460, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_4_pri_b0.notch_corr_dc_q_pri_b0" => { type => "field", addr => 0x10460, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_4_pri_b0.notch_corr_dc_i_pri_b0" => { type => "field", addr => 0x10460, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_5_pri_b0" => { type => "reg", addr => 0x10464, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_5_pri_b0.notch_corr_agg_i_pri_b0" => { type => "field", addr => 0x10464, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_2_ext_b0" => { type => "reg", addr => 0x10468, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_2_ext_b0.notch_corr_spur1_q_ext_b0" => { type => "field", addr => 0x10468, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_2_ext_b0.notch_corr_spur1_i_ext_b0" => { type => "field", addr => 0x10468, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_3_ext_b0" => { type => "reg", addr => 0x1046c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_3_ext_b0.notch_corr_spur2_q_ext_b0" => { type => "field", addr => 0x1046c, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_3_ext_b0.notch_corr_spur2_i_ext_b0" => { type => "field", addr => 0x1046c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_4_ext_b0" => { type => "reg", addr => 0x10470, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_4_ext_b0.notch_corr_dc_q_ext_b0" => { type => "field", addr => 0x10470, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_4_ext_b0.notch_corr_dc_i_ext_b0" => { type => "field", addr => 0x10470, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_5_ext_b0" => { type => "reg", addr => 0x10474, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_5_ext_b0.notch_corr_agg_i_ext_b0" => { type => "field", addr => 0x10474, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_multichain_control" => { type => "reg", addr => 0x10480, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_multichain_control.enable_dyn_deweight" => { type => "field", addr => 0x10480, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_multichain_control.enable_static_deweight" => { type => "field", addr => 0x10480, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_multichain_control.force_sigma_zero" => { type => "field", addr => 0x10480, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_control.forced_gain_diff_02" => { type => "field", addr => 0x10480, width => 7, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_control.cf_short_sat" => { type => "field", addr => 0x10480, width => 11, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_control.use_posedge_refclk" => { type => "field", addr => 0x10480, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_multichain_control.sync_synthon" => { type => "field", addr => 0x10480, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_multichain_control.forced_gain_diff_01" => { type => "field", addr => 0x10480, width => 7, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_control.force_analog_gain_diff" => { type => "field", addr => 0x10480, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_per_chain_ht_csd" => { type => "reg", addr => 0x10484, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_per_chain_ht_csd.ht_csd_chn3_4chains" => { type => "field", addr => 0x10484, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_per_chain_ht_csd.ht_csd_chn2_4chains" => { type => "field", addr => 0x10484, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_per_chain_ht_csd.ht_csd_chn1_4chains" => { type => "field", addr => 0x10484, width => 5, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_per_chain_ht_csd.ht_csd_chn2_3chains" => { type => "field", addr => 0x10484, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_per_chain_ht_csd.ht_csd_chn1_3chains" => { type => "field", addr => 0x10484, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_per_chain_ht_csd.ht_csd_chn1_2chains" => { type => "field", addr => 0x10484, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_pre_emphasis_bw20_b0" => { type => "reg", addr => 0x10488, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pre_emphasis_bw20_b0.pre_emp_db_neg_bw20_0" => { type => "field", addr => 0x10488, width => 15, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pre_emphasis_bw20_b0.pre_emp_db_pos_bw20_0" => { type => "field", addr => 0x10488, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pre_emphasis_bw40_b0" => { type => "reg", addr => 0x1048c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pre_emphasis_bw40_b0.pre_emp_db_neg_bw40_0" => { type => "field", addr => 0x1048c, width => 15, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pre_emphasis_bw40_b0.pre_emp_db_pos_bw40_0" => { type => "field", addr => 0x1048c, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pre_emphasis_bw80_b0" => { type => "reg", addr => 0x10490, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pre_emphasis_bw80_b0.pre_emp_db_neg_bw80_0" => { type => "field", addr => 0x10490, width => 15, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pre_emphasis_bw80_b0.pre_emp_db_pos_bw80_0" => { type => "field", addr => 0x10490, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chn_tables_intf_addr" => { type => "reg", addr => 0x10494, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chn_tables_intf_addr.chn_addr_auto_incr" => { type => "field", addr => 0x10494, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0, athPortalAttr => "chn_table_map.autoIncr" }, "BB_chn_tables_intf_addr.chn_tables_addr" => { type => "field", addr => 0x10494, width => 16, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0, athPortalAttr => "chn_table_map.addr" }, "BB_chn_tables_intf_data" => { type => "reg", addr => 0x10498, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chn_tables_intf_data.chn_tables_data" => { type => "field", addr => 0x10498, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0, athPortalAttr => "chn_table_map.data" }, "BB_phydbg_control1" => { type => "reg", addr => 0x1049c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_phydbg_control1.phydbg_cap_chn_sel" => { type => "field", addr => 0x1049c, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_control1.phydbg_plybck_count" => { type => "field", addr => 0x1049c, width => 14, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_control1.phydbg_cap_trig_mode" => { type => "field", addr => 0x1049c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_control1.phydbg_plybck_trig_mode" => { type => "field", addr => 0x1049c, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_control1.phydbg_cap_pre_store" => { type => "field", addr => 0x1049c, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_control2" => { type => "reg", addr => 0x104a0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_phydbg_control2.phydbg_cap_en" => { type => "field", addr => 0x104a0, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_control2.phydbg_cap_trig_addr" => { type => "field", addr => 0x104a0, width => 15, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_phydbg_control2.phydbg_cap_trig_select" => { type => "field", addr => 0x104a0, width => 5, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_control2.phydbg_fsmstate" => { type => "field", addr => 0x104a0, width => 4, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_control2.phydbg_apb_autoincr" => { type => "field", addr => 0x104a0, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_control2.phydbg_plybck_en" => { type => "field", addr => 0x104a0, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_control2.phydbg_mode" => { type => "field", addr => 0x104a0, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf }, "BB_tstdac_constant" => { type => "reg", addr => 0x104a4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tstdac_constant.cf_tstdac_constant_q" => { type => "field", addr => 0x104a4, width => 11, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tstdac_constant.cf_tstdac_constant_i" => { type => "field", addr => 0x104a4, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_spur_report_b0" => { type => "reg", addr => 0x104a8, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_spur_report_b0.power_with_spur_removed_0" => { type => "field", addr => 0x104a8, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_spur_report_b0.spur_est_q_0" => { type => "field", addr => 0x104a8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_spur_report_b0.spur_est_i_0" => { type => "field", addr => 0x104a8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_green_tx_control_1" => { type => "reg", addr => 0x104bc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_green_tx_control_1.green_cases" => { type => "field", addr => 0x104bc, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_green_tx_control_1.green_tx_enable" => { type => "field", addr => 0x104bc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_iq_adc_meas_0_b0" => { type => "reg", addr => 0x104c0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_iq_adc_meas_0_b0.gain_dc_iq_cal_meas_0_0" => { type => "field", addr => 0x104c0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_iq_adc_meas_1_b0" => { type => "reg", addr => 0x104c4, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_iq_adc_meas_1_b0.gain_dc_iq_cal_meas_1_0" => { type => "field", addr => 0x104c4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_iq_adc_meas_2_b0" => { type => "reg", addr => 0x104c8, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_iq_adc_meas_2_b0.gain_dc_iq_cal_meas_2_0" => { type => "field", addr => 0x104c8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_iq_adc_meas_3_b0" => { type => "reg", addr => 0x104cc, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_iq_adc_meas_3_b0.gain_dc_iq_cal_meas_3_0" => { type => "field", addr => 0x104cc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tx_phase_ramp_b0" => { type => "reg", addr => 0x104d0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_phase_ramp_b0.cf_phase_ramp_alpha_0" => { type => "field", addr => 0x104d0, width => 8, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_phase_ramp_b0.cf_phase_ramp_init_0" => { type => "field", addr => 0x104d0, width => 10, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_phase_ramp_b0.cf_phase_ramp_bias_0" => { type => "field", addr => 0x104d0, width => 6, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_phase_ramp_b0.cf_phase_ramp_enable_0" => { type => "field", addr => 0x104d0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_adc_gain_corr_b0" => { type => "reg", addr => 0x104d4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_adc_gain_corr_b0.adc_fixed_gain" => { type => "field", addr => 0x104d4, width => 9, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 256 }, "BB_adc_gain_corr_b0.enable_bw_mode_sel_for_tiadc_corr" => { type => "field", addr => 0x104d4, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_adc_gain_corr_b0.adc_gain_corr_enable" => { type => "field", addr => 0x104d4, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_adc_gain_corr_b0.adc_gain_corr_i_coeff_0" => { type => "field", addr => 0x104d4, width => 9, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 32 }, "BB_adc_gain_corr_b0.adc_gain_corr_q_coeff_0" => { type => "field", addr => 0x104d4, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 32 }, "BB_adc_dc_corr_b0" => { type => "reg", addr => 0x104d8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_adc_dc_corr_b0.adc_dc_corr_enable" => { type => "field", addr => 0x104d8, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_adc_dc_corr_b0.adc_dc_corr_i_coeff_0" => { type => "field", addr => 0x104d8, width => 9, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_adc_dc_corr_b0.adc_dc_corr_q_coeff_0" => { type => "field", addr => 0x104d8, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rx_iq_corr_b0" => { type => "reg", addr => 0x104dc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_iq_corr_b0.rx_iqcorr_bypass_lb" => { type => "field", addr => 0x104dc, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_iq_corr_b0.rx_iqc_use_onetap" => { type => "field", addr => 0x104dc, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_iq_corr_b0.rx_iqcorr_bypass_in_agc" => { type => "field", addr => 0x104dc, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_iq_corr_b0.rx_iqcorr_enable" => { type => "field", addr => 0x104dc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_iq_corr_loopback_b0" => { type => "reg", addr => 0x104e0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_iq_corr_loopback_b0.loopback_iqcorr_enable" => { type => "field", addr => 0x104e0, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_iq_corr_loopback_b0.loopback_iqcorr_q_i_coff_0" => { type => "field", addr => 0x104e0, width => 9, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rx_iq_corr_loopback_b0.loopback_iqcorr_q_q_coff_0" => { type => "field", addr => 0x104e0, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_am2am_mask" => { type => "reg", addr => 0x104e4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_am2am_mask.paprd_am2am_mask" => { type => "field", addr => 0x104e4, width => 31, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_am2pm_mask" => { type => "reg", addr => 0x104e8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_am2pm_mask.paprd_am2pm_mask" => { type => "field", addr => 0x104e8, width => 31, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ht40_mask" => { type => "reg", addr => 0x104ec, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_ht40_mask.paprd_ht40_mask" => { type => "field", addr => 0x104ec, width => 31, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl0_b0" => { type => "reg", addr => 0x104f0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_ctrl0_b0.paprd_valid_gain_5_0_0" => { type => "field", addr => 0x104f0, width => 30, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl0_b0.paprd_reg_chain_indexed" => { type => "field", addr => 0x104f0, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_paprd_ctrl0_b0.paprd_enable_0" => { type => "field", addr => 0x104f0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_ctrl1_b0" => { type => "reg", addr => 0x104f4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_ctrl1_b0.paprd_trainer_iandq_sel_0" => { type => "field", addr => 0x104f4, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_ctrl1_b0.paprd_target_pwr_min_0" => { type => "field", addr => 0x104f4, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl1_b0.paprd_target_pwr_max_0" => { type => "field", addr => 0x104f4, width => 6, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl1_b0.paprd_adaptive_am2pm_enable_0" => { type => "field", addr => 0x104f4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_ctrl1_b0.paprd_adaptive_am2am_enable_0" => { type => "field", addr => 0x104f4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_ctrl2_b0" => { type => "reg", addr => 0x104f8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_ctrl2_b0.paprd_mag_thrsh_0" => { type => "field", addr => 0x104f8, width => 5, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl2_b0.paprd_table_rfbmode_0" => { type => "field", addr => 0x104f8, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl2_b0.paprd_adaptive_table_valid_0" => { type => "field", addr => 0x104f8, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl2_b0.paprd_valid_pa_setting_0" => { type => "field", addr => 0x104f8, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_vht80_mask" => { type => "reg", addr => 0x104fc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_vht80_mask.paprd_vht80_mask" => { type => "field", addr => 0x104fc, width => 31, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_phydbg_mem_addr" => { type => "reg", addr => 0x10500, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_phydbg_mem_addr.phydbg_mem_addr" => { type => "field", addr => 0x10500, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phydbg_mem_data" => { type => "reg", addr => 0x10504, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_phydbg_mem_data.phydbg_mem_data" => { type => "field", addr => 0x10504, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "BB_btcf_config" => { type => "reg", addr => 0x10508, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_btcf_config.btcf_finetim_corr_en" => { type => "field", addr => 0x10508, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_btcf_config.btcf_en" => { type => "field", addr => 0x10508, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_btcf_config.btcf_lgfirpwr_ideal" => { type => "field", addr => 0x10508, width => 12, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0xE8B }, "BB_btcf_config.btcf_det_dshift" => { type => "field", addr => 0x10508, width => 3, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_btcf_config.btcf_det_ratio" => { type => "field", addr => 0x10508, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_btcf_config.fft_toffset256" => { type => "field", addr => 0x10508, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0xe }, "BB_btcf_config.fft_toffset128" => { type => "field", addr => 0x10508, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0xd }, "BB_btcf_config.fft_toffset64" => { type => "field", addr => 0x10508, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xd }, "BB_btcf_th_config" => { type => "reg", addr => 0x1050c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_btcf_th_config.btcf_low_snr_branch" => { type => "field", addr => 0x1050c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_btcf_th_config.btcf_snr_th_db" => { type => "field", addr => 0x1050c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_btcf_th_config.btcf_th2" => { type => "field", addr => 0x1050c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 34 }, "BB_btcf_th_config.btcf_th1" => { type => "field", addr => 0x1050c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 36 }, "BB_btcf_dcn_config" => { type => "reg", addr => 0x10510, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_btcf_dcn_config.dcn_bypass" => { type => "field", addr => 0x10510, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_btcf_dcn_config.dcn_alpha_sel" => { type => "field", addr => 0x10510, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_btcf_dcn_config.btcf_agc_dly" => { type => "field", addr => 0x10510, width => 9, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 320 }, "BB_btcf_dcn_config.dcn_alpha2" => { type => "field", addr => 0x10510, width => 9, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 300 }, "BB_btcf_dcn_config.dcn_alpha1" => { type => "field", addr => 0x10510, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 300 }, "BB_btcf_tim_cpature" => { type => "reg", addr => 0x10514, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_btcf_tim_cpature.btcf_cap_skip_btcf" => { type => "field", addr => 0x10514, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_btcf_tim_cpature.btcf_cap_skip" => { type => "field", addr => 0x10514, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_btcf_tim_cpature.btcf_cap_coarse_sb" => { type => "field", addr => 0x10514, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_btcf_idx_cpature" => { type => "reg", addr => 0x10518, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_btcf_idx_cpature.btcf_cap_picked_idx" => { type => "field", addr => 0x10518, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_btcf_idx_cpature.btcf_cap_min_idx" => { type => "field", addr => 0x10518, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_btcf_fftstartstore" => { type => "reg", addr => 0x1051c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_btcf_fftstartstore.btcf_freeze" => { type => "field", addr => 0x1051c, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_btcf_fftstartstore.btcf_br2_fftstart" => { type => "field", addr => 0x1051c, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_btcf_fftstartstore.btcf_br1_fftstart" => { type => "field", addr => 0x1051c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_btcf_pwr_atmin_169" => { type => "reg", addr => 0x10528, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_btcf_pwr_atmin_169.btcf_pwr_atmin_d169_value" => { type => "field", addr => 0x10528, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_bcf_offscnt_atmin_169" => { type => "reg", addr => 0x1052c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bcf_offscnt_atmin_169.btcf_delta_neg_lim" => { type => "field", addr => 0x1052c, width => 9, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1F9 }, "BB_bcf_offscnt_atmin_169.btcf_delta_pos_lim" => { type => "field", addr => 0x1052c, width => 9, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_bcf_offscnt_atmin_169.btcf_offscnt_atmin_d169_value" => { type => "field", addr => 0x1052c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_btcf_abort_cnt" => { type => "reg", addr => 0x10530, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_btcf_abort_cnt.btcf_abort_count" => { type => "field", addr => 0x10530, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_bcf_minstore_br1" => { type => "reg", addr => 0x10538, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bcf_minstore_br1.btcf_br1_value" => { type => "field", addr => 0x10538, width => 21, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x1FFFFF }, "BB_bcf_minstore_br1.btcf_br1_postminindx" => { type => "field", addr => 0x10538, width => 5, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bcf_minstore_br1.btcf_br1_id" => { type => "field", addr => 0x10538, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bcf_minstore_br2" => { type => "reg", addr => 0x1053c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bcf_minstore_br2.btcf_br2_value" => { type => "field", addr => 0x1053c, width => 21, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x1FFFFF }, "BB_bcf_minstore_br2.btcf_br2_postminindx" => { type => "field", addr => 0x1053c, width => 5, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bcf_minstore_br2.btcf_br2_id" => { type => "field", addr => 0x1053c, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_overlap_window" => { type => "reg", addr => 0x10540, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_overlap_window.overlap_window_bw80MHz" => { type => "field", addr => 0x10540, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_overlap_window.overlap_window_bw40MHz" => { type => "field", addr => 0x10540, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_overlap_window.overlap_window_bw20MHz" => { type => "field", addr => 0x10540, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_per_chain_legacy_csd" => { type => "reg", addr => 0x10544, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_per_chain_legacy_csd.leg_csd_chn3_4chains" => { type => "field", addr => 0x10544, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_per_chain_legacy_csd.leg_csd_chn2_4chains" => { type => "field", addr => 0x10544, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_per_chain_legacy_csd.leg_csd_chn1_4chains" => { type => "field", addr => 0x10544, width => 5, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_per_chain_legacy_csd.leg_csd_chn2_3chains" => { type => "field", addr => 0x10544, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_per_chain_legacy_csd.leg_csd_chn1_3chains" => { type => "field", addr => 0x10544, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_per_chain_legacy_csd.leg_csd_chn1_2chains" => { type => "field", addr => 0x10544, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_fdtg_control0" => { type => "reg", addr => 0x10548, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_control0.fdtg_suppress_preamble" => { type => "field", addr => 0x10548, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_fdtg_control0.fdtg_ss0_b_addr" => { type => "field", addr => 0x10548, width => 8, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_control0.fdtg_ss0_a_addr" => { type => "field", addr => 0x10548, width => 8, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_control0.fdtg_enable" => { type => "field", addr => 0x10548, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_control1" => { type => "reg", addr => 0x1054c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_control1.fdtg_ss2_b_addr" => { type => "field", addr => 0x1054c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_control1.fdtg_ss2_a_addr" => { type => "field", addr => 0x1054c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_control1.fdtg_ss1_b_addr" => { type => "field", addr => 0x1054c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_control1.fdtg_ss1_a_addr" => { type => "field", addr => 0x1054c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss0_data_b0" => { type => "reg", addr => 0x10550, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_ss0_data_b0.fdtg_ss0_b_data_im_0" => { type => "field", addr => 0x10550, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss0_data_b0.fdtg_ss0_b_data_re_0" => { type => "field", addr => 0x10550, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss0_data_b0.fdtg_ss0_a_data_im_0" => { type => "field", addr => 0x10550, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss0_data_b0.fdtg_ss0_a_data_re_0" => { type => "field", addr => 0x10550, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss1_data_b0" => { type => "reg", addr => 0x10554, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_ss1_data_b0.fdtg_ss1_b_data_im_0" => { type => "field", addr => 0x10554, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss1_data_b0.fdtg_ss1_b_data_re_0" => { type => "field", addr => 0x10554, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss1_data_b0.fdtg_ss1_a_data_im_0" => { type => "field", addr => 0x10554, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss1_data_b0.fdtg_ss1_a_data_re_0" => { type => "field", addr => 0x10554, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss2_data_b0" => { type => "reg", addr => 0x10558, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_ss2_data_b0.fdtg_ss2_b_data_im_0" => { type => "field", addr => 0x10558, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss2_data_b0.fdtg_ss2_b_data_re_0" => { type => "field", addr => 0x10558, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss2_data_b0.fdtg_ss2_a_data_im_0" => { type => "field", addr => 0x10558, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss2_data_b0.fdtg_ss2_a_data_re_0" => { type => "field", addr => 0x10558, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_am2am_mask2" => { type => "reg", addr => 0x1055c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_am2am_mask2.paprd_am2am_mask2" => { type => "field", addr => 0x1055c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_am2pm_mask2" => { type => "reg", addr => 0x10560, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_am2pm_mask2.paprd_am2pm_mask2" => { type => "field", addr => 0x10560, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ht40_mask2" => { type => "reg", addr => 0x10564, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_ht40_mask2.paprd_ht40_mask2" => { type => "field", addr => 0x10564, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_vht80_mask2" => { type => "reg", addr => 0x10568, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_vht80_mask2.paprd_vht80_mask2" => { type => "field", addr => 0x10568, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl1_pri_b0" => { type => "reg", addr => 0x1056c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spur_ctrl1_pri_b0.enable_spur_filter_pri_b0" => { type => "field", addr => 0x1056c, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl1_pri_b0.agc_ht_stf_spur_filter_ena_pri_b0" => { type => "field", addr => 0x1056c, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_spur_ctrl1_pri_b0.spur_delta_phase_pri_b0" => { type => "field", addr => 0x1056c, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl2_pri_b0" => { type => "reg", addr => 0x10570, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spur_ctrl2_pri_b0.spur_delta_phase_2nd_pri_b0" => { type => "field", addr => 0x10570, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl1_ext_b0" => { type => "reg", addr => 0x10574, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spur_ctrl1_ext_b0.enable_spur_filter_ext_b0" => { type => "field", addr => 0x10574, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl1_ext_b0.agc_ht_stf_spur_filter_ena_ext_b0" => { type => "field", addr => 0x10574, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_spur_ctrl1_ext_b0.spur_delta_phase_ext_b0" => { type => "field", addr => 0x10574, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl2_ext_b0" => { type => "reg", addr => 0x10578, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spur_ctrl2_ext_b0.spur_delta_phase_2nd_ext_b0" => { type => "field", addr => 0x10578, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fdtg_ss3_data_b0" => { type => "reg", addr => 0x1057c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_ss3_data_b0.fdtg_ss3_b_data_im_0" => { type => "field", addr => 0x1057c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss3_data_b0.fdtg_ss3_b_data_re_0" => { type => "field", addr => 0x1057c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss3_data_b0.fdtg_ss3_a_data_im_0" => { type => "field", addr => 0x1057c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss3_data_b0.fdtg_ss3_a_data_re_0" => { type => "field", addr => 0x1057c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_control2" => { type => "reg", addr => 0x10580, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_control2.fdtg_ss3_b_addr" => { type => "field", addr => 0x10580, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_control2.fdtg_ss3_a_addr" => { type => "field", addr => 0x10580, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pdc_a1_0_m0" => { type => "reg", addr => 0x10584, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_a1_0_m0.pdc_a1_0_m0" => { type => "field", addr => 0x10584, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b1_0_m0" => { type => "reg", addr => 0x10588, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b1_0_m0.pdc_b1_0_m0" => { type => "field", addr => 0x10588, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b2_0_m0" => { type => "reg", addr => 0x1058c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b2_0_m0.pdc_b2_0_m0" => { type => "field", addr => 0x1058c, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_a1_0_m1" => { type => "reg", addr => 0x10590, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_a1_0_m1.pdc_a1_0_m1" => { type => "field", addr => 0x10590, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b1_0_m1" => { type => "reg", addr => 0x10594, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b1_0_m1.pdc_b1_0_m1" => { type => "field", addr => 0x10594, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b2_0_m1" => { type => "reg", addr => 0x10598, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b2_0_m1.pdc_b2_0_m1" => { type => "field", addr => 0x10598, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_a1_0_m2" => { type => "reg", addr => 0x1059c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_a1_0_m2.pdc_a1_0_m2" => { type => "field", addr => 0x1059c, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b1_0_m2" => { type => "reg", addr => 0x105a0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b1_0_m2.pdc_b1_0_m2" => { type => "field", addr => 0x105a0, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b2_0_m2" => { type => "reg", addr => 0x105a4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b2_0_m2.pdc_b2_0_m2" => { type => "field", addr => 0x105a4, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_step_p1_0" => { type => "reg", addr => 0x105a8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_step_p1_0.pdc_step_p1_0" => { type => "field", addr => 0x105a8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pdc_step_p2_0" => { type => "reg", addr => 0x105ac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_step_p2_0.pdc_step_p2_0" => { type => "field", addr => 0x105ac, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pdc_gap_time_0" => { type => "reg", addr => 0x105b0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_pdc_gap_time_0.pdc_gap_time_0" => { type => "field", addr => 0x105b0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_pdc_time_0" => { type => "reg", addr => 0x105b4, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_pdc_time_0.pdc_time_0" => { type => "field", addr => 0x105b4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_pdc_disable" => { type => "reg", addr => 0x105b8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_disable.pdc_disable" => { type => "field", addr => 0x105b8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_pdc_num_p1_max" => { type => "reg", addr => 0x105bc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_num_p1_max.pdc_num_p1_max" => { type => "field", addr => 0x105bc, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pdc_num_p2_max" => { type => "reg", addr => 0x105c0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_num_p2_max.pdc_num_p2_max" => { type => "field", addr => 0x105c0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pdc_gap_th1" => { type => "reg", addr => 0x105c4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_gap_th1.pdc_gap_th1" => { type => "field", addr => 0x105c4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000 }, "BB_pdc_gap_th2" => { type => "reg", addr => 0x105c8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_gap_th2.pdc_gap_th2" => { type => "field", addr => 0x105c8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000 }, "BB_pdc_dly_tl" => { type => "reg", addr => 0x105cc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_dly_tl.pdc_dly_tl" => { type => "field", addr => 0x105cc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000 }, "BB_pdc_gap_tl" => { type => "reg", addr => 0x105d0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_gap_tl.pdc_gap_tl" => { type => "field", addr => 0x105d0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000 }, "BB_pdc_tl" => { type => "reg", addr => 0x105d4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_tl.pdc_tl" => { type => "field", addr => 0x105d4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000 }, "BB_pdc_num_step_p1" => { type => "reg", addr => 0x105d8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_num_step_p1.pdc_num_step_p1" => { type => "field", addr => 0x105d8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, ################################################################### ## bb_reg_map.bb_sm_reg_map Register/Field definitions ################################################################### "BB_gen_controls" => { type => "reg", addr => 0x10604, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_gen_controls.enable_err_tpc_miss" => { type => "field", addr => 0x10604, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gen_controls.enable_err_tx_illegal_rate" => { type => "field", addr => 0x10604, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.enable_err_tx_bw_gt_dyn_bw" => { type => "field", addr => 0x10604, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.enable_err_lsig_length_check" => { type => "field", addr => 0x10604, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.enable_err_extra_sym_mismatch" => { type => "field", addr => 0x10604, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.enable_err_tx_chain_mask_zero" => { type => "field", addr => 0x10604, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.unsupp_ht_rate_threshold" => { type => "field", addr => 0x10604, width => 7, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 76 }, "BB_gen_controls.chain0_upper_segment" => { type => "field", addr => 0x10604, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gen_controls.static20_mode_ht40_packet_error_rpt" => { type => "field", addr => 0x10604, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gen_controls.static20_mode_ht40_packet_handling" => { type => "field", addr => 0x10604, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gen_controls.enable_adc_async_fifo" => { type => "field", addr => 0x10604, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.enable_dac_async_fifo" => { type => "field", addr => 0x10604, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.gf_enable" => { type => "field", addr => 0x10604, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gen_controls.apply_walsh_on_legacy" => { type => "field", addr => 0x10604, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.use_walsh_for_nsts_eq_ntx" => { type => "field", addr => 0x10604, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.allow_short_gi" => { type => "field", addr => 0x10604, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.vht_enable" => { type => "field", addr => 0x10604, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_gen_controls.dyn_non_contig" => { type => "field", addr => 0x10604, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gen_controls.dyn_chn_gap" => { type => "field", addr => 0x10604, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gen_controls.dyn_pri_chn" => { type => "field", addr => 0x10604, width => 3, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_gen_controls.dyn_bw" => { type => "field", addr => 0x10604, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_modes_select" => { type => "reg", addr => 0x10608, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_modes_select.pmi_fifo_threshold" => { type => "field", addr => 0x10608, width => 5, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 24 }, "BB_modes_select.en_err_crc_abort" => { type => "field", addr => 0x10608, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_modes_select.en_err_vht_grp1to62" => { type => "field", addr => 0x10608, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_modes_select.en_err_vht_rx_nsym_lt_zero" => { type => "field", addr => 0x10608, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_modes_select.en_err_vht_rx_ndp_or_zlf" => { type => "field", addr => 0x10608, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_modes_select.en_err_vht_lsig_len_invalid" => { type => "field", addr => 0x10608, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_modes_select.en_err_vht_rx_siga_unsup" => { type => "field", addr => 0x10608, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_modes_select.skip_rx_grp_id_63" => { type => "field", addr => 0x10608, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_modes_select.skip_rx_grp_id_0" => { type => "field", addr => 0x10608, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_modes_select.ovsamp_clk_mode" => { type => "field", addr => 0x10608, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_modes_select.disable_dyn_cck_det" => { type => "field", addr => 0x10608, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_modes_select.mac_clk_mode" => { type => "field", addr => 0x10608, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_modes_select.quarter_rate_mode" => { type => "field", addr => 0x10608, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_modes_select.half_rate_mode" => { type => "field", addr => 0x10608, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_modes_select.dyn_ofdm_cck_mode" => { type => "field", addr => 0x10608, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_modes_select.cck_mode" => { type => "field", addr => 0x10608, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_active" => { type => "reg", addr => 0x1060c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_active.cf_reset_core" => { type => "field", addr => 0x1060c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_active.cf_active" => { type => "field", addr => 0x1060c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_spare_01" => { type => "reg", addr => 0x10610, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spare_01.sm_eco_ctrl" => { type => "field", addr => 0x10610, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spectral_scan" => { type => "reg", addr => 0x10628, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spectral_scan.spectral_scan_restart_ena" => { type => "field", addr => 0x10628, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_spectral_scan.spectral_scan_gc_ena" => { type => "field", addr => 0x10628, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_spectral_scan.spectral_scan_priority" => { type => "field", addr => 0x10628, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_spectral_scan.spectral_scan_count" => { type => "field", addr => 0x10628, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spectral_scan.spectral_scan_period" => { type => "field", addr => 0x10628, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 35 }, "BB_spectral_scan.spectral_scan_fft_size" => { type => "field", addr => 0x10628, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 9 }, "BB_spectral_scan.sscan_path_sel" => { type => "field", addr => 0x10628, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "BB_spectral_scan.spectral_scan_active" => { type => "field", addr => 0x10628, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_spectral_scan.spectral_scan_ena" => { type => "field", addr => 0x10628, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_search_start_delay" => { type => "reg", addr => 0x10630, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_search_start_delay.search_start_mask_sifs" => { type => "field", addr => 0x10630, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_search_start_delay.search_start_delay_sifs" => { type => "field", addr => 0x10630, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 240 }, "BB_search_start_delay.search_start_delay_rifs" => { type => "field", addr => 0x10630, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 20 }, "BB_max_rx_length" => { type => "reg", addr => 0x10634, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_max_rx_length.max_ht_duration" => { type => "field", addr => 0x10634, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_max_rx_length.max_ht_length" => { type => "field", addr => 0x10634, width => 18, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_max_rx_length.max_rx_length" => { type => "field", addr => 0x10634, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 4095 }, "BB_frame_control" => { type => "reg", addr => 0x10638, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_frame_control.en_err_rx_abort" => { type => "field", addr => 0x10638, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_tx_underrun" => { type => "field", addr => 0x10638, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_service" => { type => "field", addr => 0x10638, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.no_6mbps_service_err" => { type => "field", addr => 0x10638, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_length_illegal" => { type => "field", addr => 0x10638, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_rate_illegal" => { type => "field", addr => 0x10638, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_signal_parity" => { type => "field", addr => 0x10638, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_tim_timeout" => { type => "field", addr => 0x10638, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_tim_early_trig" => { type => "field", addr => 0x10638, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_tim_long1" => { type => "field", addr => 0x10638, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_long_sc_thr" => { type => "field", addr => 0x10638, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_ofdm_xcorr" => { type => "field", addr => 0x10638, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_static20_mode_ht40_packet" => { type => "field", addr => 0x10638, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.en_err_green_field" => { type => "field", addr => 0x10638, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.short_high_par_norm" => { type => "field", addr => 0x10638, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.prepend_chan_info" => { type => "field", addr => 0x10638, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.tx_end_adjust" => { type => "field", addr => 0x10638, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 16 }, "BB_frame_control.cf_tx_doublesamp_dac" => { type => "field", addr => 0x10638, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_frame_control.cf_tx_clip" => { type => "field", addr => 0x10638, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "BB_frame_control.cf_overlap_window" => { type => "field", addr => 0x10638, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rfbus_request" => { type => "reg", addr => 0x1063c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rfbus_request.rfbus_request" => { type => "field", addr => 0x1063c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rfbus_grant" => { type => "reg", addr => 0x10640, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rfbus_grant.bt_ant" => { type => "field", addr => 0x10640, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rfbus_grant.rfbus_grant" => { type => "field", addr => 0x10640, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rifs" => { type => "reg", addr => 0x10644, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rifs.disable_rx_mask_mac_wait" => { type => "field", addr => 0x10644, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rifs.enable_reset_tdomain" => { type => "field", addr => 0x10644, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rifs.rifs_eco_disable" => { type => "field", addr => 0x10644, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pmi_debug_status" => { type => "reg", addr => 0x10648, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_pmi_debug_status.pmi_debug_status" => { type => "field", addr => 0x10648, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x000000ff }, "BB_rx_clear_delay" => { type => "reg", addr => 0x10650, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_clear_delay.ndp_timeout_fdomain_delay" => { type => "field", addr => 0x10650, width => 3, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "BB_rx_clear_delay.ofdm_rx_clear_delay" => { type => "field", addr => 0x10650, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_analog_power_on_time" => { type => "reg", addr => 0x10654, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_analog_power_on_time.active_to_receive" => { type => "field", addr => 0x10654, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_1" => { type => "reg", addr => 0x10658, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_timing_1.tx_frame_to_a2_tx_on" => { type => "field", addr => 0x10658, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_1.tx_frame_to_dac_on" => { type => "field", addr => 0x10658, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_1.tx_frame_to_a2_rx_off" => { type => "field", addr => 0x10658, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_1.tx_frame_to_adc_off" => { type => "field", addr => 0x10658, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_2" => { type => "reg", addr => 0x1065c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_timing_2.tx_end_to_a2_tx_off" => { type => "field", addr => 0x1065c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_2.tx_end_to_pa_off" => { type => "field", addr => 0x1065c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_2.tx_frame_to_pa_on" => { type => "field", addr => 0x1065c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_2.tx_frame_to_tx_d_start" => { type => "field", addr => 0x1065c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_3" => { type => "reg", addr => 0x10660, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_timing_3.tx_end_to_adc_on" => { type => "field", addr => 0x10660, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_3.tx_end_to_a2_rx_on" => { type => "field", addr => 0x10660, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_3.tx_frame_to_therm_chain_on" => { type => "field", addr => 0x10660, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_timing_3.tx_end_to_dac_off" => { type => "field", addr => 0x10660, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_xpa_timing_control" => { type => "reg", addr => 0x10664, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_xpa_timing_control.tx_end_to_xpab_off" => { type => "field", addr => 0x10664, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_xpa_timing_control.tx_end_to_xpaa_off" => { type => "field", addr => 0x10664, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_xpa_timing_control.tx_frame_to_xpab_on" => { type => "field", addr => 0x10664, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_xpa_timing_control.tx_frame_to_xpaa_on" => { type => "field", addr => 0x10664, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_warm_tx" => { type => "reg", addr => 0x10668, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_warm_tx.num_extra_lstf_samples" => { type => "field", addr => 0x10668, width => 8, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 128 }, "BB_warm_tx.enable_warm_tx" => { type => "field", addr => 0x10668, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_en_power_optim" => { type => "reg", addr => 0x1066c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_en_power_optim.rssi_nap_thr" => { type => "field", addr => 0x1066c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_en_power_optim.enable_power_optim_paprd" => { type => "field", addr => 0x1066c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_en_power_optim.enable_power_optim_sm" => { type => "field", addr => 0x1066c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_en_power_optim.enable_power_optim_mrc" => { type => "field", addr => 0x1066c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_en_power_optim.enable_power_optim_chn" => { type => "field", addr => 0x1066c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_misc_pa_control" => { type => "reg", addr => 0x10680, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_misc_pa_control.enable_xpab" => { type => "field", addr => 0x10680, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_misc_pa_control.enable_xpaa" => { type => "field", addr => 0x10680, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_misc_pa_control.xpab_active_high" => { type => "field", addr => 0x10680, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_misc_pa_control.xpaa_active_high" => { type => "field", addr => 0x10680, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_switch_table_chn_b0" => { type => "reg", addr => 0x10684, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_switch_table_chn_b0.enable_bt_override" => { type => "field", addr => 0x10684, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_switch_table_chn_b0.bt_in_tx_xlna_override" => { type => "field", addr => 0x10684, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_switch_table_chn_b0.switch_table_b_0" => { type => "field", addr => 0x10684, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_chn_b0.switch_table_rx12_0" => { type => "field", addr => 0x10684, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_chn_b0.switch_table_rx1_0" => { type => "field", addr => 0x10684, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_chn_b0.switch_table_r_0" => { type => "field", addr => 0x10684, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_chn_b0.switch_table_t_0" => { type => "field", addr => 0x10684, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_chn_b0.switch_table_idle_0" => { type => "field", addr => 0x10684, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_com1" => { type => "reg", addr => 0x10688, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_switch_table_com1.switch_table_com_tx_1chn" => { type => "field", addr => 0x10688, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_com1.switch_table_com_idle_alt" => { type => "field", addr => 0x10688, width => 6, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0xa }, "BB_switch_table_com1.switch_table_com_b" => { type => "field", addr => 0x10688, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_com1.switch_table_com_t2" => { type => "field", addr => 0x10688, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_com1.switch_table_com_t1" => { type => "field", addr => 0x10688, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_com1.switch_table_com_idle" => { type => "field", addr => 0x10688, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_switch_table_com2" => { type => "reg", addr => 0x1068c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_switch_table_com2.switch_table_com_ra12" => { type => "field", addr => 0x1068c, width => 4, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_com2.switch_table_com_ra2l2" => { type => "field", addr => 0x1068c, width => 4, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_com2.switch_table_com_ra1l2" => { type => "field", addr => 0x1068c, width => 4, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_com2.switch_table_com_ra2l1" => { type => "field", addr => 0x1068c, width => 4, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_com2.switch_table_com_ra1l1" => { type => "field", addr => 0x1068c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_multichain_enable" => { type => "reg", addr => 0x106a0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_multichain_enable.disable_dyn_listen" => { type => "field", addr => 0x106a0, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_multichain_enable.cf_VHT160_pkswitch_use_pbd" => { type => "field", addr => 0x106a0, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_multichain_enable.cf_VHT160_mode_forced" => { type => "field", addr => 0x106a0, width => 2, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_multichain_enable.cf_VHT160_mode_force" => { type => "field", addr => 0x106a0, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_multichain_enable.ack_response_timeout" => { type => "field", addr => 0x106a0, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x000 }, "BB_multichain_enable.dyn_listen_mask" => { type => "field", addr => 0x106a0, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_multichain_enable.rx_chain_mask" => { type => "field", addr => 0x106a0, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_rx_notch_cntl_0" => { type => "reg", addr => 0x106a4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_0.htstf_end_dc_notch_count" => { type => "field", addr => 0x106a4, width => 11, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 150 }, "BB_rx_notch_cntl_0.enable_dc_notch_filter_htstf" => { type => "field", addr => 0x106a4, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_rx_notch_cntl_0.enable_dc_notch_filter_ofdm" => { type => "field", addr => 0x106a4, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_rx_notch_cntl_0.enable_dc_notch_filter_11b" => { type => "field", addr => 0x106a4, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_0.enable_dc_notch_filter_detect" => { type => "field", addr => 0x106a4, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_rx_notch_cntl_0.enable_dc_notch_fd_ht_only" => { type => "field", addr => 0x106a4, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_0.enable_dc_notch_fd" => { type => "field", addr => 0x106a4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_0.enable_dc_notch_filter" => { type => "field", addr => 0x106a4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_1" => { type => "reg", addr => 0x106a8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_1.spur_gain_thr_ena" => { type => "field", addr => 0x106a8, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_1.spur_gain_thr" => { type => "field", addr => 0x106a8, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x200 }, "BB_rx_notch_cntl_1.alpha_dc" => { type => "field", addr => 0x106a8, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_rx_notch_cntl_1.alpha_spur2" => { type => "field", addr => 0x106a8, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_rx_notch_cntl_1.alpha_spur1" => { type => "field", addr => 0x106a8, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_vht160mode_debug" => { type => "reg", addr => 0x106bc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_vht160mode_debug.cf_force_rxtimed_switchtime" => { type => "field", addr => 0x106bc, width => 14, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vht160mode_debug.cf_force_rxtimed_final_val" => { type => "field", addr => 0x106bc, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vht160mode_debug.cf_force_rxtimed_start_val" => { type => "field", addr => 0x106bc, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vht160mode_debug.cf_VHT160_mode_rxtimed" => { type => "field", addr => 0x106bc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_chain_mask" => { type => "reg", addr => 0x106c0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cal_chain_mask.cal_chain_mask" => { type => "field", addr => 0x106c0, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_agc_control" => { type => "reg", addr => 0x106c4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc_control.max_gainchanges" => { type => "field", addr => 0x106c4, width => 4, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_control.enable_pkdet_cal" => { type => "field", addr => 0x106c4, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_control.clc_success" => { type => "field", addr => 0x106c4, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_agc_control.extend_NF_pwr_meas" => { type => "field", addr => 0x106c4, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_agc_control.no_update_noisefloor" => { type => "field", addr => 0x106c4, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_control.enable_fltr_cal" => { type => "field", addr => 0x106c4, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_control.enable_noisefloor" => { type => "field", addr => 0x106c4, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_agc_control.CAL_enable" => { type => "field", addr => 0x106c4, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_control.leaky_bucket_enable" => { type => "field", addr => 0x106c4, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_control.ycok_max" => { type => "field", addr => 0x106c4, width => 4, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_control.min_num_gain_change" => { type => "field", addr => 0x106c4, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_control.do_noisefloor" => { type => "field", addr => 0x106c4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_agc_control.do_calibrate" => { type => "field", addr => 0x106c4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_iq_adc_cal_mode" => { type => "reg", addr => 0x106c8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_iq_adc_cal_mode.test_caladcoff" => { type => "field", addr => 0x106c8, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_iq_adc_cal_mode.gain_dc_iq_cal_mode" => { type => "field", addr => 0x106c8, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fcal_1" => { type => "reg", addr => 0x106cc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fcal_1.flc_sb_atten" => { type => "field", addr => 0x106cc, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_fcal_1.flc_pb_atten" => { type => "field", addr => 0x106cc, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_fcal_1.flc_sb_fstep" => { type => "field", addr => 0x106cc, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 269 }, "BB_fcal_1.flc_pb_fstep" => { type => "field", addr => 0x106cc, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 51 }, "BB_fcal_2_b0" => { type => "reg", addr => 0x106d0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fcal_2_b0.flc_txbb6dbgain" => { type => "field", addr => 0x106d0, width => 2, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcal_2_b0.flc_txbb1dbgain" => { type => "field", addr => 0x106d0, width => 4, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcal_2_b0.flc_cap_val_status_0" => { type => "field", addr => 0x106d0, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_fcal_2_b0.flc_meas_win" => { type => "field", addr => 0x106d0, width => 3, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_fcal_2_b0.flc_sw_cap_set" => { type => "field", addr => 0x106d0, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcal_2_b0.flc_bb6dbgain" => { type => "field", addr => 0x106d0, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcal_2_b0.flc_bb1dbgain" => { type => "field", addr => 0x106d0, width => 4, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcal_2_b0.flc_bbmiscgain" => { type => "field", addr => 0x106d0, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcal_2_b0.flc_sw_cap_val_0" => { type => "field", addr => 0x106d0, width => 5, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_fcal_2_b0.flc_pwr_thresh" => { type => "field", addr => 0x106d0, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_dft_tone_ctrl_b0" => { type => "reg", addr => 0x106d4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dft_tone_ctrl_b0.dft_tone_freq_ang_0" => { type => "field", addr => 0x106d4, width => 9, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dft_tone_ctrl_b0.dft_tone_amp_sel_0" => { type => "field", addr => 0x106d4, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dft_tone_ctrl_b0.dft_tone_en_0" => { type => "field", addr => 0x106d4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cl_cal_ctrl" => { type => "reg", addr => 0x106d8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cl_cal_ctrl.cl_map_hw_gen" => { type => "field", addr => 0x106d8, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_cal_ctrl.use_dac_cl_correction" => { type => "field", addr => 0x106d8, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_cal_ctrl.cf_adc_bound" => { type => "field", addr => 0x106d8, width => 8, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_cal_ctrl.cf_clc_init_bbgain" => { type => "field", addr => 0x106d8, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 25 }, "BB_cl_cal_ctrl.carr_leak_max_offset" => { type => "field", addr => 0x106d8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_cal_ctrl.cf_clc_forced_pagain" => { type => "field", addr => 0x106d8, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_cal_ctrl.cf_clc_test_point" => { type => "field", addr => 0x106d8, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_cal_ctrl.enable_cl_calibrate" => { type => "field", addr => 0x106d8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cl_cal_ctrl.enable_parallel_cal" => { type => "field", addr => 0x106d8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cl_map_0_b0" => { type => "reg", addr => 0x106dc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cl_map_0_b0.cl_map_0" => { type => "field", addr => 0x106dc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_map_1_b0" => { type => "reg", addr => 0x106e0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cl_map_1_b0.cl_map_1" => { type => "field", addr => 0x106e0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_map_2_b0" => { type => "reg", addr => 0x106e4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cl_map_2_b0.cl_map_2" => { type => "field", addr => 0x106e4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_map_3_b0" => { type => "reg", addr => 0x106e8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cl_map_3_b0.cl_map_3" => { type => "field", addr => 0x106e8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_tab_b0" => { type => "reg", addr => 0x10700, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "BB_cl_tab_b0.bb_gain" => { type => "field", addr => 0x10700, width => 4, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_tab_b0.carr_lk_dc_add_I" => { type => "field", addr => 0x10700, width => 11, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_tab_b0.carr_lk_dc_add_Q" => { type => "field", addr => 0x10700, width => 11, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_tab_b0.cl_gain_mod" => { type => "field", addr => 0x10700, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_synth_control" => { type => "reg", addr => 0x10740, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_synth_control.sel_alt_tables" => { type => "field", addr => 0x10740, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_synth_control.rfsynth_ctrl_sshift" => { type => "field", addr => 0x10740, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_synth_control.rfbmode" => { type => "field", addr => 0x10740, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_synth_control.rfFracmode" => { type => "field", addr => 0x10740, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_synth_control.rfAmodeRefSel" => { type => "field", addr => 0x10740, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_synth_control.rfchannel" => { type => "field", addr => 0x10740, width => 9, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_synth_control.rfchanFrac" => { type => "field", addr => 0x10740, width => 17, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_addac_clk_select" => { type => "reg", addr => 0x10744, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_addac_clk_select.bb_adc_clk_select_ch3" => { type => "field", addr => 0x10744, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_addac_clk_select.bb_adc_clk_select_ch2" => { type => "field", addr => 0x10744, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_addac_clk_select.bb_adc_clk_select_ch1" => { type => "field", addr => 0x10744, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_addac_clk_select.bb_adc_clk_select_ch0" => { type => "field", addr => 0x10744, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_addac_clk_select.bb_dac_clk_select" => { type => "field", addr => 0x10744, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pll_cntl" => { type => "reg", addr => 0x10748, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pll_cntl.bb_pll_settle_time" => { type => "field", addr => 0x10748, width => 11, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 1024 }, "BB_pll_cntl.bb_pllbypass" => { type => "field", addr => 0x10748, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_pll_cntl.bb_pll_clk_sel" => { type => "field", addr => 0x10748, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pll_cntl.bb_pll_refdiv" => { type => "field", addr => 0x10748, width => 4, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_pll_cntl.bb_pll_div" => { type => "field", addr => 0x10748, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 50 }, "BB_analog_swap" => { type => "reg", addr => 0x1074c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_analog_swap.analog_pkdet_dac_polarity" => { type => "field", addr => 0x1074c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_analog_swap.analog_dc_dac_polarity" => { type => "field", addr => 0x1074c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_analog_swap.swap_alt_chn" => { type => "field", addr => 0x1074c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_analog_swap.analog_tx_swap_cntl" => { type => "field", addr => 0x1074c, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_analog_swap.analog_rx_swap_cntl" => { type => "field", addr => 0x1074c, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_addac_parallel_control" => { type => "reg", addr => 0x10750, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_addac_parallel_control.on_pwdAdc" => { type => "field", addr => 0x10750, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_addac_parallel_control.on_pwdDac" => { type => "field", addr => 0x10750, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_addac_parallel_control.on_daclpmode" => { type => "field", addr => 0x10750, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_addac_parallel_control.off_pwdAdc" => { type => "field", addr => 0x10750, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_addac_parallel_control.off_pwdDac" => { type => "field", addr => 0x10750, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_addac_parallel_control.off_daclpmode" => { type => "field", addr => 0x10750, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_clock" => { type => "reg", addr => 0x10754, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_force_clock.ena_reg_clk_gating" => { type => "field", addr => 0x10754, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_clock.cf_dpd_tx_radio_bw" => { type => "field", addr => 0x10754, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_force_clock.cf_forced_tx_radio_bw" => { type => "field", addr => 0x10754, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_force_clock.cf_force_tx_radio_bw" => { type => "field", addr => 0x10754, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_clock.cf_synthon_in_activelow" => { type => "field", addr => 0x10754, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_clock.cf_double_tx_radio_bw" => { type => "field", addr => 0x10754, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_clock.cf_forced_clktadc" => { type => "field", addr => 0x10754, width => 3, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_force_clock.cf_force_clktadc" => { type => "field", addr => 0x10754, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_clock.cf_forced_clkgen_bw" => { type => "field", addr => 0x10754, width => 3, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_force_clock.cf_force_clkgen_bw" => { type => "field", addr => 0x10754, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_clock.cf_forced_radio_bw" => { type => "field", addr => 0x10754, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_clock.cf_force_radio_bw" => { type => "field", addr => 0x10754, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_clock.cf_forced_adc_clk_rate" => { type => "field", addr => 0x10754, width => 2, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_clock.cf_force_adc_clk_rate" => { type => "field", addr => 0x10754, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_analog" => { type => "reg", addr => 0x10758, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_force_analog.forced_paprd_xpaon" => { type => "field", addr => 0x10758, width => 4, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_force_analog.forced_xpaon" => { type => "field", addr => 0x10758, width => 3, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_analog.force_xpaon" => { type => "field", addr => 0x10758, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_force_ss_ctrl" => { type => "reg", addr => 0x1075c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_force_ss_ctrl.update_offset_sw_en" => { type => "field", addr => 0x1075c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls" => { type => "reg", addr => 0x10760, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_test_controls.tstdac_out_sel" => { type => "field", addr => 0x10760, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.force_agc_clear" => { type => "field", addr => 0x10760, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.agc_obs_sel_4" => { type => "field", addr => 0x10760, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.rx_obs_sel_5th_bit" => { type => "field", addr => 0x10760, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.cf_bbb_obs_sel" => { type => "field", addr => 0x10760, width => 4, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.agc_obs_sel_3" => { type => "field", addr => 0x10760, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.slow_clk160" => { type => "field", addr => 0x10760, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.enable_mini_obs" => { type => "field", addr => 0x10760, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.enable_rfsilent_bb" => { type => "field", addr => 0x10760, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.clkout_is_clk32" => { type => "field", addr => 0x10760, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.cardbus_mode" => { type => "field", addr => 0x10760, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.cf_rfshift_sel" => { type => "field", addr => 0x10760, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.cf_tsttrig" => { type => "field", addr => 0x10760, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls.cf_tsttrig_sel" => { type => "field", addr => 0x10760, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_test_controls_status" => { type => "reg", addr => 0x10764, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_test_controls_status.cf_debugport_sel" => { type => "field", addr => 0x10764, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.cf_debugport_en" => { type => "field", addr => 0x10764, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.disable_agc_to_a2" => { type => "field", addr => 0x10764, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.cf_debugport_in" => { type => "field", addr => 0x10764, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.cf_enable_fft_dump" => { type => "field", addr => 0x10764, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.agc_obs_sel" => { type => "field", addr => 0x10764, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.reset_a2" => { type => "field", addr => 0x10764, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.disable_a2_warm_reset" => { type => "field", addr => 0x10764, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.rx_obs_sel" => { type => "field", addr => 0x10764, width => 4, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.cf_rx_src_is_tstadc" => { type => "field", addr => 0x10764, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.cf_tstadc_en" => { type => "field", addr => 0x10764, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.cf_tx_src_alternate" => { type => "field", addr => 0x10764, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.cf_tx_obs_mux_sel" => { type => "field", addr => 0x10764, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.cf_tx_obs_sel" => { type => "field", addr => 0x10764, width => 3, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.cf_tx_src_is_tstdac" => { type => "field", addr => 0x10764, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_test_controls_status.cf_tstdac_en" => { type => "field", addr => 0x10764, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tstdac" => { type => "reg", addr => 0x10768, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tstdac.tstdac_out_i" => { type => "field", addr => 0x10768, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tstdac.tstdac_out_q" => { type => "field", addr => 0x10768, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_channel_status" => { type => "reg", addr => 0x1076c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_channel_status.ant_div_cfg_used" => { type => "field", addr => 0x1076c, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_channel_status.bb_sw_com_out" => { type => "field", addr => 0x1076c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_channel_status.bb_sw_out_3" => { type => "field", addr => 0x1076c, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_channel_status.bb_sw_out_2" => { type => "field", addr => 0x1076c, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_channel_status.bb_sw_out_1" => { type => "field", addr => 0x1076c, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_channel_status.bb_sw_out_0" => { type => "field", addr => 0x1076c, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_channel_status.rx_clear_pad" => { type => "field", addr => 0x1076c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_channel_status.rx_clear_mac" => { type => "field", addr => 0x1076c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_channel_status.rx_clear_raw" => { type => "field", addr => 0x1076c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_channel_status.bt_active" => { type => "field", addr => 0x1076c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chaninfo_ctrl" => { type => "reg", addr => 0x10770, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chaninfo_ctrl.rtt_rxsm_delay_enable" => { type => "field", addr => 0x10770, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chaninfo_ctrl.rtt_mu_filt_enable" => { type => "field", addr => 0x10770, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_chaninfo_ctrl.rtt_mimo_stbc_filt_enable" => { type => "field", addr => 0x10770, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_chaninfo_ctrl.rtt_itp_cnt_rx_begin_data" => { type => "field", addr => 0x10770, width => 4, bitOffset => 25, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chaninfo_ctrl.agc_str_chain_rtt" => { type => "field", addr => 0x10770, width => 2, bitOffset => 23, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chaninfo_ctrl.rtt_post_chan_mask_en" => { type => "field", addr => 0x10770, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_chaninfo_ctrl.rtt_det_thr" => { type => "field", addr => 0x10770, width => 5, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 9 }, "BB_chaninfo_ctrl.rtt_srch_window" => { type => "field", addr => 0x10770, width => 8, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 20 }, "BB_chaninfo_ctrl.rtt_hardware_iFFT" => { type => "field", addr => 0x10770, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_chaninfo_ctrl.rtt_enable_cch_rot" => { type => "field", addr => 0x10770, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chaninfo_ctrl.rtt_mac_phy_phase" => { type => "field", addr => 0x10770, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chaninfo_ctrl.chaninfomem_bw" => { type => "field", addr => 0x10770, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chaninfo_ctrl.chaninfomem_s2_read" => { type => "field", addr => 0x10770, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chaninfo_ctrl.capture_sounding_packet" => { type => "field", addr => 0x10770, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chaninfo_ctrl.disable_chaninfomem" => { type => "field", addr => 0x10770, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chaninfo_ctrl.capture_chan_info" => { type => "field", addr => 0x10770, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chan_info_noise_pwr_b0" => { type => "reg", addr => 0x10774, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_chan_info_noise_pwr_b0.chan_info_fine_dc_q_0" => { type => "field", addr => 0x10774, width => 8, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_noise_pwr_b0.chan_info_fine_dc_i_0" => { type => "field", addr => 0x10774, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_noise_pwr_b0.noise_power" => { type => "field", addr => 0x10774, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_diff" => { type => "reg", addr => 0x10778, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_chan_info_gain_diff.analog_gain_diff_01" => { type => "field", addr => 0x10778, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_fine_timing" => { type => "reg", addr => 0x1077c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_chan_info_fine_timing.fine_timing" => { type => "field", addr => 0x1077c, width => 10, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_fine_timing.coarse_ppm" => { type => "field", addr => 0x1077c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_b0" => { type => "reg", addr => 0x10780, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_chan_info_gain_b0.chan_info_xatten2_sw_0" => { type => "field", addr => 0x10780, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_b0.chan_info_xatten1_sw_0" => { type => "field", addr => 0x10780, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_b0.chan_info_mb_gain_0" => { type => "field", addr => 0x10780, width => 7, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_b0.chan_info_rf_gain_0" => { type => "field", addr => 0x10780, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_b0.chan_info_rssi_0" => { type => "field", addr => 0x10780, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rtt_corr_value" => { type => "reg", addr => 0x10784, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rtt_corr_value.rtt_TM_Rx_rxclr_phase" => { type => "field", addr => 0x10784, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rtt_corr_value.rtt_tx_data_start_x_phase" => { type => "field", addr => 0x10784, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rtt_corr_value.rtt_cfr_ready" => { type => "field", addr => 0x10784, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rtt_corr_value.rtt_cir_ready" => { type => "field", addr => 0x10784, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rtt_corr_value.rtt_fac_status" => { type => "field", addr => 0x10784, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rtt_corr_value.rtt_async_fifo_phase" => { type => "field", addr => 0x10784, width => 5, bitOffset => 21, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rtt_corr_value.rtt_tx_frame_phase" => { type => "field", addr => 0x10784, width => 4, bitOffset => 17, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rtt_corr_value.rtt_corr_value" => { type => "field", addr => 0x10784, width => 17, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_nf_dcoff_b0" => { type => "reg", addr => 0x10788, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_nf_dcoff_b0.dc_off_q_0" => { type => "field", addr => 0x10788, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_nf_dcoff_b0.dc_off_i_0" => { type => "field", addr => 0x10788, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_fine_ppm" => { type => "reg", addr => 0x1078c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_chan_info_fine_ppm.fine_ppm" => { type => "field", addr => 0x1078c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_scrambler_seed" => { type => "reg", addr => 0x10790, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_scrambler_seed.fixed_scrambler_seed" => { type => "field", addr => 0x10790, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bbb_tx_ctrl" => { type => "reg", addr => 0x10794, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bbb_tx_ctrl.tx_cck_delay_3" => { type => "field", addr => 0x10794, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_tx_ctrl.tx_cck_delay_2" => { type => "field", addr => 0x10794, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_tx_ctrl.tx_cck_delay_1" => { type => "field", addr => 0x10794, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_tx_ctrl.allow_1mbps_short" => { type => "field", addr => 0x10794, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_tx_ctrl.txfir_japan_cck" => { type => "field", addr => 0x10794, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_tx_ctrl.tx_dac_scale_cck" => { type => "field", addr => 0x10794, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_tx_ctrl.use_scrambler_seed" => { type => "field", addr => 0x10794, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_bbb_tx_ctrl.disable_scrambler" => { type => "field", addr => 0x10794, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_bbb_txfir_0" => { type => "reg", addr => 0x10798, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_bbb_txfir_0.txfir_coeff_h3" => { type => "field", addr => 0x10798, width => 5, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_0.txfir_coeff_h2" => { type => "field", addr => 0x10798, width => 5, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_0.txfir_coeff_h1" => { type => "field", addr => 0x10798, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_0.txfir_coeff_h0" => { type => "field", addr => 0x10798, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_1" => { type => "reg", addr => 0x1079c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_bbb_txfir_1.txfir_coeff_h7" => { type => "field", addr => 0x1079c, width => 7, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_1.txfir_coeff_h6" => { type => "field", addr => 0x1079c, width => 7, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_1.txfir_coeff_h5" => { type => "field", addr => 0x1079c, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_1.txfir_coeff_h4" => { type => "field", addr => 0x1079c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_2" => { type => "reg", addr => 0x107a0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_bbb_txfir_2.txfir_coeff_h11" => { type => "field", addr => 0x107a0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_2.txfir_coeff_h10" => { type => "field", addr => 0x107a0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_2.txfir_coeff_h9" => { type => "field", addr => 0x107a0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_bbb_txfir_2.txfir_coeff_h8" => { type => "field", addr => 0x107a0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_heavy_clip_0" => { type => "reg", addr => 0x107a4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_heavy_clip_0.heavy_clip_factor_qam3" => { type => "field", addr => 0x107a4, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_0.heavy_clip_factor_qam2" => { type => "field", addr => 0x107a4, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_0.heavy_clip_factor_qam1" => { type => "field", addr => 0x107a4, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_0.heavy_clip_factor_qam0" => { type => "field", addr => 0x107a4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_1" => { type => "reg", addr => 0x107a8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_heavy_clip_1.heavy_clip_factor_qam7" => { type => "field", addr => 0x107a8, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_1.heavy_clip_factor_qam6" => { type => "field", addr => 0x107a8, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_1.heavy_clip_factor_qam5" => { type => "field", addr => 0x107a8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_1.heavy_clip_factor_qam4" => { type => "field", addr => 0x107a8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_2" => { type => "reg", addr => 0x107ac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_heavy_clip_2.heavy_clip_160_nss_thresh" => { type => "field", addr => 0x107ac, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "BB_heavy_clip_2.heavy_clip_80_nss_thresh" => { type => "field", addr => 0x107ac, width => 3, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "BB_heavy_clip_2.use_pre_emp" => { type => "field", addr => 0x107ac, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_heavy_clip_2.heavy_clip_enable" => { type => "field", addr => 0x107ac, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_2.heavy_clip_factor_qam9" => { type => "field", addr => 0x107ac, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_2.heavy_clip_factor_qam8" => { type => "field", addr => 0x107ac, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_3" => { type => "reg", addr => 0x107b0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_heavy_clip_3.hc_disable_for_ndp" => { type => "field", addr => 0x107b0, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_heavy_clip_3.heavy_clip_coe_2" => { type => "field", addr => 0x107b0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_3.heavy_clip_coe_1" => { type => "field", addr => 0x107b0, width => 7, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_3.heavy_clip_coe_0" => { type => "field", addr => 0x107b0, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sm_hist_0" => { type => "reg", addr => 0x107b4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sm_hist_0.sm_rec_mac_trig" => { type => "field", addr => 0x107b4, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sm_hist_0.sm_rec_agc_sel" => { type => "field", addr => 0x107b4, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_sm_hist_0.sm_rec_data_num" => { type => "field", addr => 0x107b4, width => 4, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_sm_hist_0.sm_rec_chn_en" => { type => "field", addr => 0x107b4, width => 4, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_sm_hist_0.sm_rec_part_en" => { type => "field", addr => 0x107b4, width => 10, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x7f }, "BB_sm_hist_0.sm_rec_time_res" => { type => "field", addr => 0x107b4, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sm_hist_0.sm_rec_mode" => { type => "field", addr => 0x107b4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_sm_hist_0.sm_rec_en" => { type => "field", addr => 0x107b4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_sm_hist_1" => { type => "reg", addr => 0x107b8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sm_hist_1.sm_rec_last_addr" => { type => "field", addr => 0x107b8, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_sm_hist_1.sm_rec_ss_format" => { type => "field", addr => 0x107b8, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rtt_cntl" => { type => "reg", addr => 0x107bc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rtt_cntl.rtt_do_fac_interp" => { type => "field", addr => 0x107bc, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rtt_cntl.cf_rx_err_rst_rtt" => { type => "field", addr => 0x107bc, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rtt_cntl.rtt_vht_beamform_filt_enable" => { type => "field", addr => 0x107bc, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rtt_cntl.rtt_ht_beamform_filt_enable" => { type => "field", addr => 0x107bc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_heavy_clip_4" => { type => "reg", addr => 0x107c0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_heavy_clip_4.heavy_clip_factor_nonhtdup40_qam3" => { type => "field", addr => 0x107c0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_4.heavy_clip_factor_nonhtdup40_qam2" => { type => "field", addr => 0x107c0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_4.heavy_clip_factor_nonhtdup40_qam1" => { type => "field", addr => 0x107c0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_4.heavy_clip_factor_nonhtdup40_qam0" => { type => "field", addr => 0x107c0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_5" => { type => "reg", addr => 0x107c4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_heavy_clip_5.heavy_clip_factor_nonhtdup40_qam6" => { type => "field", addr => 0x107c4, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_5.heavy_clip_factor_nonhtdup40_qam5" => { type => "field", addr => 0x107c4, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_5.heavy_clip_factor_nonhtdup40_qam4" => { type => "field", addr => 0x107c4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_6" => { type => "reg", addr => 0x107c8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_heavy_clip_6.heavy_clip_factor_nonhtdup80_qam3" => { type => "field", addr => 0x107c8, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_6.heavy_clip_factor_nonhtdup80_qam2" => { type => "field", addr => 0x107c8, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_6.heavy_clip_factor_nonhtdup80_qam1" => { type => "field", addr => 0x107c8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_6.heavy_clip_factor_nonhtdup80_qam0" => { type => "field", addr => 0x107c8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_7" => { type => "reg", addr => 0x107cc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_heavy_clip_7.heavy_clip_factor_nonhtdup80_qam6" => { type => "field", addr => 0x107cc, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_7.heavy_clip_factor_nonhtdup80_qam5" => { type => "field", addr => 0x107cc, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_heavy_clip_7.heavy_clip_factor_nonhtdup80_qam4" => { type => "field", addr => 0x107cc, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rtt_pbd_stat" => { type => "reg", addr => 0x107d0, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_rtt_pbd_stat.rtt_leg_bw_vld" => { type => "field", addr => 0x107d0, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RCLR", resetVal => 0x0 }, "BB_rtt_pbd_stat.rtt_leg_bw" => { type => "field", addr => 0x107d0, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_rtt_location_pri80" => { type => "reg", addr => 0x107d4, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rtt_location_pri80.agc_str_chain_rtt_pri80" => { type => "field", addr => 0x107d4, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rtt_location_pri80.rtt_fac_vht_status" => { type => "field", addr => 0x107d4, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_rtt_location_pri80.rtt_fac_vht" => { type => "field", addr => 0x107d4, width => 14, bitOffset => 15, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_rtt_location_pri80.rtt_fac_legacy_status" => { type => "field", addr => 0x107d4, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_rtt_location_pri80.rtt_fac_legacy" => { type => "field", addr => 0x107d4, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_rtt_tx_phase" => { type => "reg", addr => 0x107dc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rtt_tx_phase.tx_mixer1_phaseoffset_40_p10" => { type => "field", addr => 0x107dc, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_rtt_tx_phase.tx_mixer1_phaseoffset_40_n10" => { type => "field", addr => 0x107dc, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rtt_tx_phase.tx_mixer1_phaseoffset_80_p30" => { type => "field", addr => 0x107dc, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_rtt_tx_phase.tx_mixer1_phaseoffset_80_p10" => { type => "field", addr => 0x107dc, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rtt_tx_phase.tx_mixer1_phaseoffset_80_n10" => { type => "field", addr => 0x107dc, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_rtt_tx_phase.tx_mixer1_phaseoffset_80_n30" => { type => "field", addr => 0x107dc, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_powertx_max_sub" => { type => "reg", addr => 0x107f0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_powertx_max_sub.powertx_sub_for_2chain" => { type => "field", addr => 0x107f0, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_powertx_max_sub.use_per_packet_olpc_gain_delta_adj" => { type => "field", addr => 0x107f0, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_powertx_max_sub.use_per_packet_powertx_max" => { type => "field", addr => 0x107f0, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_1" => { type => "reg", addr => 0x107f8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_1.pwr_meas_trig_sw" => { type => "field", addr => 0x107f8, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_1.clpc_err_update_dis" => { type => "field", addr => 0x107f8, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_1.atb_meas_dur" => { type => "field", addr => 0x107f8, width => 3, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_tpc_1.therm_meas_dur" => { type => "field", addr => 0x107f8, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_tpc_1.volt_meas_dur" => { type => "field", addr => 0x107f8, width => 3, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_tpc_1.atb_ini_dur" => { type => "field", addr => 0x107f8, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_tpc_1.therm_ini_dur" => { type => "field", addr => 0x107f8, width => 3, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_tpc_1.volt_ini_dur" => { type => "field", addr => 0x107f8, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_tpc_1.pd_dc_sel" => { type => "field", addr => 0x107f8, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_1.pd_dc_win" => { type => "field", addr => 0x107f8, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_1.pd_dc_start" => { type => "field", addr => 0x107f8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_tpc_2" => { type => "reg", addr => 0x107fc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_2.pdadc_strobe_inv" => { type => "field", addr => 0x107fc, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_2.forced_target_power" => { type => "field", addr => 0x107fc, width => 6, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_2.use_forced_target_power" => { type => "field", addr => 0x107fc, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_tpc_2.tx_frame_to_pd_acc_cck" => { type => "field", addr => 0x107fc, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_tpc_2.tx_frame_to_pd_acc_ofdm" => { type => "field", addr => 0x107fc, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_2.tx_frame_to_pdadc_on" => { type => "field", addr => 0x107fc, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_3" => { type => "reg", addr => 0x10800, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_3.pdacc_mode" => { type => "field", addr => 0x10800, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_3.pdadc_strobe_dly_sel" => { type => "field", addr => 0x10800, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_3.tpc_clk_gate_enable" => { type => "field", addr => 0x10800, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_tpc_3.pd_acc_window_cck" => { type => "field", addr => 0x10800, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_tpc_3.pd_acc_window_ofdm" => { type => "field", addr => 0x10800, width => 3, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_3.therm_gain_err_db_max" => { type => "field", addr => 0x10800, width => 5, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_3.tx_end_to_pd_acc_on" => { type => "field", addr => 0x10800, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_3.tx_end_to_pdadc_on" => { type => "field", addr => 0x10800, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_4_b0" => { type => "reg", addr => 0x10804, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tpc_4_b0.pdadc_clip_2_cnt_0" => { type => "field", addr => 0x10804, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_tpc_4_b0.pdadc_clip_1_cnt_0" => { type => "field", addr => 0x10804, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_tpc_5" => { type => "reg", addr => 0x10808, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_5.heavy_clip_comp_factor_qam3" => { type => "field", addr => 0x10808, width => 7, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_5.heavy_clip_comp_factor_qam2" => { type => "field", addr => 0x10808, width => 7, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_5.heavy_clip_comp_factor_qam1" => { type => "field", addr => 0x10808, width => 7, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_5.heavy_clip_comp_factor_qam0" => { type => "field", addr => 0x10808, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_6" => { type => "reg", addr => 0x1080c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_6.heavy_clip_comp_factor_qam7" => { type => "field", addr => 0x1080c, width => 7, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_6.heavy_clip_comp_factor_qam6" => { type => "field", addr => 0x1080c, width => 7, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_6.heavy_clip_comp_factor_qam5" => { type => "field", addr => 0x1080c, width => 7, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_6.heavy_clip_comp_factor_qam4" => { type => "field", addr => 0x1080c, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_7" => { type => "reg", addr => 0x10810, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_7.max_gset_idx" => { type => "field", addr => 0x10810, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_7.clpc_attn_en" => { type => "field", addr => 0x10810, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_7.use_init_tx_gain_setting_after_warm_reset" => { type => "field", addr => 0x10810, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_7.extend_tx_frame_for_tpc" => { type => "field", addr => 0x10810, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_tpc_7.use_tx_pd_in_xpa" => { type => "field", addr => 0x10810, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_7.en_cl_gain_mod" => { type => "field", addr => 0x10810, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_7.ana_set_sel" => { type => "field", addr => 0x10810, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_7.ana_set_lst" => { type => "field", addr => 0x10810, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_tpc_7.ana_set_fst" => { type => "field", addr => 0x10810, width => 3, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_7.try_nxt_set" => { type => "field", addr => 0x10810, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_tpc_7.gain_calc_mode" => { type => "field", addr => 0x10810, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_tpc_7.olpc_mode" => { type => "field", addr => 0x10810, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_7.force_pa_cfg" => { type => "field", addr => 0x10810, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_7.force_txgain_idx" => { type => "field", addr => 0x10810, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_7.force_dac_gain" => { type => "field", addr => 0x10810, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_7.tx_gain_table_max" => { type => "field", addr => 0x10810, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_8" => { type => "reg", addr => 0x10814, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_8.power_offset_ofdm80" => { type => "field", addr => 0x10814, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "BB_tpc_8.power_offset_ofdm40" => { type => "field", addr => 0x10814, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "BB_tpc_8.power_offset_ofdm20" => { type => "field", addr => 0x10814, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "BB_tpc_8.power_offset_cck" => { type => "field", addr => 0x10814, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_tpc_9" => { type => "reg", addr => 0x10818, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_9.forced_target_power_sec80" => { type => "field", addr => 0x10818, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_9.wait_residue_settle" => { type => "field", addr => 0x10818, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_9.wait_caltx_settle" => { type => "field", addr => 0x10818, width => 4, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_10" => { type => "reg", addr => 0x1081c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_10.clpc_start_ofdm" => { type => "field", addr => 0x1081c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0010 }, "BB_tpc_10.clpc_start_cck" => { type => "field", addr => 0x1081c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_tpc_11_b0" => { type => "reg", addr => 0x10820, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_11_b0.forced_pa_cfg_0" => { type => "field", addr => 0x10820, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_11_b0.forced_dac_gain_0" => { type => "field", addr => 0x10820, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_11_b0.forced_txgain_idx_0" => { type => "field", addr => 0x10820, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_11_b0.olpc_gain_delta_0_lsb_ext" => { type => "field", addr => 0x10820, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_11_b0.olpc_gain_delta_0" => { type => "field", addr => 0x10820, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_12_b0" => { type => "reg", addr => 0x10824, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_12_b0.pdadc_bias_0" => { type => "field", addr => 0x10824, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_13" => { type => "reg", addr => 0x10828, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_13.min_dac_bo_qam0" => { type => "field", addr => 0x10828, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_13.max_dac_bo_qam0" => { type => "field", addr => 0x10828, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_13.min_dac_bo_cck" => { type => "field", addr => 0x10828, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_tpc_13.max_dac_bo_cck" => { type => "field", addr => 0x10828, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_tpc_14" => { type => "reg", addr => 0x1082c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_14.min_dac_bo_qam2" => { type => "field", addr => 0x1082c, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_14.max_dac_bo_qam2" => { type => "field", addr => 0x1082c, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_14.min_dac_bo_qam1" => { type => "field", addr => 0x1082c, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_14.max_dac_bo_qam1" => { type => "field", addr => 0x1082c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_15" => { type => "reg", addr => 0x10830, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_15.min_dac_bo_qam4" => { type => "field", addr => 0x10830, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_15.max_dac_bo_qam4" => { type => "field", addr => 0x10830, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_15.min_dac_bo_qam3" => { type => "field", addr => 0x10830, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_15.max_dac_bo_qam3" => { type => "field", addr => 0x10830, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_17" => { type => "reg", addr => 0x10838, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_17.tpc_cl_err_clip_en" => { type => "field", addr => 0x10838, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_17.pdadc_clip_en" => { type => "field", addr => 0x10838, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_17.pdadc_clip_thres" => { type => "field", addr => 0x10838, width => 9, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "BB_tpc_17.meas_pwr_sw" => { type => "field", addr => 0x10838, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_17.cl_err_is_common" => { type => "field", addr => 0x10838, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_17.min_pwr_tpc_corr" => { type => "field", addr => 0x10838, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "BB_tpc_17.tpc_cl_err_clip" => { type => "field", addr => 0x10838, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x20 }, "BB_tpc_17.tpc_cl_err_scale" => { type => "field", addr => 0x10838, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x20 }, "BB_tpc_18" => { type => "reg", addr => 0x1083c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_18.tpc_alut_base" => { type => "field", addr => 0x1083c, width => 8, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "BB_tpc_18.heavy_clip_comp_factor_qam9" => { type => "field", addr => 0x1083c, width => 7, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_18.heavy_clip_comp_factor_qam8" => { type => "field", addr => 0x1083c, width => 7, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_18.min_power_therm_volt_gain_corr" => { type => "field", addr => 0x1083c, width => 6, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_18.use_legacy_tpc" => { type => "field", addr => 0x1083c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_19_b0" => { type => "reg", addr => 0x10840, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_19_b0.bt_clpc_err_updt_0" => { type => "field", addr => 0x10840, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_19_b0.alpha_volt_0" => { type => "field", addr => 0x10840, width => 7, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_19_b0.alpha_therm_0" => { type => "field", addr => 0x10840, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_19_b0.volt_cal_value_0" => { type => "field", addr => 0x10840, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_19_b0.therm_cal_value_0" => { type => "field", addr => 0x10840, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_therm_adc_1_b0" => { type => "reg", addr => 0x10848, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_therm_adc_1_b0.init_atb_setting_0" => { type => "field", addr => 0x10848, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_therm_adc_1_b0.init_volt_setting_0" => { type => "field", addr => 0x10848, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_therm_adc_1_b0.init_therm_setting_0" => { type => "field", addr => 0x10848, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_therm_adc_2" => { type => "reg", addr => 0x1084c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_therm_adc_2.force_therm_volt_atb_to_init_settings" => { type => "field", addr => 0x1084c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_therm_adc_2.use_init_therm_volt_atb_after_warm_reset" => { type => "field", addr => 0x1084c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_therm_adc_3_b0" => { type => "reg", addr => 0x10850, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_therm_adc_3_b0.therm_adc_scaled_gain_0" => { type => "field", addr => 0x10850, width => 9, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 256 }, "BB_therm_adc_3_b0.therm_adc_offset_0" => { type => "field", addr => 0x10850, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_therm_adc_4_b0" => { type => "reg", addr => 0x10854, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_therm_adc_4_b0.latest_atb_value_0" => { type => "field", addr => 0x10854, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_therm_adc_4_b0.latest_volt_value_0" => { type => "field", addr => 0x10854, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_therm_adc_4_b0.latest_therm_value_0" => { type => "field", addr => 0x10854, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tx_forced_gain" => { type => "reg", addr => 0x10858, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_forced_gain.forced_enable_PAL" => { type => "field", addr => 0x10858, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_forced_gain.forced_txmxrgain" => { type => "field", addr => 0x10858, width => 4, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_forced_gain.forced_txbb6dbgain" => { type => "field", addr => 0x10858, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_forced_gain.forced_txbb1dbgain" => { type => "field", addr => 0x10858, width => 4, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_forced_gain.force_tx_gain" => { type => "field", addr => 0x10858, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_stat_0_b0" => { type => "reg", addr => 0x1085c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tpc_stat_0_b0.latest_dc_value_0" => { type => "field", addr => 0x1085c, width => 9, bitOffset => 17, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_0_b0.pdacc_avg_out_0" => { type => "field", addr => 0x1085c, width => 8, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_0_b0.meas_pwr_out_0" => { type => "field", addr => 0x1085c, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_1_b0" => { type => "reg", addr => 0x10860, width => 32, athEmulAttr => 0, acc => "RCLRW" }, "BB_tpc_stat_1_b0.gain_miss_mid_0" => { type => "field", addr => 0x10860, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RCLRW", resetVal => 0x0 }, "BB_tpc_stat_1_b0.gain_miss_high_0" => { type => "field", addr => 0x10860, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RCLRW", resetVal => 0x0 }, "BB_tpc_stat_1_b0.gain_miss_low_0" => { type => "field", addr => 0x10860, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RCLRW", resetVal => 0x0 }, "BB_tpc_stat_2_b0" => { type => "reg", addr => 0x10864, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tpc_stat_2_b0.ana_set_ndp_0" => { type => "field", addr => 0x10864, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_2_b0.clpc_err_mu_0" => { type => "field", addr => 0x10864, width => 10, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_2_b0.dac_gain_ndp_0" => { type => "field", addr => 0x10864, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_max_mu_dac" => { type => "reg", addr => 0x10868, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_max_mu_dac.max_mu_dac_bo_qam4" => { type => "field", addr => 0x10868, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_max_mu_dac.max_mu_dac_bo_qam3" => { type => "field", addr => 0x10868, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_max_mu_dac.max_mu_dac_bo_qam2" => { type => "field", addr => 0x10868, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_max_mu_dac.max_mu_dac_bo_qam1" => { type => "field", addr => 0x10868, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_max_mu_dac.max_mu_dac_bo_qam0" => { type => "field", addr => 0x10868, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_min_mu_dac" => { type => "reg", addr => 0x1086c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_min_mu_dac.min_mu_dac_bo_qam4" => { type => "field", addr => 0x1086c, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_min_mu_dac.min_mu_dac_bo_qam3" => { type => "field", addr => 0x1086c, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_min_mu_dac.min_mu_dac_bo_qam2" => { type => "field", addr => 0x1086c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_min_mu_dac.min_mu_dac_bo_qam1" => { type => "field", addr => 0x1086c, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_min_mu_dac.min_mu_dac_bo_qam0" => { type => "field", addr => 0x1086c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_mu_ctrl" => { type => "reg", addr => 0x10870, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_mu_ctrl.tpc_mu_enable" => { type => "field", addr => 0x10870, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_mu_ctrl.mu_tpc_cl_err_clip_en" => { type => "field", addr => 0x10870, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_mu_ctrl.mu_tpc_cl_err_clip" => { type => "field", addr => 0x10870, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x20 }, "BB_tpc_mu_ctrl.mu_tpc_cl_err_scale" => { type => "field", addr => 0x10870, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x20 }, "BB_tpc_stat_3_b0" => { type => "reg", addr => 0x10874, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tpc_stat_3_b0.latest_glut_set_0" => { type => "field", addr => 0x10874, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_tpc_stat_3_b0.latest_clpc_err_0" => { type => "field", addr => 0x10874, width => 10, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_tpc_stat_3_b0.latest_dac_gain_0" => { type => "field", addr => 0x10874, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_tpc_20" => { type => "reg", addr => 0x10878, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_20.heavy_clip_comp_factor_nonhtdup40_qam3" => { type => "field", addr => 0x10878, width => 7, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_20.heavy_clip_comp_factor_nonhtdup40_qam2" => { type => "field", addr => 0x10878, width => 7, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_20.heavy_clip_comp_factor_nonhtdup40_qam1" => { type => "field", addr => 0x10878, width => 7, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_20.heavy_clip_comp_factor_nonhtdup40_qam0" => { type => "field", addr => 0x10878, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_21" => { type => "reg", addr => 0x1087c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_21.heavy_clip_comp_factor_nonhtdup40_qam6" => { type => "field", addr => 0x1087c, width => 7, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_21.heavy_clip_comp_factor_nonhtdup40_qam5" => { type => "field", addr => 0x1087c, width => 7, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_21.heavy_clip_comp_factor_nonhtdup40_qam4" => { type => "field", addr => 0x1087c, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_22" => { type => "reg", addr => 0x10880, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_22.heavy_clip_comp_factor_nonhtdup80_qam3" => { type => "field", addr => 0x10880, width => 7, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_22.heavy_clip_comp_factor_nonhtdup80_qam2" => { type => "field", addr => 0x10880, width => 7, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_22.heavy_clip_comp_factor_nonhtdup80_qam1" => { type => "field", addr => 0x10880, width => 7, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_22.heavy_clip_comp_factor_nonhtdup80_qam0" => { type => "field", addr => 0x10880, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_23" => { type => "reg", addr => 0x10884, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_23.heavy_clip_comp_factor_nonhtdup80_qam6" => { type => "field", addr => 0x10884, width => 7, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_23.heavy_clip_comp_factor_nonhtdup80_qam5" => { type => "field", addr => 0x10884, width => 7, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_23.heavy_clip_comp_factor_nonhtdup80_qam4" => { type => "field", addr => 0x10884, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tbtpa_en" => { type => "reg", addr => 0x10888, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tbtpa_en.tbtpa_en" => { type => "field", addr => 0x10888, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tbtpa_mode" => { type => "reg", addr => 0x1088c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tbtpa_mode.tbtpa_mode" => { type => "field", addr => 0x1088c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_mcs_mask" => { type => "reg", addr => 0x10890, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_mcs_mask.mcs_mask" => { type => "field", addr => 0x10890, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tempthr" => { type => "reg", addr => 0x10894, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tempthr.tempthrh1" => { type => "field", addr => 0x10894, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tempthr.tempthrh2" => { type => "field", addr => 0x10894, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tempthr.tempthrl1" => { type => "field", addr => 0x10894, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tempthr.tempthrl2" => { type => "field", addr => 0x10894, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pwrthr" => { type => "reg", addr => 0x10898, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pwrthr.pwrthrhigh" => { type => "field", addr => 0x10898, width => 7, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pwrthr.pwrthrmid" => { type => "field", addr => 0x10898, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_betam" => { type => "reg", addr => 0x1089c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_betam.betam" => { type => "field", addr => 0x1089c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_max_target_power_adjust" => { type => "reg", addr => 0x108a0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_max_target_power_adjust.max_target_power_adjust" => { type => "field", addr => 0x108a0, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pkttimeout_high" => { type => "reg", addr => 0x108a4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pkttimeout_high.pkttimeout_high" => { type => "field", addr => 0x108a4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_therm_mask" => { type => "reg", addr => 0x108a8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_therm_mask.therm_timeout_mask" => { type => "field", addr => 0x108a8, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_therm_mask.therm_ini_mask" => { type => "field", addr => 0x108a8, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_alpha_therm0" => { type => "reg", addr => 0x108ac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_alpha_therm0.alpha_h2_high" => { type => "field", addr => 0x108ac, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_alpha_therm0.alpha_h1h2_high" => { type => "field", addr => 0x108ac, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_alpha_therm1" => { type => "reg", addr => 0x108b4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_alpha_therm1.alpha_l1h1_high" => { type => "field", addr => 0x108b4, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_alpha_therm1.alpha_l2l1_high" => { type => "field", addr => 0x108b4, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_alpha_therm1.alpha_l2_high" => { type => "field", addr => 0x108b4, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_alpha_therm1.alpha_h2_mid" => { type => "field", addr => 0x108b4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_alpha_therm2" => { type => "reg", addr => 0x108b8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_alpha_therm2.alpha_h1h2_mid" => { type => "field", addr => 0x108b8, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_alpha_therm2.alpha_l1h1_mid" => { type => "field", addr => 0x108b8, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_alpha_therm2.alpha_l2l1_mid" => { type => "field", addr => 0x108b8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_alpha_therm2.alpha_l2_mid" => { type => "field", addr => 0x108b8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_alpha_therm0" => { type => "reg", addr => 0x108bc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sec80_alpha_therm0.alpha_h2_high_sec80" => { type => "field", addr => 0x108bc, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_alpha_therm0.alpha_h1h2_high_sec80" => { type => "field", addr => 0x108bc, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_alpha_therm1" => { type => "reg", addr => 0x108c0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sec80_alpha_therm1.alpha_l1h1_high_sec80" => { type => "field", addr => 0x108c0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_alpha_therm1.alpha_l2l1_high_sec80" => { type => "field", addr => 0x108c0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_alpha_therm1.alpha_l2_high_sec80" => { type => "field", addr => 0x108c0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_alpha_therm1.alpha_h2_mid_sec80" => { type => "field", addr => 0x108c0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_alpha_therm2" => { type => "reg", addr => 0x108c4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sec80_alpha_therm2.alpha_h1h2_mid_sec80" => { type => "field", addr => 0x108c4, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_alpha_therm2.alpha_l1h1_mid_sec80" => { type => "field", addr => 0x108c4, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_alpha_therm2.alpha_l2l1_mid_sec80" => { type => "field", addr => 0x108c4, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_alpha_therm2.alpha_l2_mid_sec80" => { type => "field", addr => 0x108c4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_alpha_therm0" => { type => "reg", addr => 0x108c8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fcs_alpha_therm0.alpha_h2_high_fcs" => { type => "field", addr => 0x108c8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_alpha_therm0.alpha_h1h2_high_fcs" => { type => "field", addr => 0x108c8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_alpha_therm1" => { type => "reg", addr => 0x108cc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fcs_alpha_therm1.alpha_l1h1_high_fcs" => { type => "field", addr => 0x108cc, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_alpha_therm1.alpha_l2l1_high_fcs" => { type => "field", addr => 0x108cc, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_alpha_therm1.alpha_l2_high_fcs" => { type => "field", addr => 0x108cc, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_alpha_therm1.alpha_h2_mid_fcs" => { type => "field", addr => 0x108cc, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_alpha_therm2" => { type => "reg", addr => 0x108d0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fcs_alpha_therm2.alpha_h1h2_mid_fcs" => { type => "field", addr => 0x108d0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_alpha_therm2.alpha_l1h1_mid_fcs" => { type => "field", addr => 0x108d0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_alpha_therm2.alpha_l2l1_mid_fcs" => { type => "field", addr => 0x108d0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_alpha_therm2.alpha_l2_mid_fcs" => { type => "field", addr => 0x108d0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pkttimeout_mid" => { type => "reg", addr => 0x108d4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pkttimeout_mid.pkttimeout_mid" => { type => "field", addr => 0x108d4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_power_offset0" => { type => "reg", addr => 0x108d8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_power_offset0.power_offset_h2_high" => { type => "field", addr => 0x108d8, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_power_offset0.power_offset_h1h2_high" => { type => "field", addr => 0x108d8, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_power_offset1" => { type => "reg", addr => 0x108dc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_power_offset1.power_offset_l1h1_high" => { type => "field", addr => 0x108dc, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_power_offset1.power_offset_l2l1_high" => { type => "field", addr => 0x108dc, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_power_offset1.power_offset_l2_high" => { type => "field", addr => 0x108dc, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_power_offset1.power_offset_h2_mid" => { type => "field", addr => 0x108dc, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_power_offset2" => { type => "reg", addr => 0x108e0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_power_offset2.power_offset_h1h2_mid" => { type => "field", addr => 0x108e0, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_power_offset2.power_offset_l1h1_mid" => { type => "field", addr => 0x108e0, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_power_offset2.power_offset_l2l1_mid" => { type => "field", addr => 0x108e0, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_power_offset2.power_offset_l2_mid" => { type => "field", addr => 0x108e0, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_power_offset0" => { type => "reg", addr => 0x108e4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sec80_power_offset0.power_offset_h2_high_sec80" => { type => "field", addr => 0x108e4, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_power_offset0.power_offset_h1h2_high_sec80" => { type => "field", addr => 0x108e4, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_power_offset1" => { type => "reg", addr => 0x108e8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sec80_power_offset1.power_offset_l1h1_high_sec80" => { type => "field", addr => 0x108e8, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_power_offset1.power_offset_l2l1_high_sec80" => { type => "field", addr => 0x108e8, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_power_offset1.power_offset_l2_high_sec80" => { type => "field", addr => 0x108e8, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_power_offset1.power_offset_h2_mid_sec80" => { type => "field", addr => 0x108e8, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_power_offset2" => { type => "reg", addr => 0x108ec, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sec80_power_offset2.power_offset_h1h2_mid_sec80" => { type => "field", addr => 0x108ec, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_power_offset2.power_offset_l1h1_mid_sec80" => { type => "field", addr => 0x108ec, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_power_offset2.power_offset_l2l1_mid_sec80" => { type => "field", addr => 0x108ec, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_sec80_power_offset2.power_offset_l2_mid_sec80" => { type => "field", addr => 0x108ec, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_power_offset0" => { type => "reg", addr => 0x108f0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fcs_power_offset0.power_offset_h2_high_fcs" => { type => "field", addr => 0x108f0, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_power_offset0.power_offset_h1h2_high_fcs" => { type => "field", addr => 0x108f0, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_power_offset1" => { type => "reg", addr => 0x108f4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fcs_power_offset1.power_offset_l1h1_high_fcs" => { type => "field", addr => 0x108f4, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_power_offset1.power_offset_l2l1_high_fcs" => { type => "field", addr => 0x108f4, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_power_offset1.power_offset_l2_high_fcs" => { type => "field", addr => 0x108f4, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_power_offset1.power_offset_h2_mid_fcs" => { type => "field", addr => 0x108f4, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_power_offset2" => { type => "reg", addr => 0x108f8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fcs_power_offset2.power_offset_h1h2_mid_fcs" => { type => "field", addr => 0x108f8, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_power_offset2.power_offset_l1h1_mid_fcs" => { type => "field", addr => 0x108f8, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_power_offset2.power_offset_l2l1_mid_fcs" => { type => "field", addr => 0x108f8, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcs_power_offset2.power_offset_l2_mid_fcs" => { type => "field", addr => 0x108f8, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_estimated_therm" => { type => "reg", addr => 0x108fc, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_estimated_therm.estimated_therm" => { type => "field", addr => 0x108fc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tx_clken_stagger_ctrl" => { type => "reg", addr => 0x10900, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_clken_stagger_ctrl.tx_clken_stagger_off_enable" => { type => "field", addr => 0x10900, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_clken_stagger_ctrl.tx_clken_stagger_off_delay" => { type => "field", addr => 0x10900, width => 15, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_clken_stagger_ctrl.tx_clken_stagger_on_enable" => { type => "field", addr => 0x10900, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_clken_stagger_ctrl.tx_clken_stagger_on_delay" => { type => "field", addr => 0x10900, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_ctrl" => { type => "reg", addr => 0x10980, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rrt_ctrl.use_mask_only" => { type => "field", addr => 0x10980, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_ctrl.force_radio_restore" => { type => "field", addr => 0x10980, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_ctrl.restore_mask" => { type => "field", addr => 0x10980, width => 6, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x3c }, "BB_rrt_ctrl.ena_radio_retention" => { type => "field", addr => 0x10980, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_table_sw_intf_b0" => { type => "reg", addr => 0x10984, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rrt_table_sw_intf_b0.sw_rrt_table_addr_offset_0" => { type => "field", addr => 0x10984, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_table_sw_intf_b0.sw_rrt_table_addr_0" => { type => "field", addr => 0x10984, width => 3, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_table_sw_intf_b0.sw_rrt_table_write_0" => { type => "field", addr => 0x10984, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_table_sw_intf_b0.sw_rrt_table_access_0" => { type => "field", addr => 0x10984, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_table_sw_intf_1_b0" => { type => "reg", addr => 0x10988, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rrt_table_sw_intf_1_b0.sw_rrt_table_data_0" => { type => "field", addr => 0x10988, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_txiqcal_control_0" => { type => "reg", addr => 0x10a44, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txiqcal_control_0.enable_txiq_calibrate" => { type => "field", addr => 0x10a44, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_0.enable_combined_carr_iq_cal" => { type => "field", addr => 0x10a44, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_0.loopback_delay" => { type => "field", addr => 0x10a44, width => 7, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 32 }, "BB_txiqcal_control_0.caltxshift_delay" => { type => "field", addr => 0x10a44, width => 4, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_txiqcal_control_0.min_tx_tone_gain" => { type => "field", addr => 0x10a44, width => 6, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x22 }, "BB_txiqcal_control_0.max_tx_tone_gain" => { type => "field", addr => 0x10a44, width => 6, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_0.base_tx_tone_db" => { type => "field", addr => 0x10a44, width => 6, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_0.txiqc_sw_sel_ext80_tables" => { type => "field", addr => 0x10a44, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_1" => { type => "reg", addr => 0x10a48, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txiqcal_control_1.adc_sat_sel" => { type => "field", addr => 0x10a48, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_txiqcal_control_1.adc_sat_len" => { type => "field", addr => 0x10a48, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_1.txcal_loopback_mode" => { type => "field", addr => 0x10a48, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_1.iqcal_disable_mixer" => { type => "field", addr => 0x10a48, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_1.iqcorr_i_q_coff_delpt" => { type => "field", addr => 0x10a48, width => 9, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 18 }, "BB_txiqcal_control_1.min_rx_gain_db" => { type => "field", addr => 0x10a48, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_txiqcal_control_1.max_rx_gain_db" => { type => "field", addr => 0x10a48, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 32 }, "BB_txiqcal_control_1.rx_init_gain_db" => { type => "field", addr => 0x10a48, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 20 }, "BB_txiqcal_control_2" => { type => "reg", addr => 0x10a4c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txiqcal_control_2.iqcal_max_gc_cnt" => { type => "field", addr => 0x10a4c, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_txiqcal_control_2.iqcal_meas_len" => { type => "field", addr => 0x10a4c, width => 3, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_txiqcal_control_2.dither_ctl" => { type => "field", addr => 0x10a4c, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_txiqcal_control_2.gain_update_delay" => { type => "field", addr => 0x10a4c, width => 8, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 39 }, "BB_txiqcal_control_2.iqcal_max_tx_gain" => { type => "field", addr => 0x10a4c, width => 5, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_txiqcal_control_2.iqcal_min_tx_gain" => { type => "field", addr => 0x10a4c, width => 5, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_txiqcal_control_2.iqcal_adcsat_gain_mod" => { type => "field", addr => 0x10a4c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_txiqcal_control_3" => { type => "reg", addr => 0x10a50, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txiqcal_control_3.tx_iqcorr_en" => { type => "field", addr => 0x10a50, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_txiqcal_control_3.desired_size_db" => { type => "field", addr => 0x10a50, width => 5, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_txiqcal_control_3.txiqc_dc_backoff" => { type => "field", addr => 0x10a50, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_txiqcal_control_3.dc_est_len" => { type => "field", addr => 0x10a50, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_txiqcal_control_3.iqcal_tone_phs_step" => { type => "field", addr => 0x10a50, width => 10, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 128 }, "BB_txiqcal_control_3.pwr_low_db" => { type => "field", addr => 0x10a50, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x2e }, "BB_txiqcal_control_3.pwr_high_db" => { type => "field", addr => 0x10a50, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3e }, "BB_txiqcal_control_4" => { type => "reg", addr => 0x10a54, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txiqcal_control_4.txiqc_sel_ext80_alt_tables" => { type => "field", addr => 0x10a54, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_4.sw_cl_lut_sel" => { type => "field", addr => 0x10a54, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_4.hw_cl_lut_ovr" => { type => "field", addr => 0x10a54, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_4.dc_odac_lut_xlna_ovr" => { type => "field", addr => 0x10a54, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "BB_txiqcal_control_4.sw_dc_odac_lut_sel" => { type => "field", addr => 0x10a54, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_4.hw_dc_odac_lut_ovr" => { type => "field", addr => 0x10a54, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_4.en_rxcal_txgain_update_fix" => { type => "field", addr => 0x10a54, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_txiqcal_control_4.dc_odac_lb_lut_sel" => { type => "field", addr => 0x10a54, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_control_4.iqcal_peak_est_corr_factor" => { type => "field", addr => 0x10a54, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_cal_rxbb_gain_tbl_0" => { type => "reg", addr => 0x10a70, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cal_rxbb_gain_tbl_0.txcal_rx_bb_gain_table_3" => { type => "field", addr => 0x10a70, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_0.txcal_rx_bb_gain_table_2" => { type => "field", addr => 0x10a70, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_0.txcal_rx_bb_gain_table_1" => { type => "field", addr => 0x10a70, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_0.txcal_rx_bb_gain_table_0" => { type => "field", addr => 0x10a70, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_4" => { type => "reg", addr => 0x10a74, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cal_rxbb_gain_tbl_4.txcal_rx_bb_gain_table_7" => { type => "field", addr => 0x10a74, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_4.txcal_rx_bb_gain_table_6" => { type => "field", addr => 0x10a74, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_4.txcal_rx_bb_gain_table_5" => { type => "field", addr => 0x10a74, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_4.txcal_rx_bb_gain_table_4" => { type => "field", addr => 0x10a74, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_8" => { type => "reg", addr => 0x10a78, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cal_rxbb_gain_tbl_8.txcal_rx_bb_gain_table_11" => { type => "field", addr => 0x10a78, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_8.txcal_rx_bb_gain_table_10" => { type => "field", addr => 0x10a78, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_8.txcal_rx_bb_gain_table_9" => { type => "field", addr => 0x10a78, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_8.txcal_rx_bb_gain_table_8" => { type => "field", addr => 0x10a78, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_12" => { type => "reg", addr => 0x10a7c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cal_rxbb_gain_tbl_12.txcal_rx_bb_gain_table_15" => { type => "field", addr => 0x10a7c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_12.txcal_rx_bb_gain_table_14" => { type => "field", addr => 0x10a7c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_12.txcal_rx_bb_gain_table_13" => { type => "field", addr => 0x10a7c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_12.txcal_rx_bb_gain_table_12" => { type => "field", addr => 0x10a7c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_16" => { type => "reg", addr => 0x10a80, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cal_rxbb_gain_tbl_16.txcal_rx_bb_gain_table_19" => { type => "field", addr => 0x10a80, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_16.txcal_rx_bb_gain_table_18" => { type => "field", addr => 0x10a80, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_16.txcal_rx_bb_gain_table_17" => { type => "field", addr => 0x10a80, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_16.txcal_rx_bb_gain_table_16" => { type => "field", addr => 0x10a80, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_20" => { type => "reg", addr => 0x10a84, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cal_rxbb_gain_tbl_20.txcal_rx_bb_gain_table_23" => { type => "field", addr => 0x10a84, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_20.txcal_rx_bb_gain_table_22" => { type => "field", addr => 0x10a84, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_20.txcal_rx_bb_gain_table_21" => { type => "field", addr => 0x10a84, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_20.txcal_rx_bb_gain_table_20" => { type => "field", addr => 0x10a84, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_gain_tbl_24" => { type => "reg", addr => 0x10a88, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cal_rxbb_gain_tbl_24.txcal_rx_bb_gain_table_24" => { type => "field", addr => 0x10a88, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcal_status_b0" => { type => "reg", addr => 0x10a8c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_txiqcal_status_b0.last_meas_addr_0" => { type => "field", addr => 0x10a8c, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_txiqcal_status_b0.rx_gain_used_0" => { type => "field", addr => 0x10a8c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_txiqcal_status_b0.tone_gain_used_0" => { type => "field", addr => 0x10a8c, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_txiqcal_status_b0.calibrated_gains_0" => { type => "field", addr => 0x10a8c, width => 5, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_txiqcal_status_b0.txiqcal_failed_0" => { type => "field", addr => 0x10a8c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_cal_rxbb_tia_gain_tbl_1" => { type => "reg", addr => 0x10a90, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cal_rxbb_tia_gain_tbl_1.txcal_rx_bb_tia_gain_table_1" => { type => "field", addr => 0x10a90, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cal_rxbb_tia_gain_tbl_2" => { type => "reg", addr => 0x10a94, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cal_rxbb_tia_gain_tbl_2.txcal_rx_bb_tia_gain_table_2" => { type => "field", addr => 0x10a94, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxiqcal_status_b0" => { type => "reg", addr => 0x10aac, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rxiqcal_status_b0.rxiqcal_last_meas_addr_0" => { type => "field", addr => 0x10aac, width => 6, bitOffset => 11, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxiqcal_status_b0.rxiqcal_txgain_idx_used_0" => { type => "field", addr => 0x10aac, width => 5, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxiqcal_status_b0.rxiqcal_calibrated_gains_0" => { type => "field", addr => 0x10aac, width => 5, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxiqcal_status_b0.rxiqcal_failed_0" => { type => "field", addr => 0x10aac, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_hsprd_train_cntl_0" => { type => "reg", addr => 0x10ad0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_hsprd_train_cntl_0.cf_cal_xpa" => { type => "field", addr => 0x10ad0, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pefcal_cntl_0" => { type => "reg", addr => 0x10aec, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pefcal_cntl_0.cf_pefcal_lb_sel" => { type => "field", addr => 0x10aec, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pefcal_cntl_0.cf_pefcal_mag_sel" => { type => "field", addr => 0x10aec, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_pefcal_cntl_0.cf_pefcal_fstep" => { type => "field", addr => 0x10aec, width => 6, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_pefcal_cntl_0.cf_pefcal_f4agc2" => { type => "field", addr => 0x10aec, width => 7, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 16 }, "BB_pefcal_cntl_0.cf_pefcal_fmin" => { type => "field", addr => 0x10aec, width => 7, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x42 }, "BB_pefcal_cntl_0.cf_pefcal_fmax" => { type => "field", addr => 0x10aec, width => 7, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 62 }, "BB_pefcal_cntl_0.enable_pef_calibrate" => { type => "field", addr => 0x10aec, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pefcal_cntl_1" => { type => "reg", addr => 0x10af0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pefcal_cntl_1.cf_pefcal_table_sel" => { type => "field", addr => 0x10af0, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pefcal_cntl_1.cf_pefcal_continuous_cal" => { type => "field", addr => 0x10af0, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pefcal_cntl_1.cf_pefcal_smart_preamble" => { type => "field", addr => 0x10af0, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pefcal_cntl_1.cf_pefcal_txgain_idx" => { type => "field", addr => 0x10af0, width => 5, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pefcal_cntl_1.cf_pefcal_timeout" => { type => "field", addr => 0x10af0, width => 8, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 10 }, "BB_pefcal_cntl_1.cf_pefcal_chn_sel" => { type => "field", addr => 0x10af0, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pefcal_cntl_1.cf_pefcal_timeout_enable" => { type => "field", addr => 0x10af0, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_pefcal_cntl_1.cf_pefcal_trxiqcl_corrected" => { type => "field", addr => 0x10af0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pefcal_cntl_2" => { type => "reg", addr => 0x10af4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pefcal_cntl_2.cf_pefcal_corr_len" => { type => "field", addr => 0x10af4, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "BB_pefcal_cntl_2.cf_pefcal_settling_time" => { type => "field", addr => 0x10af4, width => 6, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_pefcal_cntl_2.cf_pefcal_idle_time" => { type => "field", addr => 0x10af4, width => 6, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_pefcal_cntl_2.cf_pefcal_preamble_time" => { type => "field", addr => 0x10af4, width => 12, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0xff }, "BB_pefcal_cntl_2.cf_pefcal_is_waiting" => { type => "field", addr => 0x10af4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_pefcal_cntl_2.cf_pefcal_phase_sel" => { type => "field", addr => 0x10af4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_preemp_cntl_0" => { type => "reg", addr => 0x10af8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_cntl_0.preemp_mask" => { type => "field", addr => 0x10af8, width => 31, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_preemp_cntl_0.tx_preemp_fir_en" => { type => "field", addr => 0x10af8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_preemp_cntl_1" => { type => "reg", addr => 0x10afc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_cntl_1.tx_preemp_half_rate_en" => { type => "field", addr => 0x10afc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_bw_cntl_0" => { type => "reg", addr => 0x10b00, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_bw_cntl_0.paprd_control_bw_en" => { type => "field", addr => 0x10b00, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxiqcal_control_0" => { type => "reg", addr => 0x10b04, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxiqcal_control_0.enable_rxiq_calibrate" => { type => "field", addr => 0x10b04, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxiqcal_control_0.rxcal_tx_gain_init_db" => { type => "field", addr => 0x10b04, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 60 }, "BB_rxiqcal_control_0.rxcal_tx_gain_max_db" => { type => "field", addr => 0x10b04, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 60 }, "BB_rxiqcal_control_0.rxcal_tx_gain_min_db" => { type => "field", addr => 0x10b04, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rxiqcal_control_0.rxcal_max_rx_gain" => { type => "field", addr => 0x10b04, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_rxiqcal_control_0.rxcal_min_rx_gain" => { type => "field", addr => 0x10b04, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rxiqcal_control_0.rxcal_loopback_mode" => { type => "field", addr => 0x10b04, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxiqcal_control_0.sel_ext80_alt_tables" => { type => "field", addr => 0x10b04, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxiqcal_control_0.sw_sel_ext80_tables" => { type => "field", addr => 0x10b04, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_notch_cntl_0" => { type => "reg", addr => 0x10b08, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_notch_cntl_0.notch_mask" => { type => "field", addr => 0x10b08, width => 31, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_notch_cntl_0.cf_tx_notch_iir_en" => { type => "field", addr => 0x10b08, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_agc" => { type => "reg", addr => 0x10b10, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_agc.debug_mux_ena" => { type => "field", addr => 0x10b10, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_agc.dbg_bus_agc_sel_B" => { type => "field", addr => 0x10b10, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dbg_mask_agc.dbg_bus_agc_sel_A" => { type => "field", addr => 0x10b10, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dbg_mask_agc.dbg_mask_agc" => { type => "field", addr => 0x10b10, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_rxsm" => { type => "reg", addr => 0x10b14, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_rxsm.dbg_bus_rxsm_sel_B" => { type => "field", addr => 0x10b14, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dbg_mask_rxsm.dbg_bus_rxsm_sel_A" => { type => "field", addr => 0x10b14, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dbg_mask_rxsm.dbg_mask_rxsm" => { type => "field", addr => 0x10b14, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_txsm" => { type => "reg", addr => 0x10b18, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_txsm.dbg_mask_txsm" => { type => "field", addr => 0x10b18, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_tctl" => { type => "reg", addr => 0x10b1c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_tctl.dbg_mask_tctl" => { type => "field", addr => 0x10b1c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_vit" => { type => "reg", addr => 0x10b20, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_vit.dbg_mask_vit" => { type => "field", addr => 0x10b20, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_dfs" => { type => "reg", addr => 0x10b24, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_dfs.dbg_bus_dfs_sel_B" => { type => "field", addr => 0x10b24, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dbg_mask_dfs.dbg_bus_dfs_sel_A" => { type => "field", addr => 0x10b24, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dbg_mask_dfs.dbg_mask_dfs" => { type => "field", addr => 0x10b24, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_cal" => { type => "reg", addr => 0x10b28, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_cal.dbg_mask_cal" => { type => "field", addr => 0x10b28, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_tpc" => { type => "reg", addr => 0x10b2c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_tpc.dbg_mask_tpc" => { type => "field", addr => 0x10b2c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_svd" => { type => "reg", addr => 0x10b30, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_svd.dbg_mask_svd" => { type => "field", addr => 0x10b30, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_mpi" => { type => "reg", addr => 0x10b34, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_mpi.dbg_mask_mpi" => { type => "field", addr => 0x10b34, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_mask_pmi" => { type => "reg", addr => 0x10b38, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_mask_pmi.dbg_mask_pmi" => { type => "field", addr => 0x10b38, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_bus_sel_sm" => { type => "reg", addr => 0x10b3c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dbg_bus_sel_sm.dbg_bus_sel_rxsm" => { type => "field", addr => 0x10b3c, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_bus_sel_sm.dbg_bus_sel_txbe" => { type => "field", addr => 0x10b3c, width => 2, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_bus_sel_sm.dbg_bus_sel_mpi" => { type => "field", addr => 0x10b3c, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_bus_sel_sm.dbg_bus_sel_txb" => { type => "field", addr => 0x10b3c, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dbg_bus_sel_sm.dbg_bus_sel_txa" => { type => "field", addr => 0x10b3c, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txa_state_history" => { type => "reg", addr => 0x10b40, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_txa_state_history.txa_state_history" => { type => "field", addr => 0x10b40, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_txb_state_history" => { type => "reg", addr => 0x10b44, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_txb_state_history.txb_state_history" => { type => "field", addr => 0x10b44, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_tlv_state_history" => { type => "reg", addr => 0x10b48, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tlv_state_history.tlv_state_history" => { type => "field", addr => 0x10b48, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_ibfcal_rfcntl" => { type => "reg", addr => 0x10b50, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rfcntl.cf_ibfcal_rx_xlnaon" => { type => "field", addr => 0x10b50, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ibfcal_rfcntl.cf_ibfcal_rx_xpaon" => { type => "field", addr => 0x10b50, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_tpc_error_count" => { type => "reg", addr => 0x10b54, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_error_count.tpc_error_count" => { type => "field", addr => 0x10b54, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxsm_state_history" => { type => "reg", addr => 0x10b5c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rxsm_state_history.rxsm_state_history" => { type => "field", addr => 0x10b5c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_rxsm_cck_state_history" => { type => "reg", addr => 0x10b60, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rxsm_cck_state_history.rxsm_cck_state_history" => { type => "field", addr => 0x10b60, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cntm_state_history" => { type => "reg", addr => 0x10b64, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_cntm_state_history.cntsm_state_history" => { type => "field", addr => 0x10b64, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_agc_state_history" => { type => "reg", addr => 0x10b68, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_agc_state_history.agc_current_state" => { type => "field", addr => 0x10b68, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_agc_state_history.agc_state_history" => { type => "field", addr => 0x10b68, width => 28, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_packet_counter_tx_legacy" => { type => "reg", addr => 0x10b6c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_packet_counter_tx_legacy.mpi_11b_pkt_count" => { type => "field", addr => 0x10b6c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_tx_legacy.mpi_11a_pkt_count" => { type => "field", addr => 0x10b6c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_tx_ht" => { type => "reg", addr => 0x10b70, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_packet_counter_tx_ht.mpi_11ac_pkt_count" => { type => "field", addr => 0x10b70, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_tx_ht.mpi_11n_pkt_count" => { type => "field", addr => 0x10b70, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_rx_legacy" => { type => "reg", addr => 0x10b74, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_packet_counter_rx_legacy.pmi_11b_pkt_count" => { type => "field", addr => 0x10b74, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_rx_legacy.pmi_11a_pkt_count" => { type => "field", addr => 0x10b74, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_rx_ht" => { type => "reg", addr => 0x10b78, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_packet_counter_rx_ht.pmi_11ac_pkt_count" => { type => "field", addr => 0x10b78, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_rx_ht.pmi_11n_pkt_count" => { type => "field", addr => 0x10b78, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_mimo" => { type => "reg", addr => 0x10b7c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_packet_counter_mimo.pmi_mimo_pkt_count" => { type => "field", addr => 0x10b7c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_mimo.mpi_mimo_pkt_count" => { type => "field", addr => 0x10b7c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_mu" => { type => "reg", addr => 0x10b80, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_packet_counter_mu.pmi_mu_pkt_count" => { type => "field", addr => 0x10b80, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_counter_mu.mpi_mu_pkt_count" => { type => "field", addr => 0x10b80, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_debug_register1" => { type => "reg", addr => 0x10b84, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_debug_register1.debug1" => { type => "field", addr => 0x10b84, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_debug_register2" => { type => "reg", addr => 0x10b88, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_debug_register2.debug2" => { type => "field", addr => 0x10b88, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_debug_register3" => { type => "reg", addr => 0x10b8c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_debug_register3.debug3" => { type => "field", addr => 0x10b8c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_watchdog_status" => { type => "reg", addr => 0x10bc0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_watchdog_status.watchdog_status_8" => { type => "field", addr => 0x10bc0, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status.watchdog_status_7" => { type => "field", addr => 0x10bc0, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status.watchdog_status_6" => { type => "field", addr => 0x10bc0, width => 3, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status.watchdog_status_5" => { type => "field", addr => 0x10bc0, width => 4, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status.watchdog_status_4" => { type => "field", addr => 0x10bc0, width => 4, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status.watchdog_status_3" => { type => "field", addr => 0x10bc0, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status.watchdog_status_2" => { type => "field", addr => 0x10bc0, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "BB_watchdog_status.watchdog_timeout" => { type => "field", addr => 0x10bc0, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status.watchdog_status_1" => { type => "field", addr => 0x10bc0, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_ctrl_1" => { type => "reg", addr => 0x10bc4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_watchdog_ctrl_1.watchdog_timeout_reset_idle_limit" => { type => "field", addr => 0x10bc4, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_ctrl_1.watchdog_timeout_reset_non_idle_limit" => { type => "field", addr => 0x10bc4, width => 14, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_ctrl_1.enable_watchdog_timeout_reset_idle" => { type => "field", addr => 0x10bc4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_watchdog_ctrl_1.enable_watchdog_timeout_reset_non_idle" => { type => "field", addr => 0x10bc4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_watchdog_ctrl_2" => { type => "reg", addr => 0x10bc8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_watchdog_ctrl_2.enable_watchdog_agc_ht_stf" => { type => "field", addr => 0x10bc8, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_ctrl_2.enable_watchdog_radar_arb" => { type => "field", addr => 0x10bc8, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_ctrl_2.enable_watchdog_sscan" => { type => "field", addr => 0x10bc8, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_ctrl_2.enable_watchdog_radar" => { type => "field", addr => 0x10bc8, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_ctrl_2.sw_abort_active" => { type => "field", addr => 0x10bc8, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_ctrl_2.watchdog_irq_ena" => { type => "field", addr => 0x10bc8, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_ctrl_2.watchdog_timeout_reset_ena" => { type => "field", addr => 0x10bc8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_ctrl_2.force_fast_adc_clk" => { type => "field", addr => 0x10bc8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bluetooth_cntl" => { type => "reg", addr => 0x10bcc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_bluetooth_cntl.bt_ant_halt_wlan" => { type => "field", addr => 0x10bcc, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_bluetooth_cntl.bt_break_cck_en" => { type => "field", addr => 0x10bcc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_phyonly_control" => { type => "reg", addr => 0x10bd4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_phyonly_control.en_low_freq_sleep" => { type => "field", addr => 0x10bd4, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_phyonly_control.static_rx_antenna" => { type => "field", addr => 0x10bd4, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_phyonly_control.rx_antenna_select" => { type => "field", addr => 0x10bd4, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_phyonly_control.static_tx_antenna" => { type => "field", addr => 0x10bd4, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_phyonly_control.tx_antenna_select" => { type => "field", addr => 0x10bd4, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_phyonly_control.use_fixed_scrambler_seed" => { type => "field", addr => 0x10bd4, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_phyonly_control.late_tx_signal_symbol" => { type => "field", addr => 0x10bd4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_phyonly_control.rx_drain_rate" => { type => "field", addr => 0x10bd4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_eco_ctrl" => { type => "reg", addr => 0x10bdc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_eco_ctrl.eco_ctrl" => { type => "field", addr => 0x10bdc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_B" => { type => "reg", addr => 0x10be0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_watchdog_status_B.watchdog_status_B_reserved" => { type => "field", addr => 0x10be0, width => 6, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_B.watchdog_status_B_srchfft_pwr_sm" => { type => "field", addr => 0x10be0, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_B.watchdog_status_B_srchfft_bw_sm" => { type => "field", addr => 0x10be0, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_B.watchdog_status_B_srchfft_out_sm" => { type => "field", addr => 0x10be0, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_B.watchdog_status_B_srchfft_in_sm" => { type => "field", addr => 0x10be0, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_B.watchdog_status_B_srchfft_sem_lock" => { type => "field", addr => 0x10be0, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_B.watchdog_status_B_sscan_sm" => { type => "field", addr => 0x10be0, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_B.watchdog_status_B_radar_sm" => { type => "field", addr => 0x10be0, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_B.watchdog_status_B_hang_flags" => { type => "field", addr => 0x10be0, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tlv_ctrl1" => { type => "reg", addr => 0x10be4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tlv_ctrl1.tlv_flow_control_threshold" => { type => "field", addr => 0x10be4, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_phy_rx_timeout" => { type => "reg", addr => 0x10be8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_phy_rx_timeout.rxsm_timeout_threshold" => { type => "field", addr => 0x10be8, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7ff }, "BB_tx_phase_dither" => { type => "reg", addr => 0x10bec, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_phase_dither.enable_csd_phase_dithering" => { type => "field", addr => 0x10bec, width => 3, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tables_intf_addr_b0" => { type => "reg", addr => 0x10bf0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tables_intf_addr_b0.addr_auto_incr_0" => { type => "field", addr => 0x10bf0, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0, athPortalAttr => "sm_table_map.autoIncr" }, "BB_tables_intf_addr_b0.tables_addr_0" => { type => "field", addr => 0x10bf0, width => 16, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0, athPortalAttr => "sm_table_map.addr" }, "BB_tables_intf_data_b0" => { type => "reg", addr => 0x10bf4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tables_intf_data_b0.tables_data_0" => { type => "field", addr => 0x10bf4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0, athPortalAttr => "sm_table_map.data" }, "BB_watchdog_status_C" => { type => "reg", addr => 0x10bf8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_watchdog_status_C.watchdog_status_C_tlv_error" => { type => "field", addr => 0x10bf8, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_C.watchdog_status_C_tlv_terminate" => { type => "field", addr => 0x10bf8, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_C.watchdog_status_C_tlv_abort" => { type => "field", addr => 0x10bf8, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_C.watchdog_status_C_tx_underrun" => { type => "field", addr => 0x10bf8, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_C.watchdog_status_C_tlv_count_user2" => { type => "field", addr => 0x10bf8, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_C.watchdog_status_C_tlv_count_user1" => { type => "field", addr => 0x10bf8, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_C.watchdog_status_C_tlv_count_user0" => { type => "field", addr => 0x10bf8, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_C.watchdog_status_C_current_user" => { type => "field", addr => 0x10bf8, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_C.watchdog_status_C_fill_level" => { type => "field", addr => 0x10bf8, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_C.watchdog_status_C_current_tag" => { type => "field", addr => 0x10bf8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_D" => { type => "reg", addr => 0x10bfc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_watchdog_status_D.watchdog_status_D_reserved" => { type => "field", addr => 0x10bfc, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_D.watchdog_status_D_vector_transfer_active" => { type => "field", addr => 0x10bfc, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_D.watchdog_status_D_vit_tlv_counter" => { type => "field", addr => 0x10bfc, width => 4, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_D.watchdog_status_D_pilot_tlv_counter" => { type => "field", addr => 0x10bfc, width => 4, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_D.watchdog_status_D_mpi_tlv_state" => { type => "field", addr => 0x10bfc, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_D.watchdog_status_D_mpi_tlv_start" => { type => "field", addr => 0x10bfc, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_D.watchdog_status_D_svd_tlv_counter" => { type => "field", addr => 0x10bfc, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_D.watchdog_status_D_agc_tlv_counter" => { type => "field", addr => 0x10bfc, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_D.watchdog_status_D_arbiter_state" => { type => "field", addr => 0x10bfc, width => 3, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_watchdog_status_D.watchdog_status_D_arbiter_req_register" => { type => "field", addr => 0x10bfc, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, ################################################################### ## bb_reg_map.bb_rxb_reg_map Register/Field definitions ################################################################### "BB_rxb_rx_reset" => { type => "reg", addr => 0x10c00, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rxb_rx_reset.rbapb_rbctl_reset" => { type => "field", addr => 0x10c00, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_rxb_rx_config_1" => { type => "reg", addr => 0x10c04, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rxb_rx_config_1.rbapb_rbbrk_te_th" => { type => "field", addr => 0x10c04, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 2 }, "BB_rxb_rx_config_1.rbapb_rbrsm_use_feedback" => { type => "field", addr => 0x10c04, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RO", resetVal => 1 }, "BB_rxb_rx_config_1.rbapb_rblms_mu_sh" => { type => "field", addr => 0x10c04, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 3 }, "BB_rxb_rx_config_1.rbapb_rbcmf_pll_coeff_b" => { type => "field", addr => 0x10c04, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 295 }, "BB_rxb_rx_config_1.rbapb_rbcmf_pll_coeff_a" => { type => "field", addr => 0x10c04, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 734 }, "BB_rxb_rx_config_2" => { type => "reg", addr => 0x10c08, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rxb_rx_config_2.agc_rbctl_d_agc_b" => { type => "field", addr => 0x10c08, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 16 }, "BB_rxb_rx_config_2.rbapb_rbctl_sfd_det_tmo" => { type => "field", addr => 0x10c08, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 125 }, "BB_rxb_rx_disables" => { type => "reg", addr => 0x10c0c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rxb_rx_disables.rbapb_rbdscr_disable_ssfd_detect" => { type => "field", addr => 0x10c0c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxb_rx_disables.rbapb_rbdscr_bypass_dsc" => { type => "field", addr => 0x10c0c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxb_rx_disables.rbapb_rbhpc_ign_sig" => { type => "field", addr => 0x10c0c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_rxb_rx_disables.rbapb_rbhpc_ign_svc" => { type => "field", addr => 0x10c0c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxb_rx_disables.rbapb_rbhpc_ign_crc" => { type => "field", addr => 0x10c0c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxb_rx_disables.rbapb_rbhpc_svc_mask" => { type => "field", addr => 0x10c0c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 251 }, "BB_rxb_rx_diversity_mode" => { type => "reg", addr => 0x10c10, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rxb_rx_diversity_mode.rbapb_rbcck_handoff_averager_gain" => { type => "field", addr => 0x10c10, width => 2, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 2 }, "BB_rxb_rx_diversity_mode.rbapb_rbbrk_handoff_averager_gain" => { type => "field", addr => 0x10c10, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 2 }, "BB_rxb_rx_diversity_mode.rbapb_rbbrk_antsel_averager_gain" => { type => "field", addr => 0x10c10, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxb_rx_diversity_mode.rbapb_rbctl_ant_sel_mode" => { type => "field", addr => 0x10c10, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxb_rx_diversity_mode.rbapb_rbctl_snr_threshold" => { type => "field", addr => 0x10c10, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 25 }, "BB_rxb_rx_ssfd_lsfd" => { type => "reg", addr => 0x10c14, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_rxb_rx_ssfd_lsfd.rbdscr_rbapb_ssfd_count" => { type => "field", addr => 0x10c14, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_rx_ssfd_lsfd.rbdscr_rbapb_lsfd_count" => { type => "field", addr => 0x10c14, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_rx_sig_svc_errors" => { type => "reg", addr => 0x10c18, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_rxb_rx_sig_svc_errors.rbhpc_rbapb_svc_errors_count" => { type => "field", addr => 0x10c18, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_rx_sig_svc_errors.rbhpc_rbapb_sig_errors_count" => { type => "field", addr => 0x10c18, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_rx_crc_errors" => { type => "reg", addr => 0x10c1c, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_rxb_rx_crc_errors.rbhpc_rbapb_crc_errors_count" => { type => "field", addr => 0x10c1c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_rx_bytes" => { type => "reg", addr => 0x10c20, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_rxb_rx_bytes.rbhpc_rbapb_rx_rate_1M" => { type => "field", addr => 0x10c20, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_rx_bytes.rbhpc_rbapb_rx_rate_2M" => { type => "field", addr => 0x10c20, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_rx_bytes.rbhpc_rbapb_rx_rate_5p5M" => { type => "field", addr => 0x10c20, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_rx_bytes.rbhpc_rbapb_rx_rate_11M" => { type => "field", addr => 0x10c20, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_rx_bytes.rbhpc_rbapb_rx_bytes_count" => { type => "field", addr => 0x10c20, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_mpi_sof_eof" => { type => "reg", addr => 0x10c24, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_rxb_mpi_sof_eof.rbhpc_rbapb_pmi_eof_count" => { type => "field", addr => 0x10c24, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_mpi_sof_eof.rbhpc_rbapb_pmi_sof_count" => { type => "field", addr => 0x10c24, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_start_abort" => { type => "reg", addr => 0x10c28, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_rxb_start_abort.rbctl_rbapb_rxb_abort_count" => { type => "field", addr => 0x10c28, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_start_abort.rbctl_rbapb_rxb_start_count" => { type => "field", addr => 0x10c28, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_dynsel_ant0_ant1" => { type => "reg", addr => 0x10c2c, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_rxb_dynsel_ant0_ant1.rbctl_rbapb_ant1_cnt" => { type => "field", addr => 0x10c2c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_dynsel_ant0_ant1.rbctl_rbapb_ant0_cnt" => { type => "field", addr => 0x10c2c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_dynsel_ant2_ant3" => { type => "reg", addr => 0x10c30, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_rxb_dynsel_ant2_ant3.rbctl_rbapb_ant3_cnt" => { type => "field", addr => 0x10c30, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_dynsel_ant2_ant3.rbctl_rbapb_ant2_cnt" => { type => "field", addr => 0x10c30, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_rxb_dynsel_all_ant" => { type => "reg", addr => 0x10c34, width => 32, athEmulAttr => 0, acc => "RCLR" }, "BB_rxb_dynsel_all_ant.rbctl_rbapb_allant_cnt" => { type => "field", addr => 0x10c34, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_force_clken_cck" => { type => "reg", addr => 0x10c38, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_force_clken_cck.force_txsm_clken" => { type => "field", addr => 0x10c38, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_force_clken_cck.force_rx_always" => { type => "field", addr => 0x10c38, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_force_clken_cck.force_rx_enable3" => { type => "field", addr => 0x10c38, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_force_clken_cck.force_rx_enable2" => { type => "field", addr => 0x10c38, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_force_clken_cck.force_rx_enable1" => { type => "field", addr => 0x10c38, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_force_clken_cck.force_rx_enable0" => { type => "field", addr => 0x10c38, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_rxb_spare_01" => { type => "reg", addr => 0x10c3c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rxb_spare_01.rxb_eco_ctrl" => { type => "field", addr => 0x10c3c, width => 26, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, ################################################################### ## bb_reg_map.bb_agc1_reg_map Register/Field definitions ################################################################### "BB_gain_force_max_gains_b1" => { type => "reg", addr => 0x11004, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_gain_force_max_gains_b1.xatten2_hyst_margin_1" => { type => "field", addr => 0x11004, width => 7, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b1.xatten1_hyst_margin_1" => { type => "field", addr => 0x11004, width => 7, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b1.xatten2_sw_f_1" => { type => "field", addr => 0x11004, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b1.xatten1_sw_f_1" => { type => "field", addr => 0x11004, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b1.mb_gain_f_1" => { type => "field", addr => 0x11004, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_force_max_gains_b1.rf_gain_f_1" => { type => "field", addr => 0x11004, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_atten_switch_ctl_b1" => { type => "reg", addr => 0x11018, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ext_atten_switch_ctl_b1.xlna_gain_db_1" => { type => "field", addr => 0x11018, width => 5, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_atten_switch_ctl_b1.xatten2_margin_1" => { type => "field", addr => 0x11018, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_atten_switch_ctl_b1.xatten1_margin_1" => { type => "field", addr => 0x11018, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 50 }, "BB_ext_atten_switch_ctl_b1.xatten2_db_1" => { type => "field", addr => 0x11018, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ext_atten_switch_ctl_b1.xatten1_db_1" => { type => "field", addr => 0x11018, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cca_b1" => { type => "reg", addr => 0x1101c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cca_b1.minCCApwr_1" => { type => "field", addr => 0x1101c, width => 9, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cca_b1.cf_maxCCApwr_1" => { type => "field", addr => 0x1101c, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cca_ctrl_2_b1" => { type => "reg", addr => 0x11020, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cca_ctrl_2_b1.NF_gain_comp_1" => { type => "field", addr => 0x11020, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cca_ctrl_2_b1.minCCApwr_thr_1" => { type => "field", addr => 0x11020, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cca_ext80_b1" => { type => "reg", addr => 0x11024, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cca_ext80_b1.minCCApwr_ext80_1" => { type => "field", addr => 0x11024, width => 9, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_cca_ext80_b1.cf_maxCCApwr_ext80_1" => { type => "field", addr => 0x11024, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rssi_b1" => { type => "reg", addr => 0x11180, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rssi_b1.rssi_ext80_1" => { type => "field", addr => 0x11180, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rssi_b1.rssi_ext40_1" => { type => "field", addr => 0x11180, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rssi_b1.rssi_ext20_1" => { type => "field", addr => 0x11180, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rssi_b1.rssi_pri20_1" => { type => "field", addr => 0x11180, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_agc_dig_dc_status_b1" => { type => "reg", addr => 0x11188, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_agc_dig_dc_status_b1.dc_cal_residual_dc_q_1" => { type => "field", addr => 0x11188, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_agc_dig_dc_status_b1.dc_cal_residual_dc_i_1" => { type => "field", addr => 0x11188, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dc_cal_status_b1" => { type => "reg", addr => 0x111a0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_dc_cal_status_b1.offsetC2Q_1" => { type => "field", addr => 0x111a0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_b1.offsetC2I_1" => { type => "field", addr => 0x111a0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_b1.offsetC1Q_1" => { type => "field", addr => 0x111a0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_b1.offsetC1I_1" => { type => "field", addr => 0x111a0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_2_b1" => { type => "reg", addr => 0x111a4, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_dc_cal_status_2_b1.offsetC4Q_1" => { type => "field", addr => 0x111a4, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_2_b1.offsetC4I_1" => { type => "field", addr => 0x111a4, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_2_b1.offsetC3Q_1" => { type => "field", addr => 0x111a4, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_2_b1.offsetC3I_1" => { type => "field", addr => 0x111a4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_dc_cal_status_3_b1" => { type => "reg", addr => 0x111a8, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_dc_cal_status_3_b1.offsetC6Q_1" => { type => "field", addr => 0x111a8, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_dc_cal_status_3_b1.offsetC6I_1" => { type => "field", addr => 0x111a8, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_dc_cal_status_3_b1.offsetC5Q_1" => { type => "field", addr => 0x111a8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_dc_cal_status_3_b1.offsetC5I_1" => { type => "field", addr => 0x111a8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_dc_cal_status_4_b1" => { type => "reg", addr => 0x111ac, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_dc_cal_status_4_b1.offsetC7Q_1" => { type => "field", addr => 0x111ac, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_dc_cal_status_4_b1.offsetC7I_1" => { type => "field", addr => 0x111ac, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rx_gain_nf_b1" => { type => "reg", addr => 0x111b0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rx_gain_nf_b1.gain_val_after_nf_1" => { type => "field", addr => 0x111b0, width => 17, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rx_ocgain2" => { type => "reg", addr => 0x11200, width => 32, athEmulAttr => 0, acc => "RW", depth => 128, incr => 4 }, "BB_rx_ocgain2.gain_entry2" => { type => "field", addr => 0x11200, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, ################################################################### ## bb_reg_map.bb_chn1_reg_map Register/Field definitions ################################################################### "BB_rx_notch_cntl_2_pri_b1" => { type => "reg", addr => 0x11458, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_2_pri_b1.notch_corr_spur1_q_pri_b1" => { type => "field", addr => 0x11458, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_2_pri_b1.notch_corr_spur1_i_pri_b1" => { type => "field", addr => 0x11458, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_3_pri_b1" => { type => "reg", addr => 0x1145c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_3_pri_b1.notch_corr_spur2_q_pri_b1" => { type => "field", addr => 0x1145c, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_3_pri_b1.notch_corr_spur2_i_pri_b1" => { type => "field", addr => 0x1145c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_4_pri_b1" => { type => "reg", addr => 0x11460, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_4_pri_b1.notch_corr_dc_q_pri_b1" => { type => "field", addr => 0x11460, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_4_pri_b1.notch_corr_dc_i_pri_b1" => { type => "field", addr => 0x11460, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_5_pri_b1" => { type => "reg", addr => 0x11464, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_5_pri_b1.notch_corr_agg_i_pri_b1" => { type => "field", addr => 0x11464, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_2_ext_b1" => { type => "reg", addr => 0x11468, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_2_ext_b1.notch_corr_spur1_q_ext_b1" => { type => "field", addr => 0x11468, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_2_ext_b1.notch_corr_spur1_i_ext_b1" => { type => "field", addr => 0x11468, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_3_ext_b1" => { type => "reg", addr => 0x1146c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_3_ext_b1.notch_corr_spur2_q_ext_b1" => { type => "field", addr => 0x1146c, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_3_ext_b1.notch_corr_spur2_i_ext_b1" => { type => "field", addr => 0x1146c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_4_ext_b1" => { type => "reg", addr => 0x11470, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_4_ext_b1.notch_corr_dc_q_ext_b1" => { type => "field", addr => 0x11470, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rx_notch_cntl_4_ext_b1.notch_corr_dc_i_ext_b1" => { type => "field", addr => 0x11470, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_rx_notch_cntl_5_ext_b1" => { type => "reg", addr => 0x11474, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_notch_cntl_5_ext_b1.notch_corr_agg_i_ext_b1" => { type => "field", addr => 0x11474, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x400 }, "BB_pre_emphasis_bw20_b1" => { type => "reg", addr => 0x11488, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pre_emphasis_bw20_b1.pre_emp_db_neg_bw20_1" => { type => "field", addr => 0x11488, width => 15, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pre_emphasis_bw20_b1.pre_emp_db_pos_bw20_1" => { type => "field", addr => 0x11488, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pre_emphasis_bw40_b1" => { type => "reg", addr => 0x1148c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pre_emphasis_bw40_b1.pre_emp_db_neg_bw40_1" => { type => "field", addr => 0x1148c, width => 15, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pre_emphasis_bw40_b1.pre_emp_db_pos_bw40_1" => { type => "field", addr => 0x1148c, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pre_emphasis_bw80_b1" => { type => "reg", addr => 0x11490, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pre_emphasis_bw80_b1.pre_emp_db_neg_bw80_1" => { type => "field", addr => 0x11490, width => 15, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pre_emphasis_bw80_b1.pre_emp_db_pos_bw80_1" => { type => "field", addr => 0x11490, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chn1_tables_intf_addr" => { type => "reg", addr => 0x11494, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chn1_tables_intf_addr.chn1_addr_auto_incr" => { type => "field", addr => 0x11494, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0, athPortalAttr => "chn1_table_map.autoIncr" }, "BB_chn1_tables_intf_addr.chn1_tables_addr" => { type => "field", addr => 0x11494, width => 16, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0, athPortalAttr => "chn1_table_map.addr" }, "BB_chn1_tables_intf_data" => { type => "reg", addr => 0x11498, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chn1_tables_intf_data.chn1_tables_data" => { type => "field", addr => 0x11498, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0, athPortalAttr => "chn1_table_map.data" }, "BB_spur_report_b1" => { type => "reg", addr => 0x114a8, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_spur_report_b1.power_with_spur_removed_1" => { type => "field", addr => 0x114a8, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_spur_report_b1.spur_est_q_1" => { type => "field", addr => 0x114a8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_spur_report_b1.spur_est_i_1" => { type => "field", addr => 0x114a8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_iq_adc_meas_0_b1" => { type => "reg", addr => 0x114c0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_iq_adc_meas_0_b1.gain_dc_iq_cal_meas_0_1" => { type => "field", addr => 0x114c0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_iq_adc_meas_1_b1" => { type => "reg", addr => 0x114c4, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_iq_adc_meas_1_b1.gain_dc_iq_cal_meas_1_1" => { type => "field", addr => 0x114c4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_iq_adc_meas_2_b1" => { type => "reg", addr => 0x114c8, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_iq_adc_meas_2_b1.gain_dc_iq_cal_meas_2_1" => { type => "field", addr => 0x114c8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_iq_adc_meas_3_b1" => { type => "reg", addr => 0x114cc, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_iq_adc_meas_3_b1.gain_dc_iq_cal_meas_3_1" => { type => "field", addr => 0x114cc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tx_phase_ramp_b1" => { type => "reg", addr => 0x114d0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_phase_ramp_b1.cf_phase_ramp_alpha_1" => { type => "field", addr => 0x114d0, width => 8, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_phase_ramp_b1.cf_phase_ramp_init_1" => { type => "field", addr => 0x114d0, width => 10, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_phase_ramp_b1.cf_phase_ramp_bias_1" => { type => "field", addr => 0x114d0, width => 6, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_phase_ramp_b1.cf_phase_ramp_enable_1" => { type => "field", addr => 0x114d0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_adc_gain_corr_b1" => { type => "reg", addr => 0x114d4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_adc_gain_corr_b1.adc_gain_corr_i_coeff_1" => { type => "field", addr => 0x114d4, width => 9, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 32 }, "BB_adc_gain_corr_b1.adc_gain_corr_q_coeff_1" => { type => "field", addr => 0x114d4, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 32 }, "BB_adc_dc_corr_b1" => { type => "reg", addr => 0x114d8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_adc_dc_corr_b1.adc_dc_corr_i_coeff_1" => { type => "field", addr => 0x114d8, width => 9, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_adc_dc_corr_b1.adc_dc_corr_q_coeff_1" => { type => "field", addr => 0x114d8, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rx_iq_corr_loopback_b1" => { type => "reg", addr => 0x114e0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rx_iq_corr_loopback_b1.loopback_iqcorr_q_i_coff_1" => { type => "field", addr => 0x114e0, width => 9, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rx_iq_corr_loopback_b1.loopback_iqcorr_q_q_coff_1" => { type => "field", addr => 0x114e0, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl0_b1" => { type => "reg", addr => 0x114f0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_ctrl0_b1.paprd_valid_gain_5_0_1" => { type => "field", addr => 0x114f0, width => 30, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl0_b1.paprd_sw_sel_ext80_tables_1" => { type => "field", addr => 0x114f0, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_ctrl0_b1.paprd_enable_1" => { type => "field", addr => 0x114f0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_ctrl1_b1" => { type => "reg", addr => 0x114f4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_ctrl1_b1.paprd_trainer_iandq_sel_1" => { type => "field", addr => 0x114f4, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_ctrl1_b1.paprd_target_pwr_min_1" => { type => "field", addr => 0x114f4, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl1_b1.paprd_target_pwr_max_1" => { type => "field", addr => 0x114f4, width => 6, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl1_b1.paprd_adaptive_am2pm_enable_1" => { type => "field", addr => 0x114f4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_ctrl1_b1.paprd_adaptive_am2am_enable_1" => { type => "field", addr => 0x114f4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_ctrl2_b1" => { type => "reg", addr => 0x114f8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_ctrl2_b1.paprd_mag_thrsh_1" => { type => "field", addr => 0x114f8, width => 5, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl2_b1.paprd_table_rfbmode_1" => { type => "field", addr => 0x114f8, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl2_b1.paprd_adaptive_table_valid_1" => { type => "field", addr => 0x114f8, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl2_b1.paprd_valid_pa_setting_1" => { type => "field", addr => 0x114f8, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl0_sec80_b1" => { type => "reg", addr => 0x114fc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_ctrl0_sec80_b1.paprd_valid_gain_2_0_sec80_1" => { type => "field", addr => 0x114fc, width => 15, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl0_sec80_b1.paprd_enable_sec80_1" => { type => "field", addr => 0x114fc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_ctrl2_sec80_b1" => { type => "reg", addr => 0x11500, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_ctrl2_sec80_b1.paprd_adaptive_table_valid_sec80_1" => { type => "field", addr => 0x11500, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_ctrl2_sec80_b1.paprd_valid_pa_setting_sec80_1" => { type => "field", addr => 0x11500, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fdtg_ss0_data_b1" => { type => "reg", addr => 0x11550, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_ss0_data_b1.fdtg_ss0_b_data_im_1" => { type => "field", addr => 0x11550, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss0_data_b1.fdtg_ss0_b_data_re_1" => { type => "field", addr => 0x11550, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss0_data_b1.fdtg_ss0_a_data_im_1" => { type => "field", addr => 0x11550, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss0_data_b1.fdtg_ss0_a_data_re_1" => { type => "field", addr => 0x11550, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss1_data_b1" => { type => "reg", addr => 0x11554, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_ss1_data_b1.fdtg_ss1_b_data_im_1" => { type => "field", addr => 0x11554, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss1_data_b1.fdtg_ss1_b_data_re_1" => { type => "field", addr => 0x11554, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss1_data_b1.fdtg_ss1_a_data_im_1" => { type => "field", addr => 0x11554, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss1_data_b1.fdtg_ss1_a_data_re_1" => { type => "field", addr => 0x11554, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss2_data_b1" => { type => "reg", addr => 0x11558, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_ss2_data_b1.fdtg_ss2_b_data_im_1" => { type => "field", addr => 0x11558, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss2_data_b1.fdtg_ss2_b_data_re_1" => { type => "field", addr => 0x11558, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss2_data_b1.fdtg_ss2_a_data_im_1" => { type => "field", addr => 0x11558, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss2_data_b1.fdtg_ss2_a_data_re_1" => { type => "field", addr => 0x11558, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_spur_ctrl1_pri_b1" => { type => "reg", addr => 0x1156c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spur_ctrl1_pri_b1.enable_spur_filter_pri_b1" => { type => "field", addr => 0x1156c, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl1_pri_b1.agc_ht_stf_spur_filter_ena_pri_b1" => { type => "field", addr => 0x1156c, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_spur_ctrl1_pri_b1.spur_delta_phase_pri_b1" => { type => "field", addr => 0x1156c, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl2_pri_b1" => { type => "reg", addr => 0x11570, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spur_ctrl2_pri_b1.spur_delta_phase_2nd_pri_b1" => { type => "field", addr => 0x11570, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl1_ext_b1" => { type => "reg", addr => 0x11574, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spur_ctrl1_ext_b1.enable_spur_filter_ext_b1" => { type => "field", addr => 0x11574, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl1_ext_b1.agc_ht_stf_spur_filter_ena_ext_b1" => { type => "field", addr => 0x11574, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_spur_ctrl1_ext_b1.spur_delta_phase_ext_b1" => { type => "field", addr => 0x11574, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_spur_ctrl2_ext_b1" => { type => "reg", addr => 0x11578, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_spur_ctrl2_ext_b1.spur_delta_phase_2nd_ext_b1" => { type => "field", addr => 0x11578, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fdtg_ss3_data_b1" => { type => "reg", addr => 0x1157c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fdtg_ss3_data_b1.fdtg_ss3_b_data_im_1" => { type => "field", addr => 0x1157c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss3_data_b1.fdtg_ss3_b_data_re_1" => { type => "field", addr => 0x1157c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss3_data_b1.fdtg_ss3_a_data_im_1" => { type => "field", addr => 0x1157c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_fdtg_ss3_data_b1.fdtg_ss3_a_data_re_1" => { type => "field", addr => 0x1157c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pdc_a1_1_m0" => { type => "reg", addr => 0x11584, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_a1_1_m0.pdc_a1_1_m0" => { type => "field", addr => 0x11584, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b1_1_m0" => { type => "reg", addr => 0x11588, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b1_1_m0.pdc_b1_1_m0" => { type => "field", addr => 0x11588, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b2_1_m0" => { type => "reg", addr => 0x1158c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b2_1_m0.pdc_b2_1_m0" => { type => "field", addr => 0x1158c, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_a1_1_m1" => { type => "reg", addr => 0x11590, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_a1_1_m1.pdc_a1_1_m1" => { type => "field", addr => 0x11590, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b1_1_m1" => { type => "reg", addr => 0x11594, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b1_1_m1.pdc_b1_1_m1" => { type => "field", addr => 0x11594, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b2_1_m1" => { type => "reg", addr => 0x11598, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b2_1_m1.pdc_b2_1_m1" => { type => "field", addr => 0x11598, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_a1_1_m2" => { type => "reg", addr => 0x1159c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_a1_1_m2.pdc_a1_1_m2" => { type => "field", addr => 0x1159c, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b1_1_m2" => { type => "reg", addr => 0x115a0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b1_1_m2.pdc_b1_1_m2" => { type => "field", addr => 0x115a0, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_b2_1_m2" => { type => "reg", addr => 0x115a4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_b2_1_m2.pdc_b2_1_m2" => { type => "field", addr => 0x115a4, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "BB_pdc_step_p1_1" => { type => "reg", addr => 0x115a8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_step_p1_1.pdc_step_p1_1" => { type => "field", addr => 0x115a8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pdc_step_p2_1" => { type => "reg", addr => 0x115ac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pdc_step_p2_1.pdc_step_p2_1" => { type => "field", addr => 0x115ac, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pdc_gap_time_1" => { type => "reg", addr => 0x115b0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_pdc_gap_time_1.pdc_gap_time_1" => { type => "field", addr => 0x115b0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_pdc_time_1" => { type => "reg", addr => 0x115b4, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_pdc_time_1.pdc_time_1" => { type => "field", addr => 0x115b4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, ################################################################### ## bb_reg_map.bb_sm1_reg_map Register/Field definitions ################################################################### "BB_switch_table_chn_b1" => { type => "reg", addr => 0x11684, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_switch_table_chn_b1.switch_table_b_1" => { type => "field", addr => 0x11684, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_chn_b1.switch_table_rx12_1" => { type => "field", addr => 0x11684, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_chn_b1.switch_table_rx1_1" => { type => "field", addr => 0x11684, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_chn_b1.switch_table_r_1" => { type => "field", addr => 0x11684, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_chn_b1.switch_table_t_1" => { type => "field", addr => 0x11684, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_switch_table_chn_b1.switch_table_idle_1" => { type => "field", addr => 0x11684, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_fcal_2_b1" => { type => "reg", addr => 0x116d0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_fcal_2_b1.flc_cap_val_status_1" => { type => "field", addr => 0x116d0, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_fcal_2_b1.flc_sw_cap_val_1" => { type => "field", addr => 0x116d0, width => 5, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 15 }, "BB_dft_tone_ctrl_b1" => { type => "reg", addr => 0x116d4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_dft_tone_ctrl_b1.dft_tone_freq_ang_1" => { type => "field", addr => 0x116d4, width => 9, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_dft_tone_ctrl_b1.dft_tone_amp_sel_1" => { type => "field", addr => 0x116d4, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_dft_tone_ctrl_b1.dft_tone_en_1" => { type => "field", addr => 0x116d4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_cl_map_0_b1" => { type => "reg", addr => 0x116dc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cl_map_0_b1.cl_map_0" => { type => "field", addr => 0x116dc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_map_1_b1" => { type => "reg", addr => 0x116e0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cl_map_1_b1.cl_map_1" => { type => "field", addr => 0x116e0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_map_2_b1" => { type => "reg", addr => 0x116e4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cl_map_2_b1.cl_map_2" => { type => "field", addr => 0x116e4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_map_3_b1" => { type => "reg", addr => 0x116e8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cl_map_3_b1.cl_map_3" => { type => "field", addr => 0x116e8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_tab_b1" => { type => "reg", addr => 0x11700, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "BB_cl_tab_b1.bb_gain" => { type => "field", addr => 0x11700, width => 4, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_tab_b1.carr_lk_dc_add_I" => { type => "field", addr => 0x11700, width => 11, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_tab_b1.carr_lk_dc_add_Q" => { type => "field", addr => 0x11700, width => 11, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cl_tab_b1.cl_gain_mod" => { type => "field", addr => 0x11700, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_info_noise_pwr_b1" => { type => "reg", addr => 0x11774, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_chan_info_noise_pwr_b1.chan_info_fine_dc_q_1" => { type => "field", addr => 0x11774, width => 8, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_noise_pwr_b1.chan_info_fine_dc_i_1" => { type => "field", addr => 0x11774, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_b1" => { type => "reg", addr => 0x11780, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_chan_info_gain_b1.chan_info_xatten2_sw_1" => { type => "field", addr => 0x11780, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_b1.chan_info_xatten1_sw_1" => { type => "field", addr => 0x11780, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_b1.chan_info_mb_gain_1" => { type => "field", addr => 0x11780, width => 7, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_b1.chan_info_rf_gain_1" => { type => "field", addr => 0x11780, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_chan_info_gain_b1.chan_info_rssi_1" => { type => "field", addr => 0x11780, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_nf_dcoff_b1" => { type => "reg", addr => 0x11788, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_nf_dcoff_b1.dc_off_q_1" => { type => "field", addr => 0x11788, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_nf_dcoff_b1.dc_off_i_1" => { type => "field", addr => 0x11788, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_4_b1" => { type => "reg", addr => 0x11804, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tpc_4_b1.pdadc_clip_2_cnt_1" => { type => "field", addr => 0x11804, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_4_b1.pdadc_clip_1_cnt_1" => { type => "field", addr => 0x11804, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_11_b1" => { type => "reg", addr => 0x11820, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_11_b1.forced_pa_cfg_1" => { type => "field", addr => 0x11820, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_11_b1.forced_dac_gain_1" => { type => "field", addr => 0x11820, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_11_b1.forced_txgain_idx_1" => { type => "field", addr => 0x11820, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_11_b1.olpc_gain_delta_1_lsb_ext" => { type => "field", addr => 0x11820, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_11_b1.olpc_gain_delta_1" => { type => "field", addr => 0x11820, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_12_b1" => { type => "reg", addr => 0x11824, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_12_b1.pdadc_bias_1" => { type => "field", addr => 0x11824, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tpc_19_b1" => { type => "reg", addr => 0x11840, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tpc_19_b1.bt_clpc_err_updt_1" => { type => "field", addr => 0x11840, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_19_b1.alpha_volt_1" => { type => "field", addr => 0x11840, width => 7, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_19_b1.alpha_therm_1" => { type => "field", addr => 0x11840, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_19_b1.volt_cal_value_1" => { type => "field", addr => 0x11840, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_19_b1.therm_cal_value_1" => { type => "field", addr => 0x11840, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_therm_adc_1_b1" => { type => "reg", addr => 0x11848, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_therm_adc_1_b1.init_atb_setting_1" => { type => "field", addr => 0x11848, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_therm_adc_1_b1.init_volt_setting_1" => { type => "field", addr => 0x11848, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_therm_adc_1_b1.init_therm_setting_1" => { type => "field", addr => 0x11848, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_therm_adc_3_b1" => { type => "reg", addr => 0x11850, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_therm_adc_3_b1.therm_adc_scaled_gain_1" => { type => "field", addr => 0x11850, width => 9, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 256 }, "BB_therm_adc_3_b1.therm_adc_offset_1" => { type => "field", addr => 0x11850, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_therm_adc_4_b1" => { type => "reg", addr => 0x11854, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_therm_adc_4_b1.latest_atb_value_1" => { type => "field", addr => 0x11854, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_therm_adc_4_b1.latest_volt_value_1" => { type => "field", addr => 0x11854, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_therm_adc_4_b1.latest_therm_value_1" => { type => "field", addr => 0x11854, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_0_b1" => { type => "reg", addr => 0x1185c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tpc_stat_0_b1.latest_dc_value_1" => { type => "field", addr => 0x1185c, width => 9, bitOffset => 17, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_0_b1.pdacc_avg_out_1" => { type => "field", addr => 0x1185c, width => 8, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_0_b1.meas_pwr_out_1" => { type => "field", addr => 0x1185c, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_1_b1" => { type => "reg", addr => 0x11860, width => 32, athEmulAttr => 0, acc => "RCLRW" }, "BB_tpc_stat_1_b1.gain_miss_mid_1" => { type => "field", addr => 0x11860, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RCLRW", resetVal => 0x0 }, "BB_tpc_stat_1_b1.gain_miss_high_1" => { type => "field", addr => 0x11860, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RCLRW", resetVal => 0x0 }, "BB_tpc_stat_1_b1.gain_miss_low_1" => { type => "field", addr => 0x11860, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RCLRW", resetVal => 0x0 }, "BB_tpc_stat_2_b1" => { type => "reg", addr => 0x11864, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tpc_stat_2_b1.ana_set_ndp_1" => { type => "field", addr => 0x11864, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_2_b1.clpc_err_mu_1" => { type => "field", addr => 0x11864, width => 10, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_2_b1.dac_gain_ndp_1" => { type => "field", addr => 0x11864, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tpc_stat_3_b1" => { type => "reg", addr => 0x11874, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tpc_stat_3_b1.latest_glut_set_1" => { type => "field", addr => 0x11874, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_tpc_stat_3_b1.latest_clpc_err_1" => { type => "field", addr => 0x11874, width => 10, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_tpc_stat_3_b1.latest_dac_gain_1" => { type => "field", addr => 0x11874, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_rrt_table_sw_intf_b1" => { type => "reg", addr => 0x11984, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rrt_table_sw_intf_b1.sw_rrt_table_addr_offset_1" => { type => "field", addr => 0x11984, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_table_sw_intf_b1.sw_rrt_table_addr_1" => { type => "field", addr => 0x11984, width => 3, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_table_sw_intf_b1.sw_rrt_table_write_1" => { type => "field", addr => 0x11984, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_table_sw_intf_b1.sw_rrt_table_access_1" => { type => "field", addr => 0x11984, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_rrt_table_sw_intf_1_b1" => { type => "reg", addr => 0x11988, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rrt_table_sw_intf_1_b1.sw_rrt_table_data_1" => { type => "field", addr => 0x11988, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_txiqcal_status_b1" => { type => "reg", addr => 0x11a8c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_txiqcal_status_b1.last_meas_addr_1" => { type => "field", addr => 0x11a8c, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_txiqcal_status_b1.rx_gain_used_1" => { type => "field", addr => 0x11a8c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_txiqcal_status_b1.tone_gain_used_1" => { type => "field", addr => 0x11a8c, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_txiqcal_status_b1.calibrated_gains_1" => { type => "field", addr => 0x11a8c, width => 5, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_txiqcal_status_b1.txiqcal_failed_1" => { type => "field", addr => 0x11a8c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxiqcal_status_b1" => { type => "reg", addr => 0x11aac, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_rxiqcal_status_b1.rxiqcal_last_meas_addr_1" => { type => "field", addr => 0x11aac, width => 6, bitOffset => 11, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxiqcal_status_b1.rxiqcal_txgain_idx_used_1" => { type => "field", addr => 0x11aac, width => 5, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxiqcal_status_b1.rxiqcal_calibrated_gains_1" => { type => "field", addr => 0x11aac, width => 5, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_rxiqcal_status_b1.rxiqcal_failed_1" => { type => "field", addr => 0x11aac, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tables_intf_addr_b1" => { type => "reg", addr => 0x11bf0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tables_intf_addr_b1.addr_auto_incr_1" => { type => "field", addr => 0x11bf0, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0, athPortalAttr => "sm1_table_map.autoIncr" }, "BB_tables_intf_addr_b1.tables_addr_1" => { type => "field", addr => 0x11bf0, width => 16, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0, athPortalAttr => "sm1_table_map.addr" }, "BB_tables_intf_data_b1" => { type => "reg", addr => 0x11bf4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tables_intf_data_b1.tables_data_1" => { type => "field", addr => 0x11bf4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0, athPortalAttr => "sm1_table_map.data" }, ################################################################### ## bb_reg_map.bb_agc4_reg_map Register/Field definitions ################################################################### "BB_dummy_agc_bcast" => { type => "reg", addr => 0x14000, width => 32, athEmulAttr => 0, acc => "WO", depth => 128, incr => 4 }, "BB_dummy_agc_bcast.dummy" => { type => "field", addr => 0x14000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WO", resetVal => 0 }, ################################################################### ## bb_reg_map.bb_chn4_reg_map Register/Field definitions ################################################################### "BB_dummy_chn_bcast" => { type => "reg", addr => 0x14400, width => 32, athEmulAttr => 0, acc => "WO", depth => 64, incr => 4 }, "BB_dummy_chn_bcast.dummy" => { type => "field", addr => 0x14400, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WO", resetVal => 0 }, ################################################################### ## bb_reg_map.bb_sm4_reg_map Register/Field definitions ################################################################### "BB_dummy_sm_bcast" => { type => "reg", addr => 0x14600, width => 32, athEmulAttr => 0, acc => "WO", depth => 384, incr => 4 }, "BB_dummy_sm_bcast.dummy" => { type => "field", addr => 0x14600, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WO", resetVal => 0 }, ################################################################### ## bb_reg_map.bb_svd_reg_map Register/Field definitions ################################################################### "BB_TXBF_DBG" => { type => "reg", addr => 0x15000, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_TXBF_DBG.svd_clk_free_run" => { type => "field", addr => 0x15000, width => 12, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF_DBG.svd_txbf_ready_reg" => { type => "field", addr => 0x15000, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF_DBG.svd_reg_reset" => { type => "field", addr => 0x15000, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF_DBG.svd_upload_h" => { type => "field", addr => 0x15000, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF_DBG.upload_H_tone_offset" => { type => "field", addr => 0x15000, width => 9, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_TXBF_DBG.debug_mode" => { type => "field", addr => 0x15000, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_TXBF" => { type => "reg", addr => 0x15004, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_TXBF.expect_cbf_self_rst" => { type => "field", addr => 0x15004, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF.svd_norm_mu_max" => { type => "field", addr => 0x15004, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "BB_TXBF.svd_norm_mu_min" => { type => "field", addr => 0x15004, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_TXBF.allow_LDPC_NDP" => { type => "field", addr => 0x15004, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_TXBF.svd_half_rate_mode" => { type => "field", addr => 0x15004, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF.disable_txbf_thr" => { type => "field", addr => 0x15004, width => 5, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF.txcv_bfweight_method" => { type => "field", addr => 0x15004, width => 2, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF.fb_max_nc" => { type => "field", addr => 0x15004, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF.ng_idx_rpt_tx" => { type => "field", addr => 0x15004, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF.cb_info_tx" => { type => "field", addr => 0x15004, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "BB_txbf_premmse_ctrl" => { type => "reg", addr => 0x15008, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txbf_premmse_ctrl.txbf_no_csd" => { type => "field", addr => 0x15008, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txbf_premmse_ctrl.mu_psn_factor" => { type => "field", addr => 0x15008, width => 5, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0xa }, "BB_txbf_premmse_ctrl.mu_reg_factor" => { type => "field", addr => 0x15008, width => 5, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "BB_txbf_premmse_ctrl.txbf_V_smooth" => { type => "field", addr => 0x15008, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txbf_premmse_ctrl.premmse_noise" => { type => "field", addr => 0x15008, width => 8, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 77 }, "BB_txbf_premmse_ctrl.txbf_premmse_nss" => { type => "field", addr => 0x15008, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txbf_premmse_ctrl.txbf_premmse" => { type => "field", addr => 0x15008, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txbf_premmse_snr" => { type => "reg", addr => 0x1500c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txbf_premmse_snr.premmse_snr_c2" => { type => "field", addr => 0x1500c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 64 }, "BB_txbf_premmse_snr.premmse_snr_c1" => { type => "field", addr => 0x1500c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 168 }, "BB_txbf_premmse_snr.premmse_snr_c0" => { type => "field", addr => 0x1500c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 192 }, "BB_txbf_bfee_rx_ctrl" => { type => "reg", addr => 0x15010, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txbf_bfee_rx_ctrl.txbf_snr_bias" => { type => "field", addr => 0x15010, width => 4, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txbf_bfee_rx_ctrl.rm_hcsd4svd" => { type => "field", addr => 0x15010, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_txbf_bfee_rx_ctrl.rx_sounding_enable_reg" => { type => "field", addr => 0x15010, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_txbf_bfee_rx_ctrl.enable_send_chan" => { type => "field", addr => 0x15010, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_txbf_bfee_rx_ctrl.enable_flt_svd" => { type => "field", addr => 0x15010, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_txbf_implicit_rx_ctrl" => { type => "reg", addr => 0x15014, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txbf_implicit_rx_ctrl.apply_ibf_coef" => { type => "field", addr => 0x15014, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_txbf_implicit_rx_ctrl.txbf_implicit_legacy_only" => { type => "field", addr => 0x15014, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_txbf_implicit_rx_ctrl.implicit_fb_all_rx_pkts" => { type => "field", addr => 0x15014, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_TXBF_SM" => { type => "reg", addr => 0x15100, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_TXBF_SM.txbf_sm_obs" => { type => "field", addr => 0x15100, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_TXBF1_CNTL" => { type => "reg", addr => 0x15104, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_TXBF1_CNTL.txbf1_cntl_obs" => { type => "field", addr => 0x15104, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_TXBF2_CNTL" => { type => "reg", addr => 0x15108, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_TXBF2_CNTL.txbf2_cntl_obs" => { type => "field", addr => 0x15108, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x8000 }, "BB_TXBF3_CNTL" => { type => "reg", addr => 0x1510c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_TXBF3_CNTL.txbf3_cntl_obs" => { type => "field", addr => 0x1510c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x200033 }, "BB_TXBF4_CNTL" => { type => "reg", addr => 0x15110, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_TXBF4_CNTL.txbf4_cntl_obs" => { type => "field", addr => 0x15110, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_TXBF5_CNTL" => { type => "reg", addr => 0x15114, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_TXBF5_CNTL.txbf5_cntl_obs" => { type => "field", addr => 0x15114, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_TXBF6_CNTL" => { type => "reg", addr => 0x15118, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_TXBF6_CNTL.txbf6_cntl_obs" => { type => "field", addr => 0x15118, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_TXBF7_CNTL" => { type => "reg", addr => 0x1511c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_TXBF7_CNTL.txbf7_cntl_obs" => { type => "field", addr => 0x1511c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_TXBF8_CNTL" => { type => "reg", addr => 0x15120, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_TXBF8_CNTL.txbf8_cntl_obs" => { type => "field", addr => 0x15120, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_TXBF_DBG2" => { type => "reg", addr => 0x15124, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_TXBF_DBG2.svd_cbf_reset_timer" => { type => "field", addr => 0x15124, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF_DBG2.svd_rx_reset_timer" => { type => "field", addr => 0x15124, width => 7, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_TXBF_DBG2.svd_dbg_bus_sel" => { type => "field", addr => 0x15124, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_SVD_MEM0" => { type => "reg", addr => 0x16400, width => 32, athEmulAttr => 0, acc => "RW", depth => 242, incr => 4 }, "BB_SVD_MEM0.SVD_MEM0" => { type => "field", addr => 0x16400, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_SVD_MEM1" => { type => "reg", addr => 0x16800, width => 32, athEmulAttr => 0, acc => "RW", depth => 242, incr => 4 }, "BB_SVD_MEM1.SVD_MEM1" => { type => "field", addr => 0x16800, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_svd_spare_01" => { type => "reg", addr => 0x17000, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_svd_spare_01.svd_eco_ctrl" => { type => "field", addr => 0x17000, width => 27, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_svd_spare_01.cvmem_num_extra_writes" => { type => "field", addr => 0x17000, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, ################################################################### ## bb_reg_map.bb_mrc_reg_map Register/Field definitions ################################################################### "BB_timing_control_3a" => { type => "reg", addr => 0x18000, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_timing_control_3a.ste_to_long1_vh_rssi" => { type => "field", addr => 0x18000, width => 6, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 28 }, "BB_timing_control_3a.ste_thr_vh_rssi" => { type => "field", addr => 0x18000, width => 7, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 125 }, "BB_timing_control_3a.vh_rssi_thresh" => { type => "field", addr => 0x18000, width => 7, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 26 }, "BB_timing_control_3a.disable_fte_high_snr" => { type => "field", addr => 0x18000, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_timing_control_3a.use_non_ht_bw_for_cca" => { type => "field", addr => 0x18000, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_timing_control_3a.use_vht_bw_for_cca" => { type => "field", addr => 0x18000, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_timing_control_3a.ste_thr_hi_rssi" => { type => "field", addr => 0x18000, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ldpc_cntl1" => { type => "reg", addr => 0x18004, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ldpc_cntl1.ldpc_llr_scaling0" => { type => "field", addr => 0x18004, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x015FFD55 }, "BB_ldpc_cntl2" => { type => "reg", addr => 0x18008, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ldpc_cntl2.disable_ldpc_mem_pd" => { type => "field", addr => 0x18008, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ldpc_cntl2.enable_iter_cal" => { type => "field", addr => 0x18008, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ldpc_cntl2.disable_ldpc_dec" => { type => "field", addr => 0x18008, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ldpc_cntl2.ldpc_latency_lastcw" => { type => "field", addr => 0x18008, width => 11, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 800 }, "BB_ldpc_cntl2.ldpc_llr_scaling1" => { type => "field", addr => 0x18008, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_A" => { type => "reg", addr => 0x1800c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_vit_spur_mask_A.cf_punc_mask_A_sel" => { type => "field", addr => 0x1800c, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vit_spur_mask_A.cf_punc_mask_idx_A" => { type => "field", addr => 0x1800c, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_A.cf_punc_mask_A" => { type => "field", addr => 0x1800c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_B" => { type => "reg", addr => 0x18010, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_vit_spur_mask_B.cf_punc_mask_B_sel" => { type => "field", addr => 0x18010, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vit_spur_mask_B.cf_punc_mask_idx_B" => { type => "field", addr => 0x18010, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_B.cf_punc_mask_B" => { type => "field", addr => 0x18010, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask" => { type => "reg", addr => 0x18014, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pilot_spur_mask.cf_pilot_mask_B_sel" => { type => "field", addr => 0x18014, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pilot_spur_mask.cf_pilot_mask_A_sel" => { type => "field", addr => 0x18014, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pilot_spur_mask.cf_pilot_mask_idx_B" => { type => "field", addr => 0x18014, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask.cf_pilot_mask_B" => { type => "field", addr => 0x18014, width => 5, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask.cf_pilot_mask_idx_A" => { type => "field", addr => 0x18014, width => 8, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask.cf_pilot_mask_A" => { type => "field", addr => 0x18014, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask" => { type => "reg", addr => 0x18018, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chan_spur_mask.cf_chan_mask_B_sel" => { type => "field", addr => 0x18018, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chan_spur_mask.cf_chan_mask_A_sel" => { type => "field", addr => 0x18018, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chan_spur_mask.cf_chan_mask_idx_B" => { type => "field", addr => 0x18018, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask.cf_chan_mask_B" => { type => "field", addr => 0x18018, width => 5, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask.cf_chan_mask_idx_A" => { type => "field", addr => 0x18018, width => 8, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask.cf_chan_mask_A" => { type => "field", addr => 0x18018, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_short_gi_delta_slope" => { type => "reg", addr => 0x1801c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_short_gi_delta_slope.forced_lfte_skip" => { type => "field", addr => 0x1801c, width => 6, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_short_gi_delta_slope.delta_slope_coef_man_short_gi" => { type => "field", addr => 0x1801c, width => 15, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_short_gi_delta_slope.delta_slope_coef_exp_short_gi" => { type => "field", addr => 0x1801c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ml_cntl1" => { type => "reg", addr => 0x18020, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ml_cntl1.cf_is_flat_ch_thr_ml" => { type => "field", addr => 0x18020, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ml_cntl1.cf_ml_2s_weight_table" => { type => "field", addr => 0x18020, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ml_cntl2" => { type => "reg", addr => 0x18024, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ml_cntl2.cf_is_flat_ch_thr_zf" => { type => "field", addr => 0x18024, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ml_cntl2.cf_ml_3s_weight_table" => { type => "field", addr => 0x18024, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tstadc" => { type => "reg", addr => 0x18028, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_tstadc.tstadc_out_i" => { type => "field", addr => 0x18028, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_tstadc.tstadc_out_q" => { type => "field", addr => 0x18028, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_vit_spur_mask_C" => { type => "reg", addr => 0x1802c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_vit_spur_mask_C.cf_punc_mask_C_sel" => { type => "field", addr => 0x1802c, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vit_spur_mask_C.cf_punc_mask_idx_C" => { type => "field", addr => 0x1802c, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_C.cf_punc_mask_C" => { type => "field", addr => 0x1802c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_D" => { type => "reg", addr => 0x18030, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_vit_spur_mask_D.cf_punc_mask_D_sel" => { type => "field", addr => 0x18030, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vit_spur_mask_D.cf_punc_mask_idx_D" => { type => "field", addr => 0x18030, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_D.cf_punc_mask_D" => { type => "field", addr => 0x18030, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_CD" => { type => "reg", addr => 0x18034, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pilot_spur_mask_CD.cf_pilot_mask_D_sel" => { type => "field", addr => 0x18034, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pilot_spur_mask_CD.cf_pilot_mask_C_sel" => { type => "field", addr => 0x18034, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pilot_spur_mask_CD.cf_pilot_mask_idx_D" => { type => "field", addr => 0x18034, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_CD.cf_pilot_mask_D" => { type => "field", addr => 0x18034, width => 5, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_CD.cf_pilot_mask_idx_C" => { type => "field", addr => 0x18034, width => 8, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_CD.cf_pilot_mask_C" => { type => "field", addr => 0x18034, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_CD" => { type => "reg", addr => 0x18038, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chan_spur_mask_CD.cf_chan_mask_D_sel" => { type => "field", addr => 0x18038, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chan_spur_mask_CD.cf_chan_mask_C_sel" => { type => "field", addr => 0x18038, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chan_spur_mask_CD.cf_chan_mask_idx_D" => { type => "field", addr => 0x18038, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_CD.cf_chan_mask_D" => { type => "field", addr => 0x18038, width => 5, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_CD.cf_chan_mask_idx_C" => { type => "field", addr => 0x18038, width => 8, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_CD.cf_chan_mask_C" => { type => "field", addr => 0x18038, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_E" => { type => "reg", addr => 0x1803c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_vit_spur_mask_E.cf_punc_mask_E_sel" => { type => "field", addr => 0x1803c, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vit_spur_mask_E.cf_punc_mask_idx_E" => { type => "field", addr => 0x1803c, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_E.cf_punc_mask_E" => { type => "field", addr => 0x1803c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_F" => { type => "reg", addr => 0x18040, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_vit_spur_mask_F.cf_punc_mask_F_sel" => { type => "field", addr => 0x18040, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vit_spur_mask_F.cf_punc_mask_idx_F" => { type => "field", addr => 0x18040, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_F.cf_punc_mask_F" => { type => "field", addr => 0x18040, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_EF" => { type => "reg", addr => 0x18044, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pilot_spur_mask_EF.cf_pilot_mask_F_sel" => { type => "field", addr => 0x18044, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pilot_spur_mask_EF.cf_pilot_mask_E_sel" => { type => "field", addr => 0x18044, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pilot_spur_mask_EF.cf_pilot_mask_idx_F" => { type => "field", addr => 0x18044, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_EF.cf_pilot_mask_F" => { type => "field", addr => 0x18044, width => 5, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_EF.cf_pilot_mask_idx_E" => { type => "field", addr => 0x18044, width => 8, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_EF.cf_pilot_mask_E" => { type => "field", addr => 0x18044, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_EF" => { type => "reg", addr => 0x18048, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chan_spur_mask_EF.cf_chan_mask_F_sel" => { type => "field", addr => 0x18048, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chan_spur_mask_EF.cf_chan_mask_E_sel" => { type => "field", addr => 0x18048, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chan_spur_mask_EF.cf_chan_mask_idx_F" => { type => "field", addr => 0x18048, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_EF.cf_chan_mask_F" => { type => "field", addr => 0x18048, width => 5, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_EF.cf_chan_mask_idx_E" => { type => "field", addr => 0x18048, width => 8, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_EF.cf_chan_mask_E" => { type => "field", addr => 0x18048, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_G" => { type => "reg", addr => 0x1804c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_vit_spur_mask_G.cf_punc_mask_G_sel" => { type => "field", addr => 0x1804c, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vit_spur_mask_G.cf_punc_mask_idx_G" => { type => "field", addr => 0x1804c, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_G.cf_punc_mask_G" => { type => "field", addr => 0x1804c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_H" => { type => "reg", addr => 0x18050, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_vit_spur_mask_H.cf_punc_mask_H_sel" => { type => "field", addr => 0x18050, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_vit_spur_mask_H.cf_punc_mask_idx_H" => { type => "field", addr => 0x18050, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_vit_spur_mask_H.cf_punc_mask_H" => { type => "field", addr => 0x18050, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_GH" => { type => "reg", addr => 0x18054, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pilot_spur_mask_GH.cf_pilot_mask_H_sel" => { type => "field", addr => 0x18054, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pilot_spur_mask_GH.cf_pilot_mask_G_sel" => { type => "field", addr => 0x18054, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pilot_spur_mask_GH.cf_pilot_mask_idx_H" => { type => "field", addr => 0x18054, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_GH.cf_pilot_mask_H" => { type => "field", addr => 0x18054, width => 5, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_GH.cf_pilot_mask_idx_G" => { type => "field", addr => 0x18054, width => 8, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pilot_spur_mask_GH.cf_pilot_mask_G" => { type => "field", addr => 0x18054, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_GH" => { type => "reg", addr => 0x18058, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chan_spur_mask_GH.cf_chan_mask_H_sel" => { type => "field", addr => 0x18058, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chan_spur_mask_GH.cf_chan_mask_G_sel" => { type => "field", addr => 0x18058, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chan_spur_mask_GH.cf_chan_mask_idx_H" => { type => "field", addr => 0x18058, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_GH.cf_chan_mask_H" => { type => "field", addr => 0x18058, width => 5, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_GH.cf_chan_mask_idx_G" => { type => "field", addr => 0x18058, width => 8, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_chan_spur_mask_GH.cf_chan_mask_G" => { type => "field", addr => 0x18058, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ldpc_cntl3" => { type => "reg", addr => 0x1805c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ldpc_cntl3.ldpc_latency_gap_pre2" => { type => "field", addr => 0x1805c, width => 11, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 70 }, "BB_ldpc_cntl3.ldpc_latency_gap_pre" => { type => "field", addr => 0x1805c, width => 11, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 50 }, "BB_ldpc_cntl3.ldpc_timeout_thresh" => { type => "field", addr => 0x1805c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 330 }, "BB_ldpc_cntl4" => { type => "reg", addr => 0x18060, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ldpc_cntl4.ldpc_parity_win_rate2" => { type => "field", addr => 0x18060, width => 5, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 12 }, "BB_ldpc_cntl4.ldpc_parity_win_rate1" => { type => "field", addr => 0x18060, width => 5, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 16 }, "BB_ldpc_cntl4.ldpc_parity_win_rate0" => { type => "field", addr => 0x18060, width => 6, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 24 }, "BB_ldpc_cntl4.ldpc_ifs_cnt" => { type => "field", addr => 0x18060, width => 2, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ldpc_cntl4.ldpc_fast_inbuf_near_rdy" => { type => "field", addr => 0x18060, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ldpc_cntl4.ldpc_inbuf_near_rdy_thresh" => { type => "field", addr => 0x18060, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 510 }, "BB_gid_upa_entry_0_to_15" => { type => "reg", addr => 0x18064, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_15" => { type => "field", addr => 0x18064, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_14" => { type => "field", addr => 0x18064, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_13" => { type => "field", addr => 0x18064, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_12" => { type => "field", addr => 0x18064, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_11" => { type => "field", addr => 0x18064, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_10" => { type => "field", addr => 0x18064, width => 2, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_9" => { type => "field", addr => 0x18064, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_8" => { type => "field", addr => 0x18064, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_7" => { type => "field", addr => 0x18064, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_6" => { type => "field", addr => 0x18064, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_5" => { type => "field", addr => 0x18064, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_4" => { type => "field", addr => 0x18064, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_3" => { type => "field", addr => 0x18064, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_2" => { type => "field", addr => 0x18064, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_1" => { type => "field", addr => 0x18064, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_0_to_15.cf_gid_upa_entry_0" => { type => "field", addr => 0x18064, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31" => { type => "reg", addr => 0x18068, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_31" => { type => "field", addr => 0x18068, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_30" => { type => "field", addr => 0x18068, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_29" => { type => "field", addr => 0x18068, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_28" => { type => "field", addr => 0x18068, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_27" => { type => "field", addr => 0x18068, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_26" => { type => "field", addr => 0x18068, width => 2, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_25" => { type => "field", addr => 0x18068, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_24" => { type => "field", addr => 0x18068, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_23" => { type => "field", addr => 0x18068, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_22" => { type => "field", addr => 0x18068, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_21" => { type => "field", addr => 0x18068, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_20" => { type => "field", addr => 0x18068, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_19" => { type => "field", addr => 0x18068, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_18" => { type => "field", addr => 0x18068, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_17" => { type => "field", addr => 0x18068, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_16_to_31.cf_gid_upa_entry_16" => { type => "field", addr => 0x18068, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47" => { type => "reg", addr => 0x1806c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_47" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_46" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_45" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_44" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_43" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_42" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_41" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_40" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_39" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_38" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_37" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_36" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_35" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_34" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_33" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_32_to_47.cf_gid_upa_entry_32" => { type => "field", addr => 0x1806c, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63" => { type => "reg", addr => 0x18070, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_63" => { type => "field", addr => 0x18070, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_62" => { type => "field", addr => 0x18070, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_61" => { type => "field", addr => 0x18070, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_60" => { type => "field", addr => 0x18070, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_59" => { type => "field", addr => 0x18070, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_58" => { type => "field", addr => 0x18070, width => 2, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_57" => { type => "field", addr => 0x18070, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_56" => { type => "field", addr => 0x18070, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_55" => { type => "field", addr => 0x18070, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_54" => { type => "field", addr => 0x18070, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_53" => { type => "field", addr => 0x18070, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_52" => { type => "field", addr => 0x18070, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_51" => { type => "field", addr => 0x18070, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_50" => { type => "field", addr => 0x18070, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_49" => { type => "field", addr => 0x18070, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gid_upa_entry_48_to_63.cf_gid_upa_entry_48" => { type => "field", addr => 0x18070, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_lsig_reliability_cntl" => { type => "reg", addr => 0x18074, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_lsig_reliability_cntl.enable_lsig_vit_check" => { type => "field", addr => 0x18074, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_lsig_reliability_cntl.enh_vit_init" => { type => "field", addr => 0x18074, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_lsig_reliability_cntl.en_vhtsigb_crc_chk_su" => { type => "field", addr => 0x18074, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_lsig_reliability_cntl.en_vhtsigb_crc_chk_mu" => { type => "field", addr => 0x18074, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_lsig_reliability_cntl.lsig_min_s0_63_diff_thr" => { type => "field", addr => 0x18074, width => 11, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x004 }, "BB_lsig_reliability_cntl.lsig_max_s0_thr" => { type => "field", addr => 0x18074, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 28 }, "BB_mmse_cntl" => { type => "reg", addr => 0x18078, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_mmse_cntl.sec_mmse_is_noise_pwr_exp_shift" => { type => "field", addr => 0x18078, width => 4, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0xf }, "BB_mmse_cntl.cf_mmse_dbg_en" => { type => "field", addr => 0x18078, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_mmse_cntl.use_su_zf" => { type => "field", addr => 0x18078, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_mmse_cntl.mmse_is_noise_pwr_exp_shift" => { type => "field", addr => 0x18078, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0xf }, "BB_mmse_cntl.mmse_is_max_snr_level" => { type => "field", addr => 0x18078, width => 2, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_mmse_cntl.mmse_is_snr_corr_factor" => { type => "field", addr => 0x18078, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_mmse_cntl.mmse_is_forced_snr" => { type => "field", addr => 0x18078, width => 5, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_mmse_cntl.use_mmse_ic" => { type => "field", addr => 0x18078, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_ldpc_cntl5" => { type => "reg", addr => 0x1807c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ldpc_cntl5.ldpc_parity_win_rate3" => { type => "field", addr => 0x1807c, width => 4, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 8 }, "BB_ldpc_cntl5.ldpc_latency_sel" => { type => "field", addr => 0x1807c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_ldpc_cntl5.ldpc_latency_lastcw_rxclr" => { type => "field", addr => 0x1807c, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 2112 }, "BB_ldpc_cntl5.ldpc_latency_lastcw_rxclr_stbc" => { type => "field", addr => 0x1807c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 2464 }, "BB_mmse_cntl2" => { type => "reg", addr => 0x18080, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_mmse_cntl2.mmse_mu_nss_user" => { type => "field", addr => 0x18080, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_mmse_cntl2.mmse_turbo_mode" => { type => "field", addr => 0x18080, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_mmse_cntl2.mmse_sir_db_ss2" => { type => "field", addr => 0x18080, width => 14, bitOffset => 14, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_mmse_cntl2.mmse_sir_db_ss1" => { type => "field", addr => 0x18080, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_mmse_cntl3" => { type => "reg", addr => 0x18084, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_mmse_cntl3.mmse_is_noise_pwr" => { type => "field", addr => 0x18084, width => 14, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_mmse_cntl3.snr_est_mmse_is" => { type => "field", addr => 0x18084, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_packet_bw_det_cntl" => { type => "reg", addr => 0x18088, width => 32, athEmulAttr => 0, acc => "RCLRW" }, "BB_packet_bw_det_cntl.mrcapb_det_bw_fail" => { type => "field", addr => 0x18088, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RCLR", resetVal => 0 }, "BB_packet_bw_det_cntl.mrcapb_pbdbe_det_bw_force_en" => { type => "field", addr => 0x18088, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_bw_det_cntl.mrcapb_pbdbe_det_bw_force" => { type => "field", addr => 0x18088, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_packet_bw_det_cntl.mrcapb_pbdbe_pwr_thr" => { type => "field", addr => 0x18088, width => 4, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "BB_packet_bw_det_cntl.mrcapb_pbdbe_thn" => { type => "field", addr => 0x18088, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "BB_packet_bw_det_cntl.mrcapb_pbdbe_thp" => { type => "field", addr => 0x18088, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "BB_ml_cntl3" => { type => "reg", addr => 0x1808c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ml_cntl3.cf_ml_4s_weight_table" => { type => "field", addr => 0x1808c, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_pbs_cntl" => { type => "reg", addr => 0x18090, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_pbs_cntl.rxwin_rolloff" => { type => "field", addr => 0x18090, width => 2, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_pbs_cntl.pbs_disable" => { type => "field", addr => 0x18090, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ste_coarse_tim_cntl_1" => { type => "reg", addr => 0x18094, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ste_coarse_tim_cntl_1.cf_coarse_tim_thr_4" => { type => "field", addr => 0x18094, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 212 }, "BB_ste_coarse_tim_cntl_1.cf_coarse_tim_thr_3" => { type => "field", addr => 0x18094, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 252 }, "BB_ste_coarse_tim_cntl_1.cf_coarse_tim_thr_2" => { type => "field", addr => 0x18094, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 230 }, "BB_ste_coarse_tim_cntl_1.cf_coarse_tim_thr_1" => { type => "field", addr => 0x18094, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 230 }, "BB_ste_coarse_tim_cntl_2" => { type => "reg", addr => 0x18098, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ste_coarse_tim_cntl_2.cf_coarse_tim_thr_8" => { type => "field", addr => 0x18098, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 154 }, "BB_ste_coarse_tim_cntl_2.cf_coarse_tim_thr_7" => { type => "field", addr => 0x18098, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 102 }, "BB_ste_coarse_tim_cntl_2.cf_coarse_tim_thr_6" => { type => "field", addr => 0x18098, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 230 }, "BB_ste_coarse_tim_cntl_2.cf_coarse_tim_thr_5" => { type => "field", addr => 0x18098, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 223 }, "BB_ste_coarse_tim_cntl_3" => { type => "reg", addr => 0x1809c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ste_coarse_tim_cntl_3.cf_coarse_tim_offset_3" => { type => "field", addr => 0x1809c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ste_coarse_tim_cntl_3.cf_coarse_tim_offset_2" => { type => "field", addr => 0x1809c, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 20 }, "BB_ste_coarse_tim_cntl_3.cf_coarse_tim_offset_1" => { type => "field", addr => 0x1809c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 24 }, "BB_delta_slope_coef_man_corr_sg" => { type => "reg", addr => 0x180a0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_delta_slope_coef_man_corr_sg.delta_slope_coef_man_pri40_corr_sg" => { type => "field", addr => 0x180a0, width => 9, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_delta_slope_coef_man_corr_sg.delta_slope_coef_man_pri80_corr_sg" => { type => "field", addr => 0x180a0, width => 10, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_delta_slope_coef_man_corr_sg.delta_slope_coef_man_ext80_corr_sg" => { type => "field", addr => 0x180a0, width => 13, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_delta_slope_coef_man_corr" => { type => "reg", addr => 0x180a4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_delta_slope_coef_man_corr.delta_slope_coef_man_pri40_corr" => { type => "field", addr => 0x180a4, width => 9, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_delta_slope_coef_man_corr.delta_slope_coef_man_pri80_corr" => { type => "field", addr => 0x180a4, width => 10, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_delta_slope_coef_man_corr.delta_slope_coef_man_ext80_corr" => { type => "field", addr => 0x180a4, width => 13, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cfo_corr_scale_frac" => { type => "reg", addr => 0x180a8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_cfo_corr_scale_frac.cfo_corr_scale_frac_en" => { type => "field", addr => 0x180a8, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cfo_corr_scale_frac.cfo_corr_scale_frac_pri40" => { type => "field", addr => 0x180a8, width => 5, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cfo_corr_scale_frac.cfo_corr_scale_frac_pri80" => { type => "field", addr => 0x180a8, width => 6, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_cfo_corr_scale_frac.cfo_corr_scale_frac_ext80" => { type => "field", addr => 0x180a8, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_gain_ratio_cntl" => { type => "reg", addr => 0x180ac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_gain_ratio_cntl.agc_ht_stf_gain_ratio_ena" => { type => "field", addr => 0x180ac, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ldpc_cntl6" => { type => "reg", addr => 0x18100, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ldpc_cntl6.ldpc_latency_gap_pre3" => { type => "field", addr => 0x18100, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 90 }, "BB_ldpc_cntl7" => { type => "reg", addr => 0x18104, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ldpc_cntl7.ldpc_ms_offset" => { type => "field", addr => 0x18104, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_ldpc_cntl7.ldpc_ms_scale" => { type => "field", addr => 0x18104, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_ldpc_cntl8" => { type => "reg", addr => 0x18108, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ldpc_cntl8.high_precision_ldpc_llr_scaling0" => { type => "field", addr => 0x18108, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x36db2492 }, "BB_ldpc_cntl9" => { type => "reg", addr => 0x1810c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ldpc_cntl9.en_high_precision_ldpc_llr_scaling" => { type => "field", addr => 0x1810c, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ldpc_cntl9.high_precision_ldpc_llr_scaling1" => { type => "field", addr => 0x1810c, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000092 }, "BB_mrc_spare_01" => { type => "reg", addr => 0x18110, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_mrc_spare_01.mrc_eco_ctrl" => { type => "field", addr => 0x18110, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, ################################################################### ## fpga_reg Register/Field definitions ################################################################### "FPGA_REG1" => { type => "reg", addr => 0x18120, width => 32, athEmulAttr => 0, acc => "RW" }, "FPGA_REG1.fpga_fake_pa_sel_0" => { type => "field", addr => 0x18120, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG1.fpga_fake_pa_sel_1" => { type => "field", addr => 0x18120, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG1.fpga_rxiq_coeff_i_0" => { type => "field", addr => 0x18120, width => 7, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG1.fpga_rxiq_coeff_q_0" => { type => "field", addr => 0x18120, width => 7, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG1.fpga_rxiq_coeff_i_1" => { type => "field", addr => 0x18120, width => 7, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG1.fpga_rxiq_coeff_q_1" => { type => "field", addr => 0x18120, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG2" => { type => "reg", addr => 0x18124, width => 32, athEmulAttr => 0, acc => "RW" }, "FPGA_REG2.fpga_adc_dc_i_0" => { type => "field", addr => 0x18124, width => 6, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG2.fpga_adc_dc_q_0" => { type => "field", addr => 0x18124, width => 6, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG2.fpga_fifo_delay_0" => { type => "field", addr => 0x18124, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG2.fpga_adc_dc_i_1" => { type => "field", addr => 0x18124, width => 6, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG2.fpga_adc_dc_q_1" => { type => "field", addr => 0x18124, width => 6, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG2.fpga_fifo_delay_1" => { type => "field", addr => 0x18124, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG3" => { type => "reg", addr => 0x18128, width => 32, athEmulAttr => 0, acc => "RW" }, "FPGA_REG3.fpga_adc_clk_sel_1" => { type => "field", addr => 0x18128, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG3.fpga_adc_clk_sel_0" => { type => "field", addr => 0x18128, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FPGA_REG3.fpga_rxiq_enable" => { type => "field", addr => 0x18128, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## merlin_reg_sel Register/Field definitions ################################################################### "MERLIN_RADIO_SEL" => { type => "reg", addr => 0x1f000, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RADIO_SEL.SPARE" => { type => "field", addr => 0x1f000, width => 31, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RADIO_SEL.RADIO_SEL" => { type => "field", addr => 0x1f000, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## emu_phy_reg Register/Field definitions ################################################################### "PHY_CTRL_0" => { type => "reg", addr => 0x1fe00, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_CTRL_0.rsvd_1" => { type => "field", addr => 0x1fe00, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.pkt_usr_tlv_len" => { type => "field", addr => 0x1fe00, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PHY_CTRL_0.ndp_drop_enable" => { type => "field", addr => 0x1fe00, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.vec_frag_bw_override" => { type => "field", addr => 0x1fe00, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.vec_frag_bw" => { type => "field", addr => 0x1fe00, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.vec_frag_nr_override" => { type => "field", addr => 0x1fe00, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.vec_frag_nr" => { type => "field", addr => 0x1fe00, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.vec_frag_nc_override" => { type => "field", addr => 0x1fe00, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.vec_frag_nc" => { type => "field", addr => 0x1fe00, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.rsvd_0" => { type => "field", addr => 0x1fe00, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.rx_clr_stomp_en" => { type => "field", addr => 0x1fe00, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.rx_delay" => { type => "field", addr => 0x1fe00, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_0.tx_delay" => { type => "field", addr => 0x1fe00, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "PHY_CTRL_1" => { type => "reg", addr => 0x1fe04, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_CTRL_1.rsvd_2" => { type => "field", addr => 0x1fe04, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_1.rx_clr_swp_override" => { type => "field", addr => 0x1fe04, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PHY_CTRL_1.rx_clr_s80_override" => { type => "field", addr => 0x1fe04, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PHY_CTRL_1.rx_clr_s40_override" => { type => "field", addr => 0x1fe04, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PHY_CTRL_1.rx_clr_s20_override" => { type => "field", addr => 0x1fe04, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PHY_CTRL_1.rx_clr_pri_override" => { type => "field", addr => 0x1fe04, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PHY_CTRL_1.ppdu_end_non_err_rate" => { type => "field", addr => 0x1fe04, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "PHY_CTRL_1.pkt_end_non_err_rate" => { type => "field", addr => 0x1fe04, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "PHY_CTRL_1.rsvd_1" => { type => "field", addr => 0x1fe04, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_1.ppdu_end_err_inject_enable" => { type => "field", addr => 0x1fe04, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_1.pkt_end_err_inject_enable" => { type => "field", addr => 0x1fe04, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_1.rsvd_0" => { type => "field", addr => 0x1fe04, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_1.vec_frag_opt_h" => { type => "field", addr => 0x1fe04, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_1.implicit_bf_sounding" => { type => "field", addr => 0x1fe04, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_2" => { type => "reg", addr => 0x1fe08, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_CTRL_2.rsvd" => { type => "field", addr => 0x1fe08, width => 24, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_CTRL_2.pkt_end_err_mask" => { type => "field", addr => 0x1fe08, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf8 }, "PHY_CTRL_3" => { type => "reg", addr => 0x1fe0c, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_CTRL_3.ppdu_end_err_mask_lo" => { type => "field", addr => 0x1fe0c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xfff5f5fc }, "PHY_CTRL_4" => { type => "reg", addr => 0x1fe10, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_CTRL_4.ppdu_end_err_mask_hi" => { type => "field", addr => 0x1fe10, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000003ff }, "PHY_CTRL_5" => { type => "reg", addr => 0x1fe14, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_CTRL_5.ppdu_end_zl_err_lo" => { type => "field", addr => 0x1fe14, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xfaf5f5e0 }, "PHY_CTRL_6" => { type => "reg", addr => 0x1fe18, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_CTRL_6.ppdu_end_zl_err_hi" => { type => "field", addr => 0x1fe18, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0000027f }, "PHY_CTRL_7" => { type => "reg", addr => 0x1fe1c, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_CTRL_7.ppdu_end_nz_err_lo" => { type => "field", addr => 0x1fe1c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x05000014 }, "PHY_CTRL_8" => { type => "reg", addr => 0x1fe20, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_CTRL_8.ppdu_end_nz_err_hi" => { type => "field", addr => 0x1fe20, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000180 }, "PHY_STOMP_PRI_CLR" => { type => "reg", addr => 0x1fe24, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_STOMP_PRI_CLR.cnt" => { type => "field", addr => 0x1fe24, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_STOMP_PRI_BUSY" => { type => "reg", addr => 0x1fe28, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_STOMP_PRI_BUSY.cnt" => { type => "field", addr => 0x1fe28, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_STOMP_SEC20_CLR" => { type => "reg", addr => 0x1fe2c, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_STOMP_SEC20_CLR.cnt" => { type => "field", addr => 0x1fe2c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_STOMP_SEC20_BUSY" => { type => "reg", addr => 0x1fe30, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_STOMP_SEC20_BUSY.cnt" => { type => "field", addr => 0x1fe30, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_STOMP_SEC40_CLR" => { type => "reg", addr => 0x1fe34, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_STOMP_SEC40_CLR.cnt" => { type => "field", addr => 0x1fe34, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_STOMP_SEC40_BUSY" => { type => "reg", addr => 0x1fe38, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_STOMP_SEC40_BUSY.cnt" => { type => "field", addr => 0x1fe38, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_STOMP_SEC80_CLR" => { type => "reg", addr => 0x1fe3c, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_STOMP_SEC80_CLR.cnt" => { type => "field", addr => 0x1fe3c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_STOMP_SEC80_BUSY" => { type => "reg", addr => 0x1fe40, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_STOMP_SEC80_BUSY.cnt" => { type => "field", addr => 0x1fe40, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_DATA_0" => { type => "reg", addr => 0x1fe44, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_DATA_0.rssi" => { type => "field", addr => 0x1fe44, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x43424140 }, "PHY_DATA_1" => { type => "reg", addr => 0x1fe48, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_DATA_1.rsvd_1" => { type => "field", addr => 0x1fe48, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_DATA_1.timing_offset" => { type => "field", addr => 0x1fe48, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_DATA_1.rsvd_0" => { type => "field", addr => 0x1fe48, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_DATA_1.bandwidth" => { type => "field", addr => 0x1fe48, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_DATA_1.rssi_comb" => { type => "field", addr => 0x1fe48, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x44 }, "PHY_DATA_2" => { type => "reg", addr => 0x1fe4c, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_DATA_2.cv_length_h" => { type => "field", addr => 0x1fe4c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x3e8 }, "PHY_DATA_2.cv_length" => { type => "field", addr => 0x1fe4c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x374 }, "PHY_DATA_3" => { type => "reg", addr => 0x1fe50, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_DATA_3.vec_frag_h_tlv" => { type => "field", addr => 0x1fe50, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0xbbf0 }, "PHY_DATA_3.vec_frag_tlv" => { type => "field", addr => 0x1fe50, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xbb01 }, "PHY_DATA_4" => { type => "reg", addr => 0x1fe54, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_DATA_4.vec_frag_2" => { type => "field", addr => 0x1fe54, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x05000000 }, "PHY_DATA_5" => { type => "reg", addr => 0x1fe58, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_DATA_5.vec_frag_3" => { type => "field", addr => 0x1fe58, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x20202000 }, "PHY_DATA_6" => { type => "reg", addr => 0x1fe5c, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_DATA_6.vec_frag_rept" => { type => "field", addr => 0x1fe5c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xcbcbcbcb }, "PHY_DATA_7" => { type => "reg", addr => 0x1fe60, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_DATA_7.vec_frag_h_rept" => { type => "field", addr => 0x1fe60, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xaaaaaaaa }, "PHY_DATA_8" => { type => "reg", addr => 0x1fe64, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_DATA_8.svd_rdy_brst_dly" => { type => "field", addr => 0x1fe64, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_DATA_8.svd_rdy_dly" => { type => "field", addr => 0x1fe64, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x78 }, "PHY_DATA_9" => { type => "reg", addr => 0x1fe68, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_DATA_9.evm" => { type => "field", addr => 0x1fe68, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_DATA_GP_USR" => { type => "reg", addr => 0x1fe70, width => 32, athEmulAttr => 0, acc => "RW", depth => 4, incr => 4 }, "PHY_DATA_GP_USR.group_to_user_entry" => { type => "field", addr => 0x1fe70, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_STATUS" => { type => "reg", addr => 0x1fe80, width => 32, athEmulAttr => 0, acc => "RW" }, "PHY_STATUS.rsvd_1" => { type => "field", addr => 0x1fe80, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_STATUS.rx_abort" => { type => "field", addr => 0x1fe80, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PHY_STATUS.tx_stomp_rx" => { type => "field", addr => 0x1fe80, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PHY_STATUS.tlv_err_cnt" => { type => "field", addr => 0x1fe80, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PHY_STATUS.rsvd_0" => { type => "field", addr => 0x1fe80, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PHY_STATUS.tx_underrun_fifo_2" => { type => "field", addr => 0x1fe80, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PHY_STATUS.tx_underrun_fifo_1" => { type => "field", addr => 0x1fe80, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PHY_STATUS.tx_underrun_fifo_0" => { type => "field", addr => 0x1fe80, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CHN_CTRL_0" => { type => "reg", addr => 0x1fe84, width => 32, athEmulAttr => 0, acc => "RW" }, "CHN_CTRL_0.rsvd_3" => { type => "field", addr => 0x1fe84, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CHN_CTRL_0.max_bit_err_3" => { type => "field", addr => 0x1fe84, width => 5, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CHN_CTRL_0.rsvd_2" => { type => "field", addr => 0x1fe84, width => 3, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CHN_CTRL_0.max_bit_err_2" => { type => "field", addr => 0x1fe84, width => 5, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CHN_CTRL_0.rsvd_1" => { type => "field", addr => 0x1fe84, width => 3, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CHN_CTRL_0.max_bit_err_1" => { type => "field", addr => 0x1fe84, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CHN_CTRL_0.rsvd_0" => { type => "field", addr => 0x1fe84, width => 3, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CHN_CTRL_0.max_bit_err_0" => { type => "field", addr => 0x1fe84, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CHN_CTRL_1" => { type => "reg", addr => 0x1fe90, width => 32, athEmulAttr => 0, acc => "RW", depth => 4, incr => 4 }, "CHN_CTRL_1.lfsr_spread" => { type => "field", addr => 0x1fe90, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFFF }, "CHN_CTRL_2" => { type => "reg", addr => 0x1fea0, width => 32, athEmulAttr => 0, acc => "RW", depth => 4, incr => 4 }, "CHN_CTRL_2.dnsty_mask" => { type => "field", addr => 0x1fea0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFFF }, "TLVI_TX_PHY_DESC" => { type => "reg", addr => 0x1feb0, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_TX_PHY_DESC.CNT" => { type => "field", addr => 0x1feb0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVI_TX_SERVICE" => { type => "reg", addr => 0x1feb4, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_TX_SERVICE.CNT" => { type => "field", addr => 0x1feb4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVI_MAC_PKT_END" => { type => "reg", addr => 0x1feb8, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_MAC_PKT_END.CNT" => { type => "field", addr => 0x1feb8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVI_VECTOR_XFER_START" => { type => "reg", addr => 0x1febc, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_VECTOR_XFER_START.CNT" => { type => "field", addr => 0x1febc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVI_TLV_TERMINATE" => { type => "reg", addr => 0x1fec0, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_TLV_TERMINATE.CNT" => { type => "field", addr => 0x1fec0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVI_TX_EXPECT_CBF" => { type => "reg", addr => 0x1fec4, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_TX_EXPECT_CBF.CNT" => { type => "field", addr => 0x1fec4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVI_TX_CBF_OFFSET" => { type => "reg", addr => 0x1fec8, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_TX_CBF_OFFSET.CNT" => { type => "field", addr => 0x1fec8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVI_TX_BF_PARAMS" => { type => "reg", addr => 0x1fecc, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_TX_BF_PARAMS.CNT" => { type => "field", addr => 0x1fecc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVI_TX_EXPECT_NDP" => { type => "reg", addr => 0x1fed0, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_TX_EXPECT_NDP.CNT" => { type => "field", addr => 0x1fed0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVI_PHY_OFF" => { type => "reg", addr => 0x1fed4, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_PHY_OFF.CNT" => { type => "field", addr => 0x1fed4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVI_PHY_ON" => { type => "reg", addr => 0x1fed8, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVI_PHY_ON.CNT" => { type => "field", addr => 0x1fed8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVO_SVD_READY" => { type => "reg", addr => 0x1fedc, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVO_SVD_READY.CNT" => { type => "field", addr => 0x1fedc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVO_VECTOR_FRAGMENT" => { type => "reg", addr => 0x1fee0, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVO_VECTOR_FRAGMENT.CNT" => { type => "field", addr => 0x1fee0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVO_RX_PHY_PPDU_END" => { type => "reg", addr => 0x1fee4, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVO_RX_PHY_PPDU_END.CNT" => { type => "field", addr => 0x1fee4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVO_RX_PKT_END" => { type => "reg", addr => 0x1fee8, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVO_RX_PKT_END.CNT" => { type => "field", addr => 0x1fee8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVO_RX_SERVICE" => { type => "reg", addr => 0x1feec, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVO_RX_SERVICE.CNT" => { type => "field", addr => 0x1feec, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVO_RX_EVM" => { type => "reg", addr => 0x1fef0, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVO_RX_EVM.CNT" => { type => "field", addr => 0x1fef0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVO_RX_RSSI_HT" => { type => "reg", addr => 0x1fef4, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVO_RX_RSSI_HT.CNT" => { type => "field", addr => 0x1fef4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TLVO_RX_RSSI_LEGACY" => { type => "reg", addr => 0x1fef8, width => 32, athEmulAttr => 0, acc => "RO" }, "TLVO_RX_RSSI_LEGACY.CNT" => { type => "field", addr => 0x1fef8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, ################################################################### ## merlin2_0_radio_reg Register/Field definitions ################################################################### "MERLIN_RXTXBB1_CH1" => { type => "reg", addr => 0x1ff00, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RXTXBB1_CH1.SPARE" => { type => "field", addr => 0x1ff00, width => 13, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.FNOTCH" => { type => "field", addr => 0x1ff00, width => 2, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.SEL_ATB" => { type => "field", addr => 0x1ff00, width => 8, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.PDDACINTERFACE" => { type => "field", addr => 0x1ff00, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.PDV2I" => { type => "field", addr => 0x1ff00, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.PDI2V" => { type => "field", addr => 0x1ff00, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.PDRXTXBB" => { type => "field", addr => 0x1ff00, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.PDOFFSETLOQ" => { type => "field", addr => 0x1ff00, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.PDOFFSETHIQ" => { type => "field", addr => 0x1ff00, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.PDOFFSETI2V" => { type => "field", addr => 0x1ff00, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.PDLOQ" => { type => "field", addr => 0x1ff00, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH1.PDHIQ" => { type => "field", addr => 0x1ff00, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1" => { type => "reg", addr => 0x1ff04, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RXTXBB2_CH1.IBN_37P5_OSHI_CTRL" => { type => "field", addr => 0x1ff04, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "MERLIN_RXTXBB2_CH1.IBN_37P5_OSLO_CTRL" => { type => "field", addr => 0x1ff04, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "MERLIN_RXTXBB2_CH1.IBN_37P5_OSI2V_CTRL" => { type => "field", addr => 0x1ff04, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "MERLIN_RXTXBB2_CH1.SPARE" => { type => "field", addr => 0x1ff04, width => 2, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.SHORTBUFFER" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.SELBUFFER" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.SEL_DAC_TEST" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.SEL_LOQ_TEST" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.SEL_HIQ_TEST" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.SEL_I2V_TEST" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.CMSEL" => { type => "field", addr => 0x1ff04, width => 2, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_RXTXBB2_CH1.FILTERFC" => { type => "field", addr => 0x1ff04, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB2_CH1.LOCALFILTERTUNING" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.FILTERDOUBLEBW" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.PATH2HIQ_EN" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.PATH1HIQ_EN" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_RXTXBB2_CH1.PATH3LOQ_EN" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.PATH2LOQ_EN" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH1.PATH1LOQ_EN" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_RXTXBB2_CH1.PATH_OVERRIDE" => { type => "field", addr => 0x1ff04, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB3_CH1" => { type => "reg", addr => 0x1ff08, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RXTXBB3_CH1.SPARE" => { type => "field", addr => 0x1ff08, width => 5, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB3_CH1.IBN_25U_CM_BUFAMP_CTRL" => { type => "field", addr => 0x1ff08, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH1.IBN_25U_BKV2I_CTRL" => { type => "field", addr => 0x1ff08, width => 3, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH1.IBN_25U_I2V_CTRL" => { type => "field", addr => 0x1ff08, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH1.IBN_25U_HI1_CTRL" => { type => "field", addr => 0x1ff08, width => 3, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH1.IBN_25U_HI2_CTRL" => { type => "field", addr => 0x1ff08, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH1.IBN_25U_LO1_CTRL" => { type => "field", addr => 0x1ff08, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH1.IBN_25U_LO2_CTRL" => { type => "field", addr => 0x1ff08, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH1.IBRN_12P5_CM_CTRL" => { type => "field", addr => 0x1ff08, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "MERLIN_RXTXBB3_CH1.IBN_100U_TEST_CTRL" => { type => "field", addr => 0x1ff08, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB4_CH1" => { type => "reg", addr => 0x1ff0c, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RXTXBB4_CH1.SPARE" => { type => "field", addr => 0x1ff0c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB4_CH1.LOCALOFFSET" => { type => "field", addr => 0x1ff0c, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB4_CH1.OFSTCORRHII" => { type => "field", addr => 0x1ff0c, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB4_CH1.OFSTCORRHIQ" => { type => "field", addr => 0x1ff0c, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB4_CH1.OFSTCORRLOI" => { type => "field", addr => 0x1ff0c, width => 5, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB4_CH1.OFSTCORRLOQ" => { type => "field", addr => 0x1ff0c, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB4_CH1.OFSTCORRI2VI" => { type => "field", addr => 0x1ff0c, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB4_CH1.OFSTCORRI2VQ" => { type => "field", addr => 0x1ff0c, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RF2G1_CH1" => { type => "reg", addr => 0x1ff10, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RF2G1_CH1.PDIC25U_LNA" => { type => "field", addr => 0x1ff10, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G1_CH1.DB" => { type => "field", addr => 0x1ff10, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G1_CH1.OB" => { type => "field", addr => 0x1ff10, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G1_CH1.LOATB_SEL" => { type => "field", addr => 0x1ff10, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH1.RXATB_SEL" => { type => "field", addr => 0x1ff10, width => 3, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH1.TXATB_SEL" => { type => "field", addr => 0x1ff10, width => 3, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH1.LOCONTROL" => { type => "field", addr => 0x1ff10, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH1.PACA_SEL" => { type => "field", addr => 0x1ff10, width => 2, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "MERLIN_RF2G1_CH1.PDIC25U_VGM" => { type => "field", addr => 0x1ff10, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G1_CH1.REGLNA_BYPASS" => { type => "field", addr => 0x1ff10, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH1.REGLO_BYPASS" => { type => "field", addr => 0x1ff10, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH1.SPARES" => { type => "field", addr => 0x1ff10, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1" => { type => "reg", addr => 0x1ff14, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RF2G2_CH1.PDLNA" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDDIV" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDPADRV" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDPAOUT" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDREGLNA" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDREGLO" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDVGM" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDRXLO" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDTXLO" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDTXMIX" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDIR25U_TXMIX" => { type => "field", addr => 0x1ff14, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G2_CH1.PDIR25U_TXPA" => { type => "field", addr => 0x1ff14, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH1.PDIC25U_TXPA" => { type => "field", addr => 0x1ff14, width => 3, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G2_CH1.PDIC25U_TXRF" => { type => "field", addr => 0x1ff14, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G2_CH1.PDIC25U_RXRF" => { type => "field", addr => 0x1ff14, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_RF2G2_CH1.PDIC50U_DIV" => { type => "field", addr => 0x1ff14, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G2_CH1.PDIC25U_VREGLO" => { type => "field", addr => 0x1ff14, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_RF2G2_CH1.PDIR25U_VREGLO" => { type => "field", addr => 0x1ff14, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_RF5G1_CH1" => { type => "reg", addr => 0x1ff18, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RF5G1_CH1.PDTXLO5" => { type => "field", addr => 0x1ff18, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH1.PDTXMIX5" => { type => "field", addr => 0x1ff18, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH1.PDTXBUF5" => { type => "field", addr => 0x1ff18, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH1.PDPADRV5" => { type => "field", addr => 0x1ff18, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH1.PDPAOUT5" => { type => "field", addr => 0x1ff18, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH1.PACASCBIAS" => { type => "field", addr => 0x1ff18, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF5G1_CH1.PWDTXPKD" => { type => "field", addr => 0x1ff18, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_RF5G1_CH1.DB5" => { type => "field", addr => 0x1ff18, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G1_CH1.OB5" => { type => "field", addr => 0x1ff18, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G1_CH1.TX5_ATB_SEL" => { type => "field", addr => 0x1ff18, width => 3, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH1.LO5CONTROL" => { type => "field", addr => 0x1ff18, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH1.REGLO_BYPASS5" => { type => "field", addr => 0x1ff18, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH1.PDREGLO5" => { type => "field", addr => 0x1ff18, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH1.SPARE" => { type => "field", addr => 0x1ff18, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH1" => { type => "reg", addr => 0x1ff1c, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RF5G2_CH1.REGFE_BYPASS5" => { type => "field", addr => 0x1ff1c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH1.PDREGFE5" => { type => "field", addr => 0x1ff1c, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH1.PDRXLO5" => { type => "field", addr => 0x1ff1c, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH1.PDVGM5" => { type => "field", addr => 0x1ff1c, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH1.PDCSLNA5" => { type => "field", addr => 0x1ff1c, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH1.PDRFVGA5" => { type => "field", addr => 0x1ff1c, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH1.RX5_ATB_SEL" => { type => "field", addr => 0x1ff1c, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH1.PDBIRTXMIX" => { type => "field", addr => 0x1ff1c, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G2_CH1.PDBIRTXPA" => { type => "field", addr => 0x1ff1c, width => 3, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G2_CH1.PDBIR1" => { type => "field", addr => 0x1ff1c, width => 3, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G2_CH1.PDBIR2" => { type => "field", addr => 0x1ff1c, width => 3, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G2_CH1.SPARE" => { type => "field", addr => 0x1ff1c, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G3_CH1" => { type => "reg", addr => 0x1ff20, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RF5G3_CH1.PDBICTXBUF" => { type => "field", addr => 0x1ff20, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH1.PDBICTXPA" => { type => "field", addr => 0x1ff20, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH1.PDBICTXMIX" => { type => "field", addr => 0x1ff20, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH1.PDBIC1" => { type => "field", addr => 0x1ff20, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH1.PDBIC2" => { type => "field", addr => 0x1ff20, width => 3, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH1.PDBIC3" => { type => "field", addr => 0x1ff20, width => 3, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH1.PDBIBCLNA" => { type => "field", addr => 0x1ff20, width => 3, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH1.PDBIBCRFVGA" => { type => "field", addr => 0x1ff20, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH1.PDBIBCVGM" => { type => "field", addr => 0x1ff20, width => 3, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH1.SPARE" => { type => "field", addr => 0x1ff20, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0" => { type => "reg", addr => 0x1ff24, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RXTXBB1_CH0.SPARE" => { type => "field", addr => 0x1ff24, width => 13, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.FNOTCH" => { type => "field", addr => 0x1ff24, width => 2, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.SEL_ATB" => { type => "field", addr => 0x1ff24, width => 8, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.PDDACINTERFACE" => { type => "field", addr => 0x1ff24, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.PDV2I" => { type => "field", addr => 0x1ff24, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.PDI2V" => { type => "field", addr => 0x1ff24, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.PDRXTXBB" => { type => "field", addr => 0x1ff24, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.PDOFFSETLOQ" => { type => "field", addr => 0x1ff24, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.PDOFFSETHIQ" => { type => "field", addr => 0x1ff24, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.PDOFFSETI2V" => { type => "field", addr => 0x1ff24, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.PDLOQ" => { type => "field", addr => 0x1ff24, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB1_CH0.PDHIQ" => { type => "field", addr => 0x1ff24, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0" => { type => "reg", addr => 0x1ff28, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RXTXBB2_CH0.IBN_37P5_OSHI_CTRL" => { type => "field", addr => 0x1ff28, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "MERLIN_RXTXBB2_CH0.IBN_37P5_OSLO_CTRL" => { type => "field", addr => 0x1ff28, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "MERLIN_RXTXBB2_CH0.IBN_37P5_OSI2V_CTRL" => { type => "field", addr => 0x1ff28, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "MERLIN_RXTXBB2_CH0.SPARE" => { type => "field", addr => 0x1ff28, width => 2, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.SHORTBUFFER" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.SELBUFFER" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.SEL_DAC_TEST" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.SEL_LOQ_TEST" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.SEL_HIQ_TEST" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.SEL_I2V_TEST" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.CMSEL" => { type => "field", addr => 0x1ff28, width => 2, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_RXTXBB2_CH0.FILTERFC" => { type => "field", addr => 0x1ff28, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB2_CH0.LOCALFILTERTUNING" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.FILTERDOUBLEBW" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.PATH2HIQ_EN" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.PATH1HIQ_EN" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_RXTXBB2_CH0.PATH3LOQ_EN" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.PATH2LOQ_EN" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB2_CH0.PATH1LOQ_EN" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_RXTXBB2_CH0.PATH_OVERRIDE" => { type => "field", addr => 0x1ff28, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB3_CH0" => { type => "reg", addr => 0x1ff2c, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RXTXBB3_CH0.SPARE" => { type => "field", addr => 0x1ff2c, width => 5, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB3_CH0.IBN_25U_CM_BUFAMP_CTRL" => { type => "field", addr => 0x1ff2c, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH0.IBN_25U_BKV2I_CTRL" => { type => "field", addr => 0x1ff2c, width => 3, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH0.IBN_25U_I2V_CTRL" => { type => "field", addr => 0x1ff2c, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH0.IBN_25U_HI1_CTRL" => { type => "field", addr => 0x1ff2c, width => 3, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH0.IBN_25U_HI2_CTRL" => { type => "field", addr => 0x1ff2c, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH0.IBN_25U_LO1_CTRL" => { type => "field", addr => 0x1ff2c, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH0.IBN_25U_LO2_CTRL" => { type => "field", addr => 0x1ff2c, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB3_CH0.IBRN_12P5_CM_CTRL" => { type => "field", addr => 0x1ff2c, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "MERLIN_RXTXBB3_CH0.IBN_100U_TEST_CTRL" => { type => "field", addr => 0x1ff2c, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RXTXBB4_CH0" => { type => "reg", addr => 0x1ff30, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RXTXBB4_CH0.SPARE" => { type => "field", addr => 0x1ff30, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB4_CH0.LOCALOFFSET" => { type => "field", addr => 0x1ff30, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RXTXBB4_CH0.OFSTCORRHII" => { type => "field", addr => 0x1ff30, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB4_CH0.OFSTCORRHIQ" => { type => "field", addr => 0x1ff30, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB4_CH0.OFSTCORRLOI" => { type => "field", addr => 0x1ff30, width => 5, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB4_CH0.OFSTCORRLOQ" => { type => "field", addr => 0x1ff30, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB4_CH0.OFSTCORRI2VI" => { type => "field", addr => 0x1ff30, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RXTXBB4_CH0.OFSTCORRI2VQ" => { type => "field", addr => 0x1ff30, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_RF2G1_CH0" => { type => "reg", addr => 0x1ff34, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RF2G1_CH0.PDIC25U_LNA" => { type => "field", addr => 0x1ff34, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G1_CH0.DB" => { type => "field", addr => 0x1ff34, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G1_CH0.OB" => { type => "field", addr => 0x1ff34, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G1_CH0.LOATB_SEL" => { type => "field", addr => 0x1ff34, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH0.RXATB_SEL" => { type => "field", addr => 0x1ff34, width => 3, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH0.TXATB_SEL" => { type => "field", addr => 0x1ff34, width => 3, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH0.LOCONTROL" => { type => "field", addr => 0x1ff34, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH0.PACA_SEL" => { type => "field", addr => 0x1ff34, width => 2, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "MERLIN_RF2G1_CH0.PDIC25U_VGM" => { type => "field", addr => 0x1ff34, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G1_CH0.REGLNA_BYPASS" => { type => "field", addr => 0x1ff34, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH0.REGLO_BYPASS" => { type => "field", addr => 0x1ff34, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G1_CH0.SPARES" => { type => "field", addr => 0x1ff34, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0" => { type => "reg", addr => 0x1ff38, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RF2G2_CH0.PDLNA" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDDIV" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDPADRV" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDPAOUT" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDREGLNA" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDREGLO" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDVGM" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDRXLO" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDTXLO" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDTXMIX" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDIR25U_TXMIX" => { type => "field", addr => 0x1ff38, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G2_CH0.PDIR25U_TXPA" => { type => "field", addr => 0x1ff38, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF2G2_CH0.PDIC25U_TXPA" => { type => "field", addr => 0x1ff38, width => 3, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G2_CH0.PDIC25U_TXRF" => { type => "field", addr => 0x1ff38, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G2_CH0.PDIC25U_RXRF" => { type => "field", addr => 0x1ff38, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_RF2G2_CH0.PDIC50U_DIV" => { type => "field", addr => 0x1ff38, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF2G2_CH0.PDIC25U_VREGLO" => { type => "field", addr => 0x1ff38, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_RF2G2_CH0.PDIR25U_VREGLO" => { type => "field", addr => 0x1ff38, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_RF5G1_CH0" => { type => "reg", addr => 0x1ff3c, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RF5G1_CH0.PDTXLO5" => { type => "field", addr => 0x1ff3c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH0.PDTXMIX5" => { type => "field", addr => 0x1ff3c, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH0.PDTXBUF5" => { type => "field", addr => 0x1ff3c, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH0.PDPADRV5" => { type => "field", addr => 0x1ff3c, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH0.PDPAOUT5" => { type => "field", addr => 0x1ff3c, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH0.PACASCBIAS" => { type => "field", addr => 0x1ff3c, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_RF5G1_CH0.PWDTXPKD" => { type => "field", addr => 0x1ff3c, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_RF5G1_CH0.DB5" => { type => "field", addr => 0x1ff3c, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G1_CH0.OB5" => { type => "field", addr => 0x1ff3c, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G1_CH0.TX5_ATB_SEL" => { type => "field", addr => 0x1ff3c, width => 3, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH0.LO5CONTROL" => { type => "field", addr => 0x1ff3c, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH0.REGLO_BYPASS5" => { type => "field", addr => 0x1ff3c, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH0.PDREGLO5" => { type => "field", addr => 0x1ff3c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G1_CH0.SPARE" => { type => "field", addr => 0x1ff3c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH0" => { type => "reg", addr => 0x1ff40, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RF5G2_CH0.REGFE_BYPASS5" => { type => "field", addr => 0x1ff40, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH0.PDREGFE5" => { type => "field", addr => 0x1ff40, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH0.PDRXLO5" => { type => "field", addr => 0x1ff40, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH0.PDVGM5" => { type => "field", addr => 0x1ff40, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH0.PDCSLNA5" => { type => "field", addr => 0x1ff40, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH0.PDRFVGA5" => { type => "field", addr => 0x1ff40, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH0.RX5_ATB_SEL" => { type => "field", addr => 0x1ff40, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G2_CH0.PDBIRTXMIX" => { type => "field", addr => 0x1ff40, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G2_CH0.PDBIRTXPA" => { type => "field", addr => 0x1ff40, width => 3, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G2_CH0.PDBIR1" => { type => "field", addr => 0x1ff40, width => 3, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G2_CH0.PDBIR2" => { type => "field", addr => 0x1ff40, width => 3, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G2_CH0.SPARE" => { type => "field", addr => 0x1ff40, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_RF5G3_CH0" => { type => "reg", addr => 0x1ff44, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_RF5G3_CH0.PDBICTXBUF" => { type => "field", addr => 0x1ff44, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH0.PDBICTXPA" => { type => "field", addr => 0x1ff44, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH0.PDBICTXMIX" => { type => "field", addr => 0x1ff44, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH0.PDBIC1" => { type => "field", addr => 0x1ff44, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH0.PDBIC2" => { type => "field", addr => 0x1ff44, width => 3, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH0.PDBIC3" => { type => "field", addr => 0x1ff44, width => 3, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH0.PDBIBCLNA" => { type => "field", addr => 0x1ff44, width => 3, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH0.PDBIBCRFVGA" => { type => "field", addr => 0x1ff44, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH0.PDBIBCVGM" => { type => "field", addr => 0x1ff44, width => 3, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_RF5G3_CH0.SPARE" => { type => "field", addr => 0x1ff44, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1" => { type => "reg", addr => 0x1ff48, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_SYNTH1.PWD_BIAS" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWD_CP" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWD_VCMON" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWD_VCO" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWD_PRESC" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWD_LOBUF2G" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWD_LOBUF5G" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWD_LODIV" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWD_LOMIX" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWUP_LOREF" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.VCOREGBYPASS" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.VCOREGLEVEL" => { type => "field", addr => 0x1ff48, width => 2, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_SYNTH1.VCOBUFBIAS" => { type => "field", addr => 0x1ff48, width => 2, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_SYNTH1.PWUP_VCOBUF_PD" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWUP_LOBUF2G_PD" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWUP_LOBUF5G_PD" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWUP_LODIV_PD" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.PWUP_LOMIX_PD" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.MONITOR_FB" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.MONITOR_REF" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.MONITOR_FB_DIV2" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.MONITOR_VC2HIGH" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.MONITOR_VC2LOW" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.MONITOR_SYNTHLOCKVCOK" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.CON_VDDVCOREG" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.CON_IVCOREG" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.CON_IVCOBUF" => { type => "field", addr => 0x1ff48, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH1.SEL_VCMONABUS" => { type => "field", addr => 0x1ff48, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH2" => { type => "reg", addr => 0x1ff4c, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_SYNTH2.VC_CAL_REF" => { type => "field", addr => 0x1ff4c, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH2.VC_HI_REF" => { type => "field", addr => 0x1ff4c, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_SYNTH2.VC_MID_REF" => { type => "field", addr => 0x1ff4c, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH2.VC_LOW_REF" => { type => "field", addr => 0x1ff4c, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH2.CPBIAS" => { type => "field", addr => 0x1ff4c, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_SYNTH2.CPSTEERING_EN_INTN" => { type => "field", addr => 0x1ff4c, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_SYNTH2.CPLOWLK" => { type => "field", addr => 0x1ff4c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH2.LOOPLEAKCUR" => { type => "field", addr => 0x1ff4c, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH2.CAPRANGE1" => { type => "field", addr => 0x1ff4c, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH2.CAPRANGE2" => { type => "field", addr => 0x1ff4c, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "MERLIN_SYNTH2.CAPRANGE3" => { type => "field", addr => 0x1ff4c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xC }, "MERLIN_SYNTH3" => { type => "reg", addr => 0x1ff50, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_SYNTH3.DIS_CLK_XTAL" => { type => "field", addr => 0x1ff50, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH3.SEL_CLK_DIV2" => { type => "field", addr => 0x1ff50, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_SYNTH3.WAIT_SHORTR_PWRUP" => { type => "field", addr => 0x1ff50, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x14 }, "MERLIN_SYNTH3.WAIT_PWRUP" => { type => "field", addr => 0x1ff50, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x08 }, "MERLIN_SYNTH3.WAIT_CAL_BIN" => { type => "field", addr => 0x1ff50, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x14 }, "MERLIN_SYNTH3.WAIT_CAL_LIN" => { type => "field", addr => 0x1ff50, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x14 }, "MERLIN_SYNTH3.WAIT_VC_CHECK" => { type => "field", addr => 0x1ff50, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x14 }, "MERLIN_SYNTH4" => { type => "reg", addr => 0x1ff54, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_SYNTH4.DIS_LIN_CAPSEARCH" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.DIS_LOSTVC" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.ALWAYS_SHORTR" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.SHORTR_UNTIL_LOCKED" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_SYNTH4.FORCE_PINVC" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.FORCE_VCOCAP" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.VCOCAP_OVR" => { type => "field", addr => 0x1ff54, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "MERLIN_SYNTH4.VCOCAPPULLUP" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_SYNTH4.CLKXTAL_EDGE_SEL" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.FORCE_LO_ON" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.PFDDELAY_FRACN" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_SYNTH4.PFD_DISABLE" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.PRESCSEL" => { type => "field", addr => 0x1ff54, width => 2, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_SYNTH4.RESET_PRESC" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.SDM_DISABLE" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.SDM_MODE" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.SDM_DITHER" => { type => "field", addr => 0x1ff54, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.PSCOUNT_FBSEL" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.FORCE_LOBUF5GTUNE" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.LOBUF5GTUNE_OVR" => { type => "field", addr => 0x1ff54, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "MERLIN_SYNTH4.LONGSHIFTSEL" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH4.FORCE_SHIFTREG" => { type => "field", addr => 0x1ff54, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH5" => { type => "reg", addr => 0x1ff58, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_SYNTH5.IRCP" => { type => "field", addr => 0x1ff58, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH5.IRVCMON" => { type => "field", addr => 0x1ff58, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH5.IRLOPKDET" => { type => "field", addr => 0x1ff58, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH5.ICPRESC" => { type => "field", addr => 0x1ff58, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH5.ICLODIV" => { type => "field", addr => 0x1ff58, width => 3, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH5.ICLOMIX" => { type => "field", addr => 0x1ff58, width => 3, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH5.ICVCOREG" => { type => "field", addr => 0x1ff58, width => 3, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH5.ICVCO" => { type => "field", addr => 0x1ff58, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH5.ICLOBUF2G" => { type => "field", addr => 0x1ff58, width => 3, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH5.ICLOBUF5G" => { type => "field", addr => 0x1ff58, width => 3, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH5.ICPKCOMP" => { type => "field", addr => 0x1ff58, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "MERLIN_SYNTH6" => { type => "reg", addr => 0x1ff5c, width => 32, athEmulAttr => 0, acc => "RO" }, "MERLIN_SYNTH6.SYNTH_ON" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.SYNTH_SM_STATE" => { type => "field", addr => 0x1ff5c, width => 4, bitOffset => 27, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.CAP_SEARCH" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.SYNTH_LOCK_VC_OK" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.PIN_VC" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.VCO_CAP_ST" => { type => "field", addr => 0x1ff5c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.SHORT_R" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.RESET_RFD" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.RESET_PFD" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.RESET_PSCOUNTERS" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.RESET_SDM_B" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.VC2HIGH" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.VC2LOW" => { type => "field", addr => 0x1ff5c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.LOOP_IP" => { type => "field", addr => 0x1ff5c, width => 7, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH6.LOBUF5GTUNE" => { type => "field", addr => 0x1ff5c, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_SYNTH7" => { type => "reg", addr => 0x1ff60, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_SYNTH7.LOADSYNTHCHANNEL" => { type => "field", addr => 0x1ff60, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH7.FRACMODE" => { type => "field", addr => 0x1ff60, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH7.AMODEREFSEL" => { type => "field", addr => 0x1ff60, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH7.CHANSEL" => { type => "field", addr => 0x1ff60, width => 9, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH7.CHANFRAC" => { type => "field", addr => 0x1ff60, width => 17, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH7.FORCE_FRACLSB" => { type => "field", addr => 0x1ff60, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH7.OVRCHANDECODER" => { type => "field", addr => 0x1ff60, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH8" => { type => "reg", addr => 0x1ff64, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_SYNTH8.REFDIVB" => { type => "field", addr => 0x1ff64, width => 5, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_SYNTH8.LOOP_3RD_ORDER_RB" => { type => "field", addr => 0x1ff64, width => 5, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "MERLIN_SYNTH8.LOOP_CPB" => { type => "field", addr => 0x1ff64, width => 5, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "MERLIN_SYNTH8.LOOP_RSB" => { type => "field", addr => 0x1ff64, width => 5, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "MERLIN_SYNTH8.LOOP_CSB" => { type => "field", addr => 0x1ff64, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_SYNTH8.LOOP_ICPB" => { type => "field", addr => 0x1ff64, width => 7, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x07 }, "MERLIN_SYNTH8.CPSTEERING_EN_FRACN" => { type => "field", addr => 0x1ff64, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH9" => { type => "reg", addr => 0x1ff68, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_SYNTH9.REFDIVA" => { type => "field", addr => 0x1ff68, width => 5, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "MERLIN_SYNTH9.LOOP_3RD_ORDER_RA" => { type => "field", addr => 0x1ff68, width => 5, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH9.LOOP_CPA0" => { type => "field", addr => 0x1ff68, width => 5, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_SYNTH9.LOOP_RSA0" => { type => "field", addr => 0x1ff68, width => 5, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x04 }, "MERLIN_SYNTH9.LOOP_CSA0" => { type => "field", addr => 0x1ff68, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0xb }, "MERLIN_SYNTH9.LOOP_ICPA0" => { type => "field", addr => 0x1ff68, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "MERLIN_SYNTH9.SLOPE_ICPA0" => { type => "field", addr => 0x1ff68, width => 3, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "MERLIN_SYNTH9.PFDDELAY_INTN" => { type => "field", addr => 0x1ff68, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH10" => { type => "reg", addr => 0x1ff6c, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_SYNTH10.LOOP_CPA1" => { type => "field", addr => 0x1ff6c, width => 5, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_SYNTH10.LOOP_RSA1" => { type => "field", addr => 0x1ff6c, width => 5, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH10.LOOP_CSA1" => { type => "field", addr => 0x1ff6c, width => 4, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0xb }, "MERLIN_SYNTH10.LOOP_ICPA1" => { type => "field", addr => 0x1ff6c, width => 4, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x05 }, "MERLIN_SYNTH10.SLOPE_ICPA1" => { type => "field", addr => 0x1ff6c, width => 3, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "MERLIN_SYNTH10.SPARE" => { type => "field", addr => 0x1ff6c, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH11" => { type => "reg", addr => 0x1ff70, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_SYNTH11.LOOP_CPA2" => { type => "field", addr => 0x1ff70, width => 5, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "MERLIN_SYNTH11.LOOP_RSA2" => { type => "field", addr => 0x1ff70, width => 5, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "MERLIN_SYNTH11.LOOP_CSA2" => { type => "field", addr => 0x1ff70, width => 4, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0xb }, "MERLIN_SYNTH11.LOOP_ICPA2" => { type => "field", addr => 0x1ff70, width => 4, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0b }, "MERLIN_SYNTH11.SLOPE_ICPA2" => { type => "field", addr => 0x1ff70, width => 3, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "MERLIN_SYNTH11.CPSTEERING_MODE" => { type => "field", addr => 0x1ff70, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_SYNTH11.LO2GSEL" => { type => "field", addr => 0x1ff70, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH11.LOREFSEL" => { type => "field", addr => 0x1ff70, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH11.FORCE_LOBUF5G_ON" => { type => "field", addr => 0x1ff70, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_SYNTH11.SPARE" => { type => "field", addr => 0x1ff70, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS1" => { type => "reg", addr => 0x1ff74, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_BIAS1.PADON" => { type => "field", addr => 0x1ff74, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "MERLIN_BIAS1.SEL_BIAS" => { type => "field", addr => 0x1ff74, width => 6, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "MERLIN_BIAS1.BIAS1_SPARE" => { type => "field", addr => 0x1ff74, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "MERLIN_BIAS1.PWD_ICXTAL25" => { type => "field", addr => 0x1ff74, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS1.PWD_IRXTAL25" => { type => "field", addr => 0x1ff74, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS1.PWD_ICXPALDO25" => { type => "field", addr => 0x1ff74, width => 3, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS1.PWD_IRXPALDO25" => { type => "field", addr => 0x1ff74, width => 3, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS1.PWD_ICRXLDO25" => { type => "field", addr => 0x1ff74, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS1.PWD_IRRXLDO25" => { type => "field", addr => 0x1ff74, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS1.PWD_ICPLL25" => { type => "field", addr => 0x1ff74, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS1.PWD_IRPLL25" => { type => "field", addr => 0x1ff74, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS1.PWD_ICPCIE50" => { type => "field", addr => 0x1ff74, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS1.PWD_IRPCIE50" => { type => "field", addr => 0x1ff74, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2" => { type => "reg", addr => 0x1ff78, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_BIAS2.PWD_ICSYNTH50" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_IRSYNTH50" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_ICRF5G50" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_ICRF2G50" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_IRRF5G50" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_IRRF2G50" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_ICBB50" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_IRBB50" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_ICDACINTFACE25" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_ICADCCOMPI25" => { type => "field", addr => 0x1ff78, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS2.PWD_ICADCCOMPQ25" => { type => "field", addr => 0x1ff78, width => 3, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS2.PWD_ICADCREFBUFI12P5" => { type => "field", addr => 0x1ff78, width => 3, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "MERLIN_BIAS2.PWD_ICADCREFBUFQ12P5" => { type => "field", addr => 0x1ff78, width => 3, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "MERLIN_BIAS2.PWD_ICADCREFOPAMPI25" => { type => "field", addr => 0x1ff78, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS2.PWD_ICADCREFOPAMPQ25" => { type => "field", addr => 0x1ff78, width => 3, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS2.PWD_IRADCREFMSTRI12P5" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_IRADCREFMSTRQ12P5" => { type => "field", addr => 0x1ff78, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS2.PWD_ICDAC50" => { type => "field", addr => 0x1ff78, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS3" => { type => "reg", addr => 0x1ff7c, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_BIAS3.PWD_ICTXPC25" => { type => "field", addr => 0x1ff7c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS3.PWD_IRTXPC25" => { type => "field", addr => 0x1ff7c, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS3.PWD_ICTSENS25" => { type => "field", addr => 0x1ff7c, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS3.PWD_IRTSENS25" => { type => "field", addr => 0x1ff7c, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS3.PWD_IC25SPARE1" => { type => "field", addr => 0x1ff7c, width => 3, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS3.PWD_IC25SPARE2" => { type => "field", addr => 0x1ff7c, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS3.PWD_IC25SPARE3" => { type => "field", addr => 0x1ff7c, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS3.PWD_IC25SPARE4" => { type => "field", addr => 0x1ff7c, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS3.PWD_IR25SPARE1" => { type => "field", addr => 0x1ff7c, width => 3, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS3.PWD_IR25SPARE2" => { type => "field", addr => 0x1ff7c, width => 3, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS3.PWD_IR25SPARE3" => { type => "field", addr => 0x1ff7c, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS3.PWD_IR25SPARE4" => { type => "field", addr => 0x1ff7c, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS3.PWD_ICLOLDO25" => { type => "field", addr => 0x1ff7c, width => 3, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS3.BIAS3_SPARE" => { type => "field", addr => 0x1ff7c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS4" => { type => "reg", addr => 0x1ff80, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_BIAS4.BIAS4_SEL_SPARE" => { type => "field", addr => 0x1ff80, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_BIAS4.PWD_ICXLNA2G50" => { type => "field", addr => 0x1ff80, width => 3, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS4.PWD_ICXLNA5G50" => { type => "field", addr => 0x1ff80, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS4.PWD_IRLOLDO25" => { type => "field", addr => 0x1ff80, width => 3, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_BIAS4.BIAS4_SPARE" => { type => "field", addr => 0x1ff80, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_GAIN0" => { type => "reg", addr => 0x1ff84, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_GAIN0.TX6DBLOQGAIN" => { type => "field", addr => 0x1ff84, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_GAIN0.TX1DBLOQGAIN" => { type => "field", addr => 0x1ff84, width => 3, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "MERLIN_GAIN0.TXV2IGAIN" => { type => "field", addr => 0x1ff84, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_GAIN0.PABUF5GN" => { type => "field", addr => 0x1ff84, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_GAIN0.PADRVGN" => { type => "field", addr => 0x1ff84, width => 3, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_GAIN0.PAOUT2GN" => { type => "field", addr => 0x1ff84, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_GAIN0.LNAON" => { type => "field", addr => 0x1ff84, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_GAIN0.LNAGAIN" => { type => "field", addr => 0x1ff84, width => 4, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0xF }, "MERLIN_GAIN0.RFVGA5GAIN" => { type => "field", addr => 0x1ff84, width => 2, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_GAIN0.RFGMGN" => { type => "field", addr => 0x1ff84, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_GAIN0.RX6DBLOQGAIN" => { type => "field", addr => 0x1ff84, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_GAIN0.RX1DBLOQGAIN" => { type => "field", addr => 0x1ff84, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "MERLIN_GAIN0.RX6DBHIQGAIN" => { type => "field", addr => 0x1ff84, width => 2, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_GAIN0.SPARE" => { type => "field", addr => 0x1ff84, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_GAIN1" => { type => "reg", addr => 0x1ff88, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_GAIN1.TX6DBLOQGAIN" => { type => "field", addr => 0x1ff88, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_GAIN1.TX1DBLOQGAIN" => { type => "field", addr => 0x1ff88, width => 3, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "MERLIN_GAIN1.TXV2IGAIN" => { type => "field", addr => 0x1ff88, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_GAIN1.PABUF5GN" => { type => "field", addr => 0x1ff88, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_GAIN1.PADRVGN" => { type => "field", addr => 0x1ff88, width => 3, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_GAIN1.PAOUT2GN" => { type => "field", addr => 0x1ff88, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_GAIN1.LNAON" => { type => "field", addr => 0x1ff88, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_GAIN1.LNAGAIN" => { type => "field", addr => 0x1ff88, width => 4, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0xF }, "MERLIN_GAIN1.RFVGA5GAIN" => { type => "field", addr => 0x1ff88, width => 2, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_GAIN1.RFGMGN" => { type => "field", addr => 0x1ff88, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "MERLIN_GAIN1.RX6DBLOQGAIN" => { type => "field", addr => 0x1ff88, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_GAIN1.RX1DBLOQGAIN" => { type => "field", addr => 0x1ff88, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "MERLIN_GAIN1.RX6DBHIQGAIN" => { type => "field", addr => 0x1ff88, width => 2, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "MERLIN_GAIN1.SPARE" => { type => "field", addr => 0x1ff88, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0" => { type => "reg", addr => 0x1ff8c, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_TOP0.LOCALTXGAIN" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.LOCALRXGAIN" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.LOCALMODE" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.CALFC" => { type => "field", addr => 0x1ff8c, width => 2, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.CALDC" => { type => "field", addr => 0x1ff8c, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.CAL_RESIDUE" => { type => "field", addr => 0x1ff8c, width => 2, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.CALTX" => { type => "field", addr => 0x1ff8c, width => 2, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.BMODE" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_TOP0.BMODERXTX" => { type => "field", addr => 0x1ff8c, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.TURBOMODE" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.SYNTHON" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.RXON" => { type => "field", addr => 0x1ff8c, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.TXON" => { type => "field", addr => 0x1ff8c, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.PAON" => { type => "field", addr => 0x1ff8c, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.XLNAON" => { type => "field", addr => 0x1ff8c, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_TOP0.XPAON" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.LOCALXTAL" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.PWDCLKIN" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.OSCON" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_TOP0.SCLKEN_FORCE" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.SYNTHON_FORCE" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.PWDBIAS" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP0.FORCEMSBLOW" => { type => "field", addr => 0x1ff8c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1" => { type => "reg", addr => 0x1ff90, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_TOP1.REVID" => { type => "field", addr => 0x1ff90, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MERLIN_TOP1.INT2PAD" => { type => "field", addr => 0x1ff90, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.INTH2PAD" => { type => "field", addr => 0x1ff90, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.PAD2GND" => { type => "field", addr => 0x1ff90, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.INT2GND" => { type => "field", addr => 0x1ff90, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.LOCALADDAC" => { type => "field", addr => 0x1ff90, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.PWDPLL" => { type => "field", addr => 0x1ff90, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.PWDADC" => { type => "field", addr => 0x1ff90, width => 2, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.PWDDAC" => { type => "field", addr => 0x1ff90, width => 2, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.DACLPMODE" => { type => "field", addr => 0x1ff90, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.INV_CLK160_ADC" => { type => "field", addr => 0x1ff90, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.PLL_ATB" => { type => "field", addr => 0x1ff90, width => 2, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP1.PLL_FILTER" => { type => "field", addr => 0x1ff90, width => 8, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x34 }, "MERLIN_TOP1.PLL_ICP" => { type => "field", addr => 0x1ff90, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "MERLIN_TOP1.PLL_SCLAMP" => { type => "field", addr => 0x1ff90, width => 3, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "MERLIN_TOP1.PLL_SVREG" => { type => "field", addr => 0x1ff90, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_TOP2" => { type => "reg", addr => 0x1ff94, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_TOP2.XPABIAS_LVL" => { type => "field", addr => 0x1ff94, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_TOP2.FORCE_XLDO_ON" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.XLNABUFMODE" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.XLNAISEL" => { type => "field", addr => 0x1ff94, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "MERLIN_TOP2.XLNABUFIN" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.NOTCXODET" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.PWDXINPAD" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.PWDCLKIND" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.LOCALBIAS" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.LOCALBIAS2X" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MERLIN_TOP2.XTALDIV" => { type => "field", addr => 0x1ff94, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.TXPC_NEGOUT" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.TXPC_TEST" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.TXPC_TESTDAC" => { type => "field", addr => 0x1ff94, width => 6, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x20 }, "MERLIN_TOP2.TXPC_TESTGAIN" => { type => "field", addr => 0x1ff94, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.TXPC_TESTPWD" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.TXPC_XPDBS" => { type => "field", addr => 0x1ff94, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.TXPC_CLKDELAY" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.DATAOUTSEL" => { type => "field", addr => 0x1ff94, width => 2, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP2.BYPASSVREGLO" => { type => "field", addr => 0x1ff94, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP3" => { type => "reg", addr => 0x1ff98, width => 32, athEmulAttr => 0, acc => "RW" }, "MERLIN_TOP3.LOCALPLLDIV" => { type => "field", addr => 0x1ff98, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MERLIN_TOP3.PLLREFDIVA" => { type => "field", addr => 0x1ff98, width => 4, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "MERLIN_TOP3.PLLREFDIVB" => { type => "field", addr => 0x1ff98, width => 4, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "MERLIN_TOP3.PLLFBDIVA" => { type => "field", addr => 0x1ff98, width => 10, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x28 }, "MERLIN_TOP3.PLLFBDIVB" => { type => "field", addr => 0x1ff98, width => 10, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x2c }, "MERLIN_TOP3.VREGLO_ATBSEL" => { type => "field", addr => 0x1ff98, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wmac_top_reg_map Register/Field definitions ################################################################### ################################################################### ## wmac_top_reg_map.mac_pdg_reg Register/Field definitions ################################################################### "PDG_FSM_STATUS" => { type => "reg", addr => 0x30000, width => 32, athEmulAttr => 0, acc => "RO" }, "PDG_FSM_STATUS.txpcu_fsm_status" => { type => "field", addr => 0x30000, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "PDG_FSM_STATUS.comp_fsm_status" => { type => "field", addr => 0x30000, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "PDG_FSM_STATUS.main_fsm_status" => { type => "field", addr => 0x30000, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "PDG_TESTBUS_LS" => { type => "reg", addr => 0x30004, width => 32, athEmulAttr => 0, acc => "RO" }, "PDG_TESTBUS_LS.testbus" => { type => "field", addr => 0x30004, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PDG_TESTBUS_MS" => { type => "reg", addr => 0x30008, width => 32, athEmulAttr => 0, acc => "RO" }, "PDG_TESTBUS_MS.testbus" => { type => "field", addr => 0x30008, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PDG_DBG_COUNTERS" => { type => "reg", addr => 0x3000c, width => 32, athEmulAttr => 0, acc => "RO" }, "PDG_DBG_COUNTERS.num_of_pdg_response" => { type => "field", addr => 0x3000c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PDG_DBG_COUNTERS.num_of_ppdu_setup" => { type => "field", addr => 0x3000c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PDG_DBG_COUNTERS.num_of_mpdu_length_info" => { type => "field", addr => 0x3000c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PDG_DBG_COUNTERS.num_of_fes_setup" => { type => "field", addr => 0x3000c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PDG_CONFIG" => { type => "reg", addr => 0x30010, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_CONFIG.sw_11j_11af_en" => { type => "field", addr => 0x30010, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CONFIG.sw_11j_11af_scale_factor" => { type => "field", addr => 0x30010, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CONFIG.sw_sifs_time" => { type => "field", addr => 0x30010, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_SCRAMBLING_OVERIDE" => { type => "reg", addr => 0x30014, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_SCRAMBLING_OVERIDE.force_sw_shift_reg_word" => { type => "field", addr => 0x30014, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_SCRAMBLING_OVERIDE.scrambling_shift_reg_word" => { type => "field", addr => 0x30014, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RESPONSE_CHAIN_MASK" => { type => "reg", addr => 0x30018, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_RESPONSE_CHAIN_MASK.resp_chain_mask_reg" => { type => "field", addr => 0x30018, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RESPONSE_PAPRD_CHAIN_MASK" => { type => "reg", addr => 0x3001c, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_RESPONSE_PAPRD_CHAIN_MASK.resp_paprd_chain_mask_reg" => { type => "field", addr => 0x3001c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_WATCHDOG" => { type => "reg", addr => 0x30020, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_WATCHDOG.status" => { type => "field", addr => 0x30020, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PDG_WATCHDOG.limit" => { type => "field", addr => 0x30020, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, "PDG_DEBUG_MODULE_SELECT" => { type => "reg", addr => 0x30024, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_DEBUG_MODULE_SELECT.debug_module_select" => { type => "field", addr => 0x30024, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CLOCK_GATE_DISABLE" => { type => "reg", addr => 0x3002c, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_CLOCK_GATE_DISABLE.clock_gate_disable" => { type => "field", addr => 0x3002c, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7F }, "PDG_SLOT_TIME" => { type => "reg", addr => 0x30040, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_SLOT_TIME.pdg_slot_time" => { type => "field", addr => 0x30040, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_FEATURE_ENABLE" => { type => "reg", addr => 0x30044, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_FEATURE_ENABLE.enable_mprot_update_scram_seed" => { type => "field", addr => 0x30044, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_FEATURE_ENABLE.enable_eco" => { type => "field", addr => 0x30044, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_MCP" => { type => "reg", addr => 0x30048, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_MCP.bit_for_comp_eng_mcp" => { type => "field", addr => 0x30048, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "PDG_MCP.bit_for_comp_eng_nsym_mcp" => { type => "field", addr => 0x30048, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "PDG_EVENT_DEBUG_SELECT1" => { type => "reg", addr => 0x3004c, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_EVENT_DEBUG_SELECT1.event_select_22_24_26" => { type => "field", addr => 0x3004c, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT1.event_select_21_23_25" => { type => "field", addr => 0x3004c, width => 5, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT1.event_select_10to20" => { type => "field", addr => 0x3004c, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT1.event_select_8" => { type => "field", addr => 0x3004c, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT1.event_select_7" => { type => "field", addr => 0x3004c, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT2" => { type => "reg", addr => 0x30050, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_EVENT_DEBUG_SELECT2.event_select_31" => { type => "field", addr => 0x30050, width => 5, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT2.event_select_30" => { type => "field", addr => 0x30050, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT2.event_select_29" => { type => "field", addr => 0x30050, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT2.event_select_28" => { type => "field", addr => 0x30050, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT3" => { type => "reg", addr => 0x30054, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_EVENT_DEBUG_SELECT3.event_select_36" => { type => "field", addr => 0x30054, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT3.event_select_35" => { type => "field", addr => 0x30054, width => 5, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT3.event_select_34" => { type => "field", addr => 0x30054, width => 5, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT3.event_select_33" => { type => "field", addr => 0x30054, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_DEBUG_SELECT3.event_select_32" => { type => "field", addr => 0x30054, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_MASK_31_0" => { type => "reg", addr => 0x30058, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_EVENT_MASK_31_0.event_mask" => { type => "field", addr => 0x30058, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_EVENT_MASK_64_32" => { type => "reg", addr => 0x3005c, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_EVENT_MASK_64_32.event_mask" => { type => "field", addr => 0x3005c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_OFDM_11A_PKT_PHY_LIMIT" => { type => "reg", addr => 0x30060, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_OFDM_11A_PKT_PHY_LIMIT.ofdm_11a_time_limit" => { type => "field", addr => 0x30060, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xC1C }, "PDG_OFDM_11NAC_PKT_PHY_LIMIT" => { type => "reg", addr => 0x30064, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_OFDM_11NAC_PKT_PHY_LIMIT.ofdm_11nac_time_limit" => { type => "field", addr => 0x30064, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x156C }, "PDG_CBF_RESPONSE_PHY_DESC_CFG" => { type => "reg", addr => 0x30068, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_CBF_RESPONSE_PHY_DESC_CFG.tx_pwr_sec80" => { type => "field", addr => 0x30068, width => 7, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "PDG_CBF_RESPONSE_PHY_DESC_CFG.measure_power" => { type => "field", addr => 0x30068, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CBF_RESPONSE_PHY_DESC_CFG.clpc_enable" => { type => "field", addr => 0x30068, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CBF_RESPONSE_PHY_DESC_CFG.tx_pwr" => { type => "field", addr => 0x30068, width => 7, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "PDG_CBF_RESPONSE_PHY_DESC_CFG.dpd_enable" => { type => "field", addr => 0x30068, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CBF_RESPONSE_PHY_DESC_CFG.tpc_init_pwr_cfg" => { type => "field", addr => 0x30068, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RTT_HTVHT_RESPONSE_PHY_DESC_CFG" => { type => "reg", addr => 0x3006c, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_RTT_HTVHT_RESPONSE_PHY_DESC_CFG.tx_pwr_sec80" => { type => "field", addr => 0x3006c, width => 7, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "PDG_RTT_HTVHT_RESPONSE_PHY_DESC_CFG.measure_power" => { type => "field", addr => 0x3006c, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RTT_HTVHT_RESPONSE_PHY_DESC_CFG.clpc_enable" => { type => "field", addr => 0x3006c, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RTT_HTVHT_RESPONSE_PHY_DESC_CFG.tx_pwr" => { type => "field", addr => 0x3006c, width => 7, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "PDG_RTT_HTVHT_RESPONSE_PHY_DESC_CFG.dpd_enable" => { type => "field", addr => 0x3006c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RTT_HTVHT_RESPONSE_PHY_DESC_CFG.tpc_init_pwr_cfg" => { type => "field", addr => 0x3006c, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RTT_LEGACY_RESPONSE_PHY_DESC_CFG" => { type => "reg", addr => 0x30070, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_RTT_LEGACY_RESPONSE_PHY_DESC_CFG.tx_pwr_sec80" => { type => "field", addr => 0x30070, width => 7, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "PDG_RTT_LEGACY_RESPONSE_PHY_DESC_CFG.measure_power" => { type => "field", addr => 0x30070, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RTT_LEGACY_RESPONSE_PHY_DESC_CFG.clpc_enable" => { type => "field", addr => 0x30070, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RTT_LEGACY_RESPONSE_PHY_DESC_CFG.tx_pwr" => { type => "field", addr => 0x30070, width => 7, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "PDG_RTT_LEGACY_RESPONSE_PHY_DESC_CFG.dpd_enable" => { type => "field", addr => 0x30070, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RTT_LEGACY_RESPONSE_PHY_DESC_CFG.tpc_init_pwr_cfg" => { type => "field", addr => 0x30070, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_OFDM_RESPONSE_PHY_DESC_CFG" => { type => "reg", addr => 0x30074, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_OFDM_RESPONSE_PHY_DESC_CFG.tx_pwr_sec80" => { type => "field", addr => 0x30074, width => 7, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "PDG_OFDM_RESPONSE_PHY_DESC_CFG.measure_power" => { type => "field", addr => 0x30074, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_OFDM_RESPONSE_PHY_DESC_CFG.clpc_enable" => { type => "field", addr => 0x30074, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_OFDM_RESPONSE_PHY_DESC_CFG.tx_pwr" => { type => "field", addr => 0x30074, width => 7, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "PDG_OFDM_RESPONSE_PHY_DESC_CFG.dpd_enable" => { type => "field", addr => 0x30074, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_OFDM_RESPONSE_PHY_DESC_CFG.tpc_init_pwr_cfg" => { type => "field", addr => 0x30074, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CCK_RESPONSE_PHY_DESC_CFG" => { type => "reg", addr => 0x30078, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_CCK_RESPONSE_PHY_DESC_CFG.tx_pwr_sec80" => { type => "field", addr => 0x30078, width => 7, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "PDG_CCK_RESPONSE_PHY_DESC_CFG.measure_power" => { type => "field", addr => 0x30078, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CCK_RESPONSE_PHY_DESC_CFG.clpc_enable" => { type => "field", addr => 0x30078, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CCK_RESPONSE_PHY_DESC_CFG.tx_pwr" => { type => "field", addr => 0x30078, width => 7, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "PDG_CCK_RESPONSE_PHY_DESC_CFG.dpd_enable" => { type => "field", addr => 0x30078, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CCK_RESPONSE_PHY_DESC_CFG.tpc_init_pwr_cfg" => { type => "field", addr => 0x30078, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RESPONSE_RTT_CHAIN_MASK" => { type => "reg", addr => 0x3007c, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_RESPONSE_RTT_CHAIN_MASK.resp_rtt_chain_mask_reg" => { type => "field", addr => 0x3007c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_RESPONSE_PAPRD_RTT_CHAIN_MASK" => { type => "reg", addr => 0x30080, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_RESPONSE_PAPRD_RTT_CHAIN_MASK.resp_paprd_rtt_chain_mask_reg" => { type => "field", addr => 0x30080, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PDG_CCK_PKT_PHY_LIMIT" => { type => "reg", addr => 0x30084, width => 32, athEmulAttr => 0, acc => "RW" }, "PDG_CCK_PKT_PHY_LIMIT.cck_time_limit" => { type => "field", addr => 0x30084, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x48C0 }, ################################################################### ## wmac_top_reg_map.mac_txdma_reg Register/Field definitions ################################################################### "MSDU_INFO_FETCH_CFG" => { type => "reg", addr => 0x30400, width => 32, athEmulAttr => 0, acc => "RW" }, "MSDU_INFO_FETCH_CFG.MAX_FRAG_TABLE_ENTRIES" => { type => "field", addr => 0x30400, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "TXDATA_FETCH_CFG" => { type => "reg", addr => 0x30404, width => 32, athEmulAttr => 0, acc => "RW" }, "TXDATA_FETCH_CFG.DISABLE_SPACE_AWARE_DMA" => { type => "field", addr => 0x30404, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXDATA_FETCH_CFG.MARGIN_OLE_BUF_AVAIL_DWORDS" => { type => "field", addr => 0x30404, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x14 }, "TXDMA_ERROR_OLE_CFG" => { type => "reg", addr => 0x30408, width => 32, athEmulAttr => 0, acc => "RW" }, "TXDMA_ERROR_OLE_CFG.OLE_TIMEOUT_LIMIT" => { type => "field", addr => 0x30408, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7F }, "WATCHDOG" => { type => "reg", addr => 0x3040c, width => 32, athEmulAttr => 0, acc => "RW" }, "WATCHDOG.STATUS" => { type => "field", addr => 0x3040c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WATCHDOG.LIMIT" => { type => "field", addr => 0x3040c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, "TXDMA_TRACEBUS" => { type => "reg", addr => 0x30410, width => 32, athEmulAttr => 0, acc => "RW" }, "TXDMA_TRACEBUS.SELECT" => { type => "field", addr => 0x30410, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PROG_IDX_SIZE" => { type => "reg", addr => 0x30414, width => 32, athEmulAttr => 0, acc => "RW" }, "PROG_IDX_SIZE.MSDU_LINK_MULT_SHIFTED_IDX_BY3" => { type => "field", addr => 0x30414, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PROG_IDX_SIZE.MSDU_LINK_SHIFT_FACTOR" => { type => "field", addr => 0x30414, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PROG_IDX_SIZE.MPDU_LINK_MULT_SHIFTED_IDX_BY3" => { type => "field", addr => 0x30414, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PROG_IDX_SIZE.MPDU_LINK_SHIFT_FACTOR" => { type => "field", addr => 0x30414, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXDMA_TRACEBUS_READ_UPPER" => { type => "reg", addr => 0x30418, width => 32, athEmulAttr => 0, acc => "RO" }, "TXDMA_TRACEBUS_READ_UPPER.REG_8" => { type => "field", addr => 0x30418, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXDMA_TRACEBUS_READ_LOWER" => { type => "reg", addr => 0x3041c, width => 32, athEmulAttr => 0, acc => "RO" }, "TXDMA_TRACEBUS_READ_LOWER.REG_32" => { type => "field", addr => 0x3041c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x8 }, "DATA_SWAP" => { type => "reg", addr => 0x30420, width => 32, athEmulAttr => 0, acc => "RW" }, "DATA_SWAP.REG" => { type => "field", addr => 0x30420, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_COUNTER_ENABLE" => { type => "reg", addr => 0x30424, width => 32, athEmulAttr => 0, acc => "RW" }, "DEBUG_COUNTER_ENABLE.DATA_DWORDS" => { type => "field", addr => 0x30424, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_COUNTER_ENABLE.MPDU" => { type => "field", addr => 0x30424, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_COUNTER_ENABLE.FLUSH_REQ" => { type => "field", addr => 0x30424, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_COUNTER_ENABLE.FES_STATUS" => { type => "field", addr => 0x30424, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_COUNTER_ENABLE.FLUSH" => { type => "field", addr => 0x30424, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_COUNTER_ENABLE.FES_SETUP" => { type => "field", addr => 0x30424, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_FES_SETUP" => { type => "reg", addr => 0x30428, width => 32, athEmulAttr => 0, acc => "RW" }, "DEBUG_FES_SETUP.COUNT" => { type => "field", addr => 0x30428, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_FLUSH" => { type => "reg", addr => 0x3042c, width => 32, athEmulAttr => 0, acc => "RW" }, "DEBUG_FLUSH.COUNT" => { type => "field", addr => 0x3042c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_FES_STATUS" => { type => "reg", addr => 0x30430, width => 32, athEmulAttr => 0, acc => "RW" }, "DEBUG_FES_STATUS.COUNT" => { type => "field", addr => 0x30430, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_FLUSH_REQ" => { type => "reg", addr => 0x30434, width => 32, athEmulAttr => 0, acc => "RW" }, "DEBUG_FLUSH_REQ.COUNT" => { type => "field", addr => 0x30434, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_MPDU" => { type => "reg", addr => 0x30438, width => 32, athEmulAttr => 0, acc => "RW" }, "DEBUG_MPDU.COUNT" => { type => "field", addr => 0x30438, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_MSDU_DATA_DWORDS" => { type => "reg", addr => 0x3043c, width => 32, athEmulAttr => 0, acc => "RW" }, "DEBUG_MSDU_DATA_DWORDS.COUNT" => { type => "field", addr => 0x3043c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "DEBUG_STATES_0" => { type => "reg", addr => 0x30440, width => 32, athEmulAttr => 0, acc => "RO" }, "DEBUG_STATES_0.REG_25" => { type => "field", addr => 0x30440, width => 25, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x8 }, "DEBUG_STATES_1" => { type => "reg", addr => 0x30444, width => 32, athEmulAttr => 0, acc => "RO" }, "DEBUG_STATES_1.REG_16" => { type => "field", addr => 0x30444, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXDMA_EVENTBUS_31_0" => { type => "reg", addr => 0x30448, width => 32, athEmulAttr => 0, acc => "RW" }, "TXDMA_EVENTBUS_31_0.MASK" => { type => "field", addr => 0x30448, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFFF }, "TXDMA_EVENTBUS_63_32" => { type => "reg", addr => 0x3044c, width => 32, athEmulAttr => 0, acc => "RW" }, "TXDMA_EVENTBUS_63_32.MASK" => { type => "field", addr => 0x3044c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFFF }, "TXDMA_ERROR_AXI_CFG" => { type => "reg", addr => 0x30450, width => 32, athEmulAttr => 0, acc => "RW" }, "TXDMA_ERROR_AXI_CFG.AXI_TIMEOUT_LIMIT" => { type => "field", addr => 0x30450, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00FF }, "TXDMA_CLK_GATE_DISABLE" => { type => "reg", addr => 0x30454, width => 32, athEmulAttr => 0, acc => "RW" }, "TXDMA_CLK_GATE_DISABLE.VAL" => { type => "field", addr => 0x30454, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "TXDMA_MSDU_LINK_EXT_PTR_FROM_LINKLIST" => { type => "reg", addr => 0x30458, width => 32, athEmulAttr => 0, acc => "RW" }, "TXDMA_MSDU_LINK_EXT_PTR_FROM_LINKLIST.VAL" => { type => "field", addr => 0x30458, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wmac_top_reg_map.mac_rxdma_reg Register/Field definitions ################################################################### "RXDMA_CFG_RING0_0" => { type => "reg", addr => 0x30800, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING0_0.BASE_ADDR" => { type => "field", addr => 0x30800, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_1" => { type => "reg", addr => 0x30804, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING0_1.BUF_SIZE" => { type => "field", addr => 0x30804, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_1.NUM_DESCS" => { type => "field", addr => 0x30804, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2" => { type => "reg", addr => 0x30808, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING0_2.RX_FRAGINFO_SWAP" => { type => "field", addr => 0x30808, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2.RX_ATTENTION_SWAP" => { type => "field", addr => 0x30808, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2.RX_MSDU_END_SWAP" => { type => "field", addr => 0x30808, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2.RX_MSDU_START_SWAP" => { type => "field", addr => 0x30808, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2.RX_MPDU_END_SWAP" => { type => "field", addr => 0x30808, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2.RX_MPDU_START_SWAP" => { type => "field", addr => 0x30808, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2.RX_PPDU_END_SWAP" => { type => "field", addr => 0x30808, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2.RX_PPDU_START_SWAP" => { type => "field", addr => 0x30808, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2.RX_PACKET_SWAP" => { type => "field", addr => 0x30808, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2.RX_HEADER_SWAP" => { type => "field", addr => 0x30808, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_2.INTR_LWM_THRESH" => { type => "field", addr => 0x30808, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "RXDMA_CFG_RING0_3" => { type => "reg", addr => 0x3080c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING0_3.RX_PACKET_OFFSET" => { type => "field", addr => 0x3080c, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_3.RX_HEADER_OFFSET" => { type => "field", addr => 0x3080c, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_4" => { type => "reg", addr => 0x30810, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING0_4.RX_PPDU_END_OFFSET" => { type => "field", addr => 0x30810, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_4.RX_PPDU_START_OFFSET" => { type => "field", addr => 0x30810, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_5" => { type => "reg", addr => 0x30814, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING0_5.RX_MPDU_END_OFFSET" => { type => "field", addr => 0x30814, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_5.RX_MPDU_START_OFFSET" => { type => "field", addr => 0x30814, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_6" => { type => "reg", addr => 0x30818, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING0_6.RX_MSDU_END_OFFSET" => { type => "field", addr => 0x30818, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_6.RX_MSDU_START_OFFSET" => { type => "field", addr => 0x30818, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_7" => { type => "reg", addr => 0x3081c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING0_7.RX_FRAGINFO_OFFSET" => { type => "field", addr => 0x3081c, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING0_7.RX_ATTENTION_OFFSET" => { type => "field", addr => 0x3081c, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_0" => { type => "reg", addr => 0x30820, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING1_0.BASE_ADDR" => { type => "field", addr => 0x30820, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_1" => { type => "reg", addr => 0x30824, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING1_1.BUF_SIZE" => { type => "field", addr => 0x30824, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_1.NUM_DESCS" => { type => "field", addr => 0x30824, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2" => { type => "reg", addr => 0x30828, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING1_2.RX_FRAGINFO_SWAP" => { type => "field", addr => 0x30828, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2.RX_ATTENTION_SWAP" => { type => "field", addr => 0x30828, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2.RX_MSDU_END_SWAP" => { type => "field", addr => 0x30828, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2.RX_MSDU_START_SWAP" => { type => "field", addr => 0x30828, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2.RX_MPDU_END_SWAP" => { type => "field", addr => 0x30828, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2.RX_MPDU_START_SWAP" => { type => "field", addr => 0x30828, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2.RX_PPDU_END_SWAP" => { type => "field", addr => 0x30828, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2.RX_PPDU_START_SWAP" => { type => "field", addr => 0x30828, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2.RX_PACKET_SWAP" => { type => "field", addr => 0x30828, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2.RX_HEADER_SWAP" => { type => "field", addr => 0x30828, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_2.INTR_LWM_THRESH" => { type => "field", addr => 0x30828, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "RXDMA_CFG_RING1_3" => { type => "reg", addr => 0x3082c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING1_3.RX_PACKET_OFFSET" => { type => "field", addr => 0x3082c, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_3.RX_HEADER_OFFSET" => { type => "field", addr => 0x3082c, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_4" => { type => "reg", addr => 0x30830, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING1_4.RX_PPDU_END_OFFSET" => { type => "field", addr => 0x30830, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_4.RX_PPDU_START_OFFSET" => { type => "field", addr => 0x30830, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_5" => { type => "reg", addr => 0x30834, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING1_5.RX_MPDU_END_OFFSET" => { type => "field", addr => 0x30834, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_5.RX_MPDU_START_OFFSET" => { type => "field", addr => 0x30834, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_6" => { type => "reg", addr => 0x30838, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING1_6.RX_MSDU_END_OFFSET" => { type => "field", addr => 0x30838, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_6.RX_MSDU_START_OFFSET" => { type => "field", addr => 0x30838, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_7" => { type => "reg", addr => 0x3083c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING1_7.RX_FRAGINFO_OFFSET" => { type => "field", addr => 0x3083c, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING1_7.RX_ATTENTION_OFFSET" => { type => "field", addr => 0x3083c, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_0" => { type => "reg", addr => 0x30840, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING2_0.BASE_ADDR" => { type => "field", addr => 0x30840, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_1" => { type => "reg", addr => 0x30844, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING2_1.BUF_SIZE" => { type => "field", addr => 0x30844, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_1.NUM_DESCS" => { type => "field", addr => 0x30844, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2" => { type => "reg", addr => 0x30848, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING2_2.RX_FRAGINFO_SWAP" => { type => "field", addr => 0x30848, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2.RX_ATTENTION_SWAP" => { type => "field", addr => 0x30848, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2.RX_MSDU_END_SWAP" => { type => "field", addr => 0x30848, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2.RX_MSDU_START_SWAP" => { type => "field", addr => 0x30848, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2.RX_MPDU_END_SWAP" => { type => "field", addr => 0x30848, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2.RX_MPDU_START_SWAP" => { type => "field", addr => 0x30848, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2.RX_PPDU_END_SWAP" => { type => "field", addr => 0x30848, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2.RX_PPDU_START_SWAP" => { type => "field", addr => 0x30848, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2.RX_PACKET_SWAP" => { type => "field", addr => 0x30848, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2.RX_HEADER_SWAP" => { type => "field", addr => 0x30848, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_2.INTR_LWM_THRESH" => { type => "field", addr => 0x30848, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "RXDMA_CFG_RING2_3" => { type => "reg", addr => 0x3084c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING2_3.RX_PACKET_OFFSET" => { type => "field", addr => 0x3084c, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_3.RX_HEADER_OFFSET" => { type => "field", addr => 0x3084c, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_4" => { type => "reg", addr => 0x30850, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING2_4.RX_PPDU_END_OFFSET" => { type => "field", addr => 0x30850, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_4.RX_PPDU_START_OFFSET" => { type => "field", addr => 0x30850, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_5" => { type => "reg", addr => 0x30854, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING2_5.RX_MPDU_END_OFFSET" => { type => "field", addr => 0x30854, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_5.RX_MPDU_START_OFFSET" => { type => "field", addr => 0x30854, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_6" => { type => "reg", addr => 0x30858, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING2_6.RX_MSDU_END_OFFSET" => { type => "field", addr => 0x30858, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_6.RX_MSDU_START_OFFSET" => { type => "field", addr => 0x30858, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_7" => { type => "reg", addr => 0x3085c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING2_7.RX_FRAGINFO_OFFSET" => { type => "field", addr => 0x3085c, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING2_7.RX_ATTENTION_OFFSET" => { type => "field", addr => 0x3085c, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_0" => { type => "reg", addr => 0x30860, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING3_0.BASE_ADDR" => { type => "field", addr => 0x30860, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_1" => { type => "reg", addr => 0x30864, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING3_1.BUF_SIZE" => { type => "field", addr => 0x30864, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_1.NUM_DESCS" => { type => "field", addr => 0x30864, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2" => { type => "reg", addr => 0x30868, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING3_2.RX_FRAGINFO_SWAP" => { type => "field", addr => 0x30868, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2.RX_ATTENTION_SWAP" => { type => "field", addr => 0x30868, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2.RX_MSDU_END_SWAP" => { type => "field", addr => 0x30868, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2.RX_MSDU_START_SWAP" => { type => "field", addr => 0x30868, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2.RX_MPDU_END_SWAP" => { type => "field", addr => 0x30868, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2.RX_MPDU_START_SWAP" => { type => "field", addr => 0x30868, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2.RX_PPDU_END_SWAP" => { type => "field", addr => 0x30868, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2.RX_PPDU_START_SWAP" => { type => "field", addr => 0x30868, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2.RX_PACKET_SWAP" => { type => "field", addr => 0x30868, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2.RX_HEADER_SWAP" => { type => "field", addr => 0x30868, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_2.INTR_LWM_THRESH" => { type => "field", addr => 0x30868, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "RXDMA_CFG_RING3_3" => { type => "reg", addr => 0x3086c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING3_3.RX_PACKET_OFFSET" => { type => "field", addr => 0x3086c, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_3.RX_HEADER_OFFSET" => { type => "field", addr => 0x3086c, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_4" => { type => "reg", addr => 0x30870, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING3_4.RX_PPDU_END_OFFSET" => { type => "field", addr => 0x30870, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_4.RX_PPDU_START_OFFSET" => { type => "field", addr => 0x30870, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_5" => { type => "reg", addr => 0x30874, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING3_5.RX_MPDU_END_OFFSET" => { type => "field", addr => 0x30874, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_5.RX_MPDU_START_OFFSET" => { type => "field", addr => 0x30874, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_6" => { type => "reg", addr => 0x30878, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING3_6.RX_MSDU_END_OFFSET" => { type => "field", addr => 0x30878, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_6.RX_MSDU_START_OFFSET" => { type => "field", addr => 0x30878, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_7" => { type => "reg", addr => 0x3087c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_RING3_7.RX_FRAGINFO_OFFSET" => { type => "field", addr => 0x3087c, width => 8, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_RING3_7.RX_ATTENTION_OFFSET" => { type => "field", addr => 0x3087c, width => 8, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_EN_ACT_0" => { type => "reg", addr => 0x30880, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_EN_ACT_0.RING_ACTIVE" => { type => "field", addr => 0x30880, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXDMA_EN_ACT_0.RING_ENABLE" => { type => "field", addr => 0x30880, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_EN_ACT_1" => { type => "reg", addr => 0x30884, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_EN_ACT_1.RING_ACTIVE" => { type => "field", addr => 0x30884, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXDMA_EN_ACT_1.RING_ENABLE" => { type => "field", addr => 0x30884, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_EN_ACT_2" => { type => "reg", addr => 0x30888, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_EN_ACT_2.RING_ACTIVE" => { type => "field", addr => 0x30888, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXDMA_EN_ACT_2.RING_ENABLE" => { type => "field", addr => 0x30888, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_EN_ACT_3" => { type => "reg", addr => 0x3088c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_EN_ACT_3.RING_ACTIVE" => { type => "field", addr => 0x3088c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXDMA_EN_ACT_3.RING_ENABLE" => { type => "field", addr => 0x3088c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_IDX_0" => { type => "reg", addr => 0x30890, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_IDX_0.RING_HW_IDX_OVERWRITE" => { type => "field", addr => 0x30890, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "WO", resetVal => 0x0 }, "RXDMA_IDX_0.RING_HW_IDX" => { type => "field", addr => 0x30890, width => 15, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_IDX_0.RING_FW_IDX" => { type => "field", addr => 0x30890, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_IDX_1" => { type => "reg", addr => 0x30894, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_IDX_1.RING_HW_IDX_OVERWRITE" => { type => "field", addr => 0x30894, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "WO", resetVal => 0x0 }, "RXDMA_IDX_1.RING_HW_IDX" => { type => "field", addr => 0x30894, width => 15, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_IDX_1.RING_FW_IDX" => { type => "field", addr => 0x30894, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_IDX_2" => { type => "reg", addr => 0x30898, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_IDX_2.RING_HW_IDX_OVERWRITE" => { type => "field", addr => 0x30898, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "WO", resetVal => 0x0 }, "RXDMA_IDX_2.RING_HW_IDX" => { type => "field", addr => 0x30898, width => 15, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_IDX_2.RING_FW_IDX" => { type => "field", addr => 0x30898, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_IDX_3" => { type => "reg", addr => 0x3089c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_IDX_3.RING_HW_IDX_OVERWRITE" => { type => "field", addr => 0x3089c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "WO", resetVal => 0x0 }, "RXDMA_IDX_3.RING_HW_IDX" => { type => "field", addr => 0x3089c, width => 15, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_IDX_3.RING_FW_IDX" => { type => "field", addr => 0x3089c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_MISC_0" => { type => "reg", addr => 0x308a0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_MISC_0.MEM_BOUNDARY_BYTES_1" => { type => "field", addr => 0x308a0, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 128 }, "RXDMA_CFG_MISC_0.MEM_BOUNDARY_BYTES_0" => { type => "field", addr => 0x308a0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 128 }, "RXDMA_CFG_MISC_1" => { type => "reg", addr => 0x308a4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_MISC_1.MEM_BOUNDARY_BYTES_3" => { type => "field", addr => 0x308a4, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 128 }, "RXDMA_CFG_MISC_1.MEM_BOUNDARY_BYTES_2" => { type => "field", addr => 0x308a4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 128 }, "RXDMA_CFG_MISC_2" => { type => "reg", addr => 0x308a8, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CFG_MISC_2.ALIGN_TO_BYTE_BOUNDARY" => { type => "field", addr => 0x308a8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CFG_MISC_2.LONG_DMA_PAUSE_FIX_DIS" => { type => "field", addr => 0x308a8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_FETCH_IDX_0" => { type => "reg", addr => 0x308ac, width => 32, athEmulAttr => 0, acc => "RO" }, "RXDMA_FETCH_IDX_0.RING_HW_FETCH_IDX" => { type => "field", addr => 0x308ac, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXDMA_FETCH_IDX_1" => { type => "reg", addr => 0x308b0, width => 32, athEmulAttr => 0, acc => "RO" }, "RXDMA_FETCH_IDX_1.RING_HW_FETCH_IDX" => { type => "field", addr => 0x308b0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXDMA_FETCH_IDX_2" => { type => "reg", addr => 0x308b4, width => 32, athEmulAttr => 0, acc => "RO" }, "RXDMA_FETCH_IDX_2.RING_HW_FETCH_IDX" => { type => "field", addr => 0x308b4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXDMA_FETCH_IDX_3" => { type => "reg", addr => 0x308b8, width => 32, athEmulAttr => 0, acc => "RO" }, "RXDMA_FETCH_IDX_3.RING_HW_FETCH_IDX" => { type => "field", addr => 0x308b8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXDMA_GLOBAL_RER" => { type => "reg", addr => 0x308bc, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_GLOBAL_RER.ENABLE" => { type => "field", addr => 0x308bc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXDMA_SOFT_RST" => { type => "reg", addr => 0x308c0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_SOFT_RST.SET" => { type => "field", addr => 0x308c0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_WDOG" => { type => "reg", addr => 0x308c4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_WDOG.STATUS" => { type => "field", addr => 0x308c4, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXDMA_WDOG.LIMIT" => { type => "field", addr => 0x308c4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, "RXDMA_TESTBUS_SAMPLE" => { type => "reg", addr => 0x308c8, width => 32, athEmulAttr => 0, acc => "RO" }, "RXDMA_TESTBUS_SAMPLE.VAL" => { type => "field", addr => 0x308c8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXDMA_TRACEBUS_CTRL" => { type => "reg", addr => 0x308cc, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_TRACEBUS_CTRL.EN" => { type => "field", addr => 0x308cc, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXDMA_TRACEBUS_CTRL.SELECT" => { type => "field", addr => 0x308cc, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXDMA_CLOCK_GATE" => { type => "reg", addr => 0x308d0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_CLOCK_GATE.DISABLE" => { type => "field", addr => 0x308d0, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7f }, "RXDMA_EVENT_MASK_31_0" => { type => "reg", addr => 0x308d4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXDMA_EVENT_MASK_31_0.event_mask_31_0" => { type => "field", addr => 0x308d4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wmac_top_reg_map.mac_ole_reg Register/Field definitions ################################################################### "OLE_L2_WLAN_LLC_0" => { type => "reg", addr => 0x30c00, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_L2_WLAN_LLC_0.ENABLE" => { type => "field", addr => 0x30c00, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_L2_WLAN_LLC_0.BYTE6" => { type => "field", addr => 0x30c00, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "OLE_L2_WLAN_LLC_0.TYPE" => { type => "field", addr => 0x30c00, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0800 }, "OLE_L2_WLAN_LLC_1" => { type => "reg", addr => 0x30c04, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_L2_WLAN_LLC_1.ENABLE" => { type => "field", addr => 0x30c04, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_L2_WLAN_LLC_1.BYTE6" => { type => "field", addr => 0x30c04, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "OLE_L2_WLAN_LLC_1.TYPE" => { type => "field", addr => 0x30c04, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0806 }, "OLE_L2_WLAN_LLC_2" => { type => "reg", addr => 0x30c08, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_L2_WLAN_LLC_2.ENABLE" => { type => "field", addr => 0x30c08, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_L2_WLAN_LLC_2.BYTE6" => { type => "field", addr => 0x30c08, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "OLE_L2_WLAN_LLC_2.TYPE" => { type => "field", addr => 0x30c08, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x809B }, "OLE_L2_WLAN_LLC_3" => { type => "reg", addr => 0x30c0c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_L2_WLAN_LLC_3.ENABLE" => { type => "field", addr => 0x30c0c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_L2_WLAN_LLC_3.BYTE6" => { type => "field", addr => 0x30c0c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0xF8 }, "OLE_L2_WLAN_LLC_3.TYPE" => { type => "field", addr => 0x30c0c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80F3 }, "OLE_L2_WLAN_LLC_4" => { type => "reg", addr => 0x30c10, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_L2_WLAN_LLC_4.ENABLE" => { type => "field", addr => 0x30c10, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_L2_WLAN_LLC_4.BYTE6" => { type => "field", addr => 0x30c10, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0xF8 }, "OLE_L2_WLAN_LLC_4.TYPE" => { type => "field", addr => 0x30c10, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x8137 }, "OLE_L2_WLAN_LLC_5" => { type => "reg", addr => 0x30c14, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_L2_WLAN_LLC_5.ENABLE" => { type => "field", addr => 0x30c14, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_L2_WLAN_LLC_5.BYTE6" => { type => "field", addr => 0x30c14, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "OLE_L2_WLAN_LLC_5.TYPE" => { type => "field", addr => 0x30c14, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x86DD }, "OLE_L2_WLAN_LLC_6" => { type => "reg", addr => 0x30c18, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_L2_WLAN_LLC_6.ENABLE" => { type => "field", addr => 0x30c18, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_L2_WLAN_LLC_6.BYTE6" => { type => "field", addr => 0x30c18, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "OLE_L2_WLAN_LLC_6.TYPE" => { type => "field", addr => 0x30c18, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x888E }, "OLE_RX_CONFIG" => { type => "reg", addr => 0x30c20, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_CONFIG.RX_HDR_BYTELEN" => { type => "field", addr => 0x30c20, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x30 }, "OLE_RX_CONFIG_RING0" => { type => "reg", addr => 0x30c24, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_CONFIG_RING0.RESERVED_2" => { type => "field", addr => 0x30c24, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING0.ETHERNET_3" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING0.ETHERNET_2" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING0.ETHERNET_1" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING0.ETHERNET_0" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING0.RESERVED_1" => { type => "field", addr => 0x30c24, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING0.PHY_DATA_TYPE" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.NULL_DATA_TYPE" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.MCAST_DATA_TYPE" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.UCAST_DATA_TYPE" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.MGMT_TYPE" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.CTRL_TYPE" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.RESERVED_0" => { type => "field", addr => 0x30c24, width => 6, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING0.FRAG_INFO" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.ATTENTION" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.PPDU_END" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.MPDU_END" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.MSDU_END" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.PKT" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.MSDU_START" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.MPDU_START" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.HDR" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING0.PPDU_START" => { type => "field", addr => 0x30c24, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING1" => { type => "reg", addr => 0x30c28, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_CONFIG_RING1.RESERVED_2" => { type => "field", addr => 0x30c28, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.ETHERNET_3" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.ETHERNET_2" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.ETHERNET_1" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.ETHERNET_0" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.RESERVED_1" => { type => "field", addr => 0x30c28, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.PHY_DATA_TYPE" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING1.NULL_DATA_TYPE" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING1.MCAST_DATA_TYPE" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING1.UCAST_DATA_TYPE" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING1.MGMT_TYPE" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING1.CTRL_TYPE" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING1.RESERVED_0" => { type => "field", addr => 0x30c28, width => 6, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.FRAG_INFO" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.ATTENTION" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.PPDU_END" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.MPDU_END" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.MSDU_END" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.PKT" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.MSDU_START" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.MPDU_START" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.HDR" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING1.PPDU_START" => { type => "field", addr => 0x30c28, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2" => { type => "reg", addr => 0x30c2c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_CONFIG_RING2.RESERVED_2" => { type => "field", addr => 0x30c2c, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.ETHERNET_3" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.ETHERNET_2" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.ETHERNET_1" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.ETHERNET_0" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.RESERVED_1" => { type => "field", addr => 0x30c2c, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.PHY_DATA_TYPE" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING2.NULL_DATA_TYPE" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING2.MCAST_DATA_TYPE" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING2.UCAST_DATA_TYPE" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING2.MGMT_TYPE" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING2.CTRL_TYPE" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING2.RESERVED_0" => { type => "field", addr => 0x30c2c, width => 6, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.FRAG_INFO" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.ATTENTION" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.PPDU_END" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.MPDU_END" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.MSDU_END" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.PKT" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.MSDU_START" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.MPDU_START" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.HDR" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING2.PPDU_START" => { type => "field", addr => 0x30c2c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3" => { type => "reg", addr => 0x30c30, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_CONFIG_RING3.RESERVED_2" => { type => "field", addr => 0x30c30, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.ETHERNET_3" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.ETHERNET_2" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.ETHERNET_1" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.ETHERNET_0" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.RESERVED_1" => { type => "field", addr => 0x30c30, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.PHY_DATA_TYPE" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING3.NULL_DATA_TYPE" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING3.MCAST_DATA_TYPE" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING3.UCAST_DATA_TYPE" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING3.MGMT_TYPE" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING3.CTRL_TYPE" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_RX_CONFIG_RING3.RESERVED_0" => { type => "field", addr => 0x30c30, width => 6, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.FRAG_INFO" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.ATTENTION" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.PPDU_END" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.MPDU_END" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.MSDU_END" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.PKT" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.MSDU_START" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.MPDU_START" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.HDR" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CONFIG_RING3.PPDU_START" => { type => "field", addr => 0x30c30, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_DECAP_CONFIG" => { type => "reg", addr => 0x30c34, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_CONFIG.EV_135902_DISABLE" => { type => "field", addr => 0x30c34, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_CONFIG.ENABLE_PE" => { type => "field", addr => 0x30c34, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_CONFIG.CHECKSUM_TIMEOUT" => { type => "field", addr => 0x30c34, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "OLE_DECAP_CONFIG.CHECKSUM_DISABLE" => { type => "field", addr => 0x30c34, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_CONFIG.ONLY_DIRECTED_MCAST_BCAST" => { type => "field", addr => 0x30c34, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_CONFIG.TCP_UDP_CHECKSUM_SEL" => { type => "field", addr => 0x30c34, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_CONFIG.IP_CHECKSUM_SEL" => { type => "field", addr => 0x30c34, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_CONFIG.UNKNOWN_LLC_DECAP_ENABLE" => { type => "field", addr => 0x30c34, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_CONFIG.REMOVE_VLAN_TAG" => { type => "field", addr => 0x30c34, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_DECAP_CONFIG.TARGET_FORMAT" => { type => "field", addr => 0x30c34, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_CONFIG.ENABLE" => { type => "field", addr => 0x30c34, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_HEADER_PADDING" => { type => "reg", addr => 0x30c38, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_HEADER_PADDING.RX_L3_HEADER_PADDING" => { type => "field", addr => 0x30c38, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_HEADER_PADDING.TX_INSERT_HEADER_PADDING" => { type => "field", addr => 0x30c38, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_HEADER_PADDING.TX_INPUT_HEADER_PADDING" => { type => "field", addr => 0x30c38, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_DECAP_TABLE_0_HALF1" => { type => "reg", addr => 0x30c3c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_0_HALF1.SNAP_OR_TYPE2" => { type => "field", addr => 0x30c3c, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_0_HALF1.ENABLE" => { type => "field", addr => 0x30c3c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_0_HALF1.OUI" => { type => "field", addr => 0x30c3c, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000000 }, "OLE_DECAP_TABLE_0_HALF2" => { type => "reg", addr => 0x30c40, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_0_HALF2.TYPE" => { type => "field", addr => 0x30c40, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0800 }, "OLE_DECAP_TABLE_1_HALF1" => { type => "reg", addr => 0x30c44, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_1_HALF1.SNAP_OR_TYPE2" => { type => "field", addr => 0x30c44, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_1_HALF1.ENABLE" => { type => "field", addr => 0x30c44, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_1_HALF1.OUI" => { type => "field", addr => 0x30c44, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000000 }, "OLE_DECAP_TABLE_1_HALF2" => { type => "reg", addr => 0x30c48, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_1_HALF2.TYPE" => { type => "field", addr => 0x30c48, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x86DD }, "OLE_DECAP_TABLE_2_HALF1" => { type => "reg", addr => 0x30c4c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_2_HALF1.SNAP_OR_TYPE2" => { type => "field", addr => 0x30c4c, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_2_HALF1.ENABLE" => { type => "field", addr => 0x30c4c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_2_HALF1.OUI" => { type => "field", addr => 0x30c4c, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000000 }, "OLE_DECAP_TABLE_2_HALF2" => { type => "reg", addr => 0x30c50, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_2_HALF2.TYPE" => { type => "field", addr => 0x30c50, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0806 }, "OLE_DECAP_TABLE_3_HALF1" => { type => "reg", addr => 0x30c54, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_3_HALF1.SNAP_OR_TYPE2" => { type => "field", addr => 0x30c54, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_3_HALF1.ENABLE" => { type => "field", addr => 0x30c54, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_3_HALF1.OUI" => { type => "field", addr => 0x30c54, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000000 }, "OLE_DECAP_TABLE_3_HALF2" => { type => "reg", addr => 0x30c58, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_3_HALF2.TYPE" => { type => "field", addr => 0x30c58, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x809B }, "OLE_DECAP_TABLE_4_HALF1" => { type => "reg", addr => 0x30c5c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_4_HALF1.SNAP_OR_TYPE2" => { type => "field", addr => 0x30c5c, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_4_HALF1.ENABLE" => { type => "field", addr => 0x30c5c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_4_HALF1.OUI" => { type => "field", addr => 0x30c5c, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0000F8 }, "OLE_DECAP_TABLE_4_HALF2" => { type => "reg", addr => 0x30c60, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_4_HALF2.TYPE" => { type => "field", addr => 0x30c60, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80F3 }, "OLE_DECAP_TABLE_5_HALF1" => { type => "reg", addr => 0x30c64, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_5_HALF1.SNAP_OR_TYPE2" => { type => "field", addr => 0x30c64, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_5_HALF1.ENABLE" => { type => "field", addr => 0x30c64, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_5_HALF1.OUI" => { type => "field", addr => 0x30c64, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0000F8 }, "OLE_DECAP_TABLE_5_HALF2" => { type => "reg", addr => 0x30c68, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_5_HALF2.TYPE" => { type => "field", addr => 0x30c68, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x8137 }, "OLE_DECAP_TABLE_6_HALF1" => { type => "reg", addr => 0x30c6c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_6_HALF1.SNAP_OR_TYPE2" => { type => "field", addr => 0x30c6c, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_6_HALF1.ENABLE" => { type => "field", addr => 0x30c6c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_DECAP_TABLE_6_HALF1.OUI" => { type => "field", addr => 0x30c6c, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000000 }, "OLE_DECAP_TABLE_6_HALF2" => { type => "reg", addr => 0x30c70, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_6_HALF2.TYPE" => { type => "field", addr => 0x30c70, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0800 }, "OLE_DECAP_TABLE_7_HALF1" => { type => "reg", addr => 0x30c74, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_7_HALF1.SNAP_OR_TYPE2" => { type => "field", addr => 0x30c74, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_DECAP_TABLE_7_HALF1.ENABLE" => { type => "field", addr => 0x30c74, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_DECAP_TABLE_7_HALF1.OUI" => { type => "field", addr => 0x30c74, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000000 }, "OLE_DECAP_TABLE_7_HALF2" => { type => "reg", addr => 0x30c78, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DECAP_TABLE_7_HALF2.TYPE" => { type => "field", addr => 0x30c78, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0800 }, "OLE_ASE_AST_BASE_ADDR" => { type => "reg", addr => 0x30c7c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_ASE_AST_BASE_ADDR.VALUE" => { type => "field", addr => 0x30c7c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_ASE_AST_SIZE" => { type => "reg", addr => 0x30c80, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_ASE_AST_SIZE.VALUE" => { type => "field", addr => 0x30c80, width => 13, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_ASE_SEARCH_CTRL" => { type => "reg", addr => 0x30c84, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_ASE_SEARCH_CTRL.TIMEOUT_THRESH" => { type => "field", addr => 0x30c84, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_ASE_SEARCH_CTRL.ADDR_SEARCH_SWAP" => { type => "field", addr => 0x30c84, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_ASE_SEARCH_CTRL.MAX_SEARCH" => { type => "field", addr => 0x30c84, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_ASE_HASH_CTRL" => { type => "reg", addr => 0x30c88, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_ASE_HASH_CTRL.CACHE_INVALIDATE" => { type => "field", addr => 0x30c88, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_ASE_HASH_CTRL.CACHE_DISABLE" => { type => "field", addr => 0x30c88, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_ASE_HASH_CTRL.HASH_MAC_31_0_IGNORE" => { type => "field", addr => 0x30c88, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_ASE_HASH_CTRL.HASH_SEL" => { type => "field", addr => 0x30c88, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_ASE_HASH_CTRL.HASH_MCAST_SHIFT" => { type => "field", addr => 0x30c88, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "OLE_ASE_HASH_CTRL.HASH_XOR" => { type => "field", addr => 0x30c88, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "OLE_CONFIG" => { type => "reg", addr => 0x30c8c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_CONFIG.USE_KEYID_ZERO_FOR_AST" => { type => "field", addr => 0x30c8c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_CONFIG.INDUSTRY_STD_VLAN_LLC_PARSE_EN" => { type => "field", addr => 0x30c8c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_CONFIG.USE_BSSID_FOR_AMSDU" => { type => "field", addr => 0x30c8c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_CONFIG.TX_ABORT" => { type => "field", addr => 0x30c8c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_CONFIG.RX_RESET" => { type => "field", addr => 0x30c8c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_CONFIG.TX_RESET" => { type => "field", addr => 0x30c8c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_CONFIG.RESET" => { type => "field", addr => 0x30c8c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_PN_SHIFT_FACTOR" => { type => "reg", addr => 0x30c90, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_PN_SHIFT_FACTOR.USER2" => { type => "field", addr => 0x30c90, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "OLE_PN_SHIFT_FACTOR.USER1" => { type => "field", addr => 0x30c90, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "OLE_PN_SHIFT_FACTOR.USER0" => { type => "field", addr => 0x30c90, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "OLE_RX_CLASSIFY_ETHERNET_0" => { type => "reg", addr => 0x30c94, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_CLASSIFY_ETHERNET_0.ENABLE" => { type => "field", addr => 0x30c94, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CLASSIFY_ETHERNET_0.TYPE" => { type => "field", addr => 0x30c94, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x888E }, "OLE_RX_CLASSIFY_ETHERNET_1" => { type => "reg", addr => 0x30c98, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_CLASSIFY_ETHERNET_1.ENABLE" => { type => "field", addr => 0x30c98, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CLASSIFY_ETHERNET_1.TYPE" => { type => "field", addr => 0x30c98, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x888E }, "OLE_RX_CLASSIFY_ETHERNET_2" => { type => "reg", addr => 0x30c9c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_CLASSIFY_ETHERNET_2.ENABLE" => { type => "field", addr => 0x30c9c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CLASSIFY_ETHERNET_2.TYPE" => { type => "field", addr => 0x30c9c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x888E }, "OLE_RX_CLASSIFY_ETHERNET_3" => { type => "reg", addr => 0x30ca0, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_CLASSIFY_ETHERNET_3.ENABLE" => { type => "field", addr => 0x30ca0, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_CLASSIFY_ETHERNET_3.TYPE" => { type => "field", addr => 0x30ca0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x888E }, "OLE_RX_L3_IPV6_EXTN_HDR_0" => { type => "reg", addr => 0x30cc0, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_0.HDR_LEN" => { type => "field", addr => 0x30cc0, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_0.HDR_ID" => { type => "field", addr => 0x30cc0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_1" => { type => "reg", addr => 0x30cc4, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_1.HDR_LEN" => { type => "field", addr => 0x30cc4, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_1.HDR_ID" => { type => "field", addr => 0x30cc4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x2B }, "OLE_RX_L3_IPV6_EXTN_HDR_2" => { type => "reg", addr => 0x30cc8, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_2.HDR_LEN" => { type => "field", addr => 0x30cc8, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_2.HDR_ID" => { type => "field", addr => 0x30cc8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3C }, "OLE_RX_L3_IPV6_EXTN_HDR_3" => { type => "reg", addr => 0x30ccc, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_3.HDR_LEN" => { type => "field", addr => 0x30ccc, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_3.HDR_ID" => { type => "field", addr => 0x30ccc, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x33 }, "OLE_RX_L3_IPV6_EXTN_HDR_4" => { type => "reg", addr => 0x30cd0, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_4.HDR_LEN" => { type => "field", addr => 0x30cd0, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "OLE_RX_L3_IPV6_EXTN_HDR_4.HDR_ID" => { type => "field", addr => 0x30cd0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x87 }, "OLE_RX_L3_IPV6_EXTN_HDR_5" => { type => "reg", addr => 0x30cd4, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_5.HDR_LEN" => { type => "field", addr => 0x30cd4, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "OLE_RX_L3_IPV6_EXTN_HDR_5.HDR_ID" => { type => "field", addr => 0x30cd4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x2C }, "OLE_RX_L3_IPV6_EXTN_HDR_6" => { type => "reg", addr => 0x30cd8, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_6.HDR_LEN" => { type => "field", addr => 0x30cd8, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_6.HDR_ID" => { type => "field", addr => 0x30cd8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_7" => { type => "reg", addr => 0x30cdc, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_7.HDR_LEN" => { type => "field", addr => 0x30cdc, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_7.HDR_ID" => { type => "field", addr => 0x30cdc, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_8" => { type => "reg", addr => 0x30ce0, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_8.HDR_LEN" => { type => "field", addr => 0x30ce0, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_8.HDR_ID" => { type => "field", addr => 0x30ce0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_9" => { type => "reg", addr => 0x30ce4, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_9.HDR_LEN" => { type => "field", addr => 0x30ce4, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_9.HDR_ID" => { type => "field", addr => 0x30ce4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_10" => { type => "reg", addr => 0x30ce8, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_10.HDR_LEN" => { type => "field", addr => 0x30ce8, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_10.HDR_ID" => { type => "field", addr => 0x30ce8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_11" => { type => "reg", addr => 0x30cec, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_11.HDR_LEN" => { type => "field", addr => 0x30cec, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_11.HDR_ID" => { type => "field", addr => 0x30cec, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_12" => { type => "reg", addr => 0x30cf0, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_12.HDR_LEN" => { type => "field", addr => 0x30cf0, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_12.HDR_ID" => { type => "field", addr => 0x30cf0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_13" => { type => "reg", addr => 0x30cf4, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_13.HDR_LEN" => { type => "field", addr => 0x30cf4, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_13.HDR_ID" => { type => "field", addr => 0x30cf4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_14" => { type => "reg", addr => 0x30cf8, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_14.HDR_LEN" => { type => "field", addr => 0x30cf8, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_14.HDR_ID" => { type => "field", addr => 0x30cf8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_15" => { type => "reg", addr => 0x30cfc, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_L3_IPV6_EXTN_HDR_15.HDR_LEN" => { type => "field", addr => 0x30cfc, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_RX_L3_IPV6_EXTN_HDR_15.HDR_ID" => { type => "field", addr => 0x30cfc, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_BUF_STAT" => { type => "reg", addr => 0x30d00, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_BUF_STAT.CMD_FIFO_THRESHOLD" => { type => "field", addr => 0x30d00, width => 5, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "OLE_BUF_STAT.DATA_FIFO_THRESHOLD" => { type => "field", addr => 0x30d00, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x20 }, "OLE_RX_AMSDU_LIMIT" => { type => "reg", addr => 0x30d04, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_AMSDU_LIMIT.COUNT_THRESHOLD" => { type => "field", addr => 0x30d04, width => 12, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x30 }, "OLE_RX_AMSDU_LIMIT.COUNT_ENABLE" => { type => "field", addr => 0x30d04, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_LRO" => { type => "reg", addr => 0x30d0c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_LRO.TCP_FLAG_MASK" => { type => "field", addr => 0x30d0c, width => 9, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_LRO.TCP_FLAG" => { type => "field", addr => 0x30d0c, width => 9, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_LRO.PAYLOAD_CHECKSUM_ON_LRO" => { type => "field", addr => 0x30d0c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "OLE_LRO.ENABLE" => { type => "field", addr => 0x30d0c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_IPV6_CRC_OPTIONS_EN" => { type => "reg", addr => 0x30d10, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_IPV6_CRC_OPTIONS_EN.HEADERS1" => { type => "field", addr => 0x30d10, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_IPV6_CRC_OPTIONS_EN.HEADERS0" => { type => "field", addr => 0x30d10, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_IPV6_CRC_OPTIONS_HEADERS0" => { type => "reg", addr => 0x30d14, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_IPV6_CRC_OPTIONS_HEADERS0.SEL3" => { type => "field", addr => 0x30d14, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_IPV6_CRC_OPTIONS_HEADERS0.SEL2" => { type => "field", addr => 0x30d14, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_IPV6_CRC_OPTIONS_HEADERS0.SEL1" => { type => "field", addr => 0x30d14, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_IPV6_CRC_OPTIONS_HEADERS0.SEL0" => { type => "field", addr => 0x30d14, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_IPV6_CRC_OPTIONS_HEADERS1" => { type => "reg", addr => 0x30d18, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_IPV6_CRC_OPTIONS_HEADERS1.SEL7" => { type => "field", addr => 0x30d18, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_IPV6_CRC_OPTIONS_HEADERS1.SEL6" => { type => "field", addr => 0x30d18, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_IPV6_CRC_OPTIONS_HEADERS1.SEL5" => { type => "field", addr => 0x30d18, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_IPV6_CRC_OPTIONS_HEADERS1.SEL4" => { type => "field", addr => 0x30d18, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_TX_WATCHDOG" => { type => "reg", addr => 0x30d1c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_TX_WATCHDOG.STATUS" => { type => "field", addr => 0x30d1c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "OLE_TX_WATCHDOG.LIMIT" => { type => "field", addr => 0x30d1c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, "OLE_RX_WATCHDOG" => { type => "reg", addr => 0x30d20, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_RX_WATCHDOG.STATUS" => { type => "field", addr => 0x30d20, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "OLE_RX_WATCHDOG.LIMIT" => { type => "field", addr => 0x30d20, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, "OLE_WATCHDOG_INTR_STATUS" => { type => "reg", addr => 0x30d24, width => 32, athEmulAttr => 0, acc => "RO" }, "OLE_WATCHDOG_INTR_STATUS.RX" => { type => "field", addr => 0x30d24, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "OLE_WATCHDOG_INTR_STATUS.TX" => { type => "field", addr => 0x30d24, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "OLE_DEBUG_1" => { type => "reg", addr => 0x30d28, width => 32, athEmulAttr => 0, acc => "RO" }, "OLE_DEBUG_1.VAL" => { type => "field", addr => 0x30d28, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "OLE_DEBUGBUS_CONTROL" => { type => "reg", addr => 0x30d2c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_DEBUGBUS_CONTROL.TRCBUS_SELECT" => { type => "field", addr => 0x30d2c, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_TX_FIFO_STATUS" => { type => "reg", addr => 0x30d30, width => 32, athEmulAttr => 0, acc => "RCLR" }, "OLE_TX_FIFO_STATUS.CMD_FIFO_DELTA_WORDS_DRAINED" => { type => "field", addr => 0x30d30, width => 6, bitOffset => 23, athEmulAttr => 0, acc => "RCLR", resetVal => 0x0 }, "OLE_TX_FIFO_STATUS.DATA_FIFO_AVAILABLE_SPACE" => { type => "field", addr => 0x30d30, width => 11, bitOffset => 12, athEmulAttr => 0, acc => "RCLR", resetVal => 0x7FF }, "OLE_TX_FIFO_STATUS.DATA_FIFO_DELTA_WORDS_DRAINED" => { type => "field", addr => 0x30d30, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RCLR", resetVal => 0x0 }, "OLE_CLOCK_GATE" => { type => "reg", addr => 0x30d34, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_CLOCK_GATE.DISABLE" => { type => "field", addr => 0x30d34, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "OLE_EVENT_BUS_MASK0" => { type => "reg", addr => 0x30d38, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_EVENT_BUS_MASK0.VALUE" => { type => "field", addr => 0x30d38, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OLE_EVENT_BUS_MASK1" => { type => "reg", addr => 0x30d3c, width => 32, athEmulAttr => 0, acc => "RW" }, "OLE_EVENT_BUS_MASK1.VALUE" => { type => "field", addr => 0x30d3c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wmac_top_reg_map.mac_mcmn_reg Register/Field definitions ################################################################### "MCMN_ISR_P" => { type => "reg", addr => 0x31000, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_P.AMPI" => { type => "field", addr => 0x31000, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.MXI" => { type => "field", addr => 0x31000, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.HWSCH2" => { type => "field", addr => 0x31000, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.HWSCH1" => { type => "field", addr => 0x31000, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.HWSCH0" => { type => "field", addr => 0x31000, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.PDG" => { type => "field", addr => 0x31000, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.RXPCU" => { type => "field", addr => 0x31000, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.TXPCU" => { type => "field", addr => 0x31000, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.RXDMA" => { type => "field", addr => 0x31000, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.TXDMA" => { type => "field", addr => 0x31000, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.CRYPTO" => { type => "field", addr => 0x31000, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_P.OLE" => { type => "field", addr => 0x31000, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0" => { type => "reg", addr => 0x31004, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S0.PN_BITMAP_ERROR" => { type => "field", addr => 0x31004, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.RX_WMAC_ERR" => { type => "field", addr => 0x31004, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.RX_ETH_ERR" => { type => "field", addr => 0x31004, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.RX_MSDU_LEN" => { type => "field", addr => 0x31004, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.TX_ILLEGAL" => { type => "field", addr => 0x31004, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.TX_UNKN_LLC" => { type => "field", addr => 0x31004, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.TX_VLAN_LLC" => { type => "field", addr => 0x31004, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.WEP_KEY_ERR" => { type => "field", addr => 0x31004, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.TX_SEQ_BM_ERR" => { type => "field", addr => 0x31004, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.AMSDU_FRM_ERR" => { type => "field", addr => 0x31004, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.TX_TLV_ERR" => { type => "field", addr => 0x31004, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.RX_TLV_ERR" => { type => "field", addr => 0x31004, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S0.WDOG_TOUT" => { type => "field", addr => 0x31004, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S1" => { type => "reg", addr => 0x31008, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S1.TX_FLUSH_REQ" => { type => "field", addr => 0x31008, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S1.RX_ABORT" => { type => "field", addr => 0x31008, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S1.TX_ABORT" => { type => "field", addr => 0x31008, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S1.DECRPT_ERR" => { type => "field", addr => 0x31008, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S1.RX_TLV_OUT_SEQ" => { type => "field", addr => 0x31008, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S1.TX_TLV_OUT_SEQ" => { type => "field", addr => 0x31008, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S1.CRYP_WD_TMOUT" => { type => "field", addr => 0x31008, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S2" => { type => "reg", addr => 0x3100c, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S2.AXI_TMOUT" => { type => "field", addr => 0x3100c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S2.OLE_RDY_TMOUT" => { type => "field", addr => 0x3100c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S2.UNEX_NUL_PTR" => { type => "field", addr => 0x3100c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S2.WDG_TMOUT" => { type => "field", addr => 0x3100c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S2.INVA_IDX" => { type => "field", addr => 0x3100c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S2.MISSIN_TLV" => { type => "field", addr => 0x3100c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S2.UNEX_FES" => { type => "field", addr => 0x3100c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S2.INCOM_TLV" => { type => "field", addr => 0x3100c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S2.TX_DMA_IDLE" => { type => "field", addr => 0x3100c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3" => { type => "reg", addr => 0x31010, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S3.RXDMA_UAPSD" => { type => "field", addr => 0x31010, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3.RXDMA_RNG_LWM" => { type => "field", addr => 0x31010, width => 4, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3.TLV_FRME_ERR" => { type => "field", addr => 0x31010, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3.TLV_SHORT" => { type => "field", addr => 0x31010, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3.INVAL_TAG_SEG" => { type => "field", addr => 0x31010, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3.INVAL_TAG_ID" => { type => "field", addr => 0x31010, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3.NULL_RNG_MSK" => { type => "field", addr => 0x31010, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3.MDAT_TLV" => { type => "field", addr => 0x31010, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3.NON_PKT_BUF" => { type => "field", addr => 0x31010, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3.RXDMA_WD_TOUT" => { type => "field", addr => 0x31010, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S3.RXDMA_IDLE" => { type => "field", addr => 0x31010, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S4" => { type => "reg", addr => 0x31014, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S4.TXPCU_TX_PHY_ERROR" => { type => "field", addr => 0x31014, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S4.TXPCU_RESPONSE_FRAME_ERROR" => { type => "field", addr => 0x31014, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S4.TXPCU_RCVD_TLV_ABORT" => { type => "field", addr => 0x31014, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S4.TXPCU_REQD_TLVS_NOT_RCVD" => { type => "field", addr => 0x31014, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S4.TXPCU_WD_TOUT" => { type => "field", addr => 0x31014, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S4.BFEE_CV_TOUT" => { type => "field", addr => 0x31014, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S4.DATA_URUN" => { type => "field", addr => 0x31014, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S4.RECD_GT_MPDU" => { type => "field", addr => 0x31014, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S4.RECD_LT_MPDU" => { type => "field", addr => 0x31014, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5" => { type => "reg", addr => 0x31018, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S5.PHY_RXPCU_TLV_LENGTH_ERR" => { type => "field", addr => 0x31018, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.RX_MAX_LENGTH" => { type => "field", addr => 0x31018, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.WDOG_TIMEOUT" => { type => "field", addr => 0x31018, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.MIB_COUNTER" => { type => "field", addr => 0x31018, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.RX_OVFL" => { type => "field", addr => 0x31018, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.CONFIG_PHY_ERR" => { type => "field", addr => 0x31018, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.RX_DTIM" => { type => "field", addr => 0x31018, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.RX_TIM" => { type => "field", addr => 0x31018, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.RX_NOTIM" => { type => "field", addr => 0x31018, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.RSSI_LOW" => { type => "field", addr => 0x31018, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.RSSI_HIGH" => { type => "field", addr => 0x31018, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S5.BCON_MISS" => { type => "field", addr => 0x31018, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S6" => { type => "reg", addr => 0x3101c, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S6.MPDU_LENGTH_ERR" => { type => "field", addr => 0x3101c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S6.SETUP_ERR" => { type => "field", addr => 0x3101c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S6.OVERFLOW_ERR" => { type => "field", addr => 0x3101c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S6.TXDMA_PDG_LEN_ERR" => { type => "field", addr => 0x3101c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S6.HWSCH_PDG_TLV_LEN_ERR" => { type => "field", addr => 0x3101c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S6.WRNG_TLV_ORD" => { type => "field", addr => 0x3101c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S6.RCV_FCS_BSY" => { type => "field", addr => 0x3101c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S6.PDG_WD_TOUT" => { type => "field", addr => 0x3101c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S7" => { type => "reg", addr => 0x31020, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S7.HW_RNG_THR" => { type => "field", addr => 0x31020, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S7.HW_RNG_PSD" => { type => "field", addr => 0x31020, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S8" => { type => "reg", addr => 0x31024, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S8.MTU_BKOF" => { type => "field", addr => 0x31024, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S9" => { type => "reg", addr => 0x31028, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S9.MTU_TX_BOUNDARY_INT" => { type => "field", addr => 0x31028, width => 4, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S9.HWSCH_TX_STATUS_LOW_WMARK_REACHED" => { type => "field", addr => 0x31028, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S9.HWSCH_TX_STATUS_PANIC_WMARK_REACHED" => { type => "field", addr => 0x31028, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S9.AXI_RD_ERR" => { type => "field", addr => 0x31028, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S9.AXI_WR_ERR" => { type => "field", addr => 0x31028, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S9.HWSCH_WD_TOUT" => { type => "field", addr => 0x31028, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S10" => { type => "reg", addr => 0x3102c, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S10.AXI_TMOUT" => { type => "field", addr => 0x3102c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S10.AXI_RESP_ERR" => { type => "field", addr => 0x3102c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_IMR_P" => { type => "reg", addr => 0x31030, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_P.AMPI" => { type => "field", addr => 0x31030, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.MXI" => { type => "field", addr => 0x31030, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.HWSCH2" => { type => "field", addr => 0x31030, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.HWSCH1" => { type => "field", addr => 0x31030, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.HWSCH0" => { type => "field", addr => 0x31030, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.PDG" => { type => "field", addr => 0x31030, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.RXPCU" => { type => "field", addr => 0x31030, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.TXPCU" => { type => "field", addr => 0x31030, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.RXDMA" => { type => "field", addr => 0x31030, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.TXDMA" => { type => "field", addr => 0x31030, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.CRYPTO" => { type => "field", addr => 0x31030, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_P.OLE" => { type => "field", addr => 0x31030, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0" => { type => "reg", addr => 0x31034, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S0.PN_BITMAP_ERROR" => { type => "field", addr => 0x31034, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.RX_WMAC_ERR" => { type => "field", addr => 0x31034, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.RX_ETH_ERR" => { type => "field", addr => 0x31034, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.RX_MSDU_LEN" => { type => "field", addr => 0x31034, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.TX_ILLEGAL" => { type => "field", addr => 0x31034, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.TX_UNKN_LLC" => { type => "field", addr => 0x31034, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.TX_VLAN_LLC" => { type => "field", addr => 0x31034, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.WEP_KEY_ERR" => { type => "field", addr => 0x31034, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.TX_SEQ_BM_ERR" => { type => "field", addr => 0x31034, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.AMSDU_FRM_ERR" => { type => "field", addr => 0x31034, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.TX_TLV_ERR" => { type => "field", addr => 0x31034, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.RX_TLV_ERR" => { type => "field", addr => 0x31034, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S0.WDOG_TOUT" => { type => "field", addr => 0x31034, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S1" => { type => "reg", addr => 0x31038, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S1.TX_FLUSH_REQ" => { type => "field", addr => 0x31038, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S1.RX_ABORT" => { type => "field", addr => 0x31038, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S1.TX_ABORT" => { type => "field", addr => 0x31038, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S1.DECRPT_ERR" => { type => "field", addr => 0x31038, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S1.RX_TLV_OUT_SEQ" => { type => "field", addr => 0x31038, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S1.TX_TLV_OUT_SEQ" => { type => "field", addr => 0x31038, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S1.CRYP_WD_TMOUT" => { type => "field", addr => 0x31038, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S2" => { type => "reg", addr => 0x3103c, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S2.AXI_TMOUT" => { type => "field", addr => 0x3103c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S2.OLE_RDY_TMOUT" => { type => "field", addr => 0x3103c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S2.UNEX_NUL_PTR" => { type => "field", addr => 0x3103c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S2.WDG_TMOUT" => { type => "field", addr => 0x3103c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S2.INVA_IDX" => { type => "field", addr => 0x3103c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S2.MISSIN_TLV" => { type => "field", addr => 0x3103c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S2.UNEX_FES" => { type => "field", addr => 0x3103c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S2.INCOM_TLV" => { type => "field", addr => 0x3103c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S2.TX_DMA_IDLE" => { type => "field", addr => 0x3103c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3" => { type => "reg", addr => 0x31040, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S3.RXDMA_UAPSD" => { type => "field", addr => 0x31040, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3.RXDMA_RNG_LWM" => { type => "field", addr => 0x31040, width => 4, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3.TLV_FRME_ERR" => { type => "field", addr => 0x31040, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3.TLV_SHORT" => { type => "field", addr => 0x31040, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3.INVAL_TAG_SEG" => { type => "field", addr => 0x31040, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3.INVAL_TAG_ID" => { type => "field", addr => 0x31040, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3.NULL_RNG_MSK" => { type => "field", addr => 0x31040, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3.MDAT_TLV" => { type => "field", addr => 0x31040, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3.NON_PKT_BUF" => { type => "field", addr => 0x31040, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3.RXDMA_WD_TOUT" => { type => "field", addr => 0x31040, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S3.RXDMA_IDLE" => { type => "field", addr => 0x31040, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S4" => { type => "reg", addr => 0x31044, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S4.TXPCU_TX_PHY_ERROR" => { type => "field", addr => 0x31044, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S4.TXPCU_RESPONSE_FRAME_ERROR" => { type => "field", addr => 0x31044, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S4.TXPCU_RCVD_TLV_ABORT" => { type => "field", addr => 0x31044, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S4.TXPCU_REQD_TLVS_NOT_RCVD" => { type => "field", addr => 0x31044, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S4.TXPCU_WD_TOUT" => { type => "field", addr => 0x31044, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S4.BFEE_CV_TOUT" => { type => "field", addr => 0x31044, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S4.DATA_URUN" => { type => "field", addr => 0x31044, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S4.RECD_GT_MPDU" => { type => "field", addr => 0x31044, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S4.RECD_LT_MPDU" => { type => "field", addr => 0x31044, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5" => { type => "reg", addr => 0x31048, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S5.PHY_RXPCU_TLV_LENGTH_ERR" => { type => "field", addr => 0x31048, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.RX_MAX_LENGTH" => { type => "field", addr => 0x31048, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.WDOG_TIMEOUT" => { type => "field", addr => 0x31048, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.MIB_COUNTER" => { type => "field", addr => 0x31048, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.RX_OVFL" => { type => "field", addr => 0x31048, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.CONFIG_PHY_ERR" => { type => "field", addr => 0x31048, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.RX_DTIM" => { type => "field", addr => 0x31048, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.RX_TIM" => { type => "field", addr => 0x31048, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.RX_NOTIM" => { type => "field", addr => 0x31048, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.RSSI_LOW" => { type => "field", addr => 0x31048, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.RSSI_HIGH" => { type => "field", addr => 0x31048, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S5.BCON_MISS" => { type => "field", addr => 0x31048, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S6" => { type => "reg", addr => 0x3104c, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S6.MPDU_LENGTH_ERR" => { type => "field", addr => 0x3104c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S6.SETUP_ERR" => { type => "field", addr => 0x3104c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S6.OVERFLOW_ERR" => { type => "field", addr => 0x3104c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S6.TXDMA_PDG_LEN_ERR" => { type => "field", addr => 0x3104c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S6.HWSCH_PDG_TLV_LEN_ERR" => { type => "field", addr => 0x3104c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S6.WRNG_TLV_ORD" => { type => "field", addr => 0x3104c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S6.RCV_FCS_BSY" => { type => "field", addr => 0x3104c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S6.PDG_WD_TOUT" => { type => "field", addr => 0x3104c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S7" => { type => "reg", addr => 0x31050, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S7.HW_RNG_THR" => { type => "field", addr => 0x31050, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S7.HW_RNG_PSD" => { type => "field", addr => 0x31050, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S8" => { type => "reg", addr => 0x31054, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S8.MTU_BKOF" => { type => "field", addr => 0x31054, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S9" => { type => "reg", addr => 0x31058, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S9.MTU_TX_BOUNDARY_INT" => { type => "field", addr => 0x31058, width => 4, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S9.HWSCH_TX_STATUS_LOW_WMARK_REACHED" => { type => "field", addr => 0x31058, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S9.HWSCH_TX_STATUS_PANIC_WMARK_REACHED" => { type => "field", addr => 0x31058, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S9.AXI_RD_ERR" => { type => "field", addr => 0x31058, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S9.AXI_WR_ERR" => { type => "field", addr => 0x31058, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S9.HWSCH_WD_TOUT" => { type => "field", addr => 0x31058, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S10" => { type => "reg", addr => 0x3105c, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S10.AXI_TMOUT" => { type => "field", addr => 0x3105c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S10.AXI_RESP_ERR" => { type => "field", addr => 0x3105c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MPDU_LINK_DESC_BASE_ADDR" => { type => "reg", addr => 0x31068, width => 32, athEmulAttr => 0, acc => "RW", depth => 2, incr => 4 }, "MPDU_LINK_DESC_BASE_ADDR.VAL" => { type => "field", addr => 0x31068, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MPDU_LINK_DESC_MIN_IDX" => { type => "reg", addr => 0x31070, width => 32, athEmulAttr => 0, acc => "RW", depth => 2, incr => 4 }, "MPDU_LINK_DESC_MIN_IDX.VAL" => { type => "field", addr => 0x31070, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MPDU_LINK_DESC_MAX_IDX" => { type => "reg", addr => 0x31078, width => 32, athEmulAttr => 0, acc => "RW", depth => 2, incr => 4 }, "MPDU_LINK_DESC_MAX_IDX.VAL" => { type => "field", addr => 0x31078, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MPDU_LINK_EXT_DESC_SWAP" => { type => "reg", addr => 0x31080, width => 32, athEmulAttr => 0, acc => "RW" }, "MPDU_LINK_EXT_DESC_SWAP.VAL" => { type => "field", addr => 0x31080, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MSDU_LINK_DESC_SWAP" => { type => "reg", addr => 0x31084, width => 32, athEmulAttr => 0, acc => "RW" }, "MSDU_LINK_DESC_SWAP.VAL" => { type => "field", addr => 0x31084, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MPDU_LINK_EXT_DESC_BASE_ADDR" => { type => "reg", addr => 0x31088, width => 32, athEmulAttr => 0, acc => "RW" }, "MPDU_LINK_EXT_DESC_BASE_ADDR.VAL" => { type => "field", addr => 0x31088, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MSDU_LINK_DESC_BASE_ADDR" => { type => "reg", addr => 0x31090, width => 32, athEmulAttr => 0, acc => "RW" }, "MSDU_LINK_DESC_BASE_ADDR.VAL" => { type => "field", addr => 0x31090, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MSDU_LINK_EXT_DESC_BASE_ADDR" => { type => "reg", addr => 0x310a0, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "MSDU_LINK_EXT_DESC_BASE_ADDR.VAL" => { type => "field", addr => 0x310a0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MSDU_LINK_EXT_DESC_MIN_IDX" => { type => "reg", addr => 0x310e0, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "MSDU_LINK_EXT_DESC_MIN_IDX.VAL" => { type => "field", addr => 0x310e0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MSDU_LINK_EXT_DESC_MAX_IDX" => { type => "reg", addr => 0x31120, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "MSDU_LINK_EXT_DESC_MAX_IDX.VAL" => { type => "field", addr => 0x31120, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MSDU_LINK_EXT_DESC_SWAP" => { type => "reg", addr => 0x31160, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "MSDU_LINK_EXT_DESC_SWAP.VAL" => { type => "field", addr => 0x31160, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAX_AXI_RD_BURST_SIZE" => { type => "reg", addr => 0x311a0, width => 32, athEmulAttr => 0, acc => "RW" }, "MAX_AXI_RD_BURST_SIZE.VAL" => { type => "field", addr => 0x311a0, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_L32" => { type => "reg", addr => 0x311a4, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_STA_ADDR_L32.ADDR_31_0" => { type => "field", addr => 0x311a4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16" => { type => "reg", addr => 0x311a8, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_STA_ADDR_U16.ADHOC_MCAST_SEARCH" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.CBCIV_ENDIAN" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.PRESERVE_SEQNUM" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MAC_PCU_STA_ADDR_U16.KSRCH_MODE" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.CRPT_MIC_ENABLE" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.SECTOR_SELF_GEN" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.BASE_RATE_11B" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.ACKCTS_6MB" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.RTS_USE_DEF" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.DEFANT_UPDATE" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.USE_DEFANT" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.PCF" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.KEYSRCH_DIS" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.PW_SAVE" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.ADHOC" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.STA_AP" => { type => "field", addr => 0x311a8, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_STA_ADDR_U16.ADDR_47_32" => { type => "field", addr => 0x311a8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_BSSID_L32" => { type => "reg", addr => 0x311ac, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_BSSID_L32.ADDR" => { type => "field", addr => 0x311ac, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_BSSID_U16" => { type => "reg", addr => 0x311b0, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_BSSID_U16.AID" => { type => "field", addr => 0x311b0, width => 11, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_BSSID_U16.ADDR" => { type => "field", addr => 0x311b0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW" => { type => "reg", addr => 0x311b4, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_DIAG_SW.DEBUG_MODE" => { type => "field", addr => 0x311b4, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.RX_CLEAR_EXT_LOW" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.RX_CLEAR_CTL_LOW" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.OBS_SEL_2" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.SATURATE_CYCLE_CNT" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.FORCE_RX_ABORT" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.DUAL_CHAIN_CHAN_INFO" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.PHYERR_ENABLE_EIFS_CTL" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.CHAN_IDLE_HIGH" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.IGNORE_NAV" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.RX_CLEAR_HIGH" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.OBS_SEL_1_0" => { type => "field", addr => 0x311b4, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.ACCEPT_NON_V0" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.DUMP_CHAN_INFO" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.CORRUPT_FCS" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.LOOP_BACK" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.HALT_RX" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.NO_DECRYPT" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.NO_ENCRYPT" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.NO_CTS" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.NO_ACK" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_DIAG_SW.INVALID_KEY_NO_ACK" => { type => "field", addr => 0x311b4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_AZIMUTH_MODE" => { type => "reg", addr => 0x311b8, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_AZIMUTH_MODE.PROXY_STA_FIX2_ENABLE" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MAC_PCU_AZIMUTH_MODE.PROXY_STA_FIX1_ENABLE" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MAC_PCU_AZIMUTH_MODE.FILTER_PASS_HOLD" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MAC_PCU_AZIMUTH_MODE.WMAC_CLK_SEL" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MAC_PCU_AZIMUTH_MODE.BA_USES_AD1" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_AZIMUTH_MODE.ACK_CTS_MATCH_TX_AD2" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MAC_PCU_AZIMUTH_MODE.TX_DESC_EN" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_AZIMUTH_MODE.CLK_EN" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_AZIMUTH_MODE.RX_TSF_STATUS_SEL" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_AZIMUTH_MODE.TX_TSF_STATUS_SEL" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_AZIMUTH_MODE.KEY_SEARCH_AD1" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_AZIMUTH_MODE.DISABLE_TSF_UPDATE" => { type => "field", addr => 0x311b8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_WARM_TX_CONTROL" => { type => "reg", addr => 0x311c4, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_WARM_TX_CONTROL.ENABLE_SELF_GEN" => { type => "field", addr => 0x311c4, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_WARM_TX_CONTROL.ENABLE_DATA" => { type => "field", addr => 0x311c4, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_WARM_TX_CONTROL.SIFS_DUR" => { type => "field", addr => 0x311c4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x280 }, "MCMN_GO_TO_IDLE" => { type => "reg", addr => 0x311c8, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_GO_TO_IDLE.PDG" => { type => "field", addr => 0x311c8, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_GO_TO_IDLE.RXPCU" => { type => "field", addr => 0x311c8, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_GO_TO_IDLE.TXDMA" => { type => "field", addr => 0x311c8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_GO_TO_IDLE.OLE" => { type => "field", addr => 0x311c8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TESTBUS_SELECT" => { type => "reg", addr => 0x311e0, width => 32, athEmulAttr => 0, acc => "RW" }, "TESTBUS_SELECT.TRACER_SEL" => { type => "field", addr => 0x311e0, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TESTBUS_SELECT.WMAC_SEL" => { type => "field", addr => 0x311e0, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "MPDU_LINK_DESC_SWAP" => { type => "reg", addr => 0x311e4, width => 32, athEmulAttr => 0, acc => "RW" }, "MPDU_LINK_DESC_SWAP.VAL" => { type => "field", addr => 0x311e4, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_ISR_RX_OK" => { type => "reg", addr => 0x311e8, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_RX_OK.RXDMA_PPDU" => { type => "field", addr => 0x311e8, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_RX_OK.RXDMA_MPDU" => { type => "field", addr => 0x311e8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_RX_OK.RXDMA_MSDU" => { type => "field", addr => 0x311e8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_IMR_RX_OK" => { type => "reg", addr => 0x311ec, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_RX_OK.RXDMA_PPDU" => { type => "field", addr => 0x311ec, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_RX_OK.RXDMA_MPDU" => { type => "field", addr => 0x311ec, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_RX_OK.RXDMA_MSDU" => { type => "field", addr => 0x311ec, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_ISR_SIFS_RESP" => { type => "reg", addr => 0x311f0, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_SIFS_RESP.QBOOST_QOSDATA_SIFS_RESP" => { type => "field", addr => 0x311f0, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_SIFS_RESP.QBOOST_BAR_SIFS_RESP" => { type => "field", addr => 0x311f0, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_SIFS_RESP.QBOOST_EXPLICIT_SIFS_RESP" => { type => "field", addr => 0x311f0, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_SIFS_RESP.UAPSD_SIFS_RESP" => { type => "field", addr => 0x311f0, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_SIFS_RESP.PS_POLL_SIFS_RESP" => { type => "field", addr => 0x311f0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_IMR_SIFS_RESP" => { type => "reg", addr => 0x311f4, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_SIFS_RESP.QBOOST_QOSDATA_SIFS_RESP" => { type => "field", addr => 0x311f4, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_SIFS_RESP.QBOOST_BAR_SIFS_RESP" => { type => "field", addr => 0x311f4, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_SIFS_RESP.QBOOST_EXPLICIT_SIFS_RESP" => { type => "field", addr => 0x311f4, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_SIFS_RESP.UAPSD_SIFS_RESP" => { type => "field", addr => 0x311f4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_SIFS_RESP.PS_POLL_SIFS_RESP" => { type => "field", addr => 0x311f4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_ISR_TX_OK" => { type => "reg", addr => 0x311f8, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_TX_OK.HWSCH_TX_FES_STATUS_UPDATE" => { type => "field", addr => 0x311f8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_TX_OK.HWSCH_SCHEDULER_TX_STATUS_UPDATE" => { type => "field", addr => 0x311f8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_IMR_TX_OK" => { type => "reg", addr => 0x311fc, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_TX_OK.HWSCH_TX_FES_STATUS_UPDATE" => { type => "field", addr => 0x311fc, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_TX_OK.HWSCH_SCHEDULER_TX_STATUS_UPDATE" => { type => "field", addr => 0x311fc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_WOCLR_ISR_P_EN" => { type => "reg", addr => 0x31200, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_WOCLR_ISR_P_EN.Val" => { type => "field", addr => 0x31200, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_CYCLE_CNT" => { type => "reg", addr => 0x31204, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_CYCLE_CNT.VALUE" => { type => "field", addr => 0x31204, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_MIB_CNT_CTRL" => { type => "reg", addr => 0x31208, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_MIB_CNT_CTRL.wrap_cnt_en" => { type => "field", addr => 0x31208, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_MIB_CNT_CTRL.pci_mib_force" => { type => "field", addr => 0x31208, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_MIB_CNT_CTRL.pci_mib_clear" => { type => "field", addr => 0x31208, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_MIB_CNT_CTRL.pci_mib_freeze" => { type => "field", addr => 0x31208, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_MIB_CNT_CTRL.wmac_rx_abort" => { type => "field", addr => 0x31208, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_ISR_S11" => { type => "reg", addr => 0x3120c, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "MCMN_ISR_S11.RX_TLV_ERROR" => { type => "field", addr => 0x3120c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_ISR_S11.TX_TLV_ERROR" => { type => "field", addr => 0x3120c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "MCMN_IMR_S11" => { type => "reg", addr => 0x31210, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_IMR_S11.RX_TLV_ERROR" => { type => "field", addr => 0x31210, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_IMR_S11.TX_TLV_ERROR" => { type => "field", addr => 0x31210, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_EVENT_TRACE_BUS_SELECT" => { type => "reg", addr => 0x31214, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_EVENT_TRACE_BUS_SELECT.VAL" => { type => "field", addr => 0x31214, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_APB_CLK_DISABLE" => { type => "reg", addr => 0x31218, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_APB_CLK_DISABLE.CRYPTO" => { type => "field", addr => 0x31218, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_APB_CLK_DISABLE.HWSCH" => { type => "field", addr => 0x31218, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_APB_CLK_DISABLE.MXI" => { type => "field", addr => 0x31218, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_APB_CLK_DISABLE.OLE" => { type => "field", addr => 0x31218, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_APB_CLK_DISABLE.PDG" => { type => "field", addr => 0x31218, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_APB_CLK_DISABLE.RXDMA" => { type => "field", addr => 0x31218, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_APB_CLK_DISABLE.RXPCU" => { type => "field", addr => 0x31218, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_APB_CLK_DISABLE.TXDMA" => { type => "field", addr => 0x31218, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_APB_CLK_DISABLE.TXPCU" => { type => "field", addr => 0x31218, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_APB_CLK_DISABLE.AMPI" => { type => "field", addr => 0x31218, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_ECO_SPARE" => { type => "reg", addr => 0x3121c, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_ECO_SPARE.VAL" => { type => "field", addr => 0x3121c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "MCMN_CLK_GATE_DISABLE" => { type => "reg", addr => 0x31220, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_CLK_GATE_DISABLE.VAL" => { type => "field", addr => 0x31220, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_EVENTBUS_BLOCK_MASK" => { type => "reg", addr => 0x31224, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_EVENTBUS_BLOCK_MASK.VAL" => { type => "field", addr => 0x31224, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_SW_EVENTBUS" => { type => "reg", addr => 0x31228, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_SW_EVENTBUS.VALID" => { type => "field", addr => 0x31228, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_SW_EVENTBUS.IN" => { type => "field", addr => 0x31228, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0" => { type => "reg", addr => 0x3122c, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_MEM_CNTL_0.hwsch_fes_setup_ram_awt" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.hwsch_fes_setup_ram_pd" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.hwsch_fes_setup_ram_rtsel" => { type => "field", addr => 0x3122c, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_0.hwsch_fes_setup_ram_wtsel" => { type => "field", addr => 0x3122c, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_0.hwsch_tx_status_ram_pd" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.hwsch_tx_status_ram_rtsel" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.hwsch_tx_status_ram_tsel" => { type => "field", addr => 0x3122c, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_0.hwsch_tx_status_ram_turbo" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_0.rxpcu_rxbuf_ram_awt" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.rxpcu_rxbuf_ram_pd" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.rxpcu_rxbuf_ram_rtsel" => { type => "field", addr => 0x3122c, width => 2, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_0.rxpcu_rxbuf_ram_wtsel" => { type => "field", addr => 0x3122c, width => 2, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_0.ole_tx_buf_ram_pd" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.ole_rx_buf_ram_pd" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.txpcu_gen_frames_ram_awt" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.txpcu_gen_frames_ram_pd" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.txpcu_gen_frames_ram_rtsel" => { type => "field", addr => 0x3122c, width => 2, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_0.txpcu_gen_frames_ram_wtsel" => { type => "field", addr => 0x3122c, width => 2, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_0.txpcu_txbuf_ram_awt" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.txpcu_txbuf_ram_pd" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_0.txpcu_txbuf_ram_rtsel" => { type => "field", addr => 0x3122c, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_0.txpcu_txbuf_ram_wtsel" => { type => "field", addr => 0x3122c, width => 2, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_0.trc_ram_awt" => { type => "field", addr => 0x3122c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_1" => { type => "reg", addr => 0x31230, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_MEM_CNTL_1.trc_ram_pd" => { type => "field", addr => 0x31230, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_MEM_CNTL_1.trc_ram_rtsel" => { type => "field", addr => 0x31230, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MEM_CNTL_1.trc_ram_wtsel" => { type => "field", addr => 0x31230, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MCMN_MAC_IDLE" => { type => "reg", addr => 0x31234, width => 32, athEmulAttr => 0, acc => "RO" }, "MCMN_MAC_IDLE.MXI" => { type => "field", addr => 0x31234, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.AMPI_RX" => { type => "field", addr => 0x31234, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.AMPI_TX" => { type => "field", addr => 0x31234, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.CRYPTO_RX" => { type => "field", addr => 0x31234, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.CRYPTO_TX" => { type => "field", addr => 0x31234, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.RXPCU" => { type => "field", addr => 0x31234, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.TXPCU" => { type => "field", addr => 0x31234, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.OLE_RX" => { type => "field", addr => 0x31234, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.OLE_TX" => { type => "field", addr => 0x31234, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.RXDMA" => { type => "field", addr => 0x31234, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.TXDMA" => { type => "field", addr => 0x31234, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.PDG" => { type => "field", addr => 0x31234, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.HWSCH" => { type => "field", addr => 0x31234, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.RX" => { type => "field", addr => 0x31234, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MCMN_MAC_IDLE.TX" => { type => "field", addr => 0x31234, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "MAC_PCU_RX_FRAME_CNT" => { type => "reg", addr => 0x31238, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_RX_FRAME_CNT.VALUE" => { type => "field", addr => 0x31238, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_TX_FRAME_CNT" => { type => "reg", addr => 0x3123c, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_TX_FRAME_CNT.VALUE" => { type => "field", addr => 0x3123c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_PCU_RX_CLEAR_CNT" => { type => "reg", addr => 0x31240, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_PCU_RX_CLEAR_CNT.VALUE" => { type => "field", addr => 0x31240, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_EVENTBUS_MASK0" => { type => "reg", addr => 0x31248, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_EVENTBUS_MASK0.VAL" => { type => "field", addr => 0x31248, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MCMN_EVENTBUS_MASK1" => { type => "reg", addr => 0x3124c, width => 32, athEmulAttr => 0, acc => "RW" }, "MCMN_EVENTBUS_MASK1.VAL" => { type => "field", addr => 0x3124c, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wmac_top_reg_map.mac_trc_reg Register/Field definitions ################################################################### "MAC_TRC" => { type => "reg", addr => 0x31c00, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC.OBS_BUS_SEL" => { type => "field", addr => 0x31c00, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC.MAC_MODULE_SEL" => { type => "field", addr => 0x31c00, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC.CPU_ACCESS_EN_VALUE" => { type => "field", addr => 0x31c00, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC.BUF_CFG_VALUE" => { type => "field", addr => 0x31c00, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC.ENABLE_VALUE" => { type => "field", addr => 0x31c00, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_BUF_INIT" => { type => "reg", addr => 0x31c04, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_BUF_INIT.VALUE" => { type => "field", addr => 0x31c04, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_ADDR" => { type => "reg", addr => 0x31c08, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_ADDR.END_VALUE" => { type => "field", addr => 0x31c08, width => 14, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_ADDR.START_VALUE" => { type => "field", addr => 0x31c08, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_WFT_CAPTURE_CTRL" => { type => "reg", addr => 0x31c0c, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_WFT_CAPTURE_CTRL.CAP_MODE" => { type => "field", addr => 0x31c0c, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_WFT_CAPTURE_CTRL.CAP_MASK" => { type => "field", addr => 0x31c0c, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_WFT_STATE_CTRL" => { type => "reg", addr => 0x31c10, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_WFT_STATE_CTRL.MAX_CAP_CNT" => { type => "field", addr => 0x31c10, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_WFT_STATE_CTRL.NXT_TS_EN" => { type => "field", addr => 0x31c10, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS1_CAPTURE_CTRL" => { type => "reg", addr => 0x31c14, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS1_CAPTURE_CTRL.CAP_MODE" => { type => "field", addr => 0x31c14, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS1_CAPTURE_CTRL.CAP_MASK" => { type => "field", addr => 0x31c14, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS1_STATE_CTRL" => { type => "reg", addr => 0x31c18, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS1_STATE_CTRL.MAX_CAP_CNT" => { type => "field", addr => 0x31c18, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS1_STATE_CTRL.NXT_TS_EN" => { type => "field", addr => 0x31c18, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS1_TRIG_MASK" => { type => "reg", addr => 0x31c1c, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS1_TRIG_MASK.VALUE" => { type => "field", addr => 0x31c1c, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS1_TRIG" => { type => "reg", addr => 0x31c20, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS1_TRIG.VALUE" => { type => "field", addr => 0x31c20, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS2_CAPTURE_CTRL" => { type => "reg", addr => 0x31c24, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS2_CAPTURE_CTRL.CAP_MODE" => { type => "field", addr => 0x31c24, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS2_CAPTURE_CTRL.CAP_MASK" => { type => "field", addr => 0x31c24, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS2_STATE_CTRL" => { type => "reg", addr => 0x31c28, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS2_STATE_CTRL.MAX_CAP_CNT" => { type => "field", addr => 0x31c28, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS2_STATE_CTRL.NXT_TS_EN" => { type => "field", addr => 0x31c28, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS2_TRIG_MASK" => { type => "reg", addr => 0x31c2c, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS2_TRIG_MASK.VALUE" => { type => "field", addr => 0x31c2c, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS2_TRIG" => { type => "reg", addr => 0x31c30, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS2_TRIG.VALUE" => { type => "field", addr => 0x31c30, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS3_CAPTURE_CTRL" => { type => "reg", addr => 0x31c34, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS3_CAPTURE_CTRL.CAP_MODE" => { type => "field", addr => 0x31c34, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS3_CAPTURE_CTRL.CAP_MASK" => { type => "field", addr => 0x31c34, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS3_STATE_CTRL" => { type => "reg", addr => 0x31c38, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS3_STATE_CTRL.MAX_CAP_CNT" => { type => "field", addr => 0x31c38, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS3_STATE_CTRL.NXT_TS_EN" => { type => "field", addr => 0x31c38, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS3_TRIG_MASK" => { type => "reg", addr => 0x31c3c, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS3_TRIG_MASK.VALUE" => { type => "field", addr => 0x31c3c, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS3_TRIG" => { type => "reg", addr => 0x31c40, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS3_TRIG.VALUE" => { type => "field", addr => 0x31c40, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS4_CAPTURE_CTRL" => { type => "reg", addr => 0x31c44, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS4_CAPTURE_CTRL.CAP_MODE" => { type => "field", addr => 0x31c44, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS4_CAPTURE_CTRL.CAP_MASK" => { type => "field", addr => 0x31c44, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS4_STATE_CTRL" => { type => "reg", addr => 0x31c48, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS4_STATE_CTRL.MAX_CAP_CNT" => { type => "field", addr => 0x31c48, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS4_STATE_CTRL.NXT_TS_EN" => { type => "field", addr => 0x31c48, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS4_TRIG_MASK" => { type => "reg", addr => 0x31c4c, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS4_TRIG_MASK.VALUE" => { type => "field", addr => 0x31c4c, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS4_TRIG" => { type => "reg", addr => 0x31c50, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS4_TRIG.VALUE" => { type => "field", addr => 0x31c50, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS5_CAPTURE_CTRL" => { type => "reg", addr => 0x31c54, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS5_CAPTURE_CTRL.CAP_MODE" => { type => "field", addr => 0x31c54, width => 2, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS5_CAPTURE_CTRL.CAP_MASK" => { type => "field", addr => 0x31c54, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS5_STATE_CTRL" => { type => "reg", addr => 0x31c58, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS5_STATE_CTRL.MAX_CAP_CNT" => { type => "field", addr => 0x31c58, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS5_STATE_CTRL.NXT_TS_EN" => { type => "field", addr => 0x31c58, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS5_TRIG_MASK" => { type => "reg", addr => 0x31c5c, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS5_TRIG_MASK.VALUE" => { type => "field", addr => 0x31c5c, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_TS5_TRIG" => { type => "reg", addr => 0x31c60, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TS5_TRIG.VALUE" => { type => "field", addr => 0x31c60, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_CPU_ADDR" => { type => "reg", addr => 0x31c64, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_CPU_ADDR.READ_VALUE" => { type => "field", addr => 0x31c64, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_CPU_DATA" => { type => "reg", addr => 0x31c68, width => 32, athEmulAttr => 0, acc => "RO" }, "MAC_TRC_CPU_DATA.VALUE" => { type => "field", addr => 0x31c68, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MAC_TRC_STATUS_0" => { type => "reg", addr => 0x31c6c, width => 32, athEmulAttr => 0, acc => "RO" }, "MAC_TRC_STATUS_0.BUF_INIT_DONE" => { type => "field", addr => 0x31c6c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MAC_TRC_STATUS_0.BUF_FULL" => { type => "field", addr => 0x31c6c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MAC_TRC_STATUS_1" => { type => "reg", addr => 0x31c70, width => 32, athEmulAttr => 0, acc => "RO" }, "MAC_TRC_STATUS_1.BUF_RD_END_ADDR" => { type => "field", addr => 0x31c70, width => 14, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MAC_TRC_STATUS_1.BUF_RD_START_ADDR" => { type => "field", addr => 0x31c70, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MAC_TRC_STATUS_2" => { type => "reg", addr => 0x31c74, width => 32, athEmulAttr => 0, acc => "RO" }, "MAC_TRC_STATUS_2.TRIG_EVENT_FLAGS" => { type => "field", addr => 0x31c74, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MAC_TRC_STATUS_2.MAIN_CTL_STATE" => { type => "field", addr => 0x31c74, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MAC_TRC_STATUS_2.WRCTL_STATE" => { type => "field", addr => 0x31c74, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MAC_TRC_STATUS_3" => { type => "reg", addr => 0x31c78, width => 32, athEmulAttr => 0, acc => "RO" }, "MAC_TRC_STATUS_3.TRIG_SAMPLE" => { type => "field", addr => 0x31c78, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MAC_BB_OBS_BUS_SEL" => { type => "reg", addr => 0x31c7c, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_BB_OBS_BUS_SEL.VALUE" => { type => "field", addr => 0x31c7c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_CPU_DATA_READ_DATA_SEL" => { type => "reg", addr => 0x31c80, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_CPU_DATA_READ_DATA_SEL.VALUE" => { type => "field", addr => 0x31c80, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MAC_TRC_LANE_SWAP" => { type => "reg", addr => 0x31c84, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_LANE_SWAP.SEL" => { type => "field", addr => 0x31c84, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0F }, "MAC_TRC_CLK_GATE_DISABLE" => { type => "reg", addr => 0x31c88, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_CLK_GATE_DISABLE.VAL" => { type => "field", addr => 0x31c88, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MAC_TRC_TIME_STAMP" => { type => "reg", addr => 0x31c8c, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_TRC_TIME_STAMP.SEL" => { type => "field", addr => 0x31c8c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wmac_top_reg_map.mac_rxpcu_reg Register/Field definitions ################################################################### "RXPCU_BSSID2_L32" => { type => "reg", addr => 0x32000, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_BSSID2_L32.ADDR" => { type => "field", addr => 0x32000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BSSID2_U16" => { type => "reg", addr => 0x32004, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_BSSID2_U16.AID" => { type => "field", addr => 0x32004, width => 11, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BSSID2_U16.ENABLE" => { type => "field", addr => 0x32004, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BSSID2_U16.ADDR" => { type => "field", addr => 0x32004, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BSSID3_L32" => { type => "reg", addr => 0x32008, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_BSSID3_L32.ADDR" => { type => "field", addr => 0x32008, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BSSID3_U16" => { type => "reg", addr => 0x3200c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_BSSID3_U16.ENABLE" => { type => "field", addr => 0x3200c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BSSID3_U16.ADDR" => { type => "field", addr => 0x3200c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BSSID4_L32" => { type => "reg", addr => 0x32010, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_BSSID4_L32.ADDR" => { type => "field", addr => 0x32010, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BSSID4_U16" => { type => "reg", addr => 0x32014, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_BSSID4_U16.ENABLE" => { type => "field", addr => 0x32014, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BSSID4_U16.ADDR" => { type => "field", addr => 0x32014, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_ADDR1_MASK_L32" => { type => "reg", addr => 0x32018, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_ADDR1_MASK_L32.VALUE" => { type => "field", addr => 0x32018, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFFF }, "RXPCU_ADDR1_MASK_U16" => { type => "reg", addr => 0x3201c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_ADDR1_MASK_U16.VALUE" => { type => "field", addr => 0x3201c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, "RXPCU_MCAST_FILTER_L32" => { type => "reg", addr => 0x32020, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MCAST_FILTER_L32.VALUE" => { type => "field", addr => 0x32020, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MCAST_FILTER_U32" => { type => "reg", addr => 0x32024, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MCAST_FILTER_U32.VALUE" => { type => "field", addr => 0x32024, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER" => { type => "reg", addr => 0x32028, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_RX_FILTER.BSSID_BASED_MULTICAST" => { type => "field", addr => 0x32028, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.PHY_DATA" => { type => "field", addr => 0x32028, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.MY_BEACON2" => { type => "field", addr => 0x32028, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.GENERIC_FILTER" => { type => "field", addr => 0x32028, width => 2, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.GENERIC_FTYPE" => { type => "field", addr => 0x32028, width => 6, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.FROM_TO_DS" => { type => "field", addr => 0x32028, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.CONTROL_WRAPPER" => { type => "field", addr => 0x32028, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.MGMT_ACTION_MCAST" => { type => "field", addr => 0x32028, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.HW_BCN_PROC_ENABLE" => { type => "field", addr => 0x32028, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.MCAST_BCAST_ALL" => { type => "field", addr => 0x32028, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.PS_POLL" => { type => "field", addr => 0x32028, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.RESERVED_0" => { type => "field", addr => 0x32028, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.UNCOMPRESSED_BA_BAR" => { type => "field", addr => 0x32028, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.COMPRESSED_BA" => { type => "field", addr => 0x32028, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.COMPRESSED_BAR" => { type => "field", addr => 0x32028, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.MY_BEACON" => { type => "field", addr => 0x32028, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.PROBE_REQ" => { type => "field", addr => 0x32028, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.PROMISCUOUS" => { type => "field", addr => 0x32028, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.BEACON" => { type => "field", addr => 0x32028, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.CONTROL" => { type => "field", addr => 0x32028, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.BROADCAST" => { type => "field", addr => 0x32028, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.MULTICAST" => { type => "field", addr => 0x32028, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER.UNICAST" => { type => "field", addr => 0x32028, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER2" => { type => "reg", addr => 0x3202c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_RX_FILTER2.BRPOLL" => { type => "field", addr => 0x3202c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER2.NDPA" => { type => "field", addr => 0x3202c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_FILTER2.BSSID_BASED_UNICAST" => { type => "field", addr => 0x3202c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_DATA_LENGTH_THRESH" => { type => "reg", addr => 0x32030, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_DATA_LENGTH_THRESH.ENABLE" => { type => "field", addr => 0x32030, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_DATA_LENGTH_THRESH.VALUE" => { type => "field", addr => 0x32030, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x64 }, "RXPCU_BCN_RSSI_CTL" => { type => "reg", addr => 0x32034, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_BCN_RSSI_CTL.RESET" => { type => "field", addr => 0x32034, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BCN_RSSI_CTL.WEIGHT" => { type => "field", addr => 0x32034, width => 5, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BCN_RSSI_CTL.RSSI_HIGH_THRESH" => { type => "field", addr => 0x32034, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BCN_RSSI_CTL.MISS_THRESH" => { type => "field", addr => 0x32034, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BCN_RSSI_CTL.RSSI_LOW_THRESH" => { type => "field", addr => 0x32034, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BCN_RSSI_CTL2" => { type => "reg", addr => 0x32038, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_BCN_RSSI_CTL2.RESET2" => { type => "field", addr => 0x32038, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BCN_RSSI_CTL2.RSSI2_HIGH_THRESH" => { type => "field", addr => 0x32038, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BCN_RSSI_CTL2.RSSI2_LOW_THRESH" => { type => "field", addr => 0x32038, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_BCN_RSSI_AVE" => { type => "reg", addr => 0x3203c, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_BCN_RSSI_AVE.AVE_VALUE2" => { type => "field", addr => 0x3203c, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x800 }, "RXPCU_BCN_RSSI_AVE.AVE_VALUE" => { type => "field", addr => 0x3203c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x800 }, "RXPCU_FILTER_RSSI_AVE" => { type => "reg", addr => 0x32040, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_FILTER_RSSI_AVE.RESET" => { type => "field", addr => 0x32040, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_FILTER_RSSI_AVE.ENABLE" => { type => "field", addr => 0x32040, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_FILTER_RSSI_AVE.NUM_FRAMES_EXPONENT" => { type => "field", addr => 0x32040, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "RXPCU_FILTER_RSSI_AVE.AVE_VALUE" => { type => "field", addr => 0x32040, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "RXPCU_BA_BAR_CONTROL" => { type => "reg", addr => 0x32044, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_BA_BAR_CONTROL.SEARCH_DEPTH" => { type => "field", addr => 0x32044, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "RXPCU_BA_BAR_CONTROL.FORCE_NO_MATCH" => { type => "field", addr => 0x32044, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RTT_CTRL" => { type => "reg", addr => 0x32048, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_RTT_CTRL.CATEGORY" => { type => "field", addr => 0x32048, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0xb }, "RXPCU_RTT_CTRL.ALLOW_HT_VHT_ACK_BA" => { type => "field", addr => 0x32048, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RTT_CTRL.ACTION" => { type => "field", addr => 0x32048, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXPCU_RTT_CTRL.FREEZE_CHANNEL_CAPTURE_CLEAR" => { type => "field", addr => 0x32048, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_XRSTMP" => { type => "reg", addr => 0x3204c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_XRSTMP.RX_ABORT_RSSI_THRESH" => { type => "field", addr => 0x3204c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x25 }, "RXPCU_XRSTMP.RX_ABORT_DATA" => { type => "field", addr => 0x3204c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_XRSTMP.RX_ABORT_BSSID" => { type => "field", addr => 0x3204c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_XRSTMP.RX_ABORT_RSSI" => { type => "field", addr => 0x3204c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXBF_CNTL" => { type => "reg", addr => 0x32050, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_TXBF_CNTL.NDP_TIMEOUT_VALUE" => { type => "field", addr => 0x32050, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x780 }, "RXPCU_TXBF_CNTL.SIFS_TIME" => { type => "field", addr => 0x32050, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXBF_CNTL.MAX_NC_INDEX" => { type => "field", addr => 0x32050, width => 3, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXPCU_TXBF_CNTL.CHECK_CH_STATUS_EN" => { type => "field", addr => 0x32050, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_IMPLICIT_BF_CTRL" => { type => "reg", addr => 0x32054, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_IMPLICIT_BF_CTRL.TIMEOUT_VALUE" => { type => "field", addr => 0x32054, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x780 }, "RXPCU_SEC_CHANNEL_RX_PIFS_CNT" => { type => "reg", addr => 0x32058, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_SEC_CHANNEL_RX_PIFS_CNT.VALUE" => { type => "field", addr => 0x32058, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xA50 }, "RXPCU_PROXY_STA" => { type => "reg", addr => 0x3205c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PROXY_STA.MERU_VC_MODE" => { type => "field", addr => 0x3205c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PROXY_STA.INVALID_ENTRY_NO_ACK_BSSID4" => { type => "field", addr => 0x3205c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PROXY_STA.INVALID_ENTRY_NO_ACK_BSSID3" => { type => "field", addr => 0x3205c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PROXY_STA.INVALID_ENTRY_NO_ACK_BSSID2" => { type => "field", addr => 0x3205c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PROXY_STA.INVALID_ENTRY_NO_ACK_BSSID1" => { type => "field", addr => 0x3205c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PROXY_STA.PROXY_STA_AD1_SEARCH_BSSID4" => { type => "field", addr => 0x3205c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PROXY_STA.PROXY_STA_AD1_SEARCH_BSSID3" => { type => "field", addr => 0x3205c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PROXY_STA.PROXY_STA_AD1_SEARCH_BSSID2" => { type => "field", addr => 0x3205c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PROXY_STA.PROXY_STA_AD1_SEARCH_BSSID1" => { type => "field", addr => 0x3205c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_ANTENNA" => { type => "reg", addr => 0x32060, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_RX_ANTENNA.VALUE" => { type => "field", addr => 0x32060, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CLASS_1_FRAME_CFG1" => { type => "reg", addr => 0x32064, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_CLASS_1_FRAME_CFG1.CTL_BITMAP" => { type => "field", addr => 0x32064, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CLASS_1_FRAME_CFG1.MGMT_BITMAP" => { type => "field", addr => 0x32064, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_NAV_CFG" => { type => "reg", addr => 0x32068, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_NAV_CFG.EN_11G_MODE" => { type => "field", addr => 0x32068, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_NAV_CFG.NAV_UPDATE_FOR_MU_EN" => { type => "field", addr => 0x32068, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_NAV_CFG.OFDM" => { type => "field", addr => 0x32068, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x3C }, "RXPCU_NAV_CFG.CCK" => { type => "field", addr => 0x32068, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x13A }, "RXPCU_CLASS_1_FRAME_CFG2" => { type => "reg", addr => 0x3206c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_CLASS_1_FRAME_CFG2.TYPE11_BITMAP" => { type => "field", addr => 0x3206c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CLASS_1_FRAME_CFG2.DATA_BITMAP" => { type => "field", addr => 0x3206c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DIRECT_CONNECT" => { type => "reg", addr => 0x32070, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_DIRECT_CONNECT.ONE_USEC" => { type => "field", addr => 0x32070, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x81 }, "RXPCU_DIRECT_CONNECT.SYNC_TSF_ON_UCAST_PROBE_RESP" => { type => "field", addr => 0x32070, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DIRECT_CONNECT.SYNC_TSF_ON_UCAST_MOON_PROBE_RESP" => { type => "field", addr => 0x32070, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DIRECT_CONNECT.SYNC_TSF_ON_MCAST_PROBE_RESP" => { type => "field", addr => 0x32070, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DIRECT_CONNECT.SYNC_TSF_ON_BCAST_PROBE_RESP" => { type => "field", addr => 0x32070, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DIRECT_CONNECT.SYNC_TSF_ON_BEACON" => { type => "field", addr => 0x32070, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXPCU_DIRECT_CONNECT.RX_LATENCY" => { type => "field", addr => 0x32070, width => 6, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "RXPCU_DIRECT_CONNECT.BMISS_CNT_OVERRIDE" => { type => "field", addr => 0x32070, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DIRECT_CONNECT.MY_BEACON2_OVERRIDE" => { type => "field", addr => 0x32070, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DIRECT_CONNECT.MY_BEACON_OVERRIDE" => { type => "field", addr => 0x32070, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_LAST_BEACON_TSF" => { type => "reg", addr => 0x32074, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_LAST_BEACON_TSF.VALUE" => { type => "field", addr => 0x32074, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_LAST_BEACON2_TSF" => { type => "reg", addr => 0x32078, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_LAST_BEACON2_TSF.VALUE" => { type => "field", addr => 0x32078, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1" => { type => "reg", addr => 0x3207c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_HW_BCN_PROC1.ELM2_ID" => { type => "field", addr => 0x3207c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1.ELM1_ID" => { type => "field", addr => 0x3207c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1.ELM0_ID" => { type => "field", addr => 0x3207c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1.EXCLUDE_ELM2" => { type => "field", addr => 0x3207c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1.EXCLUDE_ELM1" => { type => "field", addr => 0x3207c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1.EXCLUDE_ELM0" => { type => "field", addr => 0x3207c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1.EXCLUDE_TIM_ELM" => { type => "field", addr => 0x3207c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1.EXCLUDE_CAP_INFO" => { type => "field", addr => 0x3207c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1.EXCLUDE_BCN_INTVL" => { type => "field", addr => 0x3207c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1.RESET_CRC" => { type => "field", addr => 0x3207c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC1.CRC_ENABLE" => { type => "field", addr => 0x3207c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC2" => { type => "reg", addr => 0x32080, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_HW_BCN_PROC2.ELM3_ID" => { type => "field", addr => 0x32080, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC2.FILTER_INTERVAL" => { type => "field", addr => 0x32080, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "RXPCU_HW_BCN_PROC2.EXCLUDE_ELM3" => { type => "field", addr => 0x32080, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC2.RESET_INTERVAL" => { type => "field", addr => 0x32080, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_HW_BCN_PROC2.FILTER_INTERVAL_ENABLE" => { type => "field", addr => 0x32080, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DYM_MIMO_PWR_SAVE" => { type => "reg", addr => 0x32084, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_DYM_MIMO_PWR_SAVE.HI_PWR_CHAIN_MASK" => { type => "field", addr => 0x32084, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "RXPCU_DYM_MIMO_PWR_SAVE.LOW_PWR_CHAIN_MASK" => { type => "field", addr => 0x32084, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXPCU_DYM_MIMO_PWR_SAVE.SW_CHAIN_MASK_SEL" => { type => "field", addr => 0x32084, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DYM_MIMO_PWR_SAVE.HW_CTRL_EN" => { type => "field", addr => 0x32084, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DYM_MIMO_PWR_SAVE.USE_MAC_CTRL" => { type => "field", addr => 0x32084, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0" => { type => "reg", addr => 0x32088, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_POWER_SAVE_0.PHY_ON_OFF_DELAY" => { type => "field", addr => 0x32088, width => 12, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0xc8 }, "RXPCU_POWER_SAVE_0.CONSIDER_FILTER_PASS" => { type => "field", addr => 0x32088, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.ADDR_MISMATCH_DATA_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.ADDR_MISMATCH_MGMT_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.ADDR_MISMATCH_CNTL_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.PHY_NAP_EIFS_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.RSSI_CHECK_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.GID_NSTS_ZERO_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.DELIMITER_CRC_FAIL_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.MAC_ADDRESS_MISMATCH_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.EARLY_DTIM_CLEAR_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.EARLY_TIM_CLEAR_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.EOF_PAD_DELIMITER_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.GID_MATCH_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_0.PARTIAL_AID_MATCH_ENABLE" => { type => "field", addr => 0x32088, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_1" => { type => "reg", addr => 0x3208c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_POWER_SAVE_1.P_AID_2_MATCH_EN" => { type => "field", addr => 0x3208c, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_1.P_AID_2_MATCH_VALUE" => { type => "field", addr => 0x3208c, width => 9, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_1.P_AID_1_MATCH_EN" => { type => "field", addr => 0x3208c, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_1.P_AID_1_MATCH_VALUE" => { type => "field", addr => 0x3208c, width => 9, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_1.P_AID_0_MATCH_EN" => { type => "field", addr => 0x3208c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_1.P_AID_0_MATCH_VALUE" => { type => "field", addr => 0x3208c, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_2" => { type => "reg", addr => 0x32090, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_POWER_SAVE_2.P_AID_5_MATCH_EN" => { type => "field", addr => 0x32090, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_2.P_AID_5_MATCH_VALUE" => { type => "field", addr => 0x32090, width => 9, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_2.P_AID_4_MATCH_EN" => { type => "field", addr => 0x32090, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_2.P_AID_4_MATCH_VALUE" => { type => "field", addr => 0x32090, width => 9, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_2.P_AID_3_MATCH_EN" => { type => "field", addr => 0x32090, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_2.P_AID_3_MATCH_VALUE" => { type => "field", addr => 0x32090, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_3" => { type => "reg", addr => 0x32094, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_POWER_SAVE_3.GID_LSB_BITMAP_VALUE" => { type => "field", addr => 0x32094, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_4" => { type => "reg", addr => 0x32098, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_POWER_SAVE_4.GID_MSB_BITMAP_VALUE" => { type => "field", addr => 0x32098, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_5" => { type => "reg", addr => 0x3209c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_POWER_SAVE_5.GID_USER_NUMBER_REGISTER_0" => { type => "field", addr => 0x3209c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_6" => { type => "reg", addr => 0x320a0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_POWER_SAVE_6.GID_USER_NUMBER_REGISTER_1" => { type => "field", addr => 0x320a0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_7" => { type => "reg", addr => 0x320a4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_POWER_SAVE_7.GID_USER_NUMBER_REGISTER_2" => { type => "field", addr => 0x320a4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_POWER_SAVE_8" => { type => "reg", addr => 0x320a8, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_POWER_SAVE_8.GID_USER_NUMBER_REGISTER_3" => { type => "field", addr => 0x320a8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_CLEAR_PHY_DLY_SEC20" => { type => "reg", addr => 0x320b0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_RX_CLEAR_PHY_DLY_SEC20.EN" => { type => "field", addr => 0x320b0, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_CLEAR_PHY_DLY_SEC20.CNT" => { type => "field", addr => 0x320b0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x77 }, "RXPCU_RX_CLEAR_PHY_DLY_SEC40" => { type => "reg", addr => 0x320b4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_RX_CLEAR_PHY_DLY_SEC40.EN" => { type => "field", addr => 0x320b4, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_CLEAR_PHY_DLY_SEC40.CNT" => { type => "field", addr => 0x320b4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x77 }, "RXPCU_RX_CLEAR_PHY_DLY_SEC80" => { type => "reg", addr => 0x320b8, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_RX_CLEAR_PHY_DLY_SEC80.EN" => { type => "field", addr => 0x320b8, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RX_CLEAR_PHY_DLY_SEC80.CNT" => { type => "field", addr => 0x320b8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x77 }, "RXPCU_AST_TIMEOUT" => { type => "reg", addr => 0x320bc, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_AST_TIMEOUT.VALUE" => { type => "field", addr => 0x320bc, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x4b0 }, "RXPCU_ASE_AST_BASE_ADDR" => { type => "reg", addr => 0x320c0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_ASE_AST_BASE_ADDR.VALUE" => { type => "field", addr => 0x320c0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_ASE_AST_SIZE" => { type => "reg", addr => 0x320c4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_ASE_AST_SIZE.VALUE" => { type => "field", addr => 0x320c4, width => 13, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_ASE_SEARCH_CTRL" => { type => "reg", addr => 0x320c8, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_ASE_SEARCH_CTRL.TIMEOUT_THRESH" => { type => "field", addr => 0x320c8, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_ASE_SEARCH_CTRL.ADDR_SEARCH_SWAP" => { type => "field", addr => 0x320c8, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_ASE_SEARCH_CTRL.MAX_SEARCH" => { type => "field", addr => 0x320c8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_ASE_HASH_CTRL" => { type => "reg", addr => 0x320cc, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_ASE_HASH_CTRL.CACHE_INVALIDATE" => { type => "field", addr => 0x320cc, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_ASE_HASH_CTRL.CACHE_DISABLE" => { type => "field", addr => 0x320cc, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_ASE_HASH_CTRL.HASH_MAC_31_0_IGNORE" => { type => "field", addr => 0x320cc, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_ASE_HASH_CTRL.HASH_SEL" => { type => "field", addr => 0x320cc, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_ASE_HASH_CTRL.HASH_MCAST_SHIFT" => { type => "field", addr => 0x320cc, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "RXPCU_ASE_HASH_CTRL.HASH_XOR" => { type => "field", addr => 0x320cc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xabcd }, "RXPCU_MISC_MODE" => { type => "reg", addr => 0x320d0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MISC_MODE.ALWAYS_PERFORM_KEY_SEARCH" => { type => "field", addr => 0x320d0, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE.CLEAR_BA_VALID" => { type => "field", addr => 0x320d0, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE.MISS_BEACON_IN_SLEEP" => { type => "field", addr => 0x320d0, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXPCU_MISC_MODE.DEBUG_MODE_BA_BITMAP" => { type => "field", addr => 0x320d0, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE.PHY_ERR_BT_COLL_ENABLE" => { type => "field", addr => 0x320d0, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE.ENABLE_COEX_AUTO_PHY_OFF" => { type => "field", addr => 0x320d0, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXPCU_MISC_MODE.BSSID_MATCH_FORCE" => { type => "field", addr => 0x320d0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE2" => { type => "reg", addr => 0x320d4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MISC_MODE2.MPDU_DENSITY_STS_FIX" => { type => "field", addr => 0x320d4, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE2.NO_CRYPTO_FOR_NON_DATA_PKT" => { type => "field", addr => 0x320d4, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE3" => { type => "reg", addr => 0x320d8, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MISC_MODE3.KEY_MISS_FIX" => { type => "field", addr => 0x320d8, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXPCU_MISC_MODE3.BEACON_FROM_TO_DS_CHECK" => { type => "field", addr => 0x320d8, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXPCU_MISC_MODE3.ALLOW_RAC" => { type => "field", addr => 0x320d8, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE3.WL_MED_BUSY_TIMER_TARGET" => { type => "field", addr => 0x320d8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, "RXPCU_MISC_MODE4" => { type => "reg", addr => 0x320dc, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MISC_MODE4.HT_RTS_PIFS_CHECK_EN" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE4.HT_RTS_DYNAMIC_EN" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE4.ACK_TO_PCF_HCF_EN" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "RXPCU_MISC_MODE4.EIFS_FOR_MU_EN" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE4.PEER_ENTRY_SWAP" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE4.IGNORE_FCS_ERR_FOR_EIFS" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE4.ALWAYS_REQ_IMPLICIT_FB" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE4.WAPI_BSSID4" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE4.WAPI_BSSID3" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE4.WAPI_BSSID2" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE4.WAPI_BSSID1" => { type => "field", addr => 0x320dc, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_DIAGNOSTIC_MODE" => { type => "reg", addr => 0x320e0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_DIAGNOSTIC_MODE.RXBUF_DEBUG_EN" => { type => "field", addr => 0x320e0, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_WATCHDOG" => { type => "reg", addr => 0x320e4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_WATCHDOG.STATUS" => { type => "field", addr => 0x320e4, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_WATCHDOG.LIMIT" => { type => "field", addr => 0x320e4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xffff }, "RXPCU_MISC_MODE5" => { type => "reg", addr => 0x320e8, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MISC_MODE5.WAPI_VAP_ENABLE" => { type => "field", addr => 0x320e8, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE5.FIRST_MPDU_SET_FOR_PASSING" => { type => "field", addr => 0x320e8, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE5.ALLOW_FREEZE_ON_PROBE_RESPONSE" => { type => "field", addr => 0x320e8, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE5.WAPI_WDS_ENABLE" => { type => "field", addr => 0x320e8, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE5.WAPI_WDS_USE_ADDR1" => { type => "field", addr => 0x320e8, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MISC_MODE5.WAPI_VAP_OFFSET_LSB" => { type => "field", addr => 0x320e8, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "RXPCU_FCS_FAIL_CNT" => { type => "reg", addr => 0x320f0, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_FCS_FAIL_CNT.VALUE" => { type => "field", addr => 0x320f0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_BEACON_CNT" => { type => "reg", addr => 0x320f4, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_BEACON_CNT.VALUE" => { type => "field", addr => 0x320f4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_BEACON2_CNT" => { type => "reg", addr => 0x320f8, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_BEACON2_CNT.VALUE" => { type => "field", addr => 0x320f8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_FILTER_OFDM_CNT" => { type => "reg", addr => 0x32104, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_FILTER_OFDM_CNT.VALUE" => { type => "field", addr => 0x32104, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_FILTER_CCK_CNT" => { type => "reg", addr => 0x32108, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_FILTER_CCK_CNT.VALUE" => { type => "field", addr => 0x32108, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_SIFS_RESP_STATUS" => { type => "reg", addr => 0x3210c, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_SIFS_RESP_STATUS.SEQUENCE_CONTROL" => { type => "field", addr => 0x3210c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_SIFS_RESP_STATUS.QOS_CONTROL" => { type => "field", addr => 0x3210c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_SIFS_RESP_STATUS2" => { type => "reg", addr => 0x32110, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_SIFS_RESP_STATUS2.BW" => { type => "field", addr => 0x32110, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_SIFS_RESP_STATUS2.PEER_IDX" => { type => "field", addr => 0x32110, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_SIFS_RESP_STATUS3" => { type => "reg", addr => 0x32114, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_SIFS_RESP_STATUS3.AID" => { type => "field", addr => 0x32114, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_SIFS_RESP_STATUS3.FRAME_CONTOL" => { type => "field", addr => 0x32114, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_PHY_ERROR_MASK" => { type => "reg", addr => 0x32120, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERROR_MASK.VALUE" => { type => "field", addr => 0x32120, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERROR_MASK_CONT" => { type => "reg", addr => 0x32124, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERROR_MASK_CONT.VALUE" => { type => "field", addr => 0x32124, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERROR_EIFS_MASK" => { type => "reg", addr => 0x32128, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERROR_EIFS_MASK.VALUE" => { type => "field", addr => 0x32128, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERROR_EIFS_MASK_CONT" => { type => "reg", addr => 0x3212c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERROR_EIFS_MASK_CONT.VALUE" => { type => "field", addr => 0x3212c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERROR_AIFS" => { type => "reg", addr => 0x32130, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERROR_AIFS.MASK_ENABLE" => { type => "field", addr => 0x32130, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERROR_AIFS_MASK" => { type => "reg", addr => 0x32134, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERROR_AIFS_MASK.VALUE" => { type => "field", addr => 0x32134, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERROR_AIFS_MASK_CONT" => { type => "reg", addr => 0x32138, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERROR_AIFS_MASK_CONT.VALUE" => { type => "field", addr => 0x32138, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERR_CNT_1" => { type => "reg", addr => 0x3213c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERR_CNT_1.VALUE" => { type => "field", addr => 0x3213c, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERR_CNT_1_MASK" => { type => "reg", addr => 0x32140, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERR_CNT_1_MASK.VALUE" => { type => "field", addr => 0x32140, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERR_CNT_1_MASK_CONT" => { type => "reg", addr => 0x32144, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERR_CNT_1_MASK_CONT.VALUE" => { type => "field", addr => 0x32144, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERR_CNT_2" => { type => "reg", addr => 0x32148, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERR_CNT_2.VALUE" => { type => "field", addr => 0x32148, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERR_CNT_2_MASK" => { type => "reg", addr => 0x3214c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERR_CNT_2_MASK.VALUE" => { type => "field", addr => 0x3214c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERR_CNT_2_MASK_CONT" => { type => "reg", addr => 0x32150, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERR_CNT_2_MASK_CONT.VALUE" => { type => "field", addr => 0x32150, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERR_CNT_3" => { type => "reg", addr => 0x32154, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERR_CNT_3.VALUE" => { type => "field", addr => 0x32154, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERR_CNT_3_MASK" => { type => "reg", addr => 0x32158, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERR_CNT_3_MASK.VALUE" => { type => "field", addr => 0x32158, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERR_CNT_3_MASK_CONT" => { type => "reg", addr => 0x3215c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERR_CNT_3_MASK_CONT.VALUE" => { type => "field", addr => 0x3215c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TEST_CFG" => { type => "reg", addr => 0x32160, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_TEST_CFG.TESTBUS_SEL" => { type => "field", addr => 0x32160, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TEST_CFG.SEL" => { type => "field", addr => 0x32160, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TESTBUS" => { type => "reg", addr => 0x32164, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_TESTBUS.VALUE" => { type => "field", addr => 0x32164, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_FSM_STATUS" => { type => "reg", addr => 0x32168, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_FSM_STATUS.VALUE" => { type => "field", addr => 0x32168, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_SPARE_REG1" => { type => "reg", addr => 0x3216c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_SPARE_REG1.VALUE" => { type => "field", addr => 0x3216c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_SPARE_REG2" => { type => "reg", addr => 0x32170, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_SPARE_REG2.VALUE" => { type => "field", addr => 0x32170, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x200 }, "RXPCU_PHY_INTF_TLV_CNT1" => { type => "reg", addr => 0x32174, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_INTF_TLV_CNT1.RX_PHY_PPDU_END_CNT" => { type => "field", addr => 0x32174, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_CNT1.RX_RSSI_LEGACY_CNT" => { type => "field", addr => 0x32174, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_CNT2" => { type => "reg", addr => 0x32178, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_INTF_TLV_CNT2.RX_11B_PKT_CNT" => { type => "field", addr => 0x32178, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_CNT2.RX_PKT_END_CNT" => { type => "field", addr => 0x32178, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_CNT2.RX_PKT_USER0_CNT" => { type => "field", addr => 0x32178, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_CNT2.RX_TERMINATE_CNT" => { type => "field", addr => 0x32178, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_CNT3" => { type => "reg", addr => 0x3217c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_INTF_TLV_CNT3.RX_11AC_MU_PKT_CNT" => { type => "field", addr => 0x3217c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_CNT3.RX_11AC_SU_PKT_CNT" => { type => "field", addr => 0x3217c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_CNT3.RX_11N_PKT_CNT" => { type => "field", addr => 0x3217c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_CNT3.RX_11A_PKT_CNT" => { type => "field", addr => 0x3217c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_RCVD" => { type => "reg", addr => 0x32184, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_PHY_INTF_TLV_RCVD.BITMAP_PREVIOUS" => { type => "field", addr => 0x32184, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_PHY_INTF_TLV_RCVD.BITMAP_CURRENT" => { type => "field", addr => 0x32184, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT1" => { type => "reg", addr => 0x32190, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_TXPCU_INTF_TLV_CNT1.TX_FRAME_INFO_CNT" => { type => "field", addr => 0x32190, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT2" => { type => "reg", addr => 0x32194, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_TXPCU_INTF_TLV_CNT2.RX_MESSAGE_CNT" => { type => "field", addr => 0x32194, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT2.RX_RESP_CNT" => { type => "field", addr => 0x32194, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT2.RX_FRAME_INFO_CNT" => { type => "field", addr => 0x32194, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT2.IMPLICIT_FB_CNT" => { type => "field", addr => 0x32194, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT3" => { type => "reg", addr => 0x32198, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_TXPCU_INTF_TLV_CNT3.NDP_NOT_RCVD_CNT" => { type => "field", addr => 0x32198, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT3.NDP_TIMEOUT_CNT" => { type => "field", addr => 0x32198, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT3.TX_CBF_INFO_CNT" => { type => "field", addr => 0x32198, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT3.EXPECT_NDP_CNT" => { type => "field", addr => 0x32198, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT3.NDPA_RCVD_CNT" => { type => "field", addr => 0x32198, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT4" => { type => "reg", addr => 0x3219c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_TXPCU_INTF_TLV_CNT4.TX_FREEZE_CNT" => { type => "field", addr => 0x3219c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT4.PHY_NAP_CNT" => { type => "field", addr => 0x3219c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT4.PHY_OFF_CNT" => { type => "field", addr => 0x3219c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_CNT4.PHY_ON_CNT" => { type => "field", addr => 0x3219c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TXPCU_INTF_TLV_BITMAP" => { type => "reg", addr => 0x321a0, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_TXPCU_INTF_TLV_BITMAP.BITMAP" => { type => "field", addr => 0x321a0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_CRYPTO_INTF_TLV_CNT1" => { type => "reg", addr => 0x321b0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_CRYPTO_INTF_TLV_CNT1.RX_MPDU_END_CNT" => { type => "field", addr => 0x321b0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CRYPTO_INTF_TLV_CNT1.RX_MPDU_PCU_START_CNT" => { type => "field", addr => 0x321b0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CRYPTO_INTF_TLV_CNT1.RX_PPDU_END_CNT" => { type => "field", addr => 0x321b0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CRYPTO_INTF_TLV_CNT1.RX_PPDU_START_CNT" => { type => "field", addr => 0x321b0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_TRIC_FSM_STATUS" => { type => "reg", addr => 0x321b4, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_TRIC_FSM_STATUS.FSM_STATUS" => { type => "field", addr => 0x321b4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_TRIC_DEBUG_STATUS" => { type => "reg", addr => 0x321b8, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_TRIC_DEBUG_STATUS.DEBUG_STATUS" => { type => "field", addr => 0x321b8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_DPSM_FSM_STATUS" => { type => "reg", addr => 0x321c0, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_DPSM_FSM_STATUS.FSM_STATUS" => { type => "field", addr => 0x321c0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_DPSM_DEBUG_STATUS" => { type => "reg", addr => 0x321c4, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_DPSM_DEBUG_STATUS.DEBUG_STATUS" => { type => "field", addr => 0x321c4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_RXSM_FSM_STATUS" => { type => "reg", addr => 0x321d0, width => 32, athEmulAttr => 0, acc => "RO" }, "RXPCU_RXSM_FSM_STATUS.FSM_STATUS" => { type => "field", addr => 0x321d0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RXPCU_PKT_DEBUG_CNT1" => { type => "reg", addr => 0x321d4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PKT_DEBUG_CNT1.AMPDU_CNT" => { type => "field", addr => 0x321d4, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PKT_DEBUG_CNT1.MPDU_CNT" => { type => "field", addr => 0x321d4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PKT_DEBUG_CNT2" => { type => "reg", addr => 0x321d8, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PKT_DEBUG_CNT2.FILTER_OUT_CNT" => { type => "field", addr => 0x321d8, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PKT_DEBUG_CNT2.FILTER_IN_CNT" => { type => "field", addr => 0x321d8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_EVENTBUS_MASK1" => { type => "reg", addr => 0x321dc, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_EVENTBUS_MASK1.VALUE" => { type => "field", addr => 0x321dc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_EVENTBUS_MASK2" => { type => "reg", addr => 0x321e0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_EVENTBUS_MASK2.VALUE" => { type => "field", addr => 0x321e0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CMNTRIG_CFG" => { type => "reg", addr => 0x321e4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_CMNTRIG_CFG.TESTBUS_SEL" => { type => "field", addr => 0x321e4, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CMNTRIG_CFG.SEL" => { type => "field", addr => 0x321e4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CMNTRIG_MASK_L32" => { type => "reg", addr => 0x321e8, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_CMNTRIG_MASK_L32.VALUE" => { type => "field", addr => 0x321e8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CMNTRIG_MASK_U03" => { type => "reg", addr => 0x321ec, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_CMNTRIG_MASK_U03.VALUE" => { type => "field", addr => 0x321ec, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CMNTRIG_MATCH_L32" => { type => "reg", addr => 0x321f0, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_CMNTRIG_MATCH_L32.VALUE" => { type => "field", addr => 0x321f0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CMNTRIG_MATCH_U03" => { type => "reg", addr => 0x321f4, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_CMNTRIG_MATCH_U03.VALUE" => { type => "field", addr => 0x321f4, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CRYPTO_INTF_TLV_CNT2" => { type => "reg", addr => 0x321f8, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_CRYPTO_INTF_TLV_CNT2.RX_PPDU_START_CNT" => { type => "field", addr => 0x321f8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MAX_RX_LENGTH_DATA" => { type => "reg", addr => 0x32200, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MAX_RX_LENGTH_DATA.VALUE" => { type => "field", addr => 0x32200, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MAX_RX_LENGTH_CTRL" => { type => "reg", addr => 0x32204, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MAX_RX_LENGTH_CTRL.VALUE" => { type => "field", addr => 0x32204, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MAX_RX_LENGTH_MGMT" => { type => "reg", addr => 0x32208, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MAX_RX_LENGTH_MGMT.VALUE" => { type => "field", addr => 0x32208, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MAX_RX_LENGTH_ERR_CNT" => { type => "reg", addr => 0x3220c, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_MAX_RX_LENGTH_ERR_CNT.MGMT_ERR_CNT" => { type => "field", addr => 0x3220c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MAX_RX_LENGTH_ERR_CNT.CTRL_ERR_CNT" => { type => "field", addr => 0x3220c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_MAX_RX_LENGTH_ERR_CNT.DATA_ERR_CNT" => { type => "field", addr => 0x3220c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_CLKGATE_EN" => { type => "reg", addr => 0x32210, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_CLKGATE_EN.CLKGATE_EN" => { type => "field", addr => 0x32210, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERROR_PROMISCUOUS_MASK" => { type => "reg", addr => 0x32214, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERROR_PROMISCUOUS_MASK.VALUE" => { type => "field", addr => 0x32214, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_PHY_ERROR_PROMISCUOUS_MASK_CONT" => { type => "reg", addr => 0x32218, width => 32, athEmulAttr => 0, acc => "RW" }, "RXPCU_PHY_ERROR_PROMISCUOUS_MASK_CONT.VALUE" => { type => "field", addr => 0x32218, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "RXPCU_RXBUF" => { type => "reg", addr => 0x33000, width => 32, athEmulAttr => 0, acc => "RW", depth => 2048, incr => 4 }, "RXPCU_RXBUF.DATA" => { type => "field", addr => 0x33000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wmac_top_reg_map.mac_txpcu_reg Register/Field definitions ################################################################### "TXPCU_TIMEOUT" => { type => "reg", addr => 0x36000, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_TIMEOUT.DATA_WAIT_TIME" => { type => "field", addr => 0x36000, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0xC }, "TXPCU_TIMEOUT.PREAMBLE_WAIT_TIME" => { type => "field", addr => 0x36000, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "TXPCU_TIMEOUT.CTS_TIMEOUT" => { type => "field", addr => 0x36000, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x30 }, "TXPCU_TIMEOUT.ACK_TIMEOUT" => { type => "field", addr => 0x36000, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x40 }, "TXPCU_CV_LENGTH_TIMEOUT" => { type => "reg", addr => 0x36004, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_CV_LENGTH_TIMEOUT.VALUE" => { type => "field", addr => 0x36004, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "TXPCU_WATCHDOG" => { type => "reg", addr => 0x36008, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_WATCHDOG.STATUS" => { type => "field", addr => 0x36008, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_WATCHDOG.LIMIT" => { type => "field", addr => 0x36008, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x2710 }, "TXPCU_INITIAL_CREDIT" => { type => "reg", addr => 0x3600c, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_INITIAL_CREDIT.VALUE_USER2" => { type => "field", addr => 0x3600c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "TXPCU_INITIAL_CREDIT.VALUE_USER1" => { type => "field", addr => 0x3600c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "TXPCU_INITIAL_CREDIT.VALUE_USER0" => { type => "field", addr => 0x3600c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "TXPCU_BASIC_RATE_SET0" => { type => "reg", addr => 0x36010, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_BASIC_RATE_SET0.VALUE" => { type => "field", addr => 0x36010, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x31dcfb5b }, "TXPCU_BASIC_RATE_SET1" => { type => "reg", addr => 0x36014, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_BASIC_RATE_SET1.VALUE" => { type => "field", addr => 0x36014, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x12a52d7c }, "TXPCU_BASIC_RATE_SET2" => { type => "reg", addr => 0x36018, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_BASIC_RATE_SET2.VALUE" => { type => "field", addr => 0x36018, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x14a5a529 }, "TXPCU_BASIC_RATE_SET3" => { type => "reg", addr => 0x3601c, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_BASIC_RATE_SET3.VALUE" => { type => "field", addr => 0x3601c, width => 25, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x94a529 }, "TXPCU_BASIC_RATE_SET4" => { type => "reg", addr => 0x36020, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_BASIC_RATE_SET4.VALUE" => { type => "field", addr => 0x36020, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x129 }, "TXPCU_BASIC_SET" => { type => "reg", addr => 0x36024, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_BASIC_SET.MCS" => { type => "field", addr => 0x36024, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_SIFS_TIMEOUT" => { type => "reg", addr => 0x36030, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_SIFS_TIMEOUT.VALUE" => { type => "field", addr => 0x36030, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "TXPCU_PHY_TX_LATENCY" => { type => "reg", addr => 0x36034, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_PHY_TX_LATENCY.VALUE" => { type => "field", addr => 0x36034, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_TX_ANT_CTL" => { type => "reg", addr => 0x3603c, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_TX_ANT_CTL.RUCKUS_ANT_MODE_SEL" => { type => "field", addr => 0x3603c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "TXPCU_TX_ANT_CTL.STRB_RATE_SEL" => { type => "field", addr => 0x3603c, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "TXPCU_TX_ANT_CTL.DEF_ANT_VALUE" => { type => "field", addr => 0x3603c, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_MGMT_SEQ" => { type => "reg", addr => 0x36044, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_MGMT_SEQ.MAX" => { type => "field", addr => 0x36044, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x2ff }, "TXPCU_MGMT_SEQ.MIN" => { type => "field", addr => 0x36044, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_MISC_MODE" => { type => "reg", addr => 0x36048, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_MISC_MODE.ENABLE_SEQNUM_BITMAP_SWAP" => { type => "field", addr => 0x36048, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_MISC_MODE.ENABLE_BA_BITMAP_SWAP" => { type => "field", addr => 0x36048, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_MISC_MODE.IGNORE_FLUSH_FOR_CV_VALID" => { type => "field", addr => 0x36048, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "TXPCU_MISC_MODE.RESP_ENABLE" => { type => "field", addr => 0x36048, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_MISC_MODE.RTT_ENABLE" => { type => "field", addr => 0x36048, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_MISC_MODE.IBF_ENABLE" => { type => "field", addr => 0x36048, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_MISC_MODE.ALLOW_RAC" => { type => "field", addr => 0x36048, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_RTT_CTRL" => { type => "reg", addr => 0x3604c, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_RTT_CTRL.ALLOW_HT_VHT_ACK_BA" => { type => "field", addr => 0x3604c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_TXBUF_DRAIN_THRESHOLD" => { type => "reg", addr => 0x36050, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_TXBUF_DRAIN_THRESHOLD.VALUE" => { type => "field", addr => 0x36050, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_20" => { type => "reg", addr => 0x36054, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_CBF_RESP_CTL_20.VALID" => { type => "field", addr => 0x36054, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_20.PKT_TYPE" => { type => "field", addr => 0x36054, width => 2, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_20.SGI" => { type => "field", addr => 0x36054, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_20.LDPC" => { type => "field", addr => 0x36054, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_20.STBC" => { type => "field", addr => 0x36054, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_20.TX_PWR" => { type => "field", addr => 0x36054, width => 7, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_20.DPD_ENABLE" => { type => "field", addr => 0x36054, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_20.TPC_INIT_PWR_CFG" => { type => "field", addr => 0x36054, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_20.NSS" => { type => "field", addr => 0x36054, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_20.RATE_MCS" => { type => "field", addr => 0x36054, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_40" => { type => "reg", addr => 0x36058, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_CBF_RESP_CTL_40.VALID" => { type => "field", addr => 0x36058, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_40.PKT_TYPE" => { type => "field", addr => 0x36058, width => 2, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "TXPCU_CBF_RESP_CTL_40.SGI" => { type => "field", addr => 0x36058, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_40.LDPC" => { type => "field", addr => 0x36058, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_40.STBC" => { type => "field", addr => 0x36058, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_40.TX_PWR" => { type => "field", addr => 0x36058, width => 7, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_40.DPD_ENABLE" => { type => "field", addr => 0x36058, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_40.TPC_INIT_PWR_CFG" => { type => "field", addr => 0x36058, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_40.NSS" => { type => "field", addr => 0x36058, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_40.RATE_MCS" => { type => "field", addr => 0x36058, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_80" => { type => "reg", addr => 0x3605c, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_CBF_RESP_CTL_80.VALID" => { type => "field", addr => 0x3605c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "TXPCU_CBF_RESP_CTL_80.PKT_TYPE" => { type => "field", addr => 0x3605c, width => 2, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "TXPCU_CBF_RESP_CTL_80.SGI" => { type => "field", addr => 0x3605c, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_80.LDPC" => { type => "field", addr => 0x3605c, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_80.STBC" => { type => "field", addr => 0x3605c, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_80.TX_PWR" => { type => "field", addr => 0x3605c, width => 7, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_80.DPD_ENABLE" => { type => "field", addr => 0x3605c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_80.TPC_INIT_PWR_CFG" => { type => "field", addr => 0x3605c, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_80.NSS" => { type => "field", addr => 0x3605c, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_80.RATE_MCS" => { type => "field", addr => 0x3605c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_160" => { type => "reg", addr => 0x36060, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_CBF_RESP_CTL_160.VALID" => { type => "field", addr => 0x36060, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "TXPCU_CBF_RESP_CTL_160.PKT_TYPE" => { type => "field", addr => 0x36060, width => 2, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "TXPCU_CBF_RESP_CTL_160.SGI" => { type => "field", addr => 0x36060, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_160.LDPC" => { type => "field", addr => 0x36060, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_160.STBC" => { type => "field", addr => 0x36060, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_160.TX_PWR" => { type => "field", addr => 0x36060, width => 7, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_160.DPD_ENABLE" => { type => "field", addr => 0x36060, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_160.TPC_INIT_PWR_CFG" => { type => "field", addr => 0x36060, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_160.NSS" => { type => "field", addr => 0x36060, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_CBF_RESP_CTL_160.RATE_MCS" => { type => "field", addr => 0x36060, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_DYNAMIC_BW_CTL" => { type => "reg", addr => 0x36064, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_DYNAMIC_BW_CTL.USE_RTS_BW_FOR_PPDU" => { type => "field", addr => 0x36064, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_DYNAMIC_BW_CTL.VHT_SERVICE_DYNAMIC" => { type => "field", addr => 0x36064, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "TXPCU_DYNAMIC_BW_CTL.DPD_TRAINING_SELF_CTS_BW" => { type => "field", addr => 0x36064, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_DYNAMIC_BW_CTL.HT_DYNAMIC_CBW" => { type => "field", addr => 0x36064, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_DYNAMIC_BW_CTL.HT_AGC_DYNAMIC_BW_SEL" => { type => "field", addr => 0x36064, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_TXBUF_CONTROL" => { type => "reg", addr => 0x36068, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_TXBUF_CONTROL.DEBUG_ENABLE" => { type => "field", addr => 0x36068, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_REQD_TLVS_WAIT_TIME" => { type => "reg", addr => 0x3606c, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_REQD_TLVS_WAIT_TIME.VALUE" => { type => "field", addr => 0x3606c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_TIMEOUT_11AC_DATA_WAIT_TIME" => { type => "reg", addr => 0x36070, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_TIMEOUT_11AC_DATA_WAIT_TIME.VALUE" => { type => "field", addr => 0x36070, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xC }, "TXPCU_DEBUG_STATE" => { type => "reg", addr => 0x36074, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_STATE.INFORMATION" => { type => "field", addr => 0x36074, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x2A000000 }, "TXPCU_DEBUG_TX_FES_0" => { type => "reg", addr => 0x36078, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TX_FES_0.INFORMATION" => { type => "field", addr => 0x36078, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_FES_1" => { type => "reg", addr => 0x3607c, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TX_FES_1.INFORMATION" => { type => "field", addr => 0x3607c, width => 28, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_FES_2" => { type => "reg", addr => 0x36080, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TX_FES_2.INFORMATION" => { type => "field", addr => 0x36080, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_TRACEBUS_CTRL" => { type => "reg", addr => 0x36084, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_TRACEBUS_CTRL.SELECT" => { type => "field", addr => 0x36084, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "TXPCU_DEBUG_TRACE_BUS_LOWER" => { type => "reg", addr => 0x36088, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TRACE_BUS_LOWER.VALUE" => { type => "field", addr => 0x36088, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x8000000 }, "TXPCU_DEBUG_TRACE_BUS_UPPER" => { type => "reg", addr => 0x3608c, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TRACE_BUS_UPPER.VALUE" => { type => "field", addr => 0x3608c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_CREDIT_COUNTERS" => { type => "reg", addr => 0x36090, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_CREDIT_COUNTERS.INFORMATION" => { type => "field", addr => 0x36090, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_START_TX_CNT" => { type => "reg", addr => 0x36094, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_START_TX_CNT.VALUE" => { type => "field", addr => 0x36094, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_FLUSH_CNT" => { type => "reg", addr => 0x36098, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TX_FLUSH_CNT.VALUE" => { type => "field", addr => 0x36098, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RTS_SUCCESS_CNT" => { type => "reg", addr => 0x3609c, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_RTS_SUCCESS_CNT.VALUE" => { type => "field", addr => 0x3609c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RTS_FAIL_CNT" => { type => "reg", addr => 0x360a0, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_RTS_FAIL_CNT.VALUE" => { type => "field", addr => 0x360a0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_ACK_SUCCESS_CNT" => { type => "reg", addr => 0x360a4, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_ACK_SUCCESS_CNT.VALUE" => { type => "field", addr => 0x360a4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_ACK_FAIL_CNT" => { type => "reg", addr => 0x360a8, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_ACK_FAIL_CNT.VALUE" => { type => "field", addr => 0x360a8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_MPDU_TX_FRAME_CNT" => { type => "reg", addr => 0x360ac, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_MPDU_TX_FRAME_CNT.VALUE" => { type => "field", addr => 0x360ac, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_AMPDU_TX_FRAME_CNT" => { type => "reg", addr => 0x360b0, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_AMPDU_TX_FRAME_CNT.VALUE" => { type => "field", addr => 0x360b0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_PHY_ERROR_CNT" => { type => "reg", addr => 0x360b4, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TX_PHY_ERROR_CNT.VALUE" => { type => "field", addr => 0x360b4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_FRAME_CNT" => { type => "reg", addr => 0x360b8, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_RX_FRAME_CNT.VALUE" => { type => "field", addr => 0x360b8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_PDG_RESPONSE_CNT" => { type => "reg", addr => 0x360bc, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_PDG_RESPONSE_CNT.VALUE" => { type => "field", addr => 0x360bc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RESP_FRAME_SUCCESS_CNT" => { type => "reg", addr => 0x360c0, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_RESP_FRAME_SUCCESS_CNT.VALUE" => { type => "field", addr => 0x360c0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RESP_FRAME_FAIL_CNT" => { type => "reg", addr => 0x360c4, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_RESP_FRAME_FAIL_CNT.VALUE" => { type => "field", addr => 0x360c4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_FES_STATUS_UPDATE_CNT" => { type => "reg", addr => 0x360c8, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TX_FES_STATUS_UPDATE_CNT.VALUE" => { type => "field", addr => 0x360c8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_SELF_GEN_ERROR" => { type => "reg", addr => 0x360cc, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_SELF_GEN_ERROR.STATUS" => { type => "field", addr => 0x360cc, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_EVENT_BUS_MASK0" => { type => "reg", addr => 0x360d0, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_EVENT_BUS_MASK0.VALUE" => { type => "field", addr => 0x360d0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFFF }, "TXPCU_EVENT_BUS_MASK1" => { type => "reg", addr => 0x360d4, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_EVENT_BUS_MASK1.VALUE" => { type => "field", addr => 0x360d4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFFF }, "TXPCU_CLOCK_GATE_DISABLE" => { type => "reg", addr => 0x360d8, width => 32, athEmulAttr => 0, acc => "RW" }, "TXPCU_CLOCK_GATE_DISABLE.VALUE" => { type => "field", addr => 0x360d8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "TXPCU_DEBUG_RX_MESSAGE_TLV" => { type => "reg", addr => 0x360dc, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_RX_MESSAGE_TLV.SENT_COUNT" => { type => "field", addr => 0x360dc, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_TLV.RCVD_COUNT" => { type => "field", addr => 0x360dc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_COUNT0" => { type => "reg", addr => 0x360e0, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_RX_MESSAGE_COUNT0.PHY_OFF" => { type => "field", addr => 0x360e0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_COUNT0.PHY_ON" => { type => "field", addr => 0x360e0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_COUNT0.PHY_NAP" => { type => "field", addr => 0x360e0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_COUNT0.RX_CHAIN_MASK" => { type => "field", addr => 0x360e0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_COUNT1" => { type => "reg", addr => 0x360e4, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_RX_MESSAGE_COUNT1.TX_EXPECT_NDP" => { type => "field", addr => 0x360e4, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_COUNT1.REQ_IMPLICIT_FB" => { type => "field", addr => 0x360e4, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_COUNT1.TX_MAC_TIMEOUT" => { type => "field", addr => 0x360e4, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_COUNT1.TX_CBF_OFFSET" => { type => "field", addr => 0x360e4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_COUNT2" => { type => "reg", addr => 0x360e8, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_RX_MESSAGE_COUNT2.CLEAR_NDPA_FLAG" => { type => "field", addr => 0x360e8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_RX_MESSAGE_COUNT2.TX_FREEZE_CAPTURE_CHANNEL" => { type => "field", addr => 0x360e8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_MESSAGE_COUNT0" => { type => "reg", addr => 0x360ec, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TX_MESSAGE_COUNT0.MAC_PKT_END" => { type => "field", addr => 0x360ec, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_MESSAGE_COUNT0.EXPECT_CBF" => { type => "field", addr => 0x360ec, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_MESSAGE_COUNT0.BF_PARAMS" => { type => "field", addr => 0x360ec, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_MESSAGE_COUNT1" => { type => "reg", addr => 0x360f0, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TX_MESSAGE_COUNT1.TX_MAC_TIMEOUT" => { type => "field", addr => 0x360f0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_MESSAGE_COUNT1.TLV_TERMINATE" => { type => "field", addr => 0x360f0, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_MESSAGE_COUNT1.TLV_ABORT" => { type => "field", addr => 0x360f0, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_BFEE" => { type => "reg", addr => 0x360f4, width => 32, athEmulAttr => 0, acc => "RO" }, "TXPCU_DEBUG_TX_BFEE.CV_FRAME_INVALID" => { type => "field", addr => 0x360f4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_DEBUG_TX_BFEE.CV_FRAME_VALID" => { type => "field", addr => 0x360f4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "TXPCU_TXBUF" => { type => "reg", addr => 0x37000, width => 32, athEmulAttr => 0, acc => "RW", depth => 2560, incr => 4 }, "TXPCU_TXBUF.DATA" => { type => "field", addr => 0x37000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wmac_top_reg_map.mac_ampi_reg Register/Field definitions ################################################################### "AMPI_TX_SIFS_REG" => { type => "reg", addr => 0x3a000, width => 32, athEmulAttr => 0, acc => "RW" }, "AMPI_TX_SIFS_REG.tx_sifs_value" => { type => "field", addr => 0x3a000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "AMPI_CURRENT_TIMESTAMP_REG" => { type => "reg", addr => 0x3a004, width => 32, athEmulAttr => 0, acc => "RW" }, "AMPI_CURRENT_TIMESTAMP_REG.current_timestamp" => { type => "field", addr => 0x3a004, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "AMPI_PHY_TIMESTAMP1_REG" => { type => "reg", addr => 0x3a008, width => 32, athEmulAttr => 0, acc => "RO" }, "AMPI_PHY_TIMESTAMP1_REG.phy_timestamp1" => { type => "field", addr => 0x3a008, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_PHY_TIMESTAMP2_REG" => { type => "reg", addr => 0x3a00c, width => 32, athEmulAttr => 0, acc => "RO" }, "AMPI_PHY_TIMESTAMP2_REG.phy_timestamp2" => { type => "field", addr => 0x3a00c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_DEBUG_MODE_SELECT" => { type => "reg", addr => 0x3a010, width => 32, athEmulAttr => 0, acc => "RW" }, "AMPI_DEBUG_MODE_SELECT.debug_mode_select" => { type => "field", addr => 0x3a010, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "AMPI_PHY_CLOCK_GATE_DISABLE" => { type => "reg", addr => 0x3a014, width => 32, athEmulAttr => 0, acc => "RW" }, "AMPI_PHY_CLOCK_GATE_DISABLE.clock_gate_disable" => { type => "field", addr => 0x3a014, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3F }, "AMPI_DEBUG_RX_ERROR_COUNT" => { type => "reg", addr => 0x3a018, width => 32, athEmulAttr => 0, acc => "RO" }, "AMPI_DEBUG_RX_ERROR_COUNT.rx_tlv_error_count" => { type => "field", addr => 0x3a018, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_DEBUG_TX_ERROR_COUNT" => { type => "reg", addr => 0x3a01c, width => 32, athEmulAttr => 0, acc => "RO" }, "AMPI_DEBUG_TX_ERROR_COUNT.tx_tlv_error_count" => { type => "field", addr => 0x3a01c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_STALE_TIMESTAMP_COUNT" => { type => "reg", addr => 0x3a020, width => 32, athEmulAttr => 0, acc => "RO" }, "AMPI_STALE_TIMESTAMP_COUNT.stale_timestamp_count" => { type => "field", addr => 0x3a020, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_RX_SYNC_EVENT_COUNT" => { type => "reg", addr => 0x3a024, width => 32, athEmulAttr => 0, acc => "RO" }, "AMPI_RX_SYNC_EVENT_COUNT.rx_sync_event_count" => { type => "field", addr => 0x3a024, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_INSERT_TIMESTAMP_COUNT" => { type => "reg", addr => 0x3a028, width => 32, athEmulAttr => 0, acc => "RO" }, "AMPI_INSERT_TIMESTAMP_COUNT.insert_timestamp_count" => { type => "field", addr => 0x3a028, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_FEATURE_DISABLE" => { type => "reg", addr => 0x3a02c, width => 32, athEmulAttr => 0, acc => "RW" }, "AMPI_FEATURE_DISABLE.tod_capture_invalid" => { type => "field", addr => 0x3a02c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_FEATURE_DISABLE.tod_capture_valid" => { type => "field", addr => 0x3a02c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_FEATURE_DISABLE.tod_capture_expected" => { type => "field", addr => 0x3a02c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_FEATURE_DISABLE.enable_eco" => { type => "field", addr => 0x3a02c, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "AMPI_FEATURE_DISABLE.disable_rx_clear_filter" => { type => "field", addr => 0x3a02c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "AMPI_FEATURE_DISABLE.disable_timestamp_insertion" => { type => "field", addr => 0x3a02c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "AMPI_FEATURE_DISABLE.disable_stale_timestamp_detection" => { type => "field", addr => 0x3a02c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "AMPI_PHY_CAPTURED_TOA_REG" => { type => "reg", addr => 0x3a030, width => 32, athEmulAttr => 0, acc => "RO" }, "AMPI_PHY_CAPTURED_TOA_REG.phy_captured_toa" => { type => "field", addr => 0x3a030, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_PHY_CAPTURED_TOD_REG" => { type => "reg", addr => 0x3a034, width => 32, athEmulAttr => 0, acc => "RO" }, "AMPI_PHY_CAPTURED_TOD_REG.phy_captured_tod" => { type => "field", addr => 0x3a034, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "AMPI_MAC_CLOCK_GATE_DISABLE" => { type => "reg", addr => 0x3a818, width => 32, athEmulAttr => 0, acc => "RW" }, "AMPI_MAC_CLOCK_GATE_DISABLE.clock_gate_disable" => { type => "field", addr => 0x3a818, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xF }, ################################################################### ## wmac_top_reg_map.mac_crypto_reg Register/Field definitions ################################################################### "AES_MUTE_MASK_0" => { type => "reg", addr => 0x3f000, width => 32, athEmulAttr => 0, acc => "RW" }, "AES_MUTE_MASK_0.QoS" => { type => "field", addr => 0x3f000, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x000F }, "AES_MUTE_MASK_0.FC" => { type => "field", addr => 0x3f000, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x478F }, "AES_MUTE_MASK_1" => { type => "reg", addr => 0x3f004, width => 32, athEmulAttr => 0, acc => "RW" }, "AES_MUTE_MASK_1.FC_MGMT" => { type => "field", addr => 0x3f004, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0xE7FF }, "AES_MUTE_MASK_1.SEQ" => { type => "field", addr => 0x3f004, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000F }, "MIC_QOS_CONTROL" => { type => "reg", addr => 0x3f008, width => 32, athEmulAttr => 0, acc => "RW" }, "MIC_QOS_CONTROL.Mic_qos_control" => { type => "field", addr => 0x3f008, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00AA }, "MIC_QOS_SELECT" => { type => "reg", addr => 0x3f00c, width => 32, athEmulAttr => 0, acc => "RW" }, "MIC_QOS_SELECT.mic_qos_select" => { type => "field", addr => 0x3f00c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00003210 }, "ALT_AES_MUTE_MASK" => { type => "reg", addr => 0x3f010, width => 32, athEmulAttr => 0, acc => "RW" }, "ALT_AES_MUTE_MASK.QoS" => { type => "field", addr => 0x3f010, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x008F }, "Crypto_misc_Control" => { type => "reg", addr => 0x3f014, width => 32, athEmulAttr => 0, acc => "RW" }, "Crypto_misc_Control.MGMT_QOS" => { type => "field", addr => 0x3f014, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "Crypto_misc_Control.BC_MC_WAPI_MODE2" => { type => "field", addr => 0x3f014, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_misc_Control.BC_MC_WAPI_MODE2_EN" => { type => "field", addr => 0x3f014, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_misc_Control.NO_CRYPTO_FOR_NON_DATA_PKT" => { type => "field", addr => 0x3f014, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_misc_Control.crpt_mic_enable" => { type => "field", addr => 0x3f014, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_misc_Control.ZEROLEN_CRYPTO_ENABLE" => { type => "field", addr => 0x3f014, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "Crypto_misc_Control.WAPI_ORDER_MASK" => { type => "field", addr => 0x3f014, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_misc_Control.SM_STATE_CONTROL" => { type => "field", addr => 0x3f014, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_misc_Control.MGMT_CRYPTO_ENABLE" => { type => "field", addr => 0x3f014, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "Crypto_SM_States" => { type => "reg", addr => 0x3f018, width => 32, athEmulAttr => 0, acc => "RO" }, "Crypto_SM_States.sm_states" => { type => "field", addr => 0x3f018, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Crypto_testbus_sel" => { type => "reg", addr => 0x3f01c, width => 32, athEmulAttr => 0, acc => "RW" }, "Crypto_testbus_sel.Wapi_testsel" => { type => "field", addr => 0x3f01c, width => 3, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_testbus_sel.testbus_sel" => { type => "field", addr => 0x3f01c, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_testbus_LSB" => { type => "reg", addr => 0x3f020, width => 32, athEmulAttr => 0, acc => "RO" }, "Crypto_testbus_LSB.testbus" => { type => "field", addr => 0x3f020, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Crypto_testbus_MSB" => { type => "reg", addr => 0x3f024, width => 32, athEmulAttr => 0, acc => "RO" }, "Crypto_testbus_MSB.testbus" => { type => "field", addr => 0x3f024, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "DEBUG_Interrupt_Status" => { type => "reg", addr => 0x3f028, width => 32, athEmulAttr => 0, acc => "RO" }, "DEBUG_Interrupt_Status.Interrupt_status" => { type => "field", addr => 0x3f028, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Crypto_clock_gate_enable" => { type => "reg", addr => 0x3f02c, width => 32, athEmulAttr => 0, acc => "RW" }, "Crypto_clock_gate_enable.TKIP_clk_gate_enable" => { type => "field", addr => 0x3f02c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_clock_gate_enable.RC4_clk_gate_enable" => { type => "field", addr => 0x3f02c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_clock_gate_enable.WAPI_clk_gate_enable" => { type => "field", addr => 0x3f02c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_clock_gate_enable.AES2_clk_gate_enable" => { type => "field", addr => 0x3f02c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_clock_gate_enable.AES1_clk_gate_enable" => { type => "field", addr => 0x3f02c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_clock_gate_enable.AES0_clk_gate_enable" => { type => "field", addr => 0x3f02c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Crypto_clock_gate_enable.AES_clk_gate_enable" => { type => "field", addr => 0x3f02c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WATCHDOG_TIMER_VALUE" => { type => "reg", addr => 0x3f030, width => 32, athEmulAttr => 0, acc => "RO" }, "WATCHDOG_TIMER_VALUE.watchdog_value" => { type => "field", addr => 0x3f030, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Dbg_Crypto_counters_control" => { type => "reg", addr => 0x3f034, width => 32, athEmulAttr => 0, acc => "RW" }, "Dbg_Crypto_counters_control.rx_abort_cnt_enable" => { type => "field", addr => 0x3f034, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Dbg_Crypto_counters_control.rx_decr_frame_cnt_enable" => { type => "field", addr => 0x3f034, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Dbg_Crypto_counters_control.rx_mpdu_cnt_enable" => { type => "field", addr => 0x3f034, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "Dbg_Crypto_counters_control.tx_abort_cnt_enable" => { type => "field", addr => 0x3f034, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Dbg_Crypto_counters_control.tx_flush_req_cnt_enable" => { type => "field", addr => 0x3f034, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Dbg_Crypto_counters_control.tx_flush_rcv_cnt_enable" => { type => "field", addr => 0x3f034, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Dbg_Crypto_counters_control.tx_encr_frame_cnt_enable" => { type => "field", addr => 0x3f034, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Dbg_Crypto_counters_control.tx_mpdu_cnt_enable" => { type => "field", addr => 0x3f034, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "Dbg_tx_mpdu_cnt" => { type => "reg", addr => 0x3f038, width => 32, athEmulAttr => 0, acc => "RO" }, "Dbg_tx_mpdu_cnt.tx_mpdu_cnt" => { type => "field", addr => 0x3f038, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Dbg_tx_encr_frame_cnt" => { type => "reg", addr => 0x3f03c, width => 32, athEmulAttr => 0, acc => "RO" }, "Dbg_tx_encr_frame_cnt.tx_encr_frame_cnt" => { type => "field", addr => 0x3f03c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Dbg_tx_flush_rcv_cnt" => { type => "reg", addr => 0x3f040, width => 32, athEmulAttr => 0, acc => "RO" }, "Dbg_tx_flush_rcv_cnt.tx_flush_rcv_cnt" => { type => "field", addr => 0x3f040, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Dbg_tx_flush_req_cnt" => { type => "reg", addr => 0x3f044, width => 32, athEmulAttr => 0, acc => "RO" }, "Dbg_tx_flush_req_cnt.tx_flush_req_cnt" => { type => "field", addr => 0x3f044, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Dbg_tx_abort_cnt" => { type => "reg", addr => 0x3f048, width => 32, athEmulAttr => 0, acc => "RO" }, "Dbg_tx_abort_cnt.tx_abort_cnt" => { type => "field", addr => 0x3f048, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Dbg_rx_mpdu_cnt" => { type => "reg", addr => 0x3f04c, width => 32, athEmulAttr => 0, acc => "RO" }, "Dbg_rx_mpdu_cnt.rx_mpdu_cnt" => { type => "field", addr => 0x3f04c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Dbg_rx_decr_frame_cnt" => { type => "reg", addr => 0x3f050, width => 32, athEmulAttr => 0, acc => "RO" }, "Dbg_rx_decr_frame_cnt.rx_decr_frame_cnt" => { type => "field", addr => 0x3f050, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Dbg_rx_abort_cnt" => { type => "reg", addr => 0x3f054, width => 32, athEmulAttr => 0, acc => "RO" }, "Dbg_rx_abort_cnt.rx_abort_cnt" => { type => "field", addr => 0x3f054, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "Spare_Reg" => { type => "reg", addr => 0x3f058, width => 32, athEmulAttr => 0, acc => "RW" }, "Spare_Reg.spare_bits" => { type => "field", addr => 0x3f058, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "FIPS_Control" => { type => "reg", addr => 0x3f05c, width => 32, athEmulAttr => 0, acc => "RW" }, "FIPS_Control.aes_eng_1_2" => { type => "field", addr => 0x3f05c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FIPS_Control.aes_key_128_256" => { type => "field", addr => 0x3f05c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FIPS_Control.fips_test_enable" => { type => "field", addr => 0x3f05c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FIPS_AES_KEY" => { type => "reg", addr => 0x3f060, width => 32, athEmulAttr => 0, acc => "RW", depth => 8, incr => 4 }, "FIPS_AES_KEY.aes_key" => { type => "field", addr => 0x3f060, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FIPS_AES_DATA_IN" => { type => "reg", addr => 0x3f080, width => 32, athEmulAttr => 0, acc => "RW", depth => 4, incr => 4 }, "FIPS_AES_DATA_IN.aes_data_in" => { type => "field", addr => 0x3f080, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "FIPS_AES_DATA_OUT" => { type => "reg", addr => 0x3f090, width => 32, athEmulAttr => 0, acc => "RO", depth => 4, incr => 4 }, "FIPS_AES_DATA_OUT.aes_data_out" => { type => "field", addr => 0x3f090, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "EVENTBUS_MASK" => { type => "reg", addr => 0x3f0a0, width => 32, athEmulAttr => 0, acc => "RW" }, "EVENTBUS_MASK.Eventbus_mask" => { type => "field", addr => 0x3f0a0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFFF }, "WATCHDOG_TIMER_THRESHOLD" => { type => "reg", addr => 0x3f0a4, width => 32, athEmulAttr => 0, acc => "RW" }, "WATCHDOG_TIMER_THRESHOLD.watchdog_threshold" => { type => "field", addr => 0x3f0a4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wmac_top_reg_map.mac_hwsch_reg Register/Field definitions ################################################################### "HWSCH_DIFS_LIMIT_1_0" => { type => "reg", addr => 0x3f400, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_DIFS_LIMIT_1_0.sw_mtu_difs_limit_1" => { type => "field", addr => 0x3f400, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1c }, "HWSCH_DIFS_LIMIT_1_0.sw_mtu_difs_limit_0" => { type => "field", addr => 0x3f400, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x25 }, "HWSCH_DIFS_LIMIT_3_2" => { type => "reg", addr => 0x3f404, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_DIFS_LIMIT_3_2.sw_mtu_difs_limit_3" => { type => "field", addr => 0x3f404, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1c }, "HWSCH_DIFS_LIMIT_3_2.sw_mtu_difs_limit_2" => { type => "field", addr => 0x3f404, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x25 }, "HWSCH_DIFS_LIMIT_5_4" => { type => "reg", addr => 0x3f408, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_DIFS_LIMIT_5_4.sw_mtu_difs_limit_5" => { type => "field", addr => 0x3f408, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1c }, "HWSCH_DIFS_LIMIT_5_4.sw_mtu_difs_limit_4" => { type => "field", addr => 0x3f408, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x25 }, "HWSCH_DIFS_LIMIT_7_6" => { type => "reg", addr => 0x3f40c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_DIFS_LIMIT_7_6.sw_mtu_difs_limit_7" => { type => "field", addr => 0x3f40c, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1c }, "HWSCH_DIFS_LIMIT_7_6.sw_mtu_difs_limit_6" => { type => "field", addr => 0x3f40c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x25 }, "HWSCH_DIFS_LIMIT_9_8" => { type => "reg", addr => 0x3f410, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_DIFS_LIMIT_9_8.sw_mtu_difs_limit_9" => { type => "field", addr => 0x3f410, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1c }, "HWSCH_DIFS_LIMIT_9_8.sw_mtu_difs_limit_8" => { type => "field", addr => 0x3f410, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x25 }, "HWSCH_DIFS_LIMIT_11_10" => { type => "reg", addr => 0x3f414, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_DIFS_LIMIT_11_10.sw_mtu_difs_limit_11" => { type => "field", addr => 0x3f414, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1c }, "HWSCH_DIFS_LIMIT_11_10.sw_mtu_difs_limit_10" => { type => "field", addr => 0x3f414, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x25 }, "HWSCH_DIFS_LIMIT_13_12" => { type => "reg", addr => 0x3f418, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_DIFS_LIMIT_13_12.sw_mtu_difs_limit_13" => { type => "field", addr => 0x3f418, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1c }, "HWSCH_DIFS_LIMIT_13_12.sw_mtu_difs_limit_12" => { type => "field", addr => 0x3f418, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x25 }, "HWSCH_DIFS_LIMIT_15_14" => { type => "reg", addr => 0x3f41c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_DIFS_LIMIT_15_14.sw_mtu_difs_limit_15" => { type => "field", addr => 0x3f41c, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1c }, "HWSCH_DIFS_LIMIT_15_14.sw_mtu_difs_limit_14" => { type => "field", addr => 0x3f41c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x25 }, "HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT" => { type => "reg", addr => 0x3f420, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT.sw_pifs_limit" => { type => "field", addr => 0x3f420, width => 9, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x19 }, "HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT.sw_mtu_slot_limit" => { type => "field", addr => 0x3f420, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x09 }, "HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1" => { type => "reg", addr => 0x3f424, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1.sw_mtu_eifs_limit" => { type => "field", addr => 0x3f424, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x5a }, "HWSCH_COEX_CTRL" => { type => "reg", addr => 0x3f428, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_COEX_CTRL.BT_DISALLOW_SELF_GEN" => { type => "field", addr => 0x3f428, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_COEX_CTRL.QUIET_ACK_CTS_ENABLE" => { type => "field", addr => 0x3f428, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_COEX_CTRL.QUIET_CBF_ENABLE" => { type => "field", addr => 0x3f428, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_NAV_CNT" => { type => "reg", addr => 0x3f430, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_NAV_CNT.nav_cnt" => { type => "field", addr => 0x3f430, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xff }, "HWSCH_SW_MTU_SHADOW_NAV_CNT" => { type => "reg", addr => 0x3f434, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_MTU_SHADOW_NAV_CNT.sw_mtu_shadow_nav_cnt" => { type => "field", addr => 0x3f434, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xff }, "HWSCH_BKOF_CNT_0_1" => { type => "reg", addr => 0x3f438, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_BKOF_CNT_0_1.bkof_cnt_1" => { type => "field", addr => 0x3f438, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0004 }, "HWSCH_BKOF_CNT_0_1.bkof_cnt_0" => { type => "field", addr => 0x3f438, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0003 }, "HWSCH_BKOF_CNT_2_3" => { type => "reg", addr => 0x3f440, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_BKOF_CNT_2_3.bkof_cnt_3" => { type => "field", addr => 0x3f440, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0001 }, "HWSCH_BKOF_CNT_2_3.bkof_cnt_2" => { type => "field", addr => 0x3f440, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x7 }, "HWSCH_BKOF_CNT_4_5" => { type => "reg", addr => 0x3f448, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_BKOF_CNT_4_5.bkof_cnt_5" => { type => "field", addr => 0x3f448, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0005 }, "HWSCH_BKOF_CNT_4_5.bkof_cnt_4" => { type => "field", addr => 0x3f448, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0002 }, "HWSCH_BKOF_CNT_6_7" => { type => "reg", addr => 0x3f450, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_BKOF_CNT_6_7.bkof_cnt_7" => { type => "field", addr => 0x3f450, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0000 }, "HWSCH_BKOF_CNT_6_7.bkof_cnt_6" => { type => "field", addr => 0x3f450, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0006 }, "HWSCH_BKOF_CNT_8_9" => { type => "reg", addr => 0x3f458, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_BKOF_CNT_8_9.bkof_cnt_9" => { type => "field", addr => 0x3f458, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0000 }, "HWSCH_BKOF_CNT_8_9.bkof_cnt_8" => { type => "field", addr => 0x3f458, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0000 }, "HWSCH_BKOF_CNT_10_11" => { type => "reg", addr => 0x3f460, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_BKOF_CNT_10_11.bkof_cnt_11" => { type => "field", addr => 0x3f460, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0000 }, "HWSCH_BKOF_CNT_10_11.bkof_cnt_10" => { type => "field", addr => 0x3f460, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0000 }, "HWSCH_BKOF_CNT_12_13" => { type => "reg", addr => 0x3f468, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_BKOF_CNT_12_13.bkof_cnt_13" => { type => "field", addr => 0x3f468, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0000 }, "HWSCH_BKOF_CNT_12_13.bkof_cnt_12" => { type => "field", addr => 0x3f468, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0000 }, "HWSCH_BKOF_CNT_14_15" => { type => "reg", addr => 0x3f470, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_BKOF_CNT_14_15.bkof_cnt_15" => { type => "field", addr => 0x3f470, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0000 }, "HWSCH_BKOF_CNT_14_15.bkof_cnt_14" => { type => "field", addr => 0x3f470, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0000 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0" => { type => "reg", addr => 0x3f478, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f478, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0.sw_mtu_cw_reg_0" => { type => "field", addr => 0x3f478, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1" => { type => "reg", addr => 0x3f47c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f47c, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1.sw_mtu_cw_reg_1" => { type => "field", addr => 0x3f47c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2" => { type => "reg", addr => 0x3f480, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f480, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2.sw_mtu_cw_reg_2" => { type => "field", addr => 0x3f480, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3" => { type => "reg", addr => 0x3f484, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f484, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3.sw_mtu_cw_reg_3" => { type => "field", addr => 0x3f484, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4" => { type => "reg", addr => 0x3f488, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f488, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4.sw_mtu_cw_reg_4" => { type => "field", addr => 0x3f488, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5" => { type => "reg", addr => 0x3f48c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f48c, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5.sw_mtu_cw_reg_5" => { type => "field", addr => 0x3f48c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6" => { type => "reg", addr => 0x3f490, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f490, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6.sw_mtu_cw_reg_6" => { type => "field", addr => 0x3f490, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7" => { type => "reg", addr => 0x3f494, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f494, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7.sw_mtu_cw_reg_7" => { type => "field", addr => 0x3f494, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_8" => { type => "reg", addr => 0x3f498, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_8.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f498, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_8.sw_mtu_cw_reg_8" => { type => "field", addr => 0x3f498, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_9" => { type => "reg", addr => 0x3f49c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_9.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f49c, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_9.sw_mtu_cw_reg_9" => { type => "field", addr => 0x3f49c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_10" => { type => "reg", addr => 0x3f4a0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_10.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f4a0, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_10.sw_mtu_cw_reg_10" => { type => "field", addr => 0x3f4a0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_11" => { type => "reg", addr => 0x3f4a4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_11.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f4a4, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_11.sw_mtu_cw_reg_11" => { type => "field", addr => 0x3f4a4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_12" => { type => "reg", addr => 0x3f4a8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_12.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f4a8, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_12.sw_mtu_cw_reg_12" => { type => "field", addr => 0x3f4a8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_13" => { type => "reg", addr => 0x3f4ac, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_13.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f4ac, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_13.sw_mtu_cw_reg_13" => { type => "field", addr => 0x3f4ac, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_14" => { type => "reg", addr => 0x3f4b0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_14.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f4b0, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_14.sw_mtu_cw_reg_14" => { type => "field", addr => 0x3f4b0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_15" => { type => "reg", addr => 0x3f4b4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_15.sw_mtu_cw_update_valid" => { type => "field", addr => 0x3f4b4, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CW_REG_CONTROL_FOR_BACKOFF_15.sw_mtu_cw_reg_15" => { type => "field", addr => 0x3f4b4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_SW_CW_MIN_CW_MAX_0" => { type => "reg", addr => 0x3f4b8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_0.sw_cw_max_0" => { type => "field", addr => 0x3f4b8, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_0.sw_cw_min_0" => { type => "field", addr => 0x3f4b8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_1" => { type => "reg", addr => 0x3f4bc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_1.sw_cw_max_1" => { type => "field", addr => 0x3f4bc, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_1.sw_cw_min_1" => { type => "field", addr => 0x3f4bc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_2" => { type => "reg", addr => 0x3f4c0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_2.sw_cw_max_2" => { type => "field", addr => 0x3f4c0, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_SW_CW_MIN_CW_MAX_2.sw_cw_min_2" => { type => "field", addr => 0x3f4c0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0003 }, "HWSCH_SW_CW_MIN_CW_MAX_3" => { type => "reg", addr => 0x3f4c4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_3.sw_cw_max_3" => { type => "field", addr => 0x3f4c4, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_SW_CW_MIN_CW_MAX_3.sw_cw_min_3" => { type => "field", addr => 0x3f4c4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0003 }, "HWSCH_SW_CW_MIN_CW_MAX_4" => { type => "reg", addr => 0x3f4c8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_4.sw_cw_max_4" => { type => "field", addr => 0x3f4c8, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_SW_CW_MIN_CW_MAX_4.sw_cw_min_4" => { type => "field", addr => 0x3f4c8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0003 }, "HWSCH_SW_CW_MIN_CW_MAX_5" => { type => "reg", addr => 0x3f4cc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_5.sw_cw_max_5" => { type => "field", addr => 0x3f4cc, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_5.sw_cw_min_5" => { type => "field", addr => 0x3f4cc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_SW_CW_MIN_CW_MAX_6" => { type => "reg", addr => 0x3f4d0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_6.sw_cw_max_6" => { type => "field", addr => 0x3f4d0, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_6.sw_cw_min_6" => { type => "field", addr => 0x3f4d0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_7" => { type => "reg", addr => 0x3f4d4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_7.sw_cw_max_7" => { type => "field", addr => 0x3f4d4, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_7.sw_cw_min_7" => { type => "field", addr => 0x3f4d4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_8" => { type => "reg", addr => 0x3f4d8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_8.sw_cw_max_8" => { type => "field", addr => 0x3f4d8, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_8.sw_cw_min_8" => { type => "field", addr => 0x3f4d8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_9" => { type => "reg", addr => 0x3f4dc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_9.sw_cw_max_9" => { type => "field", addr => 0x3f4dc, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_9.sw_cw_min_9" => { type => "field", addr => 0x3f4dc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_10" => { type => "reg", addr => 0x3f4e0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_10.sw_cw_max_10" => { type => "field", addr => 0x3f4e0, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_10.sw_cw_min_10" => { type => "field", addr => 0x3f4e0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_11" => { type => "reg", addr => 0x3f4e4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_11.sw_cw_max_11" => { type => "field", addr => 0x3f4e4, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_11.sw_cw_min_11" => { type => "field", addr => 0x3f4e4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_12" => { type => "reg", addr => 0x3f4e8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_12.sw_cw_max_12" => { type => "field", addr => 0x3f4e8, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_12.sw_cw_min_12" => { type => "field", addr => 0x3f4e8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_13" => { type => "reg", addr => 0x3f4ec, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_13.sw_cw_max_13" => { type => "field", addr => 0x3f4ec, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_13.sw_cw_min_13" => { type => "field", addr => 0x3f4ec, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_14" => { type => "reg", addr => 0x3f4f0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_14.sw_cw_max_14" => { type => "field", addr => 0x3f4f0, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_14.sw_cw_min_14" => { type => "field", addr => 0x3f4f0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_SW_CW_MIN_CW_MAX_15" => { type => "reg", addr => 0x3f4f4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CW_MIN_CW_MAX_15.sw_cw_max_15" => { type => "field", addr => 0x3f4f4, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x03ff }, "HWSCH_SW_CW_MIN_CW_MAX_15.sw_cw_min_15" => { type => "field", addr => 0x3f4f4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x000f }, "HWSCH_CW_ACTION_CTRL" => { type => "reg", addr => 0x3f4f8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CW_ACTION_CTRL.cw_action_ctrl" => { type => "field", addr => 0x3f4f8, width => 26, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x10082 }, "HWSCH_MTU_TIMEOUT_STATUS" => { type => "reg", addr => 0x3f500, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_MTU_TIMEOUT_STATUS.quaternary_cca_to" => { type => "field", addr => 0x3f500, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_MTU_TIMEOUT_STATUS.tertiary_cca_to" => { type => "field", addr => 0x3f500, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_MTU_TIMEOUT_STATUS.secondary_cca_to" => { type => "field", addr => 0x3f500, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_MTU_TIMEOUT_STATUS.sifs_to" => { type => "field", addr => 0x3f500, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_MTU_TIMEOUT_STATUS.pifs_to" => { type => "field", addr => 0x3f500, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_CCA_COUNTER0" => { type => "reg", addr => 0x3f50c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CCA_COUNTER0.cca_counter0" => { type => "field", addr => 0x3f50c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_COUNTER1" => { type => "reg", addr => 0x3f510, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CCA_COUNTER1.cca_counter1" => { type => "field", addr => 0x3f510, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_COUNTER2" => { type => "reg", addr => 0x3f514, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CCA_COUNTER2.cca_counter2" => { type => "field", addr => 0x3f514, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_1" => { type => "reg", addr => 0x3f518, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CCA_CONTROL_REG_1.consider_rx_cca_only" => { type => "field", addr => 0x3f518, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CCA_CONTROL_REG_1.cca_count2_sel" => { type => "field", addr => 0x3f518, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CCA_CONTROL_REG_1.cca_count1_sel" => { type => "field", addr => 0x3f518, width => 3, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CCA_CONTROL_REG_1.sw_mtu_bkof_goto_idle" => { type => "field", addr => 0x3f518, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CCA_CONTROL_REG_1.sw_mtu_cca_flag" => { type => "field", addr => 0x3f518, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CCA_CONTROL_REG_1.sw_mtu_pifs_final_cca_sel" => { type => "field", addr => 0x3f518, width => 2, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CCA_CONTROL_REG_1.sw_mtu_pifs_raw_cca_sel" => { type => "field", addr => 0x3f518, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CCA_CONTROL_REG_1.sw_mtu_eifs_cca_sel" => { type => "field", addr => 0x3f518, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "HWSCH_CCA_CONTROL_REG_2" => { type => "reg", addr => 0x3f51c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CCA_CONTROL_REG_2.sw_mtu_quaternary_cca_limit" => { type => "field", addr => 0x3f51c, width => 9, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x19 }, "HWSCH_CCA_CONTROL_REG_2.sw_mtu_tertiary_cca_limit" => { type => "field", addr => 0x3f51c, width => 9, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x19 }, "HWSCH_CCA_CONTROL_REG_2.sw_mtu_secondary_cca_limit" => { type => "field", addr => 0x3f51c, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x19 }, "HWSCH_CCA_CONTROL_REG_3" => { type => "reg", addr => 0x3f520, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CCA_CONTROL_REG_3.sw_mtu_raw_cca_sel7" => { type => "field", addr => 0x3f520, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_3.sw_mtu_raw_cca_sel6" => { type => "field", addr => 0x3f520, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_3.sw_mtu_raw_cca_sel5" => { type => "field", addr => 0x3f520, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_3.sw_mtu_raw_cca_sel4" => { type => "field", addr => 0x3f520, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_3.sw_mtu_raw_cca_sel3" => { type => "field", addr => 0x3f520, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_3.sw_mtu_raw_cca_sel2" => { type => "field", addr => 0x3f520, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_3.sw_mtu_raw_cca_sel1" => { type => "field", addr => 0x3f520, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_3.sw_mtu_raw_cca_sel0" => { type => "field", addr => 0x3f520, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_4" => { type => "reg", addr => 0x3f524, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CCA_CONTROL_REG_4.sw_mtu_raw_cca_sel15" => { type => "field", addr => 0x3f524, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_4.sw_mtu_raw_cca_sel14" => { type => "field", addr => 0x3f524, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_4.sw_mtu_raw_cca_sel13" => { type => "field", addr => 0x3f524, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_4.sw_mtu_raw_cca_sel12" => { type => "field", addr => 0x3f524, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_4.sw_mtu_raw_cca_sel11" => { type => "field", addr => 0x3f524, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_4.sw_mtu_raw_cca_sel10" => { type => "field", addr => 0x3f524, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_4.sw_mtu_raw_cca_sel9" => { type => "field", addr => 0x3f524, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_4.sw_mtu_raw_cca_sel8" => { type => "field", addr => 0x3f524, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "HWSCH_CCA_CONTROL_REG_5" => { type => "reg", addr => 0x3f528, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CCA_CONTROL_REG_5.sw_mtu_final_cca_sel7" => { type => "field", addr => 0x3f528, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_5.sw_mtu_final_cca_sel6" => { type => "field", addr => 0x3f528, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_5.sw_mtu_final_cca_sel5" => { type => "field", addr => 0x3f528, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_5.sw_mtu_final_cca_sel4" => { type => "field", addr => 0x3f528, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_5.sw_mtu_final_cca_sel3" => { type => "field", addr => 0x3f528, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_5.sw_mtu_final_cca_sel2" => { type => "field", addr => 0x3f528, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_5.sw_mtu_final_cca_sel1" => { type => "field", addr => 0x3f528, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_5.sw_mtu_final_cca_sel0" => { type => "field", addr => 0x3f528, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_6" => { type => "reg", addr => 0x3f52c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CCA_CONTROL_REG_6.sw_mtu_final_cca_sel15" => { type => "field", addr => 0x3f52c, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_6.sw_mtu_final_cca_sel14" => { type => "field", addr => 0x3f52c, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_6.sw_mtu_final_cca_sel13" => { type => "field", addr => 0x3f52c, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_6.sw_mtu_final_cca_sel12" => { type => "field", addr => 0x3f52c, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_6.sw_mtu_final_cca_sel11" => { type => "field", addr => 0x3f52c, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_6.sw_mtu_final_cca_sel10" => { type => "field", addr => 0x3f52c, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_6.sw_mtu_final_cca_sel9" => { type => "field", addr => 0x3f52c, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_CCA_CONTROL_REG_6.sw_mtu_final_cca_sel8" => { type => "field", addr => 0x3f52c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0000 }, "HWSCH_MTU_GLOBAL_CONTROL" => { type => "reg", addr => 0x3f530, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_MTU_GLOBAL_CONTROL.block_tlv_tx_in_crypto_rx" => { type => "field", addr => 0x3f530, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_MTU_GLOBAL_CONTROL.enable_cca_sensing_in_pifs_burst" => { type => "field", addr => 0x3f530, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_MTU_GLOBAL_CONTROL.disable_sifs_to_pifs_recovery" => { type => "field", addr => 0x3f530, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_MTU_GLOBAL_CONTROL.sw_mtu_nav_based_on_rts_valid" => { type => "field", addr => 0x3f530, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_MTU_GLOBAL_CONTROL.sw_mtu_rts_nav_to_limit" => { type => "field", addr => 0x3f530, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xee }, "HWSCH_PREBKOFF_LIMITS" => { type => "reg", addr => 0x3f534, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_PREBKOFF_LIMITS.sw_mtu_txp_pifs_width_limit" => { type => "field", addr => 0x3f534, width => 6, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x05 }, "HWSCH_PREBKOFF_LIMITS.sw_mtu_txp_sifs_width_limit" => { type => "field", addr => 0x3f534, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0a }, "HWSCH_PREBKOFF_LIMITS.sw_mtu_early_sw_int_limit_clks" => { type => "field", addr => 0x3f534, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x01 }, "HWSCH_PREBKOFF_LIMITS.sw_mtu_early_sw_int_limit_us" => { type => "field", addr => 0x3f534, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "HWSCH_MTU_FOR_HMAC_CONTROLS" => { type => "reg", addr => 0x3f538, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_MTU_FOR_HMAC_CONTROLS.auto_flush_tlv_start_delay" => { type => "field", addr => 0x3f538, width => 5, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "HWSCH_MTU_FOR_HMAC_CONTROLS.fes_fail_auto_flush_include_underrun" => { type => "field", addr => 0x3f538, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "HWSCH_MTU_FOR_HMAC_CONTROLS.fes_fail_auto_flush_enable" => { type => "field", addr => 0x3f538, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "HWSCH_MTU_FOR_HMAC_CONTROLS.fes_start_auto_flush_enable" => { type => "field", addr => 0x3f538, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_MTU_FOR_HMAC_CONTROLS.svd_rdy_timeout_check_enable" => { type => "field", addr => 0x3f538, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_MTU_FOR_HMAC_CONTROLS.svd_rdy_timeout_slot_limit" => { type => "field", addr => 0x3f538, width => 3, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_MTU_FOR_HMAC_CONTROLS.sw_mtu_warm_tx_limit_us" => { type => "field", addr => 0x3f538, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_MTU_FOR_HMAC_CONTROLS.sw_mtu_hw_backoff_valid" => { type => "field", addr => 0x3f538, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_LFSR_DATA_1_0" => { type => "reg", addr => 0x3f53c, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_LFSR_DATA_1_0.lfsr_data_1" => { type => "field", addr => 0x3f53c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_1_0.lfsr_data_0" => { type => "field", addr => 0x3f53c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_3_2" => { type => "reg", addr => 0x3f540, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_LFSR_DATA_3_2.lfsr_data_3" => { type => "field", addr => 0x3f540, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_3_2.lfsr_data_2" => { type => "field", addr => 0x3f540, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_5_4" => { type => "reg", addr => 0x3f544, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_LFSR_DATA_5_4.lfsr_data_5" => { type => "field", addr => 0x3f544, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_5_4.lfsr_data_4" => { type => "field", addr => 0x3f544, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_7_6" => { type => "reg", addr => 0x3f548, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_LFSR_DATA_7_6.lfsr_data_7" => { type => "field", addr => 0x3f548, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_7_6.lfsr_data_6" => { type => "field", addr => 0x3f548, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_9_8" => { type => "reg", addr => 0x3f54c, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_LFSR_DATA_9_8.lfsr_data_9" => { type => "field", addr => 0x3f54c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_9_8.lfsr_data_8" => { type => "field", addr => 0x3f54c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_11_10" => { type => "reg", addr => 0x3f550, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_LFSR_DATA_11_10.lfsr_data_11" => { type => "field", addr => 0x3f550, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_11_10.lfsr_data_10" => { type => "field", addr => 0x3f550, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_13_12" => { type => "reg", addr => 0x3f554, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_LFSR_DATA_13_12.lfsr_data_13" => { type => "field", addr => 0x3f554, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_13_12.lfsr_data_12" => { type => "field", addr => 0x3f554, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_15_14" => { type => "reg", addr => 0x3f558, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_LFSR_DATA_15_14.lfsr_data_15" => { type => "field", addr => 0x3f558, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LFSR_DATA_15_14.lfsr_data_14" => { type => "field", addr => 0x3f558, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_LONG_SHORT_XMIT_LIMIT_0" => { type => "reg", addr => 0x3f55c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_LONG_SHORT_XMIT_LIMIT_0.sw_long_short_xmit_limit_bkof_3_to_0" => { type => "field", addr => 0x3f55c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_LONG_SHORT_XMIT_LIMIT_1" => { type => "reg", addr => 0x3f560, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_LONG_SHORT_XMIT_LIMIT_1.sw_long_short_xmit_limit_bkof_7_to_4" => { type => "field", addr => 0x3f560, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_LONG_SHORT_XMIT_LIMIT_2" => { type => "reg", addr => 0x3f564, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_LONG_SHORT_XMIT_LIMIT_2.sw_long_short_xmit_limit_bkof_11_to_8" => { type => "field", addr => 0x3f564, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_LONG_SHORT_XMIT_LIMIT_3" => { type => "reg", addr => 0x3f568, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_LONG_SHORT_XMIT_LIMIT_3.sw_long_short_xmit_limit_bkof_15_to_12"=> { type => "field", addr => 0x3f568, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV" => { type => "reg", addr => 0x3f56c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV.sw_mtu_sifs_limit_forinNAV" => { type => "field", addr => 0x3f56c, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x780 }, "HWSCH_PRIMARY_CCA_HISTOGRAM_LOW" => { type => "reg", addr => 0x3f570, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_PRIMARY_CCA_HISTOGRAM_LOW.primary_cca_histogram31to0" => { type => "field", addr => 0x3f570, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0xffffffff }, "HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH" => { type => "reg", addr => 0x3f574, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH.primary_cca_histogram63to32" => { type => "field", addr => 0x3f574, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0xffffffff }, "HWSCH_SECONDARY_CCA_HISTOGRAM_LOW" => { type => "reg", addr => 0x3f578, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_SECONDARY_CCA_HISTOGRAM_LOW.secondary_cca_histogram31to0" => { type => "field", addr => 0x3f578, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0xffffffff }, "HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH" => { type => "reg", addr => 0x3f57c, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH.secondary_cca_histogram63to32" => { type => "field", addr => 0x3f57c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0xffffffff }, "HWSCH_TERTIARY_CCA_HISTOGRAM_LOW" => { type => "reg", addr => 0x3f580, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_TERTIARY_CCA_HISTOGRAM_LOW.tertiary_cca_histogram31to0" => { type => "field", addr => 0x3f580, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0xffffffff }, "HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH" => { type => "reg", addr => 0x3f584, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH.tertiary_cca_histogram63to32" => { type => "field", addr => 0x3f584, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0xffffffff }, "HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW" => { type => "reg", addr => 0x3f588, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW.quaternary_cca_histogram31to0" => { type => "field", addr => 0x3f588, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0xffffffff }, "HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH" => { type => "reg", addr => 0x3f58c, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH.quaternary_cca_histogram63to32" => { type => "field", addr => 0x3f58c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0xffffffff }, "HWSCH_SW_CCA_HISTOGRAM_MASK_MISC" => { type => "reg", addr => 0x3f59c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SW_CCA_HISTOGRAM_MASK_MISC.sw_cca_histogram_sampling_rate" => { type => "field", addr => 0x3f59c, width => 6, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_CCA_SECONDARY_HISTOGRAM" => { type => "reg", addr => 0x3f5a0, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_CCA_SECONDARY_HISTOGRAM.cca_secondary_histogram" => { type => "field", addr => 0x3f5a0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_CCA_TERTIARY_HISTOGRAM" => { type => "reg", addr => 0x3f5a4, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_CCA_TERTIARY_HISTOGRAM.cca_tertiary_histogram" => { type => "field", addr => 0x3f5a4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_CCA_QUATERNARY_HISTOGRAM" => { type => "reg", addr => 0x3f5a8, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_CCA_QUATERNARY_HISTOGRAM.cca_quaternary_histogram" => { type => "field", addr => 0x3f5a8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_CMD_RING_BASE_0" => { type => "reg", addr => 0x3f5ac, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_0.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5ac, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_1" => { type => "reg", addr => 0x3f5b0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_1.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5b0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_2" => { type => "reg", addr => 0x3f5b4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_2.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5b4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_3" => { type => "reg", addr => 0x3f5b8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_3.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5b8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_4" => { type => "reg", addr => 0x3f5bc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_4.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5bc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_5" => { type => "reg", addr => 0x3f5c0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_5.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5c0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_6" => { type => "reg", addr => 0x3f5c4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_6.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5c4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_7" => { type => "reg", addr => 0x3f5c8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_7.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5c8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_8" => { type => "reg", addr => 0x3f5cc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_8.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5cc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_9" => { type => "reg", addr => 0x3f5d0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_9.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5d0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_10" => { type => "reg", addr => 0x3f5d4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_10.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5d4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_11" => { type => "reg", addr => 0x3f5d8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_11.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5d8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_12" => { type => "reg", addr => 0x3f5dc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_12.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5dc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_13" => { type => "reg", addr => 0x3f5e0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_13.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5e0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_14" => { type => "reg", addr => 0x3f5e4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_14.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5e4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_BASE_15" => { type => "reg", addr => 0x3f5e8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_BASE_15.HWSCH_CMD_RING_BASE_DATA" => { type => "field", addr => 0x3f5e8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_NUM_ENTRY_0" => { type => "reg", addr => 0x3f5ec, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_0.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f5ec, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_1" => { type => "reg", addr => 0x3f5f0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_1.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f5f0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_2" => { type => "reg", addr => 0x3f5f4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_2.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f5f4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_3" => { type => "reg", addr => 0x3f5f8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_3.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f5f8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_4" => { type => "reg", addr => 0x3f5fc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_4.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f5fc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_5" => { type => "reg", addr => 0x3f600, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_5.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f600, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_6" => { type => "reg", addr => 0x3f604, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_6.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f604, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_7" => { type => "reg", addr => 0x3f608, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_7.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f608, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_8" => { type => "reg", addr => 0x3f60c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_8.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f60c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_9" => { type => "reg", addr => 0x3f610, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_9.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f610, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_10" => { type => "reg", addr => 0x3f614, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_10.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f614, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_11" => { type => "reg", addr => 0x3f618, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_11.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f618, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_12" => { type => "reg", addr => 0x3f61c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_12.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f61c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_13" => { type => "reg", addr => 0x3f620, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_13.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f620, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_14" => { type => "reg", addr => 0x3f624, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_14.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f624, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_NUM_ENTRY_15" => { type => "reg", addr => 0x3f628, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_NUM_ENTRY_15.HWSCH_CMD_RING_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f628, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_CMD_RING_HEAD_0" => { type => "reg", addr => 0x3f62c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_0.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f62c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_1" => { type => "reg", addr => 0x3f630, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_1.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f630, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_2" => { type => "reg", addr => 0x3f634, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_2.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f634, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_3" => { type => "reg", addr => 0x3f638, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_3.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f638, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_4" => { type => "reg", addr => 0x3f63c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_4.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f63c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_5" => { type => "reg", addr => 0x3f640, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_5.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f640, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_6" => { type => "reg", addr => 0x3f644, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_6.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f644, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_7" => { type => "reg", addr => 0x3f648, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_7.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f648, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_8" => { type => "reg", addr => 0x3f64c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_8.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f64c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_9" => { type => "reg", addr => 0x3f650, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_9.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f650, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_10" => { type => "reg", addr => 0x3f654, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_10.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f654, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_11" => { type => "reg", addr => 0x3f658, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_11.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f658, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_12" => { type => "reg", addr => 0x3f65c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_12.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f65c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_13" => { type => "reg", addr => 0x3f660, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_13.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f660, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_14" => { type => "reg", addr => 0x3f664, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_14.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f664, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_HEAD_15" => { type => "reg", addr => 0x3f668, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_HEAD_15.HWSCH_CMD_RING_HEAD_DATA" => { type => "field", addr => 0x3f668, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_0" => { type => "reg", addr => 0x3f66c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_0.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f66c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_1" => { type => "reg", addr => 0x3f670, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_1.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f670, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_2" => { type => "reg", addr => 0x3f674, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_2.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f674, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_3" => { type => "reg", addr => 0x3f678, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_3.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f678, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_4" => { type => "reg", addr => 0x3f67c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_4.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f67c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_5" => { type => "reg", addr => 0x3f680, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_5.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f680, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_6" => { type => "reg", addr => 0x3f684, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_6.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f684, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_7" => { type => "reg", addr => 0x3f688, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_7.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f688, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_8" => { type => "reg", addr => 0x3f68c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_8.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f68c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_9" => { type => "reg", addr => 0x3f690, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_9.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f690, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_10" => { type => "reg", addr => 0x3f694, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_10.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f694, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_11" => { type => "reg", addr => 0x3f698, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_11.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f698, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_12" => { type => "reg", addr => 0x3f69c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_12.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f69c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_13" => { type => "reg", addr => 0x3f6a0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_13.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f6a0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_14" => { type => "reg", addr => 0x3f6a4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_14.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f6a4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_TAIL_15" => { type => "reg", addr => 0x3f6a8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_TAIL_15.HWSCH_CMD_RING_TAIL_DATA" => { type => "field", addr => 0x3f6a8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_CMD_RING_THRESHOLD_0" => { type => "reg", addr => 0x3f6ac, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_0.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6ac, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_1" => { type => "reg", addr => 0x3f6b0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_1.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6b0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_2" => { type => "reg", addr => 0x3f6b4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_2.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6b4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_3" => { type => "reg", addr => 0x3f6b8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_3.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6b8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_4" => { type => "reg", addr => 0x3f6bc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_4.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6bc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_5" => { type => "reg", addr => 0x3f6c0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_5.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6c0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_6" => { type => "reg", addr => 0x3f6c4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_6.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6c4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_7" => { type => "reg", addr => 0x3f6c8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_7.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6c8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_8" => { type => "reg", addr => 0x3f6cc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_8.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6cc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_9" => { type => "reg", addr => 0x3f6d0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_9.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6d0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_10" => { type => "reg", addr => 0x3f6d4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_10.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6d4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_11" => { type => "reg", addr => 0x3f6d8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_11.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6d8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_12" => { type => "reg", addr => 0x3f6dc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_12.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6dc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_13" => { type => "reg", addr => 0x3f6e0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_13.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6e0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_14" => { type => "reg", addr => 0x3f6e4, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_14.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6e4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_CMD_RING_THRESHOLD_15" => { type => "reg", addr => 0x3f6e8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_RING_THRESHOLD_15.HWSCH_CMD_RING_THRESHOLD_DATA" => { type => "field", addr => 0x3f6e8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xf0 }, "HWSCH_STATUS_BASE" => { type => "reg", addr => 0x3f6ec, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_STATUS_BASE.HWSCH_STATUS_BASE_DATA" => { type => "field", addr => 0x3f6ec, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_STATUS_NUM_ENTRY" => { type => "reg", addr => 0x3f6f0, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_STATUS_NUM_ENTRY.HWSCH_STATUS_NUM_ENTRY_DATA" => { type => "field", addr => 0x3f6f0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x40 }, "HWSCH_STATUS_HEAD" => { type => "reg", addr => 0x3f6f4, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_STATUS_HEAD.HWSCH_STATUS_HEAD_DATA" => { type => "field", addr => 0x3f6f4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "HWSCH_STATUS_TAIL" => { type => "reg", addr => 0x3f6f8, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_STATUS_TAIL.HWSCH_STATUS_TAIL_DATA" => { type => "field", addr => 0x3f6f8, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "HWSCH_STATUS_RING_THRESHOLDS" => { type => "reg", addr => 0x3f6fc, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_STATUS_RING_THRESHOLDS.PANIC_WATERMARK" => { type => "field", addr => 0x3f6fc, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "HWSCH_STATUS_RING_THRESHOLDS.LOW_WATERMARK" => { type => "field", addr => 0x3f6fc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x10 }, "HWSCH_WATCHDOG_TIMER" => { type => "reg", addr => 0x3f700, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_WATCHDOG_TIMER.HWSCH_WATCHDOG_TIMEOUT" => { type => "field", addr => 0x3f700, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "HWSCH_AXI_TIMEOUT" => { type => "reg", addr => 0x3f704, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_AXI_TIMEOUT.HWSCH_AXI_TIMEOUT" => { type => "field", addr => 0x3f704, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1f4 }, "HWSCH_CMD_RING_PAUSE" => { type => "reg", addr => 0x3f708, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "HWSCH_CMD_RING_PAUSE.CMD_RING15_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING14_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING13_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING12_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING11_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING10_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING9_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING8_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING7_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING6_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING5_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING4_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING3_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING2_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING1_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CMD_RING_PAUSE.CMD_RING0_PAUSED" => { type => "field", addr => 0x3f708, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_FLUSH_CONTROL" => { type => "reg", addr => 0x3f70c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_FLUSH_CONTROL.FLUSH_REQUEST_ACTION" => { type => "field", addr => 0x3f70c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_SEND_FLUSH" => { type => "reg", addr => 0x3f710, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SEND_FLUSH.SEND_FLUSH" => { type => "field", addr => 0x3f710, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_SEND_FLUSH.FLUSH_MASK" => { type => "field", addr => 0x3f710, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_FLUSH_STATUS" => { type => "reg", addr => 0x3f714, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_FLUSH_STATUS.FLUSH_STATUS" => { type => "field", addr => 0x3f714, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_BOUNDARY_TIMER0" => { type => "reg", addr => 0x3f718, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_BOUNDARY_TIMER0.HWSCH_BOUNDARY_TIMER_ENABLE" => { type => "field", addr => 0x3f718, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_BOUNDARY_TIMER0.HWSCH_BOUNDARY_TIMER_COUNT" => { type => "field", addr => 0x3f718, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_BOUNDARY_TIMER1" => { type => "reg", addr => 0x3f71c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_BOUNDARY_TIMER1.HWSCH_BOUNDARY_TIMER_ENABLE" => { type => "field", addr => 0x3f71c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_BOUNDARY_TIMER1.HWSCH_BOUNDARY_TIMER_COUNT" => { type => "field", addr => 0x3f71c, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_BOUNDARY_TIMER2" => { type => "reg", addr => 0x3f720, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_BOUNDARY_TIMER2.HWSCH_BOUNDARY_TIMER_ENABLE" => { type => "field", addr => 0x3f720, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_BOUNDARY_TIMER2.HWSCH_BOUNDARY_TIMER_COUNT" => { type => "field", addr => 0x3f720, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_BOUNDARY_TIMER3" => { type => "reg", addr => 0x3f724, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_BOUNDARY_TIMER3.HWSCH_BOUNDARY_TIMER_ENABLE" => { type => "field", addr => 0x3f724, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_BOUNDARY_TIMER3.HWSCH_BOUNDARY_TIMER_COUNT" => { type => "field", addr => 0x3f724, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_TXOP_CONTROL0" => { type => "reg", addr => 0x3f728, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_TXOP_CONTROL0.TXOP_SEL_MASK_RING3" => { type => "field", addr => 0x3f728, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL0.TXOP_SEL_MASK_RING2" => { type => "field", addr => 0x3f728, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL0.TXOP_SEL_MASK_RING1" => { type => "field", addr => 0x3f728, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL0.TXOP_SEL_MASK_RING0" => { type => "field", addr => 0x3f728, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL1" => { type => "reg", addr => 0x3f72c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_TXOP_CONTROL1.TXOP_SEL_MASK_RING7" => { type => "field", addr => 0x3f72c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL1.TXOP_SEL_MASK_RING6" => { type => "field", addr => 0x3f72c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL1.TXOP_SEL_MASK_RING5" => { type => "field", addr => 0x3f72c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL1.TXOP_SEL_MASK_RING4" => { type => "field", addr => 0x3f72c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL2" => { type => "reg", addr => 0x3f730, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_TXOP_CONTROL2.TXOP_SEL_MASK_RING11" => { type => "field", addr => 0x3f730, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL2.TXOP_SEL_MASK_RING10" => { type => "field", addr => 0x3f730, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL2.TXOP_SEL_MASK_RING9" => { type => "field", addr => 0x3f730, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL2.TXOP_SEL_MASK_RING8" => { type => "field", addr => 0x3f730, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL3" => { type => "reg", addr => 0x3f734, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_TXOP_CONTROL3.TXOP_SEL_MASK_RING15" => { type => "field", addr => 0x3f734, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL3.TXOP_SEL_MASK_RING14" => { type => "field", addr => 0x3f734, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL3.TXOP_SEL_MASK_RING13" => { type => "field", addr => 0x3f734, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_TXOP_CONTROL3.TXOP_SEL_MASK_RING12" => { type => "field", addr => 0x3f734, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "HWSCH_DEBUG_SELECT" => { type => "reg", addr => 0x3f738, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_DEBUG_SELECT.BLOCK_SELECT" => { type => "field", addr => 0x3f738, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_DEBUG_SELECT.SIGNAL_SELECT" => { type => "field", addr => 0x3f738, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_DEBUG_OBS_U32" => { type => "reg", addr => 0x3f73c, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_DEBUG_OBS_U32.DATA" => { type => "field", addr => 0x3f73c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_DEBUG_OBS_L32" => { type => "reg", addr => 0x3f740, width => 32, athEmulAttr => 0, acc => "RO" }, "HWSCH_DEBUG_OBS_L32.DATA" => { type => "field", addr => 0x3f740, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "HWSCH_MGMT_STATS_CTRL" => { type => "reg", addr => 0x3f744, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "HWSCH_MGMT_STATS_CTRL.RESET_ALL" => { type => "field", addr => 0x3f744, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x1 }, "HWSCH_MGMT_STATS_CTRL.MONITOR_BITMAP" => { type => "field", addr => 0x3f744, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xffff }, "HWSCH_ACK_PASS_STATS" => { type => "reg", addr => 0x3f748, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_ACK_PASS_STATS.STATS_DIST" => { type => "field", addr => 0x3f748, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_ACK_PASS_STATS.STATS_COUNT" => { type => "field", addr => 0x3f748, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_RETRY_STATS" => { type => "reg", addr => 0x3f74c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_RETRY_STATS.STATS_DIST" => { type => "field", addr => 0x3f74c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_RETRY_STATS.STATS_COUNT" => { type => "field", addr => 0x3f74c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_REQUEUE_STATS" => { type => "reg", addr => 0x3f750, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_REQUEUE_STATS.STATS_DIST" => { type => "field", addr => 0x3f750, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_REQUEUE_STATS.STATS_COUNT" => { type => "field", addr => 0x3f750, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_FILTER_STATS" => { type => "reg", addr => 0x3f754, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_FILTER_STATS.STATS_DIST" => { type => "field", addr => 0x3f754, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_FILTER_STATS.STATS_COUNT" => { type => "field", addr => 0x3f754, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_BSPLIT_STATS" => { type => "reg", addr => 0x3f758, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_BSPLIT_STATS.STATS_DIST" => { type => "field", addr => 0x3f758, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_BSPLIT_STATS.STATS_COUNT" => { type => "field", addr => 0x3f758, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_FLUSH_STATS" => { type => "reg", addr => 0x3f75c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_FLUSH_STATS.STATS_DIST" => { type => "field", addr => 0x3f75c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_FLUSH_STATS.STATS_COUNT" => { type => "field", addr => 0x3f75c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_SEQEND_BIN_REG_0" => { type => "reg", addr => 0x3f760, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SEQEND_BIN_REG_0.REQUE_TYPE" => { type => "field", addr => 0x3f760, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_SEQEND_BIN_REG_0.RETRY_TYPE" => { type => "field", addr => 0x3f760, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_SEQEND_BIN_REG_1" => { type => "reg", addr => 0x3f764, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_SEQEND_BIN_REG_1.FLUSH_TYPE" => { type => "field", addr => 0x3f764, width => 18, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_SEQEND_BIN_REG_1.FILTER_TYPE" => { type => "field", addr => 0x3f764, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_TLV_IF_STATS" => { type => "reg", addr => 0x3f768, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_TLV_IF_STATS.TLV_OUT_COUNT" => { type => "field", addr => 0x3f768, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_TLV_IF_STATS.TLV_IN_COUNT" => { type => "field", addr => 0x3f768, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CMD_MGR_GLB_CTRL" => { type => "reg", addr => 0x3f76c, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CMD_MGR_GLB_CTRL.MAINTAIN_STATUS_ORDER" => { type => "field", addr => 0x3f76c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_CMD_MGR_GLB_CTRL.REQUEUE_LIMIT" => { type => "field", addr => 0x3f76c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xff }, "HWSCH_WATCHDOG_STATUS" => { type => "reg", addr => 0x3f770, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "HWSCH_WATCHDOG_STATUS.AXI_WR_RESP_ERROR" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.AXI_WR_TIMEOUT" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.AXI_RD_TIMEOUT" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.FLUSH_CTRL" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.TX_STAT_CTRL" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.FES_SETUP" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.MTU_WRAP" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING15" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING14" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING13" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING12" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING11" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING10" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING9" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING8" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING7" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING6" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING5" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING4" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING3" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING2" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING1" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_WATCHDOG_STATUS.CMD_RING0" => { type => "field", addr => 0x3f770, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "HWSCH_CLK_GATE_CONTROL" => { type => "reg", addr => 0x3f774, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_CLK_GATE_CONTROL.CLK_GATE_OVERRIDE" => { type => "field", addr => 0x3f774, width => 23, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_EVT_CTRL_MTU_MASK" => { type => "reg", addr => 0x3f778, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_EVT_CTRL_MTU_MASK.MASK" => { type => "field", addr => 0x3f778, width => 15, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7fff }, "MAC_SCH_EVENT_MASK_31_0" => { type => "reg", addr => 0x3f77c, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_SCH_EVENT_MASK_31_0.MASK" => { type => "field", addr => 0x3f77c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3fffff }, "MAC_SCH_EVENT_MASK_63_32" => { type => "reg", addr => 0x3f780, width => 32, athEmulAttr => 0, acc => "RW" }, "MAC_SCH_EVENT_MASK_63_32.MASK" => { type => "field", addr => 0x3f780, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "HWSCH_QUIET_FLUSH_STATS" => { type => "reg", addr => 0x3f784, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_QUIET_FLUSH_STATS.AUTO_FLUSH_COUNT" => { type => "field", addr => 0x3f784, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_QUIET_FLUSH_STATS.PREBKOF_FLUSH_COUNT" => { type => "field", addr => 0x3f784, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "HWSCH_INTERNAL_CTL" => { type => "reg", addr => 0x3f788, width => 32, athEmulAttr => 0, acc => "RW" }, "HWSCH_INTERNAL_CTL.cascade_160mhz_enable" => { type => "field", addr => 0x3f788, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wmac_top_reg_map.mac_mxi_reg Register/Field definitions ################################################################### "MXI_CFG_1" => { type => "reg", addr => 0x3fc00, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_1.WIFI_MEM_BASE_ADDR" => { type => "field", addr => 0x3fc00, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MXI_CFG_2" => { type => "reg", addr => 0x3fc04, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_2.WIFI_MEM_BASE_ADDR_MASK" => { type => "field", addr => 0x3fc04, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MXI_CFG_3" => { type => "reg", addr => 0x3fc08, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_3.APB_BASE_ADDR" => { type => "field", addr => 0x3fc08, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MXI_CFG_4" => { type => "reg", addr => 0x3fc0c, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_4.APB_BASE_ADDR_MASK" => { type => "field", addr => 0x3fc0c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MXI_CFG_5" => { type => "reg", addr => 0x3fc10, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_5.WIFI_MEM_MAX_AXI_RD_BURST_SIZE" => { type => "field", addr => 0x3fc10, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MXI_CFG_6" => { type => "reg", addr => 0x3fc14, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_6.WIFI_MEM_MAX_AXI_WR_BURST_SIZE" => { type => "field", addr => 0x3fc14, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MXI_CFG_7" => { type => "reg", addr => 0x3fc18, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_7.HOST_MEM_MAX_AXI_RD_BURST_SIZE" => { type => "field", addr => 0x3fc18, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MXI_CFG_8" => { type => "reg", addr => 0x3fc1c, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_8.HOST_MEM_MAX_AXI_WR_BURST_SIZE" => { type => "field", addr => 0x3fc1c, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "MXI_CFG_9" => { type => "reg", addr => 0x3fc20, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_9.APB_MEM_MAX_AXI_RD_BURST_SIZE" => { type => "field", addr => 0x3fc20, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MXI_CFG_10" => { type => "reg", addr => 0x3fc24, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_10.APB_MEM_MAX_AXI_WR_BURST_SIZE" => { type => "field", addr => 0x3fc24, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MXI_CFG_11" => { type => "reg", addr => 0x3fc28, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_11.AXI_TIMER_VALUE" => { type => "field", addr => 0x3fc28, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xff }, "MXI_CFG_12" => { type => "reg", addr => 0x3fc2c, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CFG_12.halt_req" => { type => "field", addr => 0x3fc2c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MXI_STATUS" => { type => "reg", addr => 0x3fc30, width => 32, athEmulAttr => 0, acc => "RO" }, "MXI_STATUS.halt_ack" => { type => "field", addr => 0x3fc30, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MXI_RD_ERR_RESP" => { type => "reg", addr => 0x3fc34, width => 32, athEmulAttr => 0, acc => "RO" }, "MXI_RD_ERR_RESP.AXI_RD_RESP_ERR_CAUSE" => { type => "field", addr => 0x3fc34, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MXI_RD_ERR_RESP.AXI_RD_RESP_ERR_ORIG_ID" => { type => "field", addr => 0x3fc34, width => 5, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MXI_RD_ERR_RESP.AXI_RD_RESP_ERR_ORIG_MASTER" => { type => "field", addr => 0x3fc34, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MXI_WR_ERR_RESP" => { type => "reg", addr => 0x3fc38, width => 32, athEmulAttr => 0, acc => "RO" }, "MXI_WR_ERR_RESP.AXI_WR_RESP_ERR_CAUSE" => { type => "field", addr => 0x3fc38, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MXI_WR_ERR_RESP.AXI_WR_RESP_ERR_ORIG_ID" => { type => "field", addr => 0x3fc38, width => 3, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MXI_WR_ERR_RESP.AXI_WR_RESP_ERR_ORIG_MASTER" => { type => "field", addr => 0x3fc38, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MXI_DEBUG_CUR_RD_MASTER" => { type => "reg", addr => 0x3fc3c, width => 32, athEmulAttr => 0, acc => "RO" }, "MXI_DEBUG_CUR_RD_MASTER.CUR_MXI_RD_MAS" => { type => "field", addr => 0x3fc3c, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MXI_DEBUG_CUR_WR_MASTER" => { type => "reg", addr => 0x3fc40, width => 32, athEmulAttr => 0, acc => "RO" }, "MXI_DEBUG_CUR_WR_MASTER.CUR_MXI_WR_MAS" => { type => "field", addr => 0x3fc40, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MXI_CLOCK_GATE_DISABLE" => { type => "reg", addr => 0x3fc44, width => 32, athEmulAttr => 0, acc => "RW" }, "MXI_CLOCK_GATE_DISABLE.CLOCK_GATE_DISABLE" => { type => "field", addr => 0x3fc44, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, ################################################################### ## mac_wificmn_reg Register/Field definitions ################################################################### "WIFICMN_ISR_P" => { type => "reg", addr => 0x40000, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "WIFICMN_ISR_P.MEM_ERR_INTR" => { type => "field", addr => 0x40000, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_P.CE_WATCHDOG_ERR_INTR" => { type => "field", addr => 0x40000, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_P.INVALID_BB_INTR" => { type => "field", addr => 0x40000, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_P.PTA_COEX_INTR" => { type => "field", addr => 0x40000, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_P.WIFI_TIMER_INTR" => { type => "field", addr => 0x40000, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S0" => { type => "reg", addr => 0x40004, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "WIFICMN_ISR_S0.PCU_DTIM_SYNC" => { type => "field", addr => 0x40004, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S0.PCU_BEACON_TIMEOUT" => { type => "field", addr => 0x40004, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S0.PCU_CAB_TIMEOUT" => { type => "field", addr => 0x40004, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S0.PCU_CAB_NO_MORE" => { type => "field", addr => 0x40004, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S0.PCU_TSF_OUT_OF_RANGE" => { type => "field", addr => 0x40004, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S0.PCU_SLP32_CYCLE_CNT" => { type => "field", addr => 0x40004, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S0.PCU_GEN_TIMER_OVRFLW" => { type => "field", addr => 0x40004, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S1" => { type => "reg", addr => 0x40008, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "WIFICMN_ISR_S1.PCU_GEN_TIMER_THRESH" => { type => "field", addr => 0x40008, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S1.PCU_GEN_TIMER_TRIGGER" => { type => "field", addr => 0x40008, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S2" => { type => "reg", addr => 0x4000c, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "WIFICMN_ISR_S2.INVALID_BB" => { type => "field", addr => 0x4000c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S2.pmi_cpu_panic_watchdog_irq" => { type => "field", addr => 0x4000c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S2.fecntl_cpu_panic_watchdog_irq" => { type => "field", addr => 0x4000c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S3" => { type => "reg", addr => 0x40010, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "WIFICMN_ISR_S3.PTA_WL_STOMPED" => { type => "field", addr => 0x40010, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S3.PTA_BT_STOMPED" => { type => "field", addr => 0x40010, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S3.PTA_BT_ACTIVE_RISE" => { type => "field", addr => 0x40010, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S3.PTA_BT_ACTIVE_FALL" => { type => "field", addr => 0x40010, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S3.PTA_BT_PRIORITY_RISE" => { type => "field", addr => 0x40010, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S3.PTA_BT_PRIORITY_FALL" => { type => "field", addr => 0x40010, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S3.PTA_BT_LOW_PRTY_RISE" => { type => "field", addr => 0x40010, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_ISR_S3.PTA_BT_LOW_PRTY_FALL" => { type => "field", addr => 0x40010, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_IMR_P" => { type => "reg", addr => 0x40014, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_IMR_P.MEM_ERR_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.RTC_WDT_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.THERM_SENSOR_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.CE_WATCHDOG_ERR_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.PCIE_WAKE_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.EFUSE_ERR_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.INVALID_BB_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.WMAC_MCMN_INTR_1" => { type => "field", addr => 0x40014, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.WMAC_MCMN_INTR_2" => { type => "field", addr => 0x40014, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.HOST_REG_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.CE_INTR" => { type => "field", addr => 0x40014, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.LF_HF_TIMER_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.GPIO_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.SI_UART_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.RTC_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.WIFI_TIMER_INTR" => { type => "field", addr => 0x40014, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.WMAC_MCMN_INTR_3" => { type => "field", addr => 0x40014, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P.WMAC_MCMN_INTR_0" => { type => "field", addr => 0x40014, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P_CONTD" => { type => "reg", addr => 0x40018, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_IMR_P_CONTD.RFFE_M" => { type => "field", addr => 0x40018, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P_CONTD.LTE_COEX" => { type => "field", addr => 0x40018, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_P_CONTD.PTA_COEX" => { type => "field", addr => 0x40018, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S0" => { type => "reg", addr => 0x4001c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_IMR_S0.PCU_DTIM_SYNC" => { type => "field", addr => 0x4001c, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S0.PCU_BEACON_TIMEOUT" => { type => "field", addr => 0x4001c, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S0.PCU_CAB_TIMEOUT" => { type => "field", addr => 0x4001c, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S0.PCU_CAB_NO_MORE" => { type => "field", addr => 0x4001c, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S0.PCU_TSF_OUT_OF_RANGE" => { type => "field", addr => 0x4001c, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S0.PCU_SLP32_CYCLE_CNT" => { type => "field", addr => 0x4001c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S0.PCU_GEN_TIMER_OVRFLW" => { type => "field", addr => 0x4001c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S1" => { type => "reg", addr => 0x40020, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_IMR_S1.PCU_GEN_TIMER_THRESH" => { type => "field", addr => 0x40020, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S1.PCU_GEN_TIMER_TRIGGER" => { type => "field", addr => 0x40020, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S2" => { type => "reg", addr => 0x40028, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_IMR_S2.INVALID_BB" => { type => "field", addr => 0x40028, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S2.pmi_cpu_panic_watchdog_irq" => { type => "field", addr => 0x40028, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S2.fecntl_cpu_panic_watchdog_irq" => { type => "field", addr => 0x40028, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S3" => { type => "reg", addr => 0x4002c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_IMR_S3.PTA_WL_STOMPED" => { type => "field", addr => 0x4002c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S3.PTA_BT_STOMPED" => { type => "field", addr => 0x4002c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S3.PTA_BT_ACTIVE_RISE" => { type => "field", addr => 0x4002c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S3.PTA_BT_ACTIVE_FALL" => { type => "field", addr => 0x4002c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S3.PTA_BT_PRIORITY_RISE" => { type => "field", addr => 0x4002c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S3.PTA_BT_PRIORITY_FALL" => { type => "field", addr => 0x4002c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S3.PTA_BT_LOW_PRTY_RISE" => { type => "field", addr => 0x4002c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_IMR_S3.PTA_BT_LOW_PRTY_FALL" => { type => "field", addr => 0x4002c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_PCIE_BAR_REG" => { type => "reg", addr => 0x40030, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_PCIE_BAR_REG.PCIE_BAR_REG" => { type => "field", addr => 0x40030, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_CTRL_REG" => { type => "reg", addr => 0x40034, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_CTRL_REG.PCIE_ADDR_31" => { type => "field", addr => 0x40034, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_CPU_MEM" => { type => "reg", addr => 0x40038, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_CPU_MEM.IRAM_BAR" => { type => "field", addr => 0x40038, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x9 }, "WIFICMN_CPU_MEM.DRAM_BAR" => { type => "field", addr => 0x40038, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x4 }, "WIFICMN_WOCLR_ISR_P_EN" => { type => "reg", addr => 0x4003c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_WOCLR_ISR_P_EN.Val" => { type => "field", addr => 0x4003c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_LF_HF_WDT_INT_STATUS" => { type => "reg", addr => 0x40040, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "WIFICMN_LF_HF_WDT_INT_STATUS.WDT" => { type => "field", addr => 0x40040, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_LF_HF_WDT_INT_STATUS.HF_TIMER" => { type => "field", addr => 0x40040, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_LF_HF_WDT_INT_STATUS.LF_TIMER3" => { type => "field", addr => 0x40040, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_LF_HF_WDT_INT_STATUS.LF_TIMER2" => { type => "field", addr => 0x40040, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_LF_HF_WDT_INT_STATUS.LF_TIMER1" => { type => "field", addr => 0x40040, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_LF_HF_WDT_INT_STATUS.LF_TIMER0" => { type => "field", addr => 0x40040, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "WIFICMN_SCRATCH_0" => { type => "reg", addr => 0x40044, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_SCRATCH_0.VAL" => { type => "field", addr => 0x40044, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_SCRATCH_1" => { type => "reg", addr => 0x40048, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_SCRATCH_1.VAL" => { type => "field", addr => 0x40048, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_SCRATCH_2" => { type => "reg", addr => 0x4004c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_SCRATCH_2.VAL" => { type => "field", addr => 0x4004c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_SCRATCH_3" => { type => "reg", addr => 0x40050, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_SCRATCH_3.VAL" => { type => "field", addr => 0x40050, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_INT_STATUS" => { type => "reg", addr => 0x40054, width => 32, athEmulAttr => 0, acc => "RO" }, "WIFICMN_INT_STATUS.MEM_ERR_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.RTC_WDT_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.THERM_SENSOR_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.CE_WATCHDOG_ERR_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.PCIE_WAKE_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.EFUSE_ERR_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.INVALID_BB_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.WMAC_MCMN_INTR_1" => { type => "field", addr => 0x40054, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.WMAC_MCMN_INTR_2" => { type => "field", addr => 0x40054, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.HOST_REG_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.CE_INTR" => { type => "field", addr => 0x40054, width => 12, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.LF_HF_TIMER_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.GPIO_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.SI_UART_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.RTC_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.WIFI_TIMER_INTR" => { type => "field", addr => 0x40054, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.WMAC_MCMN_INTR_3" => { type => "field", addr => 0x40054, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS.WMAC_MCMN_INTR_0" => { type => "field", addr => 0x40054, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS_CONTD" => { type => "reg", addr => 0x40058, width => 32, athEmulAttr => 0, acc => "RO" }, "WIFICMN_INT_STATUS_CONTD.RFFE_M" => { type => "field", addr => 0x40058, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS_CONTD.LTE_COEX" => { type => "field", addr => 0x40058, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_INT_STATUS_CONTD.PTA_COEX" => { type => "field", addr => 0x40058, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFICMN_TESTBUS_SELECT" => { type => "reg", addr => 0x4005c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_TESTBUS_SELECT.VAL" => { type => "field", addr => 0x4005c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_OBS_SELECT" => { type => "reg", addr => 0x40060, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_OBS_SELECT.VAL" => { type => "field", addr => 0x40060, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_OBS_BYTE_LANE_SELECT" => { type => "reg", addr => 0x40064, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_OBS_BYTE_LANE_SELECT.VAL" => { type => "field", addr => 0x40064, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_CLK_GATE_EN" => { type => "reg", addr => 0x40068, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_CLK_GATE_EN.VAL" => { type => "field", addr => 0x40068, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_PHY_TRACE_BUS_SEL" => { type => "reg", addr => 0x4006c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_PHY_TRACE_BUS_SEL.VAL" => { type => "field", addr => 0x4006c, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_EVENTBUS_SELECT" => { type => "reg", addr => 0x40070, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_EVENTBUS_SELECT.VAL" => { type => "field", addr => 0x40070, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_ECO_SPARE_REG" => { type => "reg", addr => 0x40074, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_ECO_SPARE_REG.VAL" => { type => "field", addr => 0x40074, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x14 }, "WIFICMN_MCMN_CLK_GATE_DISABLE" => { type => "reg", addr => 0x40078, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_MCMN_CLK_GATE_DISABLE.VAL" => { type => "field", addr => 0x40078, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "WIFICMN_MEM_CNTL" => { type => "reg", addr => 0x4007c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_MEM_CNTL.CE_RAM_PD" => { type => "field", addr => 0x4007c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_MEM_CNTL.WCOEX_RAM_PD" => { type => "field", addr => 0x4007c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_MEM_CNTL.CPU_SS_RAM_RTSEL" => { type => "field", addr => 0x4007c, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "WIFICMN_MEM_CNTL.CPU_SS_RAM_WTSEL" => { type => "field", addr => 0x4007c, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "WIFICMN_MEM_CNTL.CPU_SS_RAM_AWT" => { type => "field", addr => 0x4007c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_MEM_CNTL.CPU_SS_RAM_PD" => { type => "field", addr => 0x4007c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFICMN_PIFAXI_PRIORITY" => { type => "reg", addr => 0x40080, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFICMN_PIFAXI_PRIORITY.CPU_SS_AXIREQPRIORITY" => { type => "field", addr => 0x40080, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, ################################################################### ## wifi_timers_reg Register/Field definitions ################################################################### "WIFI_TIMERS_SLP32_MODE" => { type => "reg", addr => 0x41000, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_SLP32_MODE.SYNC_WB_CNT_ONLY_AFTER_WAKEUP" => { type => "field", addr => 0x41000, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "WIFI_TIMERS_SLP32_MODE.SYNC_TM_TSF2_ONLY_AFTER_WAKEUP" => { type => "field", addr => 0x41000, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "WIFI_TIMERS_SLP32_MODE.SYNC_TM_TSF_ONLY_AFTER_WAKEUP" => { type => "field", addr => 0x41000, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "WIFI_TIMERS_SLP32_MODE.TSF2_WRITE_STATUS" => { type => "field", addr => 0x41000, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "WIFI_TIMERS_SLP32_MODE.DISABLE_32KHZ" => { type => "field", addr => 0x41000, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_SLP32_MODE.TSF_WRITE_STATUS" => { type => "field", addr => 0x41000, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RO", resetVal => 0x1 }, "WIFI_TIMERS_SLP32_MODE.HALF_CLK_LATENCY" => { type => "field", addr => 0x41000, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xF424 }, "WIFI_TIMERS_SLP32_WAKE" => { type => "reg", addr => 0x41004, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_SLP32_WAKE.XTL_TIME" => { type => "field", addr => 0x41004, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x800 }, "WIFI_TIMERS_SLP32_INC" => { type => "reg", addr => 0x41008, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_SLP32_INC.TSF_INC" => { type => "field", addr => 0x41008, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1E848 }, "WIFI_TIMERS_SLP_MIB1" => { type => "reg", addr => 0x4100c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_SLP_MIB1.SLEEP_CNT" => { type => "field", addr => 0x4100c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_SLP_MIB2" => { type => "reg", addr => 0x41010, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_SLP_MIB2.CYCLE_CNT" => { type => "field", addr => 0x41010, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_SLP_MIB3" => { type => "reg", addr => 0x41014, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_SLP_MIB3.PENDING" => { type => "field", addr => 0x41014, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WIFI_TIMERS_SLP_MIB3.CLR_CNT" => { type => "field", addr => 0x41014, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_TSF_L32" => { type => "reg", addr => 0x41018, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_TSF_L32.VALUE" => { type => "field", addr => 0x41018, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFF }, "WIFI_TIMERS_TSF_U32" => { type => "reg", addr => 0x4101c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_TSF_U32.VALUE" => { type => "field", addr => 0x4101c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFF }, "WIFI_TIMERS_WBTIMER_0" => { type => "reg", addr => 0x41020, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_WBTIMER_0.ENABLE" => { type => "field", addr => 0x41020, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_WBTIMER_1" => { type => "reg", addr => 0x41024, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_WBTIMER_1.VALUE" => { type => "field", addr => 0x41024, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_GENERIC_TIMERS" => { type => "reg", addr => 0x41028, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "WIFI_TIMERS_GENERIC_TIMERS.DATA" => { type => "field", addr => 0x41028, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "WIFI_TIMERS_GENERIC_TIMERS_MODE" => { type => "reg", addr => 0x41068, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_GENERIC_TIMERS_MODE.THRESH" => { type => "field", addr => 0x41068, width => 20, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x100 }, "WIFI_TIMERS_GENERIC_TIMERS_MODE.OVERFLOW_INDEX" => { type => "field", addr => 0x41068, width => 3, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "WIFI_TIMERS_GENERIC_TIMERS_MODE.ENABLE" => { type => "field", addr => 0x41068, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_SLP1" => { type => "reg", addr => 0x4106c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_SLP1.CAB_TIMEOUT" => { type => "field", addr => 0x4106c, width => 11, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "WIFI_TIMERS_SLP1.BUG_59985_FIX_ENABLE" => { type => "field", addr => 0x4106c, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_SLP1.ASSUME_DTIM" => { type => "field", addr => 0x4106c, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_SLP1.CAB_TIMEOUT_EXT" => { type => "field", addr => 0x4106c, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_SLP2" => { type => "reg", addr => 0x41070, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_SLP2.BEACON_TIMEOUT" => { type => "field", addr => 0x41070, width => 11, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "WIFI_TIMERS_SLP2.BEACON_TIMEOUT_EXT" => { type => "field", addr => 0x41070, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_SLP3" => { type => "reg", addr => 0x41074, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_SLP3.CAB_AWAKE_ENABLE" => { type => "field", addr => 0x41074, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_SLP3.CAB_AWAKE_DUR" => { type => "field", addr => 0x41074, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "WIFI_TIMERS_SLP4" => { type => "reg", addr => 0x41078, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_SLP4.ASSUME_DTIM2" => { type => "field", addr => 0x41078, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_SLP4.CAB2_TIMEOUT" => { type => "field", addr => 0x41078, width => 15, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "WIFI_TIMERS_SLP4.BEACON2_TIMEOUT" => { type => "field", addr => 0x41078, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "WIFI_TIMERS_DIRECT_CONNECT" => { type => "reg", addr => 0x4107c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_DIRECT_CONNECT.TSF2_CLK_REQ_DISABLE" => { type => "field", addr => 0x4107c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_DIRECT_CONNECT.TSF1_CLK_REQ_DISABLE" => { type => "field", addr => 0x4107c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_DIRECT_CONNECT.BMISS_CNT_TSF_SEL" => { type => "field", addr => 0x4107c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_DIRECT_CONNECT.TSF2_UPDATE" => { type => "field", addr => 0x4107c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_DIRECT_CONNECT.TSF1_UPDATE" => { type => "field", addr => 0x4107c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "WIFI_TIMERS_DIRECT_CONNECT.TS_TSF_SEL" => { type => "field", addr => 0x4107c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_DIRECT_CONNECT.TSF2_ENABLE" => { type => "field", addr => 0x4107c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_RESET_TSF" => { type => "reg", addr => 0x4108c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_RESET_TSF.ONE_SHOT2" => { type => "field", addr => 0x4108c, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_RESET_TSF.ONE_SHOT" => { type => "field", addr => 0x4108c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_TSF2_L32" => { type => "reg", addr => 0x41090, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_TSF2_L32.VALUE" => { type => "field", addr => 0x41090, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFF }, "WIFI_TIMERS_TSF2_U32" => { type => "reg", addr => 0x41094, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_TSF2_U32.VALUE" => { type => "field", addr => 0x41094, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFFFFF }, "WIFI_TIMERS_GENERIC_TIMERS2" => { type => "reg", addr => 0x41098, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "WIFI_TIMERS_GENERIC_TIMERS2.DATA" => { type => "field", addr => 0x41098, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "WIFI_TIMERS_GENERIC_TIMERS_MODE2" => { type => "reg", addr => 0x410d8, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_GENERIC_TIMERS_MODE2.OVERFLOW_INDEX2" => { type => "field", addr => 0x410d8, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "WIFI_TIMERS_GENERIC_TIMERS_MODE2.OVERFLOW_INDEX" => { type => "field", addr => 0x410d8, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "WIFI_TIMERS_GENERIC_TIMERS_MODE2.ENABLE" => { type => "field", addr => 0x410d8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_TSF_THRESHOLD" => { type => "reg", addr => 0x410dc, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_TSF_THRESHOLD.VALUE" => { type => "field", addr => 0x410dc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, "WIFI_TIMERS_GENERIC_TIMERS_TSF_SEL" => { type => "reg", addr => 0x410e0, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_GENERIC_TIMERS_TSF_SEL.VALUE" => { type => "field", addr => 0x410e0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_BMISS_TIMEOUT" => { type => "reg", addr => 0x410e4, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_BMISS_TIMEOUT.ENABLE" => { type => "field", addr => 0x410e4, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_BMISS_TIMEOUT.VALUE" => { type => "field", addr => 0x410e4, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xffffff }, "WIFI_TIMERS_BMISS2_TIMEOUT" => { type => "reg", addr => 0x410e8, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_BMISS2_TIMEOUT.ENABLE" => { type => "field", addr => 0x410e8, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_BMISS2_TIMEOUT.VALUE" => { type => "field", addr => 0x410e8, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xffffff }, "WIFI_TIMERS_QUIET_TIME_2" => { type => "reg", addr => 0x410ec, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_QUIET_TIME_2.DURATION" => { type => "field", addr => 0x410ec, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_QUIET_TIME_2.DURATION2" => { type => "field", addr => 0x410ec, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_HCF_TIMEOUT" => { type => "reg", addr => 0x410f0, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_HCF_TIMEOUT.VALUE" => { type => "field", addr => 0x410f0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_MISC_MODE" => { type => "reg", addr => 0x410f4, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_MISC_MODE.FORCE_QUIET_COLLISION" => { type => "field", addr => 0x410f4, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_MISC_MODE.TBTT_PROTECT" => { type => "field", addr => 0x410f4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "WIFI_TIMERS_USEC_LATENCY" => { type => "reg", addr => 0x410f8, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_USEC_LATENCY.USEC" => { type => "field", addr => 0x410f8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000077 }, "WIFI_TIMERS_MAX_CFP_DUR" => { type => "reg", addr => 0x410fc, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_TIMERS_MAX_CFP_DUR.USEC_FRAC_DENOMINATOR" => { type => "field", addr => 0x410fc, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_MAX_CFP_DUR.USEC_FRAC_NUMERATOR" => { type => "field", addr => 0x410fc, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_TIMERS_MAX_CFP_DUR.VALUE" => { type => "field", addr => 0x410fc, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wifi_pta_coex_reg Register/Field definitions ################################################################### "PTA_COEX_BLUETOOTH_MODE" => { type => "reg", addr => 0x43000, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BLUETOOTH_MODE.FIRST_SLOT_TIME" => { type => "field", addr => 0x43000, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "PTA_COEX_BLUETOOTH_MODE.PRIORITY_TIME" => { type => "field", addr => 0x43000, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x12 }, "PTA_COEX_BLUETOOTH_MODE.RX_CLEAR_POLARITY" => { type => "field", addr => 0x43000, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE.QCU_THRESH" => { type => "field", addr => 0x43000, width => 4, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "PTA_COEX_BLUETOOTH_MODE.QUIET" => { type => "field", addr => 0x43000, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE.MODE" => { type => "field", addr => 0x43000, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "PTA_COEX_BLUETOOTH_MODE.TX_FRAME_EXTEND" => { type => "field", addr => 0x43000, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE.TX_STATE_EXTEND" => { type => "field", addr => 0x43000, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE.TIME_EXTEND" => { type => "field", addr => 0x43000, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2" => { type => "reg", addr => 0x43004, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BLUETOOTH_MODE2.PHY_ERR_BT_COLL_ENABLE" => { type => "field", addr => 0x43004, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.INTERRUPT_ENABLE" => { type => "field", addr => 0x43004, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.WBCNT_BT_PRIORITY_CTRL" => { type => "field", addr => 0x43004, width => 2, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.WBCNT_BT_ACTIVE_CTRL" => { type => "field", addr => 0x43004, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.RS_DISCARD_EXTEND" => { type => "field", addr => 0x43004, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.WL_TXRX_SEPARATE" => { type => "field", addr => 0x43004, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.WL_ACTIVE_MODE" => { type => "field", addr => 0x43004, width => 2, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.DISABLE_BT_STOP_RX" => { type => "field", addr => 0x43004, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PTA_COEX_BLUETOOTH_MODE2.DISABLE_BT_ANT" => { type => "field", addr => 0x43004, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.PROTECT_BT_AFTER_WAKEUP" => { type => "field", addr => 0x43004, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.SLEEP_ALLOW_BT_ACCESS" => { type => "field", addr => 0x43004, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PTA_COEX_BLUETOOTH_MODE2.HOLD_RX_CLEAR" => { type => "field", addr => 0x43004, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.BCN_MISS_CNT" => { type => "field", addr => 0x43004, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE2.BCN_MISS_THRESH" => { type => "field", addr => 0x43004, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE3" => { type => "reg", addr => 0x43008, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BLUETOOTH_MODE3.BT_PRIORITY_EXTEND_THRES" => { type => "field", addr => 0x43008, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE3.BT_TX_ON_EN" => { type => "field", addr => 0x43008, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE3.SLOT_SLOP" => { type => "field", addr => 0x43008, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PTA_COEX_BLUETOOTH_MODE3.DYNAMIC_TOGGLE_WLA_DISABLE" => { type => "field", addr => 0x43008, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PTA_COEX_BLUETOOTH_MODE3.DYNAMIC_PRI_EN" => { type => "field", addr => 0x43008, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE3.AGC_SATURATION_CNT_ENABLE" => { type => "field", addr => 0x43008, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE3.ALLOW_CONCURRENT_ACCESS" => { type => "field", addr => 0x43008, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE3.WL_QC_TIME" => { type => "field", addr => 0x43008, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE3.WL_ACTIVE_TIME" => { type => "field", addr => 0x43008, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE4" => { type => "reg", addr => 0x4300c, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BLUETOOTH_MODE4.BT_PRIORITY_EXTEND" => { type => "field", addr => 0x4300c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE4.BT_ACTIVE_EXTEND" => { type => "field", addr => 0x4300c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE5" => { type => "reg", addr => 0x43010, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BLUETOOTH_MODE5.TXSTATE_TXFRAME_EXTEND" => { type => "field", addr => 0x43010, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE5.DISABLE_WL_MED_BUSY" => { type => "field", addr => 0x43010, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PTA_COEX_BLUETOOTH_MODE5.FORCE_RX_CLEAR_VAL" => { type => "field", addr => 0x43010, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PTA_COEX_BLUETOOTH_MODE5.FORCE_RX_CLEAR_EN" => { type => "field", addr => 0x43010, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE5.USE_D2_SLEEP" => { type => "field", addr => 0x43010, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PTA_COEX_BLUETOOTH_MODE5.USE_BTP_EXT" => { type => "field", addr => 0x43010, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE5.SHARED_RX" => { type => "field", addr => 0x43010, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE5.TX_ON_SRC" => { type => "field", addr => 0x43010, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_MODE5.MCI_WL_LEVEL_MULT" => { type => "field", addr => 0x43010, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE" => { type => "reg", addr => 0x43014, width => 32, athEmulAttr => 0, acc => "RO" }, "PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE.VALUE" => { type => "field", addr => 0x43014, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY" => { type => "reg", addr => 0x43018, width => 32, athEmulAttr => 0, acc => "RO" }, "PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY.VALUE" => { type => "field", addr => 0x43018, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PTA_COEX_BT_BT" => { type => "reg", addr => 0x43020, width => 32, athEmulAttr => 0, acc => "RW", depth => 64, incr => 4 }, "PTA_COEX_BT_BT.WEIGHT" => { type => "field", addr => 0x43020, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "PTA_COEX_BT_BT_ASYNC" => { type => "reg", addr => 0x43120, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BT_BT_ASYNC.RXLP_WEIGHT" => { type => "field", addr => 0x43120, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BT_BT_ASYNC.RXHP_WEIGHT" => { type => "field", addr => 0x43120, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BT_BT_ASYNC.TXLP_WEIGHT" => { type => "field", addr => 0x43120, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BT_BT_ASYNC.TXHP_WEIGHT" => { type => "field", addr => 0x43120, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BT_WL_1" => { type => "reg", addr => 0x43124, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BT_WL_1.WEIGHT" => { type => "field", addr => 0x43124, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BT_WL_2" => { type => "reg", addr => 0x43128, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BT_WL_2.WEIGHT" => { type => "field", addr => 0x43128, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BT_WL_3" => { type => "reg", addr => 0x4312c, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BT_WL_3.WEIGHT" => { type => "field", addr => 0x4312c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BT_WL_4" => { type => "reg", addr => 0x43130, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BT_WL_4.WEIGHT" => { type => "field", addr => 0x43130, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_QUIET_TIME_1" => { type => "reg", addr => 0x43138, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_QUIET_TIME_1.ACK_CTS_ENABLE" => { type => "field", addr => 0x43138, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PTA_COEX_BT_ANT_SLEEP_EXTEND" => { type => "reg", addr => 0x4313c, width => 32, athEmulAttr => 0, acc => "RW" }, "PTA_COEX_BT_ANT_SLEEP_EXTEND.CNT" => { type => "field", addr => 0x4313c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, ################################################################### ## Wlan_CxM_reg_csr Register/Field definitions ################################################################### "UART_DATA" => { type => "reg", addr => 0x43400, width => 32, athEmulAttr => 0, acc => "RW" }, "UART_DATA.TX_CSR" => { type => "field", addr => 0x43400, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_DATA.RX_CSR" => { type => "field", addr => 0x43400, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_DATA.TXRX_DATA" => { type => "field", addr => 0x43400, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_CONTROL" => { type => "reg", addr => 0x43404, width => 32, athEmulAttr => 0, acc => "RW" }, "UART_CONTROL.TDM_RX_ENA" => { type => "field", addr => 0x43404, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_CONTROL.RX_BUSY" => { type => "field", addr => 0x43404, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "UART_CONTROL.TX_BUSY" => { type => "field", addr => 0x43404, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "UART_CONTROL.TX_BREAK" => { type => "field", addr => 0x43404, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_CONTROL.RX_BREAK" => { type => "field", addr => 0x43404, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "UART_TX_FIFO1" => { type => "reg", addr => 0x43408, width => 32, athEmulAttr => 0, acc => "RW" }, "UART_TX_FIFO1.TX_FIFO_RST" => { type => "field", addr => 0x43408, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_TX_FIFO1.DEPTH" => { type => "field", addr => 0x43408, width => 9, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "UART_TX_FIFO1.AEPT_THR" => { type => "field", addr => 0x43408, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_TX_FIFO2" => { type => "reg", addr => 0x4340c, width => 32, athEmulAttr => 0, acc => "RW" }, "UART_TX_FIFO2.RB_CSR" => { type => "field", addr => 0x4340c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_TX_FIFO2.RB_VAL" => { type => "field", addr => 0x4340c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "UART_RX_FIFO" => { type => "reg", addr => 0x43410, width => 32, athEmulAttr => 0, acc => "RW" }, "UART_RX_FIFO.RX_FIFO_RST" => { type => "field", addr => 0x43410, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_RX_FIFO.DEPTH" => { type => "field", addr => 0x43410, width => 9, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "UART_RX_FIFO.AFUL_THR" => { type => "field", addr => 0x43410, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_CLKDIV" => { type => "reg", addr => 0x43414, width => 32, athEmulAttr => 0, acc => "RW" }, "UART_CLKDIV.CLK_SCALE" => { type => "field", addr => 0x43414, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_CLKDIV.CLK_STEP" => { type => "field", addr => 0x43414, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1175 }, "UART_INT" => { type => "reg", addr => 0x43418, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "UART_INT.HOST_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "UART_INT.TX_ENA_RE" => { type => "field", addr => 0x43418, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.DIRECT_MSG_TXED" => { type => "field", addr => 0x43418, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TCM_NACK" => { type => "field", addr => 0x43418, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TCM_ACK" => { type => "field", addr => 0x43418, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TDM_MISALIGN" => { type => "field", addr => 0x43418, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TYPE7_MSG_RXED" => { type => "field", addr => 0x43418, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TYPE6_MSG_RXED" => { type => "field", addr => 0x43418, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TYPE5_MSG_RXED" => { type => "field", addr => 0x43418, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TYPE4_MSG_RXED" => { type => "field", addr => 0x43418, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TYPE3_MSG_RXED" => { type => "field", addr => 0x43418, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TYPE2_MSG_RXED" => { type => "field", addr => 0x43418, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TYPE1_MSG_RXED" => { type => "field", addr => 0x43418, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TYPE0_MSG_RXED" => { type => "field", addr => 0x43418, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.CXM_TIMER1_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.CXM_TIMER0_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.MWS_RX_FE_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.MWS_RX_RE_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.MWS_TX_FE_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.MWS_TX_RE_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.ACTIVE_FE_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.ACTIVE_RE_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.FSYNC_RE_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TX_FIFO_OVFL_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.TX_FIFO_READY_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.RX_FIFO_UDFL_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.RX_FIFO_OVFL_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.RX_FIFO_READY_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.RX_BREAK_OFF_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.RX_BREAK_ON_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT.RX_FRAMING_ERR_INT" => { type => "field", addr => 0x43418, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UART_INT_EN" => { type => "reg", addr => 0x4341c, width => 32, athEmulAttr => 0, acc => "RW" }, "UART_INT_EN.HOST_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TX_ENA_RE_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.DIRECT_MSG_TXED_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TCM_NACK_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TCM_ACK_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TDM_MISALIGN_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TYPE7_MSG_RXED_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TYPE6_MSG_RXED_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TYPE5_MSG_RXED_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TYPE4_MSG_RXED_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TYPE3_MSG_RXED_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TYPE2_MSG_RXED_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TYPE1_MSG_RXED_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TYPE0_MSG_RXED_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.CXM_TIMER1_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.CXM_TIMER0_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.MWS_RX_FE_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.MWS_RX_RE_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.MWS_TX_FE_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.MWS_TX_RE_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.ACTIVE_FE_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.ACTIVE_RE_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.FSYNC_RE_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TX_FIFO_OVFL_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.TX_FIFO_READY_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.RX_FIFO_UDFL_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.RX_FIFO_OVFL_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.RX_FIFO_READY_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.RX_BREAK_OFF_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.RX_BREAK_ON_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UART_INT_EN.RX_FRAMING_ERR_INT_EN" => { type => "field", addr => 0x4341c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WB_CNT_FSYNC_RE" => { type => "reg", addr => 0x43420, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_FSYNC_RE.VAL" => { type => "field", addr => 0x43420, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_ACTIVE_RE" => { type => "reg", addr => 0x43424, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_ACTIVE_RE.VAL" => { type => "field", addr => 0x43424, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_ACTIVE_FE" => { type => "reg", addr => 0x43428, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_ACTIVE_FE.VAL" => { type => "field", addr => 0x43428, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_MWS_TX_RE" => { type => "reg", addr => 0x4342c, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_MWS_TX_RE.VAL" => { type => "field", addr => 0x4342c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_MWS_TX_FE" => { type => "reg", addr => 0x43430, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_MWS_TX_FE.VAL" => { type => "field", addr => 0x43430, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_MWS_RX_RE" => { type => "reg", addr => 0x43434, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_MWS_RX_RE.VAL" => { type => "field", addr => 0x43434, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_MWS_RX_FE" => { type => "reg", addr => 0x43438, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_MWS_RX_FE.VAL" => { type => "field", addr => 0x43438, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_RX_TYPE7" => { type => "reg", addr => 0x4343c, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_RX_TYPE7.VAL" => { type => "field", addr => 0x4343c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_RX_TYPE6" => { type => "reg", addr => 0x43440, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_RX_TYPE6.VAL" => { type => "field", addr => 0x43440, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_RX_TYPE5" => { type => "reg", addr => 0x43444, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_RX_TYPE5.VAL" => { type => "field", addr => 0x43444, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_RX_TYPE4" => { type => "reg", addr => 0x43448, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_RX_TYPE4.VAL" => { type => "field", addr => 0x43448, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_RX_TYPE3" => { type => "reg", addr => 0x4344c, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_RX_TYPE3.VAL" => { type => "field", addr => 0x4344c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_RX_TYPE2" => { type => "reg", addr => 0x43450, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_RX_TYPE2.VAL" => { type => "field", addr => 0x43450, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_RX_TYPE1" => { type => "reg", addr => 0x43454, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_RX_TYPE1.VAL" => { type => "field", addr => 0x43454, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "WB_CNT_RX_TYPE0" => { type => "reg", addr => 0x43458, width => 32, athEmulAttr => 0, acc => "RO" }, "WB_CNT_RX_TYPE0.VAL" => { type => "field", addr => 0x43458, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RX_CxM_MSG_CONTENT1" => { type => "reg", addr => 0x4345c, width => 32, athEmulAttr => 0, acc => "RO" }, "RX_CxM_MSG_CONTENT1.TYPE3" => { type => "field", addr => 0x4345c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RX_CxM_MSG_CONTENT1.TYPE2" => { type => "field", addr => 0x4345c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RX_CxM_MSG_CONTENT1.TYPE1" => { type => "field", addr => 0x4345c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RX_CxM_MSG_CONTENT1.TYPE0" => { type => "field", addr => 0x4345c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RX_CxM_MSG_CONTENT2" => { type => "reg", addr => 0x43460, width => 32, athEmulAttr => 0, acc => "RO" }, "RX_CxM_MSG_CONTENT2.TYPE7" => { type => "field", addr => 0x43460, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RX_CxM_MSG_CONTENT2.TYPE6" => { type => "field", addr => 0x43460, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RX_CxM_MSG_CONTENT2.TYPE5" => { type => "field", addr => 0x43460, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "RX_CxM_MSG_CONTENT2.TYPE4" => { type => "field", addr => 0x43460, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CxM_Ctrl1" => { type => "reg", addr => 0x43464, width => 32, athEmulAttr => 0, acc => "RW" }, "CxM_Ctrl1.Rx_Pri" => { type => "field", addr => 0x43464, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Pri_Oride_Val" => { type => "field", addr => 0x43464, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Pri_Oride_Ena" => { type => "field", addr => 0x43464, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Pri_Val2" => { type => "field", addr => 0x43464, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Pri_Val1" => { type => "field", addr => 0x43464, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Pri_Ena2" => { type => "field", addr => 0x43464, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Pri_Ena1" => { type => "field", addr => 0x43464, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Grant" => { type => "field", addr => 0x43464, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Grant_bm" => { type => "field", addr => 0x43464, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Grant_Sel" => { type => "field", addr => 0x43464, width => 2, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Grant_Oride_Val" => { type => "field", addr => 0x43464, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Grant_Oride_Ena" => { type => "field", addr => 0x43464, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Grant_Val2" => { type => "field", addr => 0x43464, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Grant_Val1" => { type => "field", addr => 0x43464, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Grant_Ena2" => { type => "field", addr => 0x43464, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Rx_Grant_Ena1" => { type => "field", addr => 0x43464, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Tx_Grant" => { type => "field", addr => 0x43464, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CxM_Ctrl1.Tx_Grant_bm" => { type => "field", addr => 0x43464, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CxM_Ctrl1.Tx_Grant_Sel" => { type => "field", addr => 0x43464, width => 2, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Tx_Grant_Oride_Val" => { type => "field", addr => 0x43464, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Tx_Grant_Oride_Ena" => { type => "field", addr => 0x43464, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Tx_Grant_Val2" => { type => "field", addr => 0x43464, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Tx_Grant_Val1" => { type => "field", addr => 0x43464, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Tx_Grant_Ena2" => { type => "field", addr => 0x43464, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.Tx_Grant_Ena1" => { type => "field", addr => 0x43464, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl1.inf_3w_sel" => { type => "field", addr => 0x43464, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CxM_Ctrl2" => { type => "reg", addr => 0x43468, width => 32, athEmulAttr => 0, acc => "RW" }, "CxM_Ctrl2.Tout_Val" => { type => "field", addr => 0x43468, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x4b2 }, "CxM_Ctrl3" => { type => "reg", addr => 0x4346c, width => 32, athEmulAttr => 0, acc => "RW" }, "CxM_Ctrl3.RST_UART" => { type => "field", addr => 0x4346c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl3.Direct_Msg_Content" => { type => "field", addr => 0x4346c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl3.Timer1_Int_Ctrl" => { type => "field", addr => 0x4346c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl3.Timer0_Int_Ctrl" => { type => "field", addr => 0x4346c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl3.Direct_Msg_Tx" => { type => "field", addr => 0x4346c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl3.WakeUp_Clr_RTSM_Dat" => { type => "field", addr => 0x4346c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CxM_Ctrl3.Tx_Msg_Ena" => { type => "field", addr => 0x4346c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CxM_Ctrl4" => { type => "reg", addr => 0x43470, width => 32, athEmulAttr => 0, acc => "RW" }, "CxM_Ctrl4.BT_Rx_Pri" => { type => "field", addr => 0x43470, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CxM_Ctrl4.BT_Rx_Pri_Oride_Val" => { type => "field", addr => 0x43470, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl4.BT_Rx_Pri_Oride_Ena" => { type => "field", addr => 0x43470, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl4.BT_Rx_Pri_Val2" => { type => "field", addr => 0x43470, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl4.BT_Rx_Pri_Val1" => { type => "field", addr => 0x43470, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl4.BT_Rx_Pri_Ena2" => { type => "field", addr => 0x43470, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CxM_Ctrl4.BT_Rx_Pri_Ena1" => { type => "field", addr => 0x43470, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Timer0_Int_Start" => { type => "reg", addr => 0x43474, width => 32, athEmulAttr => 0, acc => "RW" }, "Timer0_Int_Start.VAL" => { type => "field", addr => 0x43474, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Timer0_Int_Period" => { type => "reg", addr => 0x43478, width => 32, athEmulAttr => 0, acc => "RW" }, "Timer0_Int_Period.VAL" => { type => "field", addr => 0x43478, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Timer1_Int_Start" => { type => "reg", addr => 0x4347c, width => 32, athEmulAttr => 0, acc => "RW" }, "Timer1_Int_Start.VAL" => { type => "field", addr => 0x4347c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Timer1_Int_Period" => { type => "reg", addr => 0x43480, width => 32, athEmulAttr => 0, acc => "RW" }, "Timer1_Int_Period.VAL" => { type => "field", addr => 0x43480, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Tx_Grant_Thr1" => { type => "reg", addr => 0x43484, width => 32, athEmulAttr => 0, acc => "RW" }, "Tx_Grant_Thr1.VAL" => { type => "field", addr => 0x43484, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Tx_Grant_Thr2" => { type => "reg", addr => 0x43488, width => 32, athEmulAttr => 0, acc => "RW" }, "Tx_Grant_Thr2.VAL" => { type => "field", addr => 0x43488, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Rx_Grant_Thr1" => { type => "reg", addr => 0x4348c, width => 32, athEmulAttr => 0, acc => "RW" }, "Rx_Grant_Thr1.VAL" => { type => "field", addr => 0x4348c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Rx_Grant_Thr2" => { type => "reg", addr => 0x43490, width => 32, athEmulAttr => 0, acc => "RW" }, "Rx_Grant_Thr2.VAL" => { type => "field", addr => 0x43490, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Rx_Pri_Thr1" => { type => "reg", addr => 0x43494, width => 32, athEmulAttr => 0, acc => "RW" }, "Rx_Pri_Thr1.VAL" => { type => "field", addr => 0x43494, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "Rx_Pri_Thr2" => { type => "reg", addr => 0x43498, width => 32, athEmulAttr => 0, acc => "RW" }, "Rx_Pri_Thr2.VAL" => { type => "field", addr => 0x43498, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BT_Rx_Pri_Thr1" => { type => "reg", addr => 0x4349c, width => 32, athEmulAttr => 0, acc => "RW" }, "BT_Rx_Pri_Thr1.VAL" => { type => "field", addr => 0x4349c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BT_Rx_Pri_Thr2" => { type => "reg", addr => 0x434a0, width => 32, athEmulAttr => 0, acc => "RW" }, "BT_Rx_Pri_Thr2.VAL" => { type => "field", addr => 0x434a0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wifi_lte_coex_reg Register/Field definitions ################################################################### "LTE_COEX_CTRL" => { type => "reg", addr => 0x43800, width => 32, athEmulAttr => 0, acc => "RW" }, "LTE_COEX_CTRL.AUTO_ACTIVE_MASK_DELAY" => { type => "field", addr => 0x43800, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x40 }, "LTE_COEX_CTRL.FORCE_WAIT_BA_DISABLE" => { type => "field", addr => 0x43800, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "LTE_COEX_CTRL.BT_TX_ENABLE" => { type => "field", addr => 0x43800, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "LTE_COEX_CTRL.BT_TX" => { type => "field", addr => 0x43800, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "LTE_COEX_CTRL.AUTO_ACTIVE_MASK" => { type => "field", addr => 0x43800, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "LTE_COEX_CTRL.RX_GRANT_ENABLE" => { type => "field", addr => 0x43800, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "LTE_COEX_CTRL.TX_GRANT_ENABLE" => { type => "field", addr => 0x43800, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## wifi_rtc_reg Register/Field definitions ################################################################### "WIFI_RESET_CONTROL" => { type => "reg", addr => 0x45000, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_RESET_CONTROL.APB_SRIF_RESET" => { type => "field", addr => 0x45000, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_RESET_CONTROL.CE_RESET" => { type => "field", addr => 0x45000, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_RESET_CONTROL.MCI_RESET" => { type => "field", addr => 0x45000, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_RESET_CONTROL.RADIO_SRESET" => { type => "field", addr => 0x45000, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x00000001 }, "WIFI_RESET_CONTROL.BB_COLD_RST" => { type => "field", addr => 0x45000, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x00000001 }, "WIFI_RESET_CONTROL.BB_WARM_RST" => { type => "field", addr => 0x45000, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x00000001 }, "WIFI_RESET_CONTROL.MAC_SM_RST" => { type => "field", addr => 0x45000, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_RESET_CONTROL.MAC_COLD_RST" => { type => "field", addr => 0x45000, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x00000001 }, "WIFI_RESET_CONTROL.MAC_WARM_RST" => { type => "field", addr => 0x45000, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000001 }, "WIFI_XTAL_CONTROL" => { type => "reg", addr => 0x45004, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_XTAL_CONTROL.TCXO" => { type => "field", addr => 0x45004, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_QUADRATURE" => { type => "reg", addr => 0x45010, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_QUADRATURE.ADC" => { type => "field", addr => 0x45010, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_QUADRATURE.DAC" => { type => "field", addr => 0x45010, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_PLL_CONTROL" => { type => "reg", addr => 0x45014, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_PLL_CONTROL.DIG_TEST_CLK" => { type => "field", addr => 0x45014, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_PLL_CONTROL.MAC_OVERRIDE" => { type => "field", addr => 0x45014, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_PLL_CONTROL.NOPWD" => { type => "field", addr => 0x45014, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_PLL_CONTROL.UPDATING" => { type => "field", addr => 0x45014, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "WIFI_PLL_CONTROL.BYPASS" => { type => "field", addr => 0x45014, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x00000001 }, "WIFI_PLL_CONTROL.CLK_SEL" => { type => "field", addr => 0x45014, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_PLL_CONTROL.REFDIV" => { type => "field", addr => 0x45014, width => 4, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x00000005 }, "WIFI_PLL_CONTROL.DIV" => { type => "field", addr => 0x45014, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000058 }, "WIFI_PLL_SETTLE" => { type => "reg", addr => 0x45018, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_PLL_SETTLE.TIME" => { type => "field", addr => 0x45018, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000400 }, "WIFI_XTAL_SETTLE" => { type => "reg", addr => 0x4501c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_XTAL_SETTLE.TIME" => { type => "field", addr => 0x4501c, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000042 }, "WIFI_CLOCK_OUT" => { type => "reg", addr => 0x45020, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_CLOCK_OUT.DELAY" => { type => "field", addr => 0x45020, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_CLOCK_OUT.SELECT" => { type => "field", addr => 0x45020, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_BIAS_OVERRIDE" => { type => "reg", addr => 0x45024, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_BIAS_OVERRIDE.ON" => { type => "field", addr => 0x45024, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_RESET_CAUSE" => { type => "reg", addr => 0x45028, width => 32, athEmulAttr => 0, acc => "RO" }, "WIFI_RESET_CAUSE.LAST" => { type => "field", addr => 0x45028, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "WIFI_SYSTEM_SLEEP" => { type => "reg", addr => 0x4502c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_SYSTEM_SLEEP.MAC_IF" => { type => "field", addr => 0x4502c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x00000001 }, "WIFI_SYSTEM_SLEEP.LIGHT" => { type => "field", addr => 0x4502c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WIFI_SYSTEM_SLEEP.DISABLE" => { type => "field", addr => 0x4502c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000001 }, "WIFI_MAC_SLEEP_CONTROL" => { type => "reg", addr => 0x45030, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_MAC_SLEEP_CONTROL.FORCE_WAKE" => { type => "field", addr => 0x45030, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_KEEP_AWAKE" => { type => "reg", addr => 0x45034, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_KEEP_AWAKE.MAC_CLK_REQ_COUNT" => { type => "field", addr => 0x45034, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x00000003 }, "WIFI_KEEP_AWAKE.COUNT" => { type => "field", addr => 0x45034, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000003 }, "WIFI_DERIVED_RTC_CLK" => { type => "reg", addr => 0x45038, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_DERIVED_RTC_CLK.EXTERNAL_DETECT_EN" => { type => "field", addr => 0x45038, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "WIFI_DERIVED_RTC_CLK.EXTERNAL_DETECT" => { type => "field", addr => 0x45038, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "WIFI_DERIVED_RTC_CLK.PERIOD" => { type => "field", addr => 0x45038, width => 15, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x262 }, "WIFI_RTC_SYNC_DERIVED" => { type => "reg", addr => 0x4503c, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_RTC_SYNC_DERIVED.FORCE" => { type => "field", addr => 0x4503c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "WIFI_RTC_SYNC_DERIVED.BYPASS" => { type => "field", addr => 0x4503c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "LF_TIMER0" => { type => "reg", addr => 0x45040, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER0.TARGET" => { type => "field", addr => 0x45040, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_COUNT0" => { type => "reg", addr => 0x45044, width => 32, athEmulAttr => 0, acc => "RO" }, "LF_TIMER_COUNT0.VALUE" => { type => "field", addr => 0x45044, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "LF_TIMER_CONTROL0" => { type => "reg", addr => 0x45048, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER_CONTROL0.ENABLE" => { type => "field", addr => 0x45048, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_CONTROL0.AUTO_RESTART" => { type => "field", addr => 0x45048, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_CONTROL0.RESET" => { type => "field", addr => 0x45048, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_STATUS0" => { type => "reg", addr => 0x4504c, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER_STATUS0.INTERRUPT" => { type => "field", addr => 0x4504c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER1" => { type => "reg", addr => 0x45050, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER1.TARGET" => { type => "field", addr => 0x45050, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_COUNT1" => { type => "reg", addr => 0x45054, width => 32, athEmulAttr => 0, acc => "RO" }, "LF_TIMER_COUNT1.VALUE" => { type => "field", addr => 0x45054, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "LF_TIMER_CONTROL1" => { type => "reg", addr => 0x45058, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER_CONTROL1.ENABLE" => { type => "field", addr => 0x45058, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_CONTROL1.AUTO_RESTART" => { type => "field", addr => 0x45058, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_CONTROL1.RESET" => { type => "field", addr => 0x45058, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_STATUS1" => { type => "reg", addr => 0x4505c, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER_STATUS1.INTERRUPT" => { type => "field", addr => 0x4505c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER2" => { type => "reg", addr => 0x45060, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER2.TARGET" => { type => "field", addr => 0x45060, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_COUNT2" => { type => "reg", addr => 0x45064, width => 32, athEmulAttr => 0, acc => "RO" }, "LF_TIMER_COUNT2.VALUE" => { type => "field", addr => 0x45064, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "LF_TIMER_CONTROL2" => { type => "reg", addr => 0x45068, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER_CONTROL2.ENABLE" => { type => "field", addr => 0x45068, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_CONTROL2.AUTO_RESTART" => { type => "field", addr => 0x45068, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_CONTROL2.RESET" => { type => "field", addr => 0x45068, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_STATUS2" => { type => "reg", addr => 0x4506c, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER_STATUS2.INTERRUPT" => { type => "field", addr => 0x4506c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER3" => { type => "reg", addr => 0x45070, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER3.TARGET" => { type => "field", addr => 0x45070, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_COUNT3" => { type => "reg", addr => 0x45074, width => 32, athEmulAttr => 0, acc => "RO" }, "LF_TIMER_COUNT3.VALUE" => { type => "field", addr => 0x45074, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "LF_TIMER_CONTROL3" => { type => "reg", addr => 0x45078, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER_CONTROL3.ENABLE" => { type => "field", addr => 0x45078, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_CONTROL3.AUTO_RESTART" => { type => "field", addr => 0x45078, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_CONTROL3.RESET" => { type => "field", addr => 0x45078, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LF_TIMER_STATUS3" => { type => "reg", addr => 0x4507c, width => 32, athEmulAttr => 0, acc => "RW" }, "LF_TIMER_STATUS3.INTERRUPT" => { type => "field", addr => 0x4507c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "HF_TIMER" => { type => "reg", addr => 0x45080, width => 32, athEmulAttr => 0, acc => "RW" }, "HF_TIMER.TARGET" => { type => "field", addr => 0x45080, width => 20, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "HF_TIMER_COUNT" => { type => "reg", addr => 0x45084, width => 32, athEmulAttr => 0, acc => "RO" }, "HF_TIMER_COUNT.VALUE" => { type => "field", addr => 0x45084, width => 20, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "HF_LF_COUNT" => { type => "reg", addr => 0x45088, width => 32, athEmulAttr => 0, acc => "RO" }, "HF_LF_COUNT.VALUE" => { type => "field", addr => 0x45088, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "HF_TIMER_CONTROL" => { type => "reg", addr => 0x4508c, width => 32, athEmulAttr => 0, acc => "RW" }, "HF_TIMER_CONTROL.ENABLE" => { type => "field", addr => 0x4508c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "HF_TIMER_CONTROL.ON" => { type => "field", addr => 0x4508c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "HF_TIMER_CONTROL.AUTO_RESTART" => { type => "field", addr => 0x4508c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "HF_TIMER_CONTROL.RESET" => { type => "field", addr => 0x4508c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "HF_TIMER_STATUS" => { type => "reg", addr => 0x45090, width => 32, athEmulAttr => 0, acc => "RW" }, "HF_TIMER_STATUS.INTERRUPT" => { type => "field", addr => 0x45090, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WDT_CONTROL" => { type => "reg", addr => 0x45094, width => 32, athEmulAttr => 0, acc => "RW" }, "WDT_CONTROL.ACTION" => { type => "field", addr => 0x45094, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WDT_STATUS" => { type => "reg", addr => 0x45098, width => 32, athEmulAttr => 0, acc => "RW" }, "WDT_STATUS.INTERRUPT" => { type => "field", addr => 0x45098, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WDT" => { type => "reg", addr => 0x4509c, width => 32, athEmulAttr => 0, acc => "RW" }, "WDT.TARGET" => { type => "field", addr => 0x4509c, width => 22, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 4194303 }, "WDT_COUNT" => { type => "reg", addr => 0x45a00, width => 32, athEmulAttr => 0, acc => "RO" }, "WDT_COUNT.VALUE" => { type => "field", addr => 0x45a00, width => 22, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "WDT_RESET" => { type => "reg", addr => 0x45a04, width => 32, athEmulAttr => 0, acc => "RW" }, "WDT_RESET.VALUE" => { type => "field", addr => 0x45a04, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WIFI_SLEEP_OVERRIDE" => { type => "reg", addr => 0x45a08, width => 32, athEmulAttr => 0, acc => "RW" }, "WIFI_SLEEP_OVERRIDE.VALUE" => { type => "field", addr => 0x45a08, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WMAC_SLEEP_OVERRIDE" => { type => "reg", addr => 0x45a0c, width => 32, athEmulAttr => 0, acc => "RW" }, "WMAC_SLEEP_OVERRIDE.VALUE" => { type => "field", addr => 0x45a0c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_PLL_CONFIG" => { type => "reg", addr => 0x45a10, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_PLL_CONFIG.OUTDIV" => { type => "field", addr => 0x45a10, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "BB_PLL_CONFIG.FRAC" => { type => "field", addr => 0x45a10, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, ################################################################### ## ce_reg_csr_0 Register/Field definitions ################################################################### "CE0_SR_BA" => { type => "reg", addr => 0x4a000, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_SR_BA.V" => { type => "field", addr => 0x4a000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_SR_SIZE" => { type => "reg", addr => 0x4a004, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_SR_SIZE.V" => { type => "field", addr => 0x4a004, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_DR_BA" => { type => "reg", addr => 0x4a008, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_DR_BA.V" => { type => "field", addr => 0x4a008, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_DR_SIZE" => { type => "reg", addr => 0x4a00c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_DR_SIZE.V" => { type => "field", addr => 0x4a00c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_CE_CTRL1" => { type => "reg", addr => 0x4a010, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4a010, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4a010, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4a010, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4a010, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE0_CE_CTRL2" => { type => "reg", addr => 0x4a014, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4a014, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE0_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4a014, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE0_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4a014, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE0_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4a014, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE0_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4a014, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE0_CE_CMD" => { type => "reg", addr => 0x4a018, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4a018, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE0_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4a018, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4a018, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_CE_CMD.HALT" => { type => "field", addr => 0x4a018, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MSI_ADDR" => { type => "reg", addr => 0x4a01c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_MSI_ADDR.V" => { type => "field", addr => 0x4a01c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MSI_DATA" => { type => "reg", addr => 0x4a020, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_MSI_DATA.V" => { type => "field", addr => 0x4a020, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_TARGET_IE" => { type => "reg", addr => 0x4a024, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a024, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a024, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a024, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a024, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4a024, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_TARGET_IS" => { type => "reg", addr => 0x4a028, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE0_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a028, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a028, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a028, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a028, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4a028, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE0_HOST_IE" => { type => "reg", addr => 0x4a02c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a02c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a02c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a02c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a02c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4a02c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_HOST_IS" => { type => "reg", addr => 0x4a030, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE0_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a030, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a030, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a030, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a030, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4a030, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE0_MISC_IE" => { type => "reg", addr => 0x4a034, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4a034, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IS" => { type => "reg", addr => 0x4a038, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE0_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE0_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE0_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE0_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE0_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE0_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE0_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4a038, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE0_SR_WR_INDEX" => { type => "reg", addr => 0x4a03c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_SR_WR_INDEX.V" => { type => "field", addr => 0x4a03c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_DST_WR_INDEX" => { type => "reg", addr => 0x4a040, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_DST_WR_INDEX.V" => { type => "field", addr => 0x4a040, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_CURRENT_SRRI" => { type => "reg", addr => 0x4a044, width => 32, athEmulAttr => 0, acc => "RO" }, "CE0_CURRENT_SRRI.V" => { type => "field", addr => 0x4a044, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE0_CURRENT_DRRI" => { type => "reg", addr => 0x4a048, width => 32, athEmulAttr => 0, acc => "RO" }, "CE0_CURRENT_DRRI.V" => { type => "field", addr => 0x4a048, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE0_SRC_WATERMARK" => { type => "reg", addr => 0x4a04c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4a04c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4a04c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_DST_WATERMARK" => { type => "reg", addr => 0x4a050, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_DST_WATERMARK.LOW" => { type => "field", addr => 0x4a050, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4a050, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_CE_DEBUG" => { type => "reg", addr => 0x4a054, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_CE_DEBUG.SEL" => { type => "field", addr => 0x4a054, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE0_CE_WATCHDOG" => { type => "reg", addr => 0x4a058, width => 32, athEmulAttr => 0, acc => "RW" }, "CE0_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4a058, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE0_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4a058, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_1 Register/Field definitions ################################################################### "CE1_SR_BA" => { type => "reg", addr => 0x4a400, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_SR_BA.V" => { type => "field", addr => 0x4a400, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_SR_SIZE" => { type => "reg", addr => 0x4a404, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_SR_SIZE.V" => { type => "field", addr => 0x4a404, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_DR_BA" => { type => "reg", addr => 0x4a408, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_DR_BA.V" => { type => "field", addr => 0x4a408, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_DR_SIZE" => { type => "reg", addr => 0x4a40c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_DR_SIZE.V" => { type => "field", addr => 0x4a40c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_CE_CTRL1" => { type => "reg", addr => 0x4a410, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4a410, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4a410, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4a410, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4a410, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE1_CE_CTRL2" => { type => "reg", addr => 0x4a414, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4a414, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE1_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4a414, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE1_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4a414, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE1_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4a414, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE1_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4a414, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE1_CE_CMD" => { type => "reg", addr => 0x4a418, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4a418, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE1_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4a418, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4a418, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_CE_CMD.HALT" => { type => "field", addr => 0x4a418, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MSI_ADDR" => { type => "reg", addr => 0x4a41c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_MSI_ADDR.V" => { type => "field", addr => 0x4a41c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MSI_DATA" => { type => "reg", addr => 0x4a420, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_MSI_DATA.V" => { type => "field", addr => 0x4a420, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_TARGET_IE" => { type => "reg", addr => 0x4a424, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a424, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a424, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a424, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a424, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4a424, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_TARGET_IS" => { type => "reg", addr => 0x4a428, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE1_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a428, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a428, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a428, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a428, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4a428, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE1_HOST_IE" => { type => "reg", addr => 0x4a42c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a42c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a42c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a42c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a42c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4a42c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_HOST_IS" => { type => "reg", addr => 0x4a430, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE1_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a430, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a430, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a430, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a430, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4a430, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE1_MISC_IE" => { type => "reg", addr => 0x4a434, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4a434, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IS" => { type => "reg", addr => 0x4a438, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE1_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE1_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE1_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE1_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE1_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE1_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE1_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4a438, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE1_SR_WR_INDEX" => { type => "reg", addr => 0x4a43c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_SR_WR_INDEX.V" => { type => "field", addr => 0x4a43c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_DST_WR_INDEX" => { type => "reg", addr => 0x4a440, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_DST_WR_INDEX.V" => { type => "field", addr => 0x4a440, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_CURRENT_SRRI" => { type => "reg", addr => 0x4a444, width => 32, athEmulAttr => 0, acc => "RO" }, "CE1_CURRENT_SRRI.V" => { type => "field", addr => 0x4a444, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE1_CURRENT_DRRI" => { type => "reg", addr => 0x4a448, width => 32, athEmulAttr => 0, acc => "RO" }, "CE1_CURRENT_DRRI.V" => { type => "field", addr => 0x4a448, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE1_SRC_WATERMARK" => { type => "reg", addr => 0x4a44c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4a44c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4a44c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_DST_WATERMARK" => { type => "reg", addr => 0x4a450, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_DST_WATERMARK.LOW" => { type => "field", addr => 0x4a450, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4a450, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_CE_DEBUG" => { type => "reg", addr => 0x4a454, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_CE_DEBUG.SEL" => { type => "field", addr => 0x4a454, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE1_CE_WATCHDOG" => { type => "reg", addr => 0x4a458, width => 32, athEmulAttr => 0, acc => "RW" }, "CE1_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4a458, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE1_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4a458, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_2 Register/Field definitions ################################################################### "CE2_SR_BA" => { type => "reg", addr => 0x4a800, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_SR_BA.V" => { type => "field", addr => 0x4a800, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_SR_SIZE" => { type => "reg", addr => 0x4a804, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_SR_SIZE.V" => { type => "field", addr => 0x4a804, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_DR_BA" => { type => "reg", addr => 0x4a808, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_DR_BA.V" => { type => "field", addr => 0x4a808, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_DR_SIZE" => { type => "reg", addr => 0x4a80c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_DR_SIZE.V" => { type => "field", addr => 0x4a80c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_CE_CTRL1" => { type => "reg", addr => 0x4a810, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4a810, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4a810, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4a810, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4a810, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE2_CE_CTRL2" => { type => "reg", addr => 0x4a814, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4a814, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE2_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4a814, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE2_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4a814, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE2_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4a814, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE2_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4a814, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE2_CE_CMD" => { type => "reg", addr => 0x4a818, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4a818, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE2_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4a818, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4a818, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_CE_CMD.HALT" => { type => "field", addr => 0x4a818, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MSI_ADDR" => { type => "reg", addr => 0x4a81c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_MSI_ADDR.V" => { type => "field", addr => 0x4a81c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MSI_DATA" => { type => "reg", addr => 0x4a820, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_MSI_DATA.V" => { type => "field", addr => 0x4a820, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_TARGET_IE" => { type => "reg", addr => 0x4a824, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a824, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a824, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a824, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a824, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4a824, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_TARGET_IS" => { type => "reg", addr => 0x4a828, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE2_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a828, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a828, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a828, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a828, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4a828, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE2_HOST_IE" => { type => "reg", addr => 0x4a82c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a82c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a82c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a82c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a82c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4a82c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_HOST_IS" => { type => "reg", addr => 0x4a830, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE2_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a830, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a830, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a830, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a830, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4a830, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE2_MISC_IE" => { type => "reg", addr => 0x4a834, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4a834, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IS" => { type => "reg", addr => 0x4a838, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE2_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE2_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE2_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE2_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE2_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE2_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE2_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4a838, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE2_SR_WR_INDEX" => { type => "reg", addr => 0x4a83c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_SR_WR_INDEX.V" => { type => "field", addr => 0x4a83c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_DST_WR_INDEX" => { type => "reg", addr => 0x4a840, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_DST_WR_INDEX.V" => { type => "field", addr => 0x4a840, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_CURRENT_SRRI" => { type => "reg", addr => 0x4a844, width => 32, athEmulAttr => 0, acc => "RO" }, "CE2_CURRENT_SRRI.V" => { type => "field", addr => 0x4a844, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE2_CURRENT_DRRI" => { type => "reg", addr => 0x4a848, width => 32, athEmulAttr => 0, acc => "RO" }, "CE2_CURRENT_DRRI.V" => { type => "field", addr => 0x4a848, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE2_SRC_WATERMARK" => { type => "reg", addr => 0x4a84c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4a84c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4a84c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_DST_WATERMARK" => { type => "reg", addr => 0x4a850, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_DST_WATERMARK.LOW" => { type => "field", addr => 0x4a850, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4a850, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_CE_DEBUG" => { type => "reg", addr => 0x4a854, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_CE_DEBUG.SEL" => { type => "field", addr => 0x4a854, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE2_CE_WATCHDOG" => { type => "reg", addr => 0x4a858, width => 32, athEmulAttr => 0, acc => "RW" }, "CE2_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4a858, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE2_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4a858, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_3 Register/Field definitions ################################################################### "CE3_SR_BA" => { type => "reg", addr => 0x4ac00, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_SR_BA.V" => { type => "field", addr => 0x4ac00, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_SR_SIZE" => { type => "reg", addr => 0x4ac04, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_SR_SIZE.V" => { type => "field", addr => 0x4ac04, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_DR_BA" => { type => "reg", addr => 0x4ac08, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_DR_BA.V" => { type => "field", addr => 0x4ac08, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_DR_SIZE" => { type => "reg", addr => 0x4ac0c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_DR_SIZE.V" => { type => "field", addr => 0x4ac0c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_CE_CTRL1" => { type => "reg", addr => 0x4ac10, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4ac10, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4ac10, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4ac10, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4ac10, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE3_CE_CTRL2" => { type => "reg", addr => 0x4ac14, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4ac14, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE3_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4ac14, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE3_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4ac14, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE3_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4ac14, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE3_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4ac14, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE3_CE_CMD" => { type => "reg", addr => 0x4ac18, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4ac18, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE3_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4ac18, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4ac18, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_CE_CMD.HALT" => { type => "field", addr => 0x4ac18, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MSI_ADDR" => { type => "reg", addr => 0x4ac1c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_MSI_ADDR.V" => { type => "field", addr => 0x4ac1c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MSI_DATA" => { type => "reg", addr => 0x4ac20, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_MSI_DATA.V" => { type => "field", addr => 0x4ac20, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_TARGET_IE" => { type => "reg", addr => 0x4ac24, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac24, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac24, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac24, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac24, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4ac24, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_TARGET_IS" => { type => "reg", addr => 0x4ac28, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE3_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac28, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac28, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac28, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac28, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4ac28, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE3_HOST_IE" => { type => "reg", addr => 0x4ac2c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac2c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac2c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac2c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac2c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4ac2c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_HOST_IS" => { type => "reg", addr => 0x4ac30, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE3_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac30, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac30, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac30, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac30, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4ac30, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE3_MISC_IE" => { type => "reg", addr => 0x4ac34, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4ac34, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IS" => { type => "reg", addr => 0x4ac38, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE3_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE3_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE3_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE3_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE3_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE3_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE3_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4ac38, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE3_SR_WR_INDEX" => { type => "reg", addr => 0x4ac3c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_SR_WR_INDEX.V" => { type => "field", addr => 0x4ac3c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_DST_WR_INDEX" => { type => "reg", addr => 0x4ac40, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_DST_WR_INDEX.V" => { type => "field", addr => 0x4ac40, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_CURRENT_SRRI" => { type => "reg", addr => 0x4ac44, width => 32, athEmulAttr => 0, acc => "RO" }, "CE3_CURRENT_SRRI.V" => { type => "field", addr => 0x4ac44, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE3_CURRENT_DRRI" => { type => "reg", addr => 0x4ac48, width => 32, athEmulAttr => 0, acc => "RO" }, "CE3_CURRENT_DRRI.V" => { type => "field", addr => 0x4ac48, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE3_SRC_WATERMARK" => { type => "reg", addr => 0x4ac4c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4ac4c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4ac4c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_DST_WATERMARK" => { type => "reg", addr => 0x4ac50, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_DST_WATERMARK.LOW" => { type => "field", addr => 0x4ac50, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4ac50, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_CE_DEBUG" => { type => "reg", addr => 0x4ac54, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_CE_DEBUG.SEL" => { type => "field", addr => 0x4ac54, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE3_CE_WATCHDOG" => { type => "reg", addr => 0x4ac58, width => 32, athEmulAttr => 0, acc => "RW" }, "CE3_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4ac58, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE3_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4ac58, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_4 Register/Field definitions ################################################################### "CE4_SR_BA" => { type => "reg", addr => 0x4b000, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_SR_BA.V" => { type => "field", addr => 0x4b000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_SR_SIZE" => { type => "reg", addr => 0x4b004, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_SR_SIZE.V" => { type => "field", addr => 0x4b004, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_DR_BA" => { type => "reg", addr => 0x4b008, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_DR_BA.V" => { type => "field", addr => 0x4b008, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_DR_SIZE" => { type => "reg", addr => 0x4b00c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_DR_SIZE.V" => { type => "field", addr => 0x4b00c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_CE_CTRL1" => { type => "reg", addr => 0x4b010, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4b010, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4b010, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4b010, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4b010, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE4_CE_CTRL2" => { type => "reg", addr => 0x4b014, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4b014, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE4_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4b014, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE4_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4b014, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE4_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4b014, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE4_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4b014, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE4_CE_CMD" => { type => "reg", addr => 0x4b018, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4b018, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE4_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4b018, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4b018, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_CE_CMD.HALT" => { type => "field", addr => 0x4b018, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MSI_ADDR" => { type => "reg", addr => 0x4b01c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_MSI_ADDR.V" => { type => "field", addr => 0x4b01c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MSI_DATA" => { type => "reg", addr => 0x4b020, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_MSI_DATA.V" => { type => "field", addr => 0x4b020, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_TARGET_IE" => { type => "reg", addr => 0x4b024, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b024, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b024, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b024, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b024, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4b024, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_TARGET_IS" => { type => "reg", addr => 0x4b028, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE4_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b028, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b028, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b028, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b028, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4b028, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE4_HOST_IE" => { type => "reg", addr => 0x4b02c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b02c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b02c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b02c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b02c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4b02c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_HOST_IS" => { type => "reg", addr => 0x4b030, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE4_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b030, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b030, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b030, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b030, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4b030, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE4_MISC_IE" => { type => "reg", addr => 0x4b034, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4b034, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IS" => { type => "reg", addr => 0x4b038, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE4_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE4_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE4_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE4_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE4_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE4_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE4_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4b038, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE4_SR_WR_INDEX" => { type => "reg", addr => 0x4b03c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_SR_WR_INDEX.V" => { type => "field", addr => 0x4b03c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_DST_WR_INDEX" => { type => "reg", addr => 0x4b040, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_DST_WR_INDEX.V" => { type => "field", addr => 0x4b040, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_CURRENT_SRRI" => { type => "reg", addr => 0x4b044, width => 32, athEmulAttr => 0, acc => "RO" }, "CE4_CURRENT_SRRI.V" => { type => "field", addr => 0x4b044, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE4_CURRENT_DRRI" => { type => "reg", addr => 0x4b048, width => 32, athEmulAttr => 0, acc => "RO" }, "CE4_CURRENT_DRRI.V" => { type => "field", addr => 0x4b048, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE4_SRC_WATERMARK" => { type => "reg", addr => 0x4b04c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4b04c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4b04c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_DST_WATERMARK" => { type => "reg", addr => 0x4b050, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_DST_WATERMARK.LOW" => { type => "field", addr => 0x4b050, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4b050, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_CE_DEBUG" => { type => "reg", addr => 0x4b054, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_CE_DEBUG.SEL" => { type => "field", addr => 0x4b054, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE4_CE_WATCHDOG" => { type => "reg", addr => 0x4b058, width => 32, athEmulAttr => 0, acc => "RW" }, "CE4_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4b058, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE4_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4b058, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_5 Register/Field definitions ################################################################### "CE5_SR_BA" => { type => "reg", addr => 0x4b400, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_SR_BA.V" => { type => "field", addr => 0x4b400, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_SR_SIZE" => { type => "reg", addr => 0x4b404, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_SR_SIZE.V" => { type => "field", addr => 0x4b404, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_DR_BA" => { type => "reg", addr => 0x4b408, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_DR_BA.V" => { type => "field", addr => 0x4b408, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_DR_SIZE" => { type => "reg", addr => 0x4b40c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_DR_SIZE.V" => { type => "field", addr => 0x4b40c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_CE_CTRL1" => { type => "reg", addr => 0x4b410, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4b410, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4b410, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4b410, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4b410, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE5_CE_CTRL2" => { type => "reg", addr => 0x4b414, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4b414, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE5_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4b414, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE5_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4b414, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE5_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4b414, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE5_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4b414, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE5_CE_CMD" => { type => "reg", addr => 0x4b418, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4b418, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE5_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4b418, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4b418, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_CE_CMD.HALT" => { type => "field", addr => 0x4b418, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MSI_ADDR" => { type => "reg", addr => 0x4b41c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_MSI_ADDR.V" => { type => "field", addr => 0x4b41c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MSI_DATA" => { type => "reg", addr => 0x4b420, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_MSI_DATA.V" => { type => "field", addr => 0x4b420, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_TARGET_IE" => { type => "reg", addr => 0x4b424, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b424, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b424, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b424, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b424, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4b424, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_TARGET_IS" => { type => "reg", addr => 0x4b428, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE5_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b428, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b428, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b428, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b428, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4b428, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE5_HOST_IE" => { type => "reg", addr => 0x4b42c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b42c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b42c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b42c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b42c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4b42c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_HOST_IS" => { type => "reg", addr => 0x4b430, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE5_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b430, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b430, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b430, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b430, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4b430, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE5_MISC_IE" => { type => "reg", addr => 0x4b434, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4b434, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IS" => { type => "reg", addr => 0x4b438, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE5_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE5_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE5_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE5_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE5_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE5_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE5_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4b438, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE5_SR_WR_INDEX" => { type => "reg", addr => 0x4b43c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_SR_WR_INDEX.V" => { type => "field", addr => 0x4b43c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_DST_WR_INDEX" => { type => "reg", addr => 0x4b440, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_DST_WR_INDEX.V" => { type => "field", addr => 0x4b440, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_CURRENT_SRRI" => { type => "reg", addr => 0x4b444, width => 32, athEmulAttr => 0, acc => "RO" }, "CE5_CURRENT_SRRI.V" => { type => "field", addr => 0x4b444, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE5_CURRENT_DRRI" => { type => "reg", addr => 0x4b448, width => 32, athEmulAttr => 0, acc => "RO" }, "CE5_CURRENT_DRRI.V" => { type => "field", addr => 0x4b448, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE5_SRC_WATERMARK" => { type => "reg", addr => 0x4b44c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4b44c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4b44c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_DST_WATERMARK" => { type => "reg", addr => 0x4b450, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_DST_WATERMARK.LOW" => { type => "field", addr => 0x4b450, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4b450, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_CE_DEBUG" => { type => "reg", addr => 0x4b454, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_CE_DEBUG.SEL" => { type => "field", addr => 0x4b454, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE5_CE_WATCHDOG" => { type => "reg", addr => 0x4b458, width => 32, athEmulAttr => 0, acc => "RW" }, "CE5_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4b458, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE5_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4b458, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_6 Register/Field definitions ################################################################### "CE6_SR_BA" => { type => "reg", addr => 0x4b800, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_SR_BA.V" => { type => "field", addr => 0x4b800, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_SR_SIZE" => { type => "reg", addr => 0x4b804, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_SR_SIZE.V" => { type => "field", addr => 0x4b804, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_DR_BA" => { type => "reg", addr => 0x4b808, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_DR_BA.V" => { type => "field", addr => 0x4b808, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_DR_SIZE" => { type => "reg", addr => 0x4b80c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_DR_SIZE.V" => { type => "field", addr => 0x4b80c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_CE_CTRL1" => { type => "reg", addr => 0x4b810, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4b810, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4b810, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4b810, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4b810, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE6_CE_CTRL2" => { type => "reg", addr => 0x4b814, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4b814, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE6_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4b814, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE6_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4b814, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE6_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4b814, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE6_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4b814, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE6_CE_CMD" => { type => "reg", addr => 0x4b818, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4b818, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE6_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4b818, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4b818, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_CE_CMD.HALT" => { type => "field", addr => 0x4b818, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MSI_ADDR" => { type => "reg", addr => 0x4b81c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_MSI_ADDR.V" => { type => "field", addr => 0x4b81c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MSI_DATA" => { type => "reg", addr => 0x4b820, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_MSI_DATA.V" => { type => "field", addr => 0x4b820, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_TARGET_IE" => { type => "reg", addr => 0x4b824, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b824, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b824, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b824, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b824, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4b824, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_TARGET_IS" => { type => "reg", addr => 0x4b828, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE6_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b828, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b828, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b828, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b828, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4b828, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE6_HOST_IE" => { type => "reg", addr => 0x4b82c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b82c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b82c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b82c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b82c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4b82c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_HOST_IS" => { type => "reg", addr => 0x4b830, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE6_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b830, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b830, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b830, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b830, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4b830, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE6_MISC_IE" => { type => "reg", addr => 0x4b834, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4b834, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IS" => { type => "reg", addr => 0x4b838, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE6_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE6_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE6_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE6_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE6_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE6_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE6_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4b838, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE6_SR_WR_INDEX" => { type => "reg", addr => 0x4b83c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_SR_WR_INDEX.V" => { type => "field", addr => 0x4b83c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_DST_WR_INDEX" => { type => "reg", addr => 0x4b840, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_DST_WR_INDEX.V" => { type => "field", addr => 0x4b840, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_CURRENT_SRRI" => { type => "reg", addr => 0x4b844, width => 32, athEmulAttr => 0, acc => "RO" }, "CE6_CURRENT_SRRI.V" => { type => "field", addr => 0x4b844, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE6_CURRENT_DRRI" => { type => "reg", addr => 0x4b848, width => 32, athEmulAttr => 0, acc => "RO" }, "CE6_CURRENT_DRRI.V" => { type => "field", addr => 0x4b848, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE6_SRC_WATERMARK" => { type => "reg", addr => 0x4b84c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4b84c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4b84c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_DST_WATERMARK" => { type => "reg", addr => 0x4b850, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_DST_WATERMARK.LOW" => { type => "field", addr => 0x4b850, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4b850, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_CE_DEBUG" => { type => "reg", addr => 0x4b854, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_CE_DEBUG.SEL" => { type => "field", addr => 0x4b854, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE6_CE_WATCHDOG" => { type => "reg", addr => 0x4b858, width => 32, athEmulAttr => 0, acc => "RW" }, "CE6_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4b858, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE6_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4b858, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_7 Register/Field definitions ################################################################### "CE7_SR_BA" => { type => "reg", addr => 0x4bc00, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_SR_BA.V" => { type => "field", addr => 0x4bc00, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_SR_SIZE" => { type => "reg", addr => 0x4bc04, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_SR_SIZE.V" => { type => "field", addr => 0x4bc04, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_DR_BA" => { type => "reg", addr => 0x4bc08, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_DR_BA.V" => { type => "field", addr => 0x4bc08, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_DR_SIZE" => { type => "reg", addr => 0x4bc0c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_DR_SIZE.V" => { type => "field", addr => 0x4bc0c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_CE_CTRL1" => { type => "reg", addr => 0x4bc10, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4bc10, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4bc10, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4bc10, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4bc10, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE7_CE_CTRL2" => { type => "reg", addr => 0x4bc14, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4bc14, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE7_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4bc14, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE7_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4bc14, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE7_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4bc14, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE7_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4bc14, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE7_CE_CMD" => { type => "reg", addr => 0x4bc18, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4bc18, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE7_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4bc18, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4bc18, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_CE_CMD.HALT" => { type => "field", addr => 0x4bc18, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MSI_ADDR" => { type => "reg", addr => 0x4bc1c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_MSI_ADDR.V" => { type => "field", addr => 0x4bc1c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MSI_DATA" => { type => "reg", addr => 0x4bc20, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_MSI_DATA.V" => { type => "field", addr => 0x4bc20, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_TARGET_IE" => { type => "reg", addr => 0x4bc24, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc24, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc24, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc24, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc24, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4bc24, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_TARGET_IS" => { type => "reg", addr => 0x4bc28, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE7_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc28, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc28, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc28, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc28, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4bc28, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE7_HOST_IE" => { type => "reg", addr => 0x4bc2c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc2c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc2c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc2c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc2c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4bc2c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_HOST_IS" => { type => "reg", addr => 0x4bc30, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE7_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc30, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc30, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc30, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc30, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4bc30, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE7_MISC_IE" => { type => "reg", addr => 0x4bc34, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4bc34, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IS" => { type => "reg", addr => 0x4bc38, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE7_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE7_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE7_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE7_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE7_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE7_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE7_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4bc38, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE7_SR_WR_INDEX" => { type => "reg", addr => 0x4bc3c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_SR_WR_INDEX.V" => { type => "field", addr => 0x4bc3c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_DST_WR_INDEX" => { type => "reg", addr => 0x4bc40, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_DST_WR_INDEX.V" => { type => "field", addr => 0x4bc40, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_CURRENT_SRRI" => { type => "reg", addr => 0x4bc44, width => 32, athEmulAttr => 0, acc => "RO" }, "CE7_CURRENT_SRRI.V" => { type => "field", addr => 0x4bc44, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE7_CURRENT_DRRI" => { type => "reg", addr => 0x4bc48, width => 32, athEmulAttr => 0, acc => "RO" }, "CE7_CURRENT_DRRI.V" => { type => "field", addr => 0x4bc48, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE7_SRC_WATERMARK" => { type => "reg", addr => 0x4bc4c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4bc4c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4bc4c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_DST_WATERMARK" => { type => "reg", addr => 0x4bc50, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_DST_WATERMARK.LOW" => { type => "field", addr => 0x4bc50, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4bc50, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_CE_DEBUG" => { type => "reg", addr => 0x4bc54, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_CE_DEBUG.SEL" => { type => "field", addr => 0x4bc54, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE7_CE_WATCHDOG" => { type => "reg", addr => 0x4bc58, width => 32, athEmulAttr => 0, acc => "RW" }, "CE7_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4bc58, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE7_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4bc58, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_8 Register/Field definitions ################################################################### "CE8_SR_BA" => { type => "reg", addr => 0x4c000, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_SR_BA.V" => { type => "field", addr => 0x4c000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_SR_SIZE" => { type => "reg", addr => 0x4c004, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_SR_SIZE.V" => { type => "field", addr => 0x4c004, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_DR_BA" => { type => "reg", addr => 0x4c008, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_DR_BA.V" => { type => "field", addr => 0x4c008, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_DR_SIZE" => { type => "reg", addr => 0x4c00c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_DR_SIZE.V" => { type => "field", addr => 0x4c00c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_CE_CTRL1" => { type => "reg", addr => 0x4c010, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4c010, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4c010, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4c010, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4c010, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE8_CE_CTRL2" => { type => "reg", addr => 0x4c014, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4c014, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE8_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4c014, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE8_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4c014, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE8_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4c014, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE8_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4c014, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE8_CE_CMD" => { type => "reg", addr => 0x4c018, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4c018, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE8_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4c018, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4c018, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_CE_CMD.HALT" => { type => "field", addr => 0x4c018, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MSI_ADDR" => { type => "reg", addr => 0x4c01c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_MSI_ADDR.V" => { type => "field", addr => 0x4c01c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MSI_DATA" => { type => "reg", addr => 0x4c020, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_MSI_DATA.V" => { type => "field", addr => 0x4c020, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_TARGET_IE" => { type => "reg", addr => 0x4c024, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c024, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c024, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c024, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c024, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4c024, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_TARGET_IS" => { type => "reg", addr => 0x4c028, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE8_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c028, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c028, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c028, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c028, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4c028, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE8_HOST_IE" => { type => "reg", addr => 0x4c02c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c02c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c02c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c02c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c02c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4c02c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_HOST_IS" => { type => "reg", addr => 0x4c030, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE8_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c030, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c030, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c030, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c030, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4c030, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE8_MISC_IE" => { type => "reg", addr => 0x4c034, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4c034, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IS" => { type => "reg", addr => 0x4c038, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE8_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE8_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE8_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE8_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE8_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE8_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE8_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4c038, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE8_SR_WR_INDEX" => { type => "reg", addr => 0x4c03c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_SR_WR_INDEX.V" => { type => "field", addr => 0x4c03c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_DST_WR_INDEX" => { type => "reg", addr => 0x4c040, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_DST_WR_INDEX.V" => { type => "field", addr => 0x4c040, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_CURRENT_SRRI" => { type => "reg", addr => 0x4c044, width => 32, athEmulAttr => 0, acc => "RO" }, "CE8_CURRENT_SRRI.V" => { type => "field", addr => 0x4c044, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE8_CURRENT_DRRI" => { type => "reg", addr => 0x4c048, width => 32, athEmulAttr => 0, acc => "RO" }, "CE8_CURRENT_DRRI.V" => { type => "field", addr => 0x4c048, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE8_SRC_WATERMARK" => { type => "reg", addr => 0x4c04c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4c04c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4c04c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_DST_WATERMARK" => { type => "reg", addr => 0x4c050, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_DST_WATERMARK.LOW" => { type => "field", addr => 0x4c050, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4c050, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_CE_DEBUG" => { type => "reg", addr => 0x4c054, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_CE_DEBUG.SEL" => { type => "field", addr => 0x4c054, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE8_CE_WATCHDOG" => { type => "reg", addr => 0x4c058, width => 32, athEmulAttr => 0, acc => "RW" }, "CE8_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4c058, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE8_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4c058, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_9 Register/Field definitions ################################################################### "CE9_SR_BA" => { type => "reg", addr => 0x4c400, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_SR_BA.V" => { type => "field", addr => 0x4c400, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_SR_SIZE" => { type => "reg", addr => 0x4c404, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_SR_SIZE.V" => { type => "field", addr => 0x4c404, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_DR_BA" => { type => "reg", addr => 0x4c408, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_DR_BA.V" => { type => "field", addr => 0x4c408, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_DR_SIZE" => { type => "reg", addr => 0x4c40c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_DR_SIZE.V" => { type => "field", addr => 0x4c40c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_CE_CTRL1" => { type => "reg", addr => 0x4c410, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4c410, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4c410, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4c410, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4c410, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE9_CE_CTRL2" => { type => "reg", addr => 0x4c414, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4c414, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE9_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4c414, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE9_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4c414, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE9_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4c414, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE9_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4c414, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE9_CE_CMD" => { type => "reg", addr => 0x4c418, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4c418, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE9_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4c418, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4c418, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_CE_CMD.HALT" => { type => "field", addr => 0x4c418, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MSI_ADDR" => { type => "reg", addr => 0x4c41c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_MSI_ADDR.V" => { type => "field", addr => 0x4c41c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MSI_DATA" => { type => "reg", addr => 0x4c420, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_MSI_DATA.V" => { type => "field", addr => 0x4c420, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_TARGET_IE" => { type => "reg", addr => 0x4c424, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c424, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c424, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c424, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c424, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4c424, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_TARGET_IS" => { type => "reg", addr => 0x4c428, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE9_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c428, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c428, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c428, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c428, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4c428, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE9_HOST_IE" => { type => "reg", addr => 0x4c42c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c42c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c42c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c42c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c42c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4c42c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_HOST_IS" => { type => "reg", addr => 0x4c430, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE9_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c430, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c430, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c430, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c430, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4c430, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE9_MISC_IE" => { type => "reg", addr => 0x4c434, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4c434, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IS" => { type => "reg", addr => 0x4c438, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE9_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE9_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE9_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE9_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE9_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE9_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE9_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4c438, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE9_SR_WR_INDEX" => { type => "reg", addr => 0x4c43c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_SR_WR_INDEX.V" => { type => "field", addr => 0x4c43c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_DST_WR_INDEX" => { type => "reg", addr => 0x4c440, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_DST_WR_INDEX.V" => { type => "field", addr => 0x4c440, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_CURRENT_SRRI" => { type => "reg", addr => 0x4c444, width => 32, athEmulAttr => 0, acc => "RO" }, "CE9_CURRENT_SRRI.V" => { type => "field", addr => 0x4c444, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE9_CURRENT_DRRI" => { type => "reg", addr => 0x4c448, width => 32, athEmulAttr => 0, acc => "RO" }, "CE9_CURRENT_DRRI.V" => { type => "field", addr => 0x4c448, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE9_SRC_WATERMARK" => { type => "reg", addr => 0x4c44c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4c44c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4c44c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_DST_WATERMARK" => { type => "reg", addr => 0x4c450, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_DST_WATERMARK.LOW" => { type => "field", addr => 0x4c450, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4c450, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_CE_DEBUG" => { type => "reg", addr => 0x4c454, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_CE_DEBUG.SEL" => { type => "field", addr => 0x4c454, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE9_CE_WATCHDOG" => { type => "reg", addr => 0x4c458, width => 32, athEmulAttr => 0, acc => "RW" }, "CE9_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4c458, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE9_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4c458, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_10 Register/Field definitions ################################################################### "CE10_SR_BA" => { type => "reg", addr => 0x4c800, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_SR_BA.V" => { type => "field", addr => 0x4c800, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_SR_SIZE" => { type => "reg", addr => 0x4c804, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_SR_SIZE.V" => { type => "field", addr => 0x4c804, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_DR_BA" => { type => "reg", addr => 0x4c808, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_DR_BA.V" => { type => "field", addr => 0x4c808, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_DR_SIZE" => { type => "reg", addr => 0x4c80c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_DR_SIZE.V" => { type => "field", addr => 0x4c80c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_CE_CTRL1" => { type => "reg", addr => 0x4c810, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4c810, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4c810, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4c810, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4c810, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE10_CE_CTRL2" => { type => "reg", addr => 0x4c814, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4c814, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE10_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4c814, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE10_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4c814, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE10_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4c814, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE10_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4c814, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE10_CE_CMD" => { type => "reg", addr => 0x4c818, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4c818, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE10_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4c818, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4c818, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_CE_CMD.HALT" => { type => "field", addr => 0x4c818, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MSI_ADDR" => { type => "reg", addr => 0x4c81c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_MSI_ADDR.V" => { type => "field", addr => 0x4c81c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MSI_DATA" => { type => "reg", addr => 0x4c820, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_MSI_DATA.V" => { type => "field", addr => 0x4c820, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_TARGET_IE" => { type => "reg", addr => 0x4c824, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c824, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c824, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c824, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c824, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4c824, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_TARGET_IS" => { type => "reg", addr => 0x4c828, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE10_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c828, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c828, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c828, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c828, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4c828, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE10_HOST_IE" => { type => "reg", addr => 0x4c82c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c82c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c82c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c82c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c82c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4c82c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_HOST_IS" => { type => "reg", addr => 0x4c830, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE10_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c830, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c830, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c830, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c830, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4c830, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE10_MISC_IE" => { type => "reg", addr => 0x4c834, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4c834, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IS" => { type => "reg", addr => 0x4c838, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE10_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE10_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE10_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE10_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE10_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE10_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE10_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4c838, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE10_SR_WR_INDEX" => { type => "reg", addr => 0x4c83c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_SR_WR_INDEX.V" => { type => "field", addr => 0x4c83c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_DST_WR_INDEX" => { type => "reg", addr => 0x4c840, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_DST_WR_INDEX.V" => { type => "field", addr => 0x4c840, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_CURRENT_SRRI" => { type => "reg", addr => 0x4c844, width => 32, athEmulAttr => 0, acc => "RO" }, "CE10_CURRENT_SRRI.V" => { type => "field", addr => 0x4c844, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE10_CURRENT_DRRI" => { type => "reg", addr => 0x4c848, width => 32, athEmulAttr => 0, acc => "RO" }, "CE10_CURRENT_DRRI.V" => { type => "field", addr => 0x4c848, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE10_SRC_WATERMARK" => { type => "reg", addr => 0x4c84c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4c84c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4c84c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_DST_WATERMARK" => { type => "reg", addr => 0x4c850, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_DST_WATERMARK.LOW" => { type => "field", addr => 0x4c850, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4c850, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_CE_DEBUG" => { type => "reg", addr => 0x4c854, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_CE_DEBUG.SEL" => { type => "field", addr => 0x4c854, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE10_CE_WATCHDOG" => { type => "reg", addr => 0x4c858, width => 32, athEmulAttr => 0, acc => "RW" }, "CE10_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4c858, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE10_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4c858, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_reg_csr_11 Register/Field definitions ################################################################### "CE11_SR_BA" => { type => "reg", addr => 0x4cc00, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_SR_BA.V" => { type => "field", addr => 0x4cc00, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_SR_SIZE" => { type => "reg", addr => 0x4cc04, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_SR_SIZE.V" => { type => "field", addr => 0x4cc04, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_DR_BA" => { type => "reg", addr => 0x4cc08, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_DR_BA.V" => { type => "field", addr => 0x4cc08, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_DR_SIZE" => { type => "reg", addr => 0x4cc0c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_DR_SIZE.V" => { type => "field", addr => 0x4cc0c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_CE_CTRL1" => { type => "reg", addr => 0x4cc10, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_CE_CTRL1.MSI_EN" => { type => "field", addr => 0x4cc10, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_CE_CTRL1.DST_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4cc10, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_CE_CTRL1.SRC_RING_BYTE_SWAP_EN" => { type => "field", addr => 0x4cc10, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_CE_CTRL1.DMAX_LENGTH" => { type => "field", addr => 0x4cc10, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x80 }, "CE11_CE_CTRL2" => { type => "reg", addr => 0x4cc14, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_CE_CTRL2.NUM_AXI_OUTSTANDING_WRITES" => { type => "field", addr => 0x4cc14, width => 5, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "CE11_CE_CTRL2.NUM_AXI_OUTSTANDING_READS" => { type => "field", addr => 0x4cc14, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE11_CE_CTRL2.AXI_TIMEOUT" => { type => "field", addr => 0x4cc14, width => 16, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x1F40 }, "CE11_CE_CTRL2.DEST_AXI_MAX_LEN" => { type => "field", addr => 0x4cc14, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE11_CE_CTRL2.SRC_AXI_MAX_LEN" => { type => "field", addr => 0x4cc14, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CE11_CE_CMD" => { type => "reg", addr => 0x4cc18, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_CE_CMD.HALT_STATUS" => { type => "field", addr => 0x4cc18, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE11_CE_CMD.DST_FLUSH" => { type => "field", addr => 0x4cc18, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_CE_CMD.SRC_FLUSH" => { type => "field", addr => 0x4cc18, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_CE_CMD.HALT" => { type => "field", addr => 0x4cc18, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MSI_ADDR" => { type => "reg", addr => 0x4cc1c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_MSI_ADDR.V" => { type => "field", addr => 0x4cc1c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MSI_DATA" => { type => "reg", addr => 0x4cc20, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_MSI_DATA.V" => { type => "field", addr => 0x4cc20, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_TARGET_IE" => { type => "reg", addr => 0x4cc24, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_TARGET_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc24, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_TARGET_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc24, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_TARGET_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc24, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_TARGET_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc24, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_TARGET_IE.COPY_COMPLETE" => { type => "field", addr => 0x4cc24, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_TARGET_IS" => { type => "reg", addr => 0x4cc28, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE11_TARGET_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc28, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_TARGET_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc28, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_TARGET_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc28, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_TARGET_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc28, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_TARGET_IS.COPY_COMPLETE" => { type => "field", addr => 0x4cc28, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE11_HOST_IE" => { type => "reg", addr => 0x4cc2c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_HOST_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc2c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_HOST_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc2c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_HOST_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc2c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_HOST_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc2c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_HOST_IE.COPY_COMPLETE" => { type => "field", addr => 0x4cc2c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_HOST_IS" => { type => "reg", addr => 0x4cc30, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE11_HOST_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc30, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_HOST_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc30, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_HOST_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc30, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_HOST_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc30, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_HOST_IS.COPY_COMPLETE" => { type => "field", addr => 0x4cc30, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE11_MISC_IE" => { type => "reg", addr => 0x4cc34, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_MISC_IE.AXI_ERR" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IE.DST_ADDR_ERR" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IE.SRC_LEN_ERR" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IE.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IE.DST_RING_OVERFLOW" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IE.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IE.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IE.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IE.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IE.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IE.COPY_COMPLETE" => { type => "field", addr => 0x4cc34, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IS" => { type => "reg", addr => 0x4cc38, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE11_MISC_IS.AXI_ERR" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE11_MISC_IS.DST_ADDR_ERR" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE11_MISC_IS.SRC_LEN_ERR" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE11_MISC_IS.DST_MAX_LEN_VIO" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE11_MISC_IS.DST_RING_OVERFLOW" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE11_MISC_IS.SRC_RING_OVERFLOW" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE11_MISC_IS.DST_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IS.DST_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IS.SRC_RING_LOW_WATERMARK" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IS.SRC_RING_HIGH_WATERMARK" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_MISC_IS.COPY_COMPLETE" => { type => "field", addr => 0x4cc38, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE11_SR_WR_INDEX" => { type => "reg", addr => 0x4cc3c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_SR_WR_INDEX.V" => { type => "field", addr => 0x4cc3c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_DST_WR_INDEX" => { type => "reg", addr => 0x4cc40, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_DST_WR_INDEX.V" => { type => "field", addr => 0x4cc40, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_CURRENT_SRRI" => { type => "reg", addr => 0x4cc44, width => 32, athEmulAttr => 0, acc => "RO" }, "CE11_CURRENT_SRRI.V" => { type => "field", addr => 0x4cc44, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE11_CURRENT_DRRI" => { type => "reg", addr => 0x4cc48, width => 32, athEmulAttr => 0, acc => "RO" }, "CE11_CURRENT_DRRI.V" => { type => "field", addr => 0x4cc48, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE11_SRC_WATERMARK" => { type => "reg", addr => 0x4cc4c, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_SRC_WATERMARK.LOW" => { type => "field", addr => 0x4cc4c, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_SRC_WATERMARK.HIGH" => { type => "field", addr => 0x4cc4c, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_DST_WATERMARK" => { type => "reg", addr => 0x4cc50, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_DST_WATERMARK.LOW" => { type => "field", addr => 0x4cc50, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_DST_WATERMARK.HIGH" => { type => "field", addr => 0x4cc50, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_CE_DEBUG" => { type => "reg", addr => 0x4cc54, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_CE_DEBUG.SEL" => { type => "field", addr => 0x4cc54, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE11_CE_WATCHDOG" => { type => "reg", addr => 0x4cc58, width => 32, athEmulAttr => 0, acc => "RW" }, "CE11_CE_WATCHDOG.STATUS" => { type => "field", addr => 0x4cc58, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE11_CE_WATCHDOG.LIMIT" => { type => "field", addr => 0x4cc58, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0xFFFF }, ################################################################### ## ce_wrapper_reg_csr Register/Field definitions ################################################################### "CE_WRAPPER_INTERRUPT_SUMMARY" => { type => "reg", addr => 0x4d000, width => 32, athEmulAttr => 0, acc => "RO" }, "CE_WRAPPER_INTERRUPT_SUMMARY.HOST_MSI" => { type => "field", addr => 0x4d000, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "CE_WRAPPER_INTERRUPT_SUMMARY.MISC" => { type => "field", addr => 0x4d000, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "NUM_AXI_OUTSTANDING" => { type => "reg", addr => 0x4d004, width => 32, athEmulAttr => 0, acc => "RW" }, "NUM_AXI_OUTSTANDING.WRITES" => { type => "field", addr => 0x4d004, width => 5, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "NUM_AXI_OUTSTANDING.READS" => { type => "field", addr => 0x4d004, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x18 }, "CE_WRAPPER_DEBUG" => { type => "reg", addr => 0x4d008, width => 32, athEmulAttr => 0, acc => "RW" }, "CE_WRAPPER_DEBUG.SEL" => { type => "field", addr => 0x4d008, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CPU_MEM_ADDR" => { type => "reg", addr => 0x4d00c, width => 32, athEmulAttr => 0, acc => "RW" }, "CPU_MEM_ADDR.VAL" => { type => "field", addr => 0x4d00c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CPU_MEM_DATA" => { type => "reg", addr => 0x4d010, width => 32, athEmulAttr => 0, acc => "RW" }, "CPU_MEM_DATA.VAL" => { type => "field", addr => 0x4d010, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CE_WRAPPER_WDG_TMR_IS" => { type => "reg", addr => 0x4d014, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "CE_WRAPPER_WDG_TMR_IS.VAL" => { type => "field", addr => 0x4d014, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "CE_WRAPPER_WDG_TMR_IE" => { type => "reg", addr => 0x4d018, width => 32, athEmulAttr => 0, acc => "RW" }, "CE_WRAPPER_WDG_TMR_IE.VAL" => { type => "field", addr => 0x4d018, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## rffe_m_csr Register/Field definitions ################################################################### "rffe_inte" => { type => "reg", addr => 0x50000, width => 32, athEmulAttr => 0, acc => "RW" }, "rffe_inte.rffe_inte_err" => { type => "field", addr => 0x50000, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_inte.rffe_inte_done" => { type => "field", addr => 0x50000, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_intf" => { type => "reg", addr => 0x50004, width => 32, athEmulAttr => 0, acc => "RW" }, "rffe_intf.rffe_intf_err" => { type => "field", addr => 0x50004, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_intf.rffe_intf_done" => { type => "field", addr => 0x50004, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_stat" => { type => "reg", addr => 0x50008, width => 32, athEmulAttr => 0, acc => "RO" }, "rffe_stat.rffe_stat_perr3" => { type => "field", addr => 0x50008, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "rffe_stat.rffe_stat_perr2" => { type => "field", addr => 0x50008, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "rffe_stat.rffe_stat_perr1" => { type => "field", addr => 0x50008, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "rffe_stat.rffe_stat_perr0" => { type => "field", addr => 0x50008, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "rffe_stat.rffe_cfg_gpio_sdata_in" => { type => "field", addr => 0x50008, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "rffe_stat.rffe_stat_act" => { type => "field", addr => 0x50008, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "rffe_cfg" => { type => "reg", addr => 0x5000c, width => 32, athEmulAttr => 0, acc => "RW" }, "rffe_cfg.rffe_cfg_spare0" => { type => "field", addr => 0x5000c, width => 6, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_cfg.rffe_cfg_sw_reset" => { type => "field", addr => 0x5000c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_cfg.rffe_cfg_divider" => { type => "field", addr => 0x5000c, width => 5, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "rffe_cfg.rffe_cfg_gpio_sclk_out" => { type => "field", addr => 0x5000c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_cfg.rffe_cfg_gpio_sdata_out" => { type => "field", addr => 0x5000c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_cfg.rffe_cfg_gpio_sdata_oe" => { type => "field", addr => 0x5000c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_cfg.rffe_cfg_gpio_mode" => { type => "field", addr => 0x5000c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_ctrl" => { type => "reg", addr => 0x50010, width => 32, athEmulAttr => 0, acc => "RW" }, "rffe_ctrl.rffe_ctrl_autox" => { type => "field", addr => 0x50010, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_ctrl.rffe_ctrl_cmd" => { type => "field", addr => 0x50010, width => 2, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_ctrl.rffe_ctrl_rbhrate" => { type => "field", addr => 0x50010, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_ctrl.rffe_ctrl_sid" => { type => "field", addr => 0x50010, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_ctrl.rffe_ctrl_xcnt" => { type => "field", addr => 0x50010, width => 2, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_ctrl.rffe_ctrl_mode" => { type => "field", addr => 0x50010, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_ctrl.rffe_ctrl_addr16" => { type => "field", addr => 0x50010, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "rffe_data" => { type => "reg", addr => 0x50014, width => 32, athEmulAttr => 0, acc => "RW" }, "rffe_data.rffe_data" => { type => "field", addr => 0x50014, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## rtc_soc_reg Register/Field definitions ################################################################### "SOC_RESET_CONTROL" => { type => "reg", addr => 0x80000, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_RESET_CONTROL.PCIE_PHY_SRESET" => { type => "field", addr => 0x80000, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RESET_CONTROL.PCIE_DIG_RST" => { type => "field", addr => 0x80000, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RESET_CONTROL.CPU_INIT_RESET" => { type => "field", addr => 0x80000, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SOC_RESET_CONTROL.COLD_RST" => { type => "field", addr => 0x80000, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RESET_CONTROL.CPU_WARM_RST" => { type => "field", addr => 0x80000, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RESET_CONTROL.PCIE_RST_SHORT_OVRD" => { type => "field", addr => 0x80000, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RESET_CONTROL.UART_RST" => { type => "field", addr => 0x80000, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RESET_CONTROL.SI0_RST" => { type => "field", addr => 0x80000, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_CPU_CLOCK" => { type => "reg", addr => 0x80020, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_CPU_CLOCK.STANDARD" => { type => "field", addr => 0x80020, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SOC_CLOCK_CONTROL" => { type => "reg", addr => 0x80028, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_CLOCK_CONTROL.SI0_CLK" => { type => "field", addr => 0x80028, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SOC_INT_STATUS" => { type => "reg", addr => 0x8002c, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "SOC_INT_STATUS.THERM" => { type => "field", addr => 0x8002c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0 }, "SOC_INT_STATUS.EFUSE_OVERWRITE" => { type => "field", addr => 0x8002c, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_INT_STATUS.RTC_POWER" => { type => "field", addr => 0x8002c, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_INT_STATUS.RTC_ALARM" => { type => "field", addr => 0x8002c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_INT_STATUS.SI" => { type => "field", addr => 0x8002c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_INT_STATUS.GPIO" => { type => "field", addr => 0x8002c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_INT_STATUS.ERROR" => { type => "field", addr => 0x8002c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_RTC_CONTROL" => { type => "reg", addr => 0x80030, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_RTC_CONTROL.ENABLE" => { type => "field", addr => 0x80030, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_CONTROL.LOAD_RTC" => { type => "field", addr => 0x80030, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_CONTROL.LOAD_ALARM" => { type => "field", addr => 0x80030, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_TIME" => { type => "reg", addr => 0x80034, width => 32, athEmulAttr => 0, acc => "RO" }, "SOC_RTC_TIME.WEEK_DAY" => { type => "field", addr => 0x80034, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 1 }, "SOC_RTC_TIME.HOUR" => { type => "field", addr => 0x80034, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 18 }, "SOC_RTC_TIME.MINUTE" => { type => "field", addr => 0x80034, width => 7, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_RTC_TIME.SECOND" => { type => "field", addr => 0x80034, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_RTC_DATE" => { type => "reg", addr => 0x80038, width => 32, athEmulAttr => 0, acc => "RO" }, "SOC_RTC_DATE.YEAR" => { type => "field", addr => 0x80038, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_RTC_DATE.MONTH" => { type => "field", addr => 0x80038, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 1 }, "SOC_RTC_DATE.MONTH_DAY" => { type => "field", addr => 0x80038, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 1 }, "SOC_RTC_SET_TIME" => { type => "reg", addr => 0x8003c, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_RTC_SET_TIME.WEEK_DAY" => { type => "field", addr => 0x8003c, width => 3, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SOC_RTC_SET_TIME.HOUR" => { type => "field", addr => 0x8003c, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_SET_TIME.MINUTE" => { type => "field", addr => 0x8003c, width => 7, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_SET_TIME.SECOND" => { type => "field", addr => 0x8003c, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_SET_DATE" => { type => "reg", addr => 0x80040, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_RTC_SET_DATE.YEAR" => { type => "field", addr => 0x80040, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_SET_DATE.MONTH" => { type => "field", addr => 0x80040, width => 5, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SOC_RTC_SET_DATE.MONTH_DAY" => { type => "field", addr => 0x80040, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SOC_RTC_SET_ALARM" => { type => "reg", addr => 0x80044, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_RTC_SET_ALARM.HOUR" => { type => "field", addr => 0x80044, width => 6, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_SET_ALARM.MINUTE" => { type => "field", addr => 0x80044, width => 7, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_SET_ALARM.SECOND" => { type => "field", addr => 0x80044, width => 7, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_CONFIG" => { type => "reg", addr => 0x80048, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_RTC_CONFIG.BCD" => { type => "field", addr => 0x80048, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SOC_RTC_CONFIG.TWELVE_HOUR" => { type => "field", addr => 0x80048, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SOC_RTC_CONFIG.DSE" => { type => "field", addr => 0x80048, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SOC_RTC_ALARM_STATUS" => { type => "reg", addr => 0x8004c, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "SOC_RTC_ALARM_STATUS.ENABLE" => { type => "field", addr => 0x8004c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_RTC_ALARM_STATUS.INTERRUPT" => { type => "field", addr => 0x8004c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0 }, "SOC_RESET_CAUSE" => { type => "reg", addr => 0x80050, width => 32, athEmulAttr => 0, acc => "RO" }, "SOC_RESET_CAUSE.LAST" => { type => "field", addr => 0x80050, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_LPO_CAL_TIME" => { type => "reg", addr => 0x800d4, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_LPO_CAL_TIME.LENGTH" => { type => "field", addr => 0x800d4, width => 14, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 500 }, "SOC_LPO_INIT_DIVIDEND_INT" => { type => "reg", addr => 0x800d8, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_LPO_INIT_DIVIDEND_INT.VALUE" => { type => "field", addr => 0x800d8, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 732433 }, "SOC_LPO_INIT_DIVIDEND_FRACTION" => { type => "reg", addr => 0x800dc, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_LPO_INIT_DIVIDEND_FRACTION.VALUE" => { type => "field", addr => 0x800dc, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1210 }, "SOC_LPO_CAL" => { type => "reg", addr => 0x800e0, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_LPO_CAL.ENABLE" => { type => "field", addr => 0x800e0, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_LPO_CAL_TEST_CONTROL" => { type => "reg", addr => 0x800e4, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_LPO_CAL_TEST_CONTROL.ENABLE" => { type => "field", addr => 0x800e4, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_LPO_CAL_TEST_CONTROL.RTC_CYCLES" => { type => "field", addr => 0x800e4, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_LPO_CAL_TEST_STATUS" => { type => "reg", addr => 0x800e8, width => 32, athEmulAttr => 0, acc => "RO" }, "SOC_LPO_CAL_TEST_STATUS.READY" => { type => "field", addr => 0x800e8, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_LPO_CAL_TEST_STATUS.COUNT" => { type => "field", addr => 0x800e8, width => 28, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_CHIP_ID" => { type => "reg", addr => 0x800ec, width => 32, athEmulAttr => 0, acc => "RO" }, "SOC_CHIP_ID.VERSION" => { type => "field", addr => 0x800ec, width => 14, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_CHIP_ID.TYPE" => { type => "field", addr => 0x800ec, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_CHIP_ID.REVISION" => { type => "field", addr => 0x800ec, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_CHIP_ID.OLD_VERSION" => { type => "field", addr => 0x800ec, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_POWER_REG" => { type => "reg", addr => 0x8010c, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_POWER_REG.SWREG_VS_EN" => { type => "field", addr => 0x8010c, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_POWER_REG.DISCON_MODE_EN" => { type => "field", addr => 0x8010c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_POWER_REG.DEEP_SLEEP_EN" => { type => "field", addr => 0x8010c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_POWER_REG.CPU_INT_ENABLE" => { type => "field", addr => 0x8010c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_POWER_REG.RADIO_PWD_EN" => { type => "field", addr => 0x8010c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_POWER_REG.POWER_EN" => { type => "field", addr => 0x8010c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_CORE_CLK_CTRL" => { type => "reg", addr => 0x80110, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_CORE_CLK_CTRL.DIV" => { type => "field", addr => 0x80110, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_GPIO_WAKEUP_CONTROL" => { type => "reg", addr => 0x80114, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_GPIO_WAKEUP_CONTROL.ENABLE" => { type => "field", addr => 0x80114, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_OTP_BITS" => { type => "reg", addr => 0x80118, width => 32, athEmulAttr => 0, acc => "RO" }, "SOC_OTP_BITS.TYPE" => { type => "field", addr => 0x80118, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "LP_PERF_COUNTER" => { type => "reg", addr => 0x80284, width => 32, athEmulAttr => 0, acc => "RW" }, "LP_PERF_COUNTER.EN" => { type => "field", addr => 0x80284, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LP_PERF_LIGHT_SLEEP" => { type => "reg", addr => 0x80288, width => 32, athEmulAttr => 0, acc => "RW" }, "LP_PERF_LIGHT_SLEEP.CNT" => { type => "field", addr => 0x80288, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LP_PERF_DEEP_SLEEP" => { type => "reg", addr => 0x8028c, width => 32, athEmulAttr => 0, acc => "RW" }, "LP_PERF_DEEP_SLEEP.CNT" => { type => "field", addr => 0x8028c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "LP_PERF_ON" => { type => "reg", addr => 0x80290, width => 32, athEmulAttr => 0, acc => "RW" }, "LP_PERF_ON.CNT" => { type => "field", addr => 0x80290, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "CHIP_MODE" => { type => "reg", addr => 0x802a8, width => 32, athEmulAttr => 0, acc => "RO" }, "CHIP_MODE.BIT" => { type => "field", addr => 0x802a8, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "OTP" => { type => "reg", addr => 0x802ac, width => 32, athEmulAttr => 0, acc => "RW" }, "OTP.LDO25_EN" => { type => "field", addr => 0x802ac, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "OTP.VDD12_EN" => { type => "field", addr => 0x802ac, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "OTP_STATUS" => { type => "reg", addr => 0x802b0, width => 32, athEmulAttr => 0, acc => "RO" }, "OTP_STATUS.LDO25_EN_READY" => { type => "field", addr => 0x802b0, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "OTP_STATUS.VDD12_EN_READY" => { type => "field", addr => 0x802b0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "PMU" => { type => "reg", addr => 0x802b4, width => 32, athEmulAttr => 0, acc => "RW" }, "PMU.REG_WAKEUP_TIME_SEL" => { type => "field", addr => 0x802b4, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "PMU_BYPASS" => { type => "reg", addr => 0x802b8, width => 32, athEmulAttr => 0, acc => "RW" }, "PMU_BYPASS.SWREG" => { type => "field", addr => 0x802b8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "PMU_BYPASS.PAREG" => { type => "field", addr => 0x802b8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "THERM_CTRL1" => { type => "reg", addr => 0x802dc, width => 32, athEmulAttr => 0, acc => "RW" }, "THERM_CTRL1.RST" => { type => "field", addr => 0x802dc, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "THERM_CTRL1.CH_SEL" => { type => "field", addr => 0x802dc, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "THERM_CTRL1.PDADC_BIAS" => { type => "field", addr => 0x802dc, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "THERM_CTRL1.PDADC_GAIN" => { type => "field", addr => 0x802dc, width => 9, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 256 }, "THERM_CTRL1.MEAS_WIN" => { type => "field", addr => 0x802dc, width => 3, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "THERM_CTRL1.DONE_INT_EN" => { type => "field", addr => 0x802dc, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "THERM_CTRL1.OUT_RANGE_INT_EN" => { type => "field", addr => 0x802dc, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "THERM_CTRL1.START" => { type => "field", addr => 0x802dc, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "THERM_CTRL2" => { type => "reg", addr => 0x802e0, width => 32, athEmulAttr => 0, acc => "RW" }, "THERM_CTRL2.THR_HIGH" => { type => "field", addr => 0x802e0, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "THERM_CTRL2.THR_LOW" => { type => "field", addr => 0x802e0, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "THERM_CTRL2.SETTLE_TIME" => { type => "field", addr => 0x802e0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 128 }, "THERM_CTRL3" => { type => "reg", addr => 0x802e4, width => 32, athEmulAttr => 0, acc => "RO" }, "THERM_CTRL3.THERM_LOW" => { type => "field", addr => 0x802e4, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "THERM_CTRL3.THERM_HIGH" => { type => "field", addr => 0x802e4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "THERM_CTRL4" => { type => "reg", addr => 0x802e8, width => 32, athEmulAttr => 0, acc => "RO" }, "THERM_CTRL4.THERM_VAL_CH3" => { type => "field", addr => 0x802e8, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "THERM_CTRL4.THERM_VAL_CH2" => { type => "field", addr => 0x802e8, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "THERM_CTRL4.THERM_VAL_CH1" => { type => "field", addr => 0x802e8, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "THERM_CTRL4.THERM_VAL_CH0" => { type => "field", addr => 0x802e8, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "THERM_CTRL5" => { type => "reg", addr => 0x802ec, width => 32, athEmulAttr => 0, acc => "RW" }, "THERM_CTRL5.ATPG_PDADC_DAT" => { type => "field", addr => 0x802ec, width => 9, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "CPU_PLL_CONFIG1" => { type => "reg", addr => 0x802f0, width => 32, athEmulAttr => 0, acc => "RW" }, "CPU_PLL_CONFIG1.FRAC" => { type => "field", addr => 0x802f0, width => 18, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "CPU_PLL_CONFIG1.INT" => { type => "field", addr => 0x802f0, width => 9, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "CPU_PLL_CONFIG1.REFDIV" => { type => "field", addr => 0x802f0, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "CPU_PLL_CONFIG2" => { type => "reg", addr => 0x802f4, width => 32, athEmulAttr => 0, acc => "RW" }, "CPU_PLL_CONFIG2.PLL_BYPASS" => { type => "field", addr => 0x802f4, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "CPU_PLL_CONFIG2.PLLPWD" => { type => "field", addr => 0x802f4, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "CPU_PLL_CONFIG2.OUTDIV" => { type => "field", addr => 0x802f4, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "RTC_CAL_DIV_DEFAULT" => { type => "reg", addr => 0x802f8, width => 32, athEmulAttr => 0, acc => "RW" }, "RTC_CAL_DIV_DEFAULT.V" => { type => "field", addr => 0x802f8, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 12499 }, "RTC_SPARE0" => { type => "reg", addr => 0x802fc, width => 32, athEmulAttr => 0, acc => "RW" }, "RTC_SPARE0.BITS" => { type => "field", addr => 0x802fc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "RTC_SPARE1" => { type => "reg", addr => 0x80300, width => 32, athEmulAttr => 0, acc => "RW" }, "RTC_SPARE1.BITS" => { type => "field", addr => 0x80300, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "RTC_DSLP_CONFIG0" => { type => "reg", addr => 0x80304, width => 32, athEmulAttr => 0, acc => "RW" }, "RTC_DSLP_CONFIG0.RST_DEAS_TIME" => { type => "field", addr => 0x80304, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "RTC_DSLP_CONFIG0.RST_ASSERT_TIME" => { type => "field", addr => 0x80304, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "RTC_DSLP_CONFIG0.BIAS_DIS_TIME" => { type => "field", addr => 0x80304, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "RTC_DSLP_CONFIG0.BIAS_EN_TIME" => { type => "field", addr => 0x80304, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "RTC_DSLP_CONFIG1" => { type => "reg", addr => 0x80308, width => 32, athEmulAttr => 0, acc => "RW" }, "RTC_DSLP_CONFIG1.HYSTERETIC_MODE_PCIE_PLL_GATING_DISABLE_CONTROL" => { type => "field", addr => 0x80308, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "RTC_DSLP_CONFIG1.HYSTERETIC_MODE_CONTROL" => { type => "field", addr => 0x80308, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "RTC_DSLP_CONFIG1.OSCON_DIS_TIME" => { type => "field", addr => 0x80308, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "RTC_DSLP_CONFIG1.LPM_DIS_TIME" => { type => "field", addr => 0x80308, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "XO_FAST_CHARGE_LPO_CNT" => { type => "reg", addr => 0x8030c, width => 32, athEmulAttr => 0, acc => "RW" }, "XO_FAST_CHARGE_LPO_CNT.XO_FAST_CHARGE_LPO_CNT" => { type => "field", addr => 0x8030c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 39 }, "PCIE_RLOOP" => { type => "reg", addr => 0x80310, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_RLOOP.VALUE" => { type => "field", addr => 0x80310, width => 4, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "PCIE_RLOOP.SEL" => { type => "field", addr => 0x80310, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "PCIE_PHY_RESET" => { type => "reg", addr => 0x80314, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_PHY_RESET.EN" => { type => "field", addr => 0x80314, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, ################################################################### ## soc_pcie_reg Register/Field definitions ################################################################### "PCIE_DEBUG_LOW" => { type => "reg", addr => 0x81000, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_DEBUG_LOW.CXPL_DEBUG_INFO_LOW" => { type => "field", addr => 0x81000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_DEBUG_HIGH" => { type => "reg", addr => 0x81004, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_DEBUG_HIGH.CXPL_DEBUG_INFO_HIGH" => { type => "field", addr => 0x81004, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM" => { type => "reg", addr => 0x81008, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_PM.WAKE" => { type => "field", addr => 0x81008, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.XMLH_L1_EXIT" => { type => "field", addr => 0x81008, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.LINK_REQ_RST_N" => { type => "field", addr => 0x81008, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.RDLH_LINK_UP" => { type => "field", addr => 0x81008, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.MASTER_STATE" => { type => "field", addr => 0x81008, width => 5, bitOffset => 17, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.PME_EN" => { type => "field", addr => 0x81008, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.AUX_PM_EN" => { type => "field", addr => 0x81008, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.XTLH_BLOCK_TLP" => { type => "field", addr => 0x81008, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.DSTATE" => { type => "field", addr => 0x81008, width => 3, bitOffset => 11, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.LTSSM_STATE" => { type => "field", addr => 0x81008, width => 6, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.STATUS" => { type => "field", addr => 0x81008, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.XMLH_LINK_UP" => { type => "field", addr => 0x81008, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_PM.CURNT_STATE" => { type => "field", addr => 0x81008, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_CTRL" => { type => "reg", addr => 0x8100c, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_CTRL.L123_PCIE_CLK_REMAIN_TIME" => { type => "field", addr => 0x8100c, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x6 }, "PCIE_CTRL.L123_PCIE_CORE_CLK_UG_GATED_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.L123_PCIETXBUF_AXI_CLK_GATED_HW_CTRL_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.L123_PCIETXBUF_AXI_CLK_GATED_SW_CTRL_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.L123_AXI_CLK_GATED_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.L123_PCIE_CORE_CLK_GATED_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.STICKY_RST_FIX_OVRD" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.STICKY_RST_FIX_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.RST_MASK" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.PME_GNT_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.DBI_OVERRIDE" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.IGNORE_AXI_PCIE_L1" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.IGNORE_MAC_FOR_L1" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.TARGET_L1_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.HOST_L1_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.TRAINING_RST_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.RDLH_LINK_RST_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.LINK_REQ_RST_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL.XMLH_LINK_RST_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PCIE_CTRL.APP_LTSSM_ENABLE" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_CTRL.ASPM_TIMER_BASED_L1_DISABLE" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_CTRL.SYS_AUX_PWR_DET" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_CTRL.D3_TO_L1_DISABLE_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_CTRL.D3_TO_L1_DISABLE_REAL_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_CTRL.NO_NAK_WA_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_CTRL.GDATA_WA_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x00000001 }, "PCIE_CTRL.TS2_WA_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x00000001 }, "PCIE_CTRL.TS1_WA_EN" => { type => "field", addr => 0x8100c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000001 }, "PCIE_NFTS" => { type => "reg", addr => 0x81010, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_NFTS.CNTL_EN" => { type => "field", addr => 0x81010, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_NFTS.ADJ" => { type => "field", addr => 0x81010, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_MSI_STATUS" => { type => "reg", addr => 0x81014, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_MSI_STATUS.MSI_INT_PENDING" => { type => "field", addr => 0x81014, width => 4, bitOffset => 21, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MSI_STATUS.MULTI" => { type => "field", addr => 0x81014, width => 3, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MSI_STATUS._64_BIT" => { type => "field", addr => 0x81014, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MSI_STATUS.DATA" => { type => "field", addr => 0x81014, width => 16, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MSI_STATUS.EN" => { type => "field", addr => 0x81014, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MSI_MASK" => { type => "reg", addr => 0x81018, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_MSI_MASK.VALUE" => { type => "field", addr => 0x81018, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MSI_ADDR" => { type => "reg", addr => 0x8101c, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_MSI_ADDR.LOW" => { type => "field", addr => 0x8101c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_CO_ERR_CTR0" => { type => "reg", addr => 0x81020, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_CO_ERR_CTR0.BAD_DLLP_ERR" => { type => "field", addr => 0x81020, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "PCIE_CO_ERR_CTR0.BAD_TLP_ERR" => { type => "field", addr => 0x81020, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "PCIE_CO_ERR_CTR0.RCVD_ERR" => { type => "field", addr => 0x81020, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "PCIE_CO_ERR_CTR1" => { type => "reg", addr => 0x81024, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_CO_ERR_CTR1.RPLY_NUM_RO_ERR" => { type => "field", addr => 0x81024, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "PCIE_CO_ERR_CTR1.RPLY_TO_ERR" => { type => "field", addr => 0x81024, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00 }, "PCIE_CO_ERR_CTR_CTRL" => { type => "reg", addr => 0x81028, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_CO_ERR_CTR_CTRL.RPLY_NUM_RO_ERR_CTR_AUTO_STOP" => { type => "field", addr => 0x81028, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CO_ERR_CTR_CTRL.RPLY_NUM_RO_ERR_CTR_RUN" => { type => "field", addr => 0x81028, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CO_ERR_CTR_CTRL.RPLY_TO_ERR_CTR_AUTO_STOP" => { type => "field", addr => 0x81028, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CO_ERR_CTR_CTRL.RPLY_TO_ERR_CTR_RUN" => { type => "field", addr => 0x81028, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CO_ERR_CTR_CTRL.BAD_DLLP_ERR_CTR_AUTO_STOP" => { type => "field", addr => 0x81028, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CO_ERR_CTR_CTRL.BAD_DLLP_ERR_CTR_RUN" => { type => "field", addr => 0x81028, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CO_ERR_CTR_CTRL.BAD_TLP_ERR_CTR_AUTO_STOP" => { type => "field", addr => 0x81028, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CO_ERR_CTR_CTRL.BAD_TLP_ERR_CTR_RUN" => { type => "field", addr => 0x81028, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CO_ERR_CTR_CTRL.RCVD_ERR_CTR_AUTO_STOP" => { type => "field", addr => 0x81028, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CO_ERR_CTR_CTRL.RCVD_ERR_CTR_RUN" => { type => "field", addr => 0x81028, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_MISC_STATUS" => { type => "reg", addr => 0x8102c, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_MISC_STATUS.CFG_ASPM_L1_EN" => { type => "field", addr => 0x8102c, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MISC_STATUS.CFG_CLK_PM_EN" => { type => "field", addr => 0x8102c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MISC_STATUS.CFG_PM_NO_SOFT_RST" => { type => "field", addr => 0x8102c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MISC_STATUS.CFG_RCB" => { type => "field", addr => 0x8102c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MISC_STATUS.CFG_MAX_PAYLOAD_SIZE" => { type => "field", addr => 0x8102c, width => 3, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MISC_STATUS.CFG_MAX_RD_REQ_SIZE" => { type => "field", addr => 0x8102c, width => 3, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MISC_STATUS.CFG_MEM_SPACE_EN" => { type => "field", addr => 0x8102c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_MISC_STATUS.CFG_BUS_MASTER_EN" => { type => "field", addr => 0x8102c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_BAR0_START" => { type => "reg", addr => 0x81030, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_BAR0_START.VAL" => { type => "field", addr => 0x81030, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_BAR0_LIMIT" => { type => "reg", addr => 0x81034, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_BAR0_LIMIT.VAL" => { type => "field", addr => 0x81034, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "AUTOCOMPL" => { type => "reg", addr => 0x81038, width => 32, athEmulAttr => 0, acc => "RW" }, "AUTOCOMPL.ENABLE" => { type => "field", addr => 0x81038, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "NUM_READS_WR_PENDING" => { type => "reg", addr => 0x8103c, width => 32, athEmulAttr => 0, acc => "RW" }, "NUM_READS_WR_PENDING.V" => { type => "field", addr => 0x8103c, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x8 }, "LOW_POWER_INT_ENABLE" => { type => "reg", addr => 0x81040, width => 32, athEmulAttr => 0, acc => "RW" }, "LOW_POWER_INT_ENABLE.Data" => { type => "field", addr => 0x81040, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "LOW_POWER_INT_MASK" => { type => "reg", addr => 0x81044, width => 32, athEmulAttr => 0, acc => "RW" }, "LOW_POWER_INT_MASK.Data" => { type => "field", addr => 0x81044, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "LOW_POWER_INT_STATUS" => { type => "reg", addr => 0x81048, width => 32, athEmulAttr => 0, acc => "RW" }, "LOW_POWER_INT_STATUS.Data" => { type => "field", addr => 0x81048, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "LTR_CFG" => { type => "reg", addr => 0x8104c, width => 32, athEmulAttr => 0, acc => "RO" }, "LTR_CFG.LTR_Enable" => { type => "field", addr => 0x8104c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "LTR_CFG.Reserved_1" => { type => "field", addr => 0x8104c, width => 2, bitOffset => 29, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "LTR_CFG.Max_NSnoop_Latency_Scale" => { type => "field", addr => 0x8104c, width => 3, bitOffset => 26, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "LTR_CFG.Max_NSnoop_Latency_Value" => { type => "field", addr => 0x8104c, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "LTR_CFG.Reserved_0" => { type => "field", addr => 0x8104c, width => 3, bitOffset => 13, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "LTR_CFG.Max_Snoop_Latency_Scale" => { type => "field", addr => 0x8104c, width => 3, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "LTR_CFG.Max_Snoop_Latency_Value" => { type => "field", addr => 0x8104c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "LTR_MSG" => { type => "reg", addr => 0x81050, width => 32, athEmulAttr => 0, acc => "RW" }, "LTR_MSG.V" => { type => "field", addr => 0x81050, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "LTR_REQ" => { type => "reg", addr => 0x81054, width => 32, athEmulAttr => 0, acc => "RW" }, "LTR_REQ.Req" => { type => "field", addr => 0x81054, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OBFF_STATUS" => { type => "reg", addr => 0x81058, width => 32, athEmulAttr => 0, acc => "RW" }, "OBFF_STATUS.OBFF_ENABLE" => { type => "field", addr => 0x81058, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "OBFF_STATUS.valid" => { type => "field", addr => 0x81058, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "OBFF_STATUS.status" => { type => "field", addr => 0x81058, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "L1SS_OBS" => { type => "reg", addr => 0x8105c, width => 32, athEmulAttr => 0, acc => "RO" }, "L1SS_OBS.L1SS_State" => { type => "field", addr => 0x8105c, width => 4, bitOffset => 5, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1SS_OBS.Pclkreq_n" => { type => "field", addr => 0x8105c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1SS_OBS.ClkReqIn" => { type => "field", addr => 0x8105c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1SS_OBS.AuxClkActive" => { type => "field", addr => 0x8105c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1SS_OBS.TxCMode_Dis" => { type => "field", addr => 0x8105c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1SS_OBS.RxEIdle_Dis" => { type => "field", addr => 0x8105c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1SS_OVRD" => { type => "reg", addr => 0x81060, width => 32, athEmulAttr => 0, acc => "RW" }, "L1SS_OVRD.PCI_PM_L1_1_DISABLE" => { type => "field", addr => 0x81060, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "L1SS_OVRD.ASPM_L1_1_DISABLE" => { type => "field", addr => 0x81060, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "L1SS_OVRD.PCI_PM_L1_2_DISABLE" => { type => "field", addr => 0x81060, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "L1SS_OVRD.ASPM_L1_2_DISABLE" => { type => "field", addr => 0x81060, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "L1SS_OVRD.Enable" => { type => "field", addr => 0x81060, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "L1SS_OVRD.Value" => { type => "field", addr => 0x81060, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_SCRATCH_0" => { type => "reg", addr => 0x81070, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_SCRATCH_0.VAL" => { type => "field", addr => 0x81070, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_SCRATCH_1" => { type => "reg", addr => 0x81074, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_SCRATCH_1.VAL" => { type => "field", addr => 0x81074, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x40000000 }, "VMI_MSG_LOW" => { type => "reg", addr => 0x81078, width => 32, athEmulAttr => 0, acc => "RW" }, "VMI_MSG_LOW.DATA" => { type => "field", addr => 0x81078, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "VMI_MSG_HIGH" => { type => "reg", addr => 0x8107c, width => 32, athEmulAttr => 0, acc => "RW" }, "VMI_MSG_HIGH.DATA" => { type => "field", addr => 0x8107c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "VMI_MSG_MISC" => { type => "reg", addr => 0x81080, width => 32, athEmulAttr => 0, acc => "RW" }, "VMI_MSG_MISC.DATA" => { type => "field", addr => 0x81080, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_DEBUG_EI" => { type => "reg", addr => 0x81084, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_DEBUG_EI.CXPL_DEBUG_INFO_EI" => { type => "field", addr => 0x81084, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_0" => { type => "reg", addr => 0x81088, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_L1SS_CTRL_STATUS_0.L1_2_THR_SCALE" => { type => "field", addr => 0x81088, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_0.L1_2_THR_VALUE" => { type => "field", addr => 0x81088, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_0.COMMON_MODE_RESTORE_TIME" => { type => "field", addr => 0x81088, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_0.T_POWER_ON_VALUE" => { type => "field", addr => 0x81088, width => 5, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_0.T_POWER_ON_SCALE" => { type => "field", addr => 0x81088, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_1" => { type => "reg", addr => 0x8108c, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_L1SS_CTRL_STATUS_1.T_POWER_ON_VALUE" => { type => "field", addr => 0x8108c, width => 5, bitOffset => 19, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_1.T_POWER_ON_SCALE" => { type => "field", addr => 0x8108c, width => 2, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_1.COMMON_MODE_RESTORE_TIME" => { type => "field", addr => 0x8108c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_1.ASPM_L1_1_ENABLE" => { type => "field", addr => 0x8108c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_1.ASPM_L1_2_ENABLE" => { type => "field", addr => 0x8108c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_1.PCI_PM_L1_1_ENABLE" => { type => "field", addr => 0x8108c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_L1SS_CTRL_STATUS_1.PCI_PM_L1_2_ENABLE" => { type => "field", addr => 0x8108c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_UNCORRECTABLE_ERROR_INT_ENABLE" => { type => "reg", addr => 0x81090, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_UNCORRECTABLE_ERROR_INT_ENABLE.Data" => { type => "field", addr => 0x81090, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_UNCORRECTABLE_ERROR_INT_MASK" => { type => "reg", addr => 0x81094, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_UNCORRECTABLE_ERROR_INT_MASK.Data" => { type => "field", addr => 0x81094, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_UNCORRECTABLE_ERROR_INT_STATUS" => { type => "reg", addr => 0x81098, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_UNCORRECTABLE_ERROR_INT_STATUS.Data" => { type => "field", addr => 0x81098, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_RX_NFTS_PATCH" => { type => "reg", addr => 0x8109c, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_RX_NFTS_PATCH.EN" => { type => "field", addr => 0x8109c, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_RX_NFTS_PATCH.VAL" => { type => "field", addr => 0x8109c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "PCIE_RX_NFTS_TMO" => { type => "reg", addr => 0x810a0, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_RX_NFTS_TMO.CLR" => { type => "field", addr => 0x810a0, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "WO", resetVal => 0x0 }, "PCIE_RX_NFTS_TMO.CNT" => { type => "field", addr => 0x810a0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "LTR_LATENCY" => { type => "reg", addr => 0x810a4, width => 32, athEmulAttr => 0, acc => "RO" }, "LTR_LATENCY.DATA" => { type => "field", addr => 0x810a4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "STATISTIC_CTRL" => { type => "reg", addr => 0x810a8, width => 32, athEmulAttr => 0, acc => "RW" }, "STATISTIC_CTRL.CLEAR" => { type => "field", addr => 0x810a8, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "STATISTIC_CTRL.ENABLE" => { type => "field", addr => 0x810a8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "STATISTIC_PERIOD_CNT" => { type => "reg", addr => 0x810ac, width => 32, athEmulAttr => 0, acc => "RO" }, "STATISTIC_PERIOD_CNT.CNT" => { type => "field", addr => 0x810ac, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1_TIME_CNT" => { type => "reg", addr => 0x810b0, width => 32, athEmulAttr => 0, acc => "RO" }, "L1_TIME_CNT.CNT" => { type => "field", addr => 0x810b0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1_1_TIME_CNT" => { type => "reg", addr => 0x810b4, width => 32, athEmulAttr => 0, acc => "RO" }, "L1_1_TIME_CNT.CNT" => { type => "field", addr => 0x810b4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1_2_TIME_CNT" => { type => "reg", addr => 0x810b8, width => 32, athEmulAttr => 0, acc => "RO" }, "L1_2_TIME_CNT.CNT" => { type => "field", addr => 0x810b8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "MSI_MAGIC" => { type => "reg", addr => 0x810bc, width => 32, athEmulAttr => 0, acc => "RW" }, "MSI_MAGIC.EN" => { type => "field", addr => 0x810bc, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "MSI_MAGIC.RDY" => { type => "field", addr => 0x810bc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "MSI_MAGIC_ADR" => { type => "reg", addr => 0x810c0, width => 32, athEmulAttr => 0, acc => "RW" }, "MSI_MAGIC_ADR.VAL" => { type => "field", addr => 0x810c0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_AXI_BRIDGE_CTRL_CLIENT" => { type => "reg", addr => 0x810c4, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_AXI_BRIDGE_CTRL_CLIENT.TLP_ATTR" => { type => "field", addr => 0x810c4, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_AXI_BRIDGE_CTRL_CLIENT.TLP_TC" => { type => "field", addr => 0x810c4, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "SOC_RDY_STATUS" => { type => "reg", addr => 0x810c8, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_RDY_STATUS.VAL" => { type => "field", addr => 0x810c8, width => 31, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "SOC_RDY_STATUS.BAR" => { type => "field", addr => 0x810c8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_MISC_CTRL" => { type => "reg", addr => 0x810cc, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_MISC_CTRL.STAR_569307" => { type => "field", addr => 0x810cc, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_MISC_CTRL.STAR_494311" => { type => "field", addr => 0x810cc, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_MISC_CTRL.STAR_471173" => { type => "field", addr => 0x810cc, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_MISC_CTRL.ts_expected_wa_en" => { type => "field", addr => 0x810cc, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PCIE_MISC_CTRL.EXT_RBIAS_CTRL" => { type => "field", addr => 0x810cc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PCIE_IDLE_DLY" => { type => "reg", addr => 0x810d0, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_IDLE_DLY.IDLE_DLY_EN" => { type => "field", addr => 0x810d0, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_IDLE_DLY.IDLE_DLY_CLR" => { type => "field", addr => 0x810d0, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_IDLE_DLY.IDLE_DLY_SCALE" => { type => "field", addr => 0x810d0, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_IDLE_DLY.IDLE_DLY_VALUE" => { type => "field", addr => 0x810d0, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "L1_ENTER_CNT" => { type => "reg", addr => 0x810d4, width => 32, athEmulAttr => 0, acc => "RO" }, "L1_ENTER_CNT.CNT" => { type => "field", addr => 0x810d4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1_1_ENTER_CNT" => { type => "reg", addr => 0x810d8, width => 32, athEmulAttr => 0, acc => "RO" }, "L1_1_ENTER_CNT.CNT" => { type => "field", addr => 0x810d8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "L1_2_ENTER_CNT" => { type => "reg", addr => 0x810dc, width => 32, athEmulAttr => 0, acc => "RO" }, "L1_2_ENTER_CNT.CNT" => { type => "field", addr => 0x810dc, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PCIE_WRAP_INTR_MASK" => { type => "reg", addr => 0x810e0, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_WRAP_INTR_MASK.CONTROL" => { type => "field", addr => 0x810e0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_WRAP_INTR_HOST_MASK" => { type => "reg", addr => 0x810e4, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_WRAP_INTR_HOST_MASK.CONTROL" => { type => "field", addr => 0x810e4, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_WRAP_INTR_STATUS" => { type => "reg", addr => 0x810e8, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "PCIE_WRAP_INTR_STATUS.VALUE" => { type => "field", addr => 0x810e8, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "EV144272" => { type => "reg", addr => 0x810ec, width => 32, athEmulAttr => 0, acc => "RW" }, "EV144272.ENABLE" => { type => "field", addr => 0x810ec, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL_EXT" => { type => "reg", addr => 0x810f0, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_CTRL_EXT.ASPM_APP_REQ_L1_DIS" => { type => "field", addr => 0x810f0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## soc_core_reg Register/Field definitions ################################################################### "CORE_CTRL" => { type => "reg", addr => 0x82000, width => 32, athEmulAttr => 0, acc => "RW" }, "CORE_CTRL.SLV_RESP_ERR_MAP" => { type => "field", addr => 0x82000, width => 6, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "CORE_CTRL.PCS_COMMON_CLOCKS" => { type => "field", addr => 0x82000, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CORE_CTRL.MASK_CORE_RST_TO_PHY" => { type => "field", addr => 0x82000, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CORE_CTRL.MASK_PCIE_RST" => { type => "field", addr => 0x82000, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CORE_CTRL.PCIE_LTSSM_EN" => { type => "field", addr => 0x82000, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CORE_CTRL.OUTBAND_PWRUP" => { type => "field", addr => 0x82000, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "CORE_CTRL.WAKE_L" => { type => "field", addr => 0x82000, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "CORE_CTRL.HOST_WAKE_INTR_CLR" => { type => "field", addr => 0x82000, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "WO", resetVal => 0x00000000 }, "CORE_CTRL.CPU_INTR" => { type => "field", addr => 0x82000, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "CORE_CTRL.PCIE_INTR" => { type => "field", addr => 0x82000, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "CORE_PM" => { type => "reg", addr => 0x82004, width => 32, athEmulAttr => 0, acc => "RO" }, "CORE_PM.PCIEPHY_RTUNE_ACK" => { type => "field", addr => 0x82004, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "CORE_PM.DSTATE" => { type => "field", addr => 0x82004, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "CORE_PM.STATUS" => { type => "field", addr => 0x82004, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "CORE_PM.AUX_PM_EN" => { type => "field", addr => 0x82004, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "CORE_PM.PME_EN" => { type => "field", addr => 0x82004, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_INTR_ENABLE" => { type => "reg", addr => 0x82008, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_INTR_ENABLE.VAL" => { type => "field", addr => 0x82008, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "PCIE_INTR_CAUSE" => { type => "reg", addr => 0x8200c, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_INTR_CAUSE.VAL" => { type => "field", addr => 0x8200c, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x00000000 }, "PCIE_INTR_CLR" => { type => "reg", addr => 0x82010, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_INTR_CLR.VAL" => { type => "field", addr => 0x82010, width => 30, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "SCRATCH_0" => { type => "reg", addr => 0x82014, width => 32, athEmulAttr => 0, acc => "RW" }, "SCRATCH_0.VAL" => { type => "field", addr => 0x82014, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "SCRATCH_1" => { type => "reg", addr => 0x82018, width => 32, athEmulAttr => 0, acc => "RW" }, "SCRATCH_1.VAL" => { type => "field", addr => 0x82018, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "SCRATCH_2" => { type => "reg", addr => 0x8201c, width => 32, athEmulAttr => 0, acc => "RW" }, "SCRATCH_2.VAL" => { type => "field", addr => 0x8201c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "SCRATCH_3" => { type => "reg", addr => 0x82020, width => 32, athEmulAttr => 0, acc => "RW" }, "SCRATCH_3.VAL" => { type => "field", addr => 0x82020, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x00000000 }, "WLAN_APB_ADDR_ERROR_CONTROL" => { type => "reg", addr => 0x82024, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "WLAN_APB_ADDR_ERROR_CONTROL.INT_STATUS" => { type => "field", addr => 0x82024, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0 }, "WLAN_APB_ADDR_ERROR_CONTROL.ENABLE" => { type => "field", addr => 0x82024, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_APB_ADDR_ERROR_STATUS" => { type => "reg", addr => 0x82028, width => 32, athEmulAttr => 0, acc => "RO" }, "WLAN_APB_ADDR_ERROR_STATUS.ADDRESS" => { type => "field", addr => 0x82028, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "WLAN_APB_ADDR_ERROR_STATUS_WRITE" => { type => "reg", addr => 0x8202c, width => 32, athEmulAttr => 0, acc => "RO" }, "WLAN_APB_ADDR_ERROR_STATUS_WRITE.VAL" => { type => "field", addr => 0x8202c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "PMU_CTRL" => { type => "reg", addr => 0x82030, width => 32, athEmulAttr => 0, acc => "RW" }, "PMU_CTRL.LPO2MHz_EN" => { type => "field", addr => 0x82030, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "PCIE_TO_HOST_INTMASK" => { type => "reg", addr => 0x82034, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_TO_HOST_INTMASK.APB_ERROR_INT_MASK" => { type => "field", addr => 0x82034, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_TO_HOST_INTMASK.EFUSE_ERROR_INT_MASK" => { type => "field", addr => 0x82034, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "PCIE_CTRL_STATUS" => { type => "reg", addr => 0x82038, width => 32, athEmulAttr => 0, acc => "RO" }, "PCIE_CTRL_STATUS.PCIE_CLK_AVAILABLE" => { type => "field", addr => 0x82038, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "PCIE_SW_PERST_N" => { type => "reg", addr => 0x82040, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE_SW_PERST_N.SW_PERST_N" => { type => "field", addr => 0x82040, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## athrUartCsr Register/Field definitions ################################################################### "UartData" => { type => "reg", addr => 0x83000, width => 32, athEmulAttr => 0, acc => "RW" }, "UartData.UartTxCsr" => { type => "field", addr => 0x83000, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartData.UartRxCsr" => { type => "field", addr => 0x83000, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartData.UartTxRxData" => { type => "field", addr => 0x83000, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartCs" => { type => "reg", addr => 0x83004, width => 32, athEmulAttr => 0, acc => "RW" }, "UartCs.UartRxBusy" => { type => "field", addr => 0x83004, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "UartCs.UartTxBusy" => { type => "field", addr => 0x83004, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "UartCs.UartHostIntEn" => { type => "field", addr => 0x83004, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartCs.UartHostInt" => { type => "field", addr => 0x83004, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "UartCs.UartTxBreak" => { type => "field", addr => 0x83004, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartCs.UartRxBreak" => { type => "field", addr => 0x83004, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "UartCs.UartSeriaTxReady" => { type => "field", addr => 0x83004, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "UartCs.UartTxReadyOride" => { type => "field", addr => 0x83004, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartCs.UartRxReadyOride" => { type => "field", addr => 0x83004, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartCs.UartDmaEn" => { type => "field", addr => 0x83004, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartCs.UartFlowControlMode" => { type => "field", addr => 0x83004, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartCs.UartInterfaceMode" => { type => "field", addr => 0x83004, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartCs.UartParityMode" => { type => "field", addr => 0x83004, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartClock" => { type => "reg", addr => 0x83008, width => 32, athEmulAttr => 0, acc => "RW" }, "UartClock.UartClockScale" => { type => "field", addr => 0x83008, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartClock.UartClockStep" => { type => "field", addr => 0x83008, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartInt" => { type => "reg", addr => 0x8300c, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "UartInt.UartTxEmptyInt" => { type => "field", addr => 0x8300c, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UartInt.UartRxFullInt" => { type => "field", addr => 0x8300c, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UartInt.UartRxBreakOffInt" => { type => "field", addr => 0x8300c, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UartInt.UartRxBreakOnInt" => { type => "field", addr => 0x8300c, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UartInt.UartRxParityErrInt" => { type => "field", addr => 0x8300c, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UartInt.UartTxOflowErrInt" => { type => "field", addr => 0x8300c, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UartInt.UartRxOflowErrInt" => { type => "field", addr => 0x8300c, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UartInt.UartRxFramingErrInt" => { type => "field", addr => 0x8300c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UartInt.UartTxReadyInt" => { type => "field", addr => 0x8300c, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UartInt.UartRxValidInt" => { type => "field", addr => 0x8300c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0x0 }, "UartIntEn" => { type => "reg", addr => 0x83010, width => 32, athEmulAttr => 0, acc => "RW" }, "UartIntEn.UartTxEmptyIntEn" => { type => "field", addr => 0x83010, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartIntEn.UartRxFullIntEn" => { type => "field", addr => 0x83010, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartIntEn.UartRxBreakOffIntEn" => { type => "field", addr => 0x83010, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartIntEn.UartRxBreakOnIntEn" => { type => "field", addr => 0x83010, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartIntEn.UartRxParityErrIntEn" => { type => "field", addr => 0x83010, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartIntEn.UartTxOflowErrIntEn" => { type => "field", addr => 0x83010, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartIntEn.UartRxOflowErrIntEn" => { type => "field", addr => 0x83010, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartIntEn.UartRxFramingErrIntEn" => { type => "field", addr => 0x83010, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartIntEn.UartTxReadyIntEn" => { type => "field", addr => 0x83010, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "UartIntEn.UartRxValidIntEn" => { type => "field", addr => 0x83010, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## si_reg Register/Field definitions ################################################################### "SI_CONFIG" => { type => "reg", addr => 0x84000, width => 32, athEmulAttr => 0, acc => "RW" }, "SI_CONFIG.ERR_INT" => { type => "field", addr => 0x84000, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_CONFIG.BIDIR_OD_DATA" => { type => "field", addr => 0x84000, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SI_CONFIG.I2C" => { type => "field", addr => 0x84000, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SI_CONFIG.POS_SAMPLE" => { type => "field", addr => 0x84000, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SI_CONFIG.POS_DRIVE" => { type => "field", addr => 0x84000, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_CONFIG.INACTIVE_DATA" => { type => "field", addr => 0x84000, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SI_CONFIG.INACTIVE_CLK" => { type => "field", addr => 0x84000, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SI_CONFIG.DIVIDER" => { type => "field", addr => 0x84000, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_CS" => { type => "reg", addr => 0x84004, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "SI_CS.BIT_CNT_IN_LAST_BYTE" => { type => "field", addr => 0x84004, width => 3, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_CS.DONE_ERR" => { type => "field", addr => 0x84004, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SI_CS.DONE_INT" => { type => "field", addr => 0x84004, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0 }, "SI_CS.START" => { type => "field", addr => 0x84004, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_CS.RX_CNT" => { type => "field", addr => 0x84004, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_CS.TX_CNT" => { type => "field", addr => 0x84004, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_TX_DATA0" => { type => "reg", addr => 0x84008, width => 32, athEmulAttr => 0, acc => "RW" }, "SI_TX_DATA0.DATA3" => { type => "field", addr => 0x84008, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_TX_DATA0.DATA2" => { type => "field", addr => 0x84008, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_TX_DATA0.DATA1" => { type => "field", addr => 0x84008, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_TX_DATA0.DATA0" => { type => "field", addr => 0x84008, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_TX_DATA1" => { type => "reg", addr => 0x8400c, width => 32, athEmulAttr => 0, acc => "RW" }, "SI_TX_DATA1.DATA7" => { type => "field", addr => 0x8400c, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_TX_DATA1.DATA6" => { type => "field", addr => 0x8400c, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_TX_DATA1.DATA5" => { type => "field", addr => 0x8400c, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_TX_DATA1.DATA4" => { type => "field", addr => 0x8400c, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SI_RX_DATA0" => { type => "reg", addr => 0x84010, width => 32, athEmulAttr => 0, acc => "RO" }, "SI_RX_DATA0.DATA3" => { type => "field", addr => 0x84010, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SI_RX_DATA0.DATA2" => { type => "field", addr => 0x84010, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SI_RX_DATA0.DATA1" => { type => "field", addr => 0x84010, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SI_RX_DATA0.DATA0" => { type => "field", addr => 0x84010, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SI_RX_DATA1" => { type => "reg", addr => 0x84014, width => 32, athEmulAttr => 0, acc => "RO" }, "SI_RX_DATA1.DATA7" => { type => "field", addr => 0x84014, width => 8, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SI_RX_DATA1.DATA6" => { type => "field", addr => 0x84014, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SI_RX_DATA1.DATA5" => { type => "field", addr => 0x84014, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SI_RX_DATA1.DATA4" => { type => "field", addr => 0x84014, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, ################################################################### ## gpio_athr_wlan_reg Register/Field definitions ################################################################### "WLAN_GPIO_OUT_LOW" => { type => "reg", addr => 0x85000, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_OUT_LOW.DATA" => { type => "field", addr => 0x85000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO1_OUT_LOW" => { type => "reg", addr => 0x85004, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO1_OUT_LOW.DATA" => { type => "field", addr => 0x85004, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_OUT_W1TS_LOW" => { type => "reg", addr => 0x85008, width => 32, athEmulAttr => 0, acc => "WOSET" }, "WLAN_GPIO_OUT_W1TS_LOW.DATA" => { type => "field", addr => 0x85008, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOSET", resetVal => 0 }, "WLAN_GPIO1_OUT_W1TS_LOW" => { type => "reg", addr => 0x8500c, width => 32, athEmulAttr => 0, acc => "WOSET" }, "WLAN_GPIO1_OUT_W1TS_LOW.DATA" => { type => "field", addr => 0x8500c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOSET", resetVal => 0 }, "WLAN_GPIO_OUT_W1TC_LOW" => { type => "reg", addr => 0x85010, width => 32, athEmulAttr => 0, acc => "WOCLR" }, "WLAN_GPIO_OUT_W1TC_LOW.DATA" => { type => "field", addr => 0x85010, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOCLR", resetVal => 0 }, "WLAN_GPIO1_OUT_W1TC_LOW" => { type => "reg", addr => 0x85014, width => 32, athEmulAttr => 0, acc => "WOCLR" }, "WLAN_GPIO1_OUT_W1TC_LOW.DATA" => { type => "field", addr => 0x85014, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOCLR", resetVal => 0 }, "WLAN_GPIO_ENABLE_LOW" => { type => "reg", addr => 0x85018, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_ENABLE_LOW.DATA" => { type => "field", addr => 0x85018, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3c0 }, "WLAN_GPIO1_ENABLE_LOW" => { type => "reg", addr => 0x8501c, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO1_ENABLE_LOW.DATA" => { type => "field", addr => 0x8501c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "WLAN_GPIO_ENABLE_W1TS_LOW" => { type => "reg", addr => 0x85020, width => 32, athEmulAttr => 0, acc => "WOSET" }, "WLAN_GPIO_ENABLE_W1TS_LOW.DATA" => { type => "field", addr => 0x85020, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOSET", resetVal => 0 }, "WLAN_GPIO1_ENABLE_W1TS_LOW" => { type => "reg", addr => 0x85024, width => 32, athEmulAttr => 0, acc => "WOSET" }, "WLAN_GPIO1_ENABLE_W1TS_LOW.DATA" => { type => "field", addr => 0x85024, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOSET", resetVal => 0 }, "WLAN_GPIO_ENABLE_W1TC_LOW" => { type => "reg", addr => 0x85028, width => 32, athEmulAttr => 0, acc => "WOCLR" }, "WLAN_GPIO_ENABLE_W1TC_LOW.DATA" => { type => "field", addr => 0x85028, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOCLR", resetVal => 0 }, "WLAN_GPIO1_ENABLE_W1TC_LOW" => { type => "reg", addr => 0x8502c, width => 32, athEmulAttr => 0, acc => "WOCLR" }, "WLAN_GPIO1_ENABLE_W1TC_LOW.DATA" => { type => "field", addr => 0x8502c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOCLR", resetVal => 0 }, "WLAN_GPIO_IN_LOW" => { type => "reg", addr => 0x85030, width => 32, athEmulAttr => 0, acc => "RO" }, "WLAN_GPIO_IN_LOW.DATA" => { type => "field", addr => 0x85030, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "WLAN_GPIO1_IN_LOW" => { type => "reg", addr => 0x85034, width => 32, athEmulAttr => 0, acc => "RO" }, "WLAN_GPIO1_IN_LOW.DATA" => { type => "field", addr => 0x85034, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "WLAN_GPIO_STATUS_LOW" => { type => "reg", addr => 0x85038, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_STATUS_LOW.INTERRUPT" => { type => "field", addr => 0x85038, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO1_STATUS_LOW" => { type => "reg", addr => 0x8503c, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO1_STATUS_LOW.INTERRUPT" => { type => "field", addr => 0x8503c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_STATUS_W1TS_LOW" => { type => "reg", addr => 0x85040, width => 32, athEmulAttr => 0, acc => "WOSET" }, "WLAN_GPIO_STATUS_W1TS_LOW.INTERRUPT" => { type => "field", addr => 0x85040, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOSET", resetVal => 0 }, "WLAN_GPIO1_STATUS_W1TS_LOW" => { type => "reg", addr => 0x85044, width => 32, athEmulAttr => 0, acc => "WOSET" }, "WLAN_GPIO1_STATUS_W1TS_LOW.INTERRUPT" => { type => "field", addr => 0x85044, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOSET", resetVal => 0 }, "WLAN_GPIO_STATUS_W1TC_LOW" => { type => "reg", addr => 0x85048, width => 32, athEmulAttr => 0, acc => "WOCLR" }, "WLAN_GPIO_STATUS_W1TC_LOW.INTERRUPT" => { type => "field", addr => 0x85048, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOCLR", resetVal => 0 }, "WLAN_GPIO1_STATUS_W1TC_LOW" => { type => "reg", addr => 0x8504c, width => 32, athEmulAttr => 0, acc => "WOCLR" }, "WLAN_GPIO1_STATUS_W1TC_LOW.INTERRUPT" => { type => "field", addr => 0x8504c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "WOCLR", resetVal => 0 }, "WLAN_GPIO_PIN0" => { type => "reg", addr => 0x85050, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN0.PAD_ENST" => { type => "field", addr => 0x85050, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN0.CONFIG" => { type => "field", addr => 0x85050, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN0.WAKEUP_ENABLE" => { type => "field", addr => 0x85050, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN0.INT_TYPE" => { type => "field", addr => 0x85050, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN0.PAD_PULL" => { type => "field", addr => 0x85050, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN0.PAD_STRENGTH" => { type => "field", addr => 0x85050, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN0.PAD_DRIVER" => { type => "field", addr => 0x85050, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN0.SOURCE" => { type => "field", addr => 0x85050, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN1" => { type => "reg", addr => 0x85054, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN1.PAD_ENST" => { type => "field", addr => 0x85054, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN1.CONFIG" => { type => "field", addr => 0x85054, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN1.WAKEUP_ENABLE" => { type => "field", addr => 0x85054, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN1.INT_TYPE" => { type => "field", addr => 0x85054, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN1.PAD_PULL" => { type => "field", addr => 0x85054, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN1.PAD_STRENGTH" => { type => "field", addr => 0x85054, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN1.PAD_DRIVER" => { type => "field", addr => 0x85054, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN1.SOURCE" => { type => "field", addr => 0x85054, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN2" => { type => "reg", addr => 0x85058, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN2.PAD_ENST" => { type => "field", addr => 0x85058, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN2.CONFIG" => { type => "field", addr => 0x85058, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN2.WAKEUP_ENABLE" => { type => "field", addr => 0x85058, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN2.INT_TYPE" => { type => "field", addr => 0x85058, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN2.PAD_PULL" => { type => "field", addr => 0x85058, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN2.PAD_STRENGTH" => { type => "field", addr => 0x85058, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN2.PAD_DRIVER" => { type => "field", addr => 0x85058, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN2.SOURCE" => { type => "field", addr => 0x85058, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN3" => { type => "reg", addr => 0x8505c, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN3.PAD_ENST" => { type => "field", addr => 0x8505c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN3.CONFIG" => { type => "field", addr => 0x8505c, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN3.WAKEUP_ENABLE" => { type => "field", addr => 0x8505c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN3.INT_TYPE" => { type => "field", addr => 0x8505c, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN3.PAD_PULL" => { type => "field", addr => 0x8505c, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN3.PAD_STRENGTH" => { type => "field", addr => 0x8505c, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN3.PAD_DRIVER" => { type => "field", addr => 0x8505c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN3.SOURCE" => { type => "field", addr => 0x8505c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN4" => { type => "reg", addr => 0x85060, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN4.PAD_ENST" => { type => "field", addr => 0x85060, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN4.CONFIG" => { type => "field", addr => 0x85060, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN4.WAKEUP_ENABLE" => { type => "field", addr => 0x85060, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN4.INT_TYPE" => { type => "field", addr => 0x85060, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN4.PAD_PULL" => { type => "field", addr => 0x85060, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN4.PAD_STRENGTH" => { type => "field", addr => 0x85060, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN4.PAD_DRIVER" => { type => "field", addr => 0x85060, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN4.SOURCE" => { type => "field", addr => 0x85060, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN5" => { type => "reg", addr => 0x85064, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN5.PAD_ENST" => { type => "field", addr => 0x85064, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN5.CONFIG" => { type => "field", addr => 0x85064, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN5.WAKEUP_ENABLE" => { type => "field", addr => 0x85064, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN5.INT_TYPE" => { type => "field", addr => 0x85064, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN5.PAD_PULL" => { type => "field", addr => 0x85064, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN5.PAD_STRENGTH" => { type => "field", addr => 0x85064, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN5.PAD_DRIVER" => { type => "field", addr => 0x85064, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN5.SOURCE" => { type => "field", addr => 0x85064, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN6" => { type => "reg", addr => 0x85068, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN6.PAD_ENST" => { type => "field", addr => 0x85068, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN6.CONFIG" => { type => "field", addr => 0x85068, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN6.WAKEUP_ENABLE" => { type => "field", addr => 0x85068, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN6.INT_TYPE" => { type => "field", addr => 0x85068, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN6.PAD_PULL" => { type => "field", addr => 0x85068, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN6.PAD_STRENGTH" => { type => "field", addr => 0x85068, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN6.PAD_DRIVER" => { type => "field", addr => 0x85068, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN6.SOURCE" => { type => "field", addr => 0x85068, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN7" => { type => "reg", addr => 0x8506c, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN7.PAD_ENST" => { type => "field", addr => 0x8506c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN7.CONFIG" => { type => "field", addr => 0x8506c, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN7.WAKEUP_ENABLE" => { type => "field", addr => 0x8506c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN7.INT_TYPE" => { type => "field", addr => 0x8506c, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN7.PAD_PULL" => { type => "field", addr => 0x8506c, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN7.PAD_STRENGTH" => { type => "field", addr => 0x8506c, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN7.PAD_DRIVER" => { type => "field", addr => 0x8506c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN7.SOURCE" => { type => "field", addr => 0x8506c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN8" => { type => "reg", addr => 0x85070, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN8.PAD_ENST" => { type => "field", addr => 0x85070, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN8.CONFIG" => { type => "field", addr => 0x85070, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN8.WAKEUP_ENABLE" => { type => "field", addr => 0x85070, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN8.INT_TYPE" => { type => "field", addr => 0x85070, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN8.PAD_PULL" => { type => "field", addr => 0x85070, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN8.PAD_STRENGTH" => { type => "field", addr => 0x85070, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN8.PAD_DRIVER" => { type => "field", addr => 0x85070, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN8.SOURCE" => { type => "field", addr => 0x85070, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN9" => { type => "reg", addr => 0x85074, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN9.PAD_ENST" => { type => "field", addr => 0x85074, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN9.CONFIG" => { type => "field", addr => 0x85074, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN9.WAKEUP_ENABLE" => { type => "field", addr => 0x85074, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN9.INT_TYPE" => { type => "field", addr => 0x85074, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN9.PAD_PULL" => { type => "field", addr => 0x85074, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN9.PAD_STRENGTH" => { type => "field", addr => 0x85074, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN9.PAD_DRIVER" => { type => "field", addr => 0x85074, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN9.SOURCE" => { type => "field", addr => 0x85074, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN10" => { type => "reg", addr => 0x85078, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN10.PAD_ENST" => { type => "field", addr => 0x85078, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN10.CONFIG" => { type => "field", addr => 0x85078, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN10.WAKEUP_ENABLE" => { type => "field", addr => 0x85078, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN10.INT_TYPE" => { type => "field", addr => 0x85078, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN10.PAD_PULL" => { type => "field", addr => 0x85078, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN10.PAD_STRENGTH" => { type => "field", addr => 0x85078, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN10.PAD_DRIVER" => { type => "field", addr => 0x85078, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN10.SOURCE" => { type => "field", addr => 0x85078, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN11" => { type => "reg", addr => 0x8507c, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN11.PAD_ENST" => { type => "field", addr => 0x8507c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN11.CONFIG" => { type => "field", addr => 0x8507c, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN11.WAKEUP_ENABLE" => { type => "field", addr => 0x8507c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN11.INT_TYPE" => { type => "field", addr => 0x8507c, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN11.PAD_PULL" => { type => "field", addr => 0x8507c, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN11.PAD_STRENGTH" => { type => "field", addr => 0x8507c, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN11.PAD_DRIVER" => { type => "field", addr => 0x8507c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN11.SOURCE" => { type => "field", addr => 0x8507c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN12" => { type => "reg", addr => 0x85080, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN12.PAD_ENST" => { type => "field", addr => 0x85080, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN12.CONFIG" => { type => "field", addr => 0x85080, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN12.WAKEUP_ENABLE" => { type => "field", addr => 0x85080, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN12.INT_TYPE" => { type => "field", addr => 0x85080, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN12.PAD_PULL" => { type => "field", addr => 0x85080, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN12.PAD_STRENGTH" => { type => "field", addr => 0x85080, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN12.PAD_DRIVER" => { type => "field", addr => 0x85080, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN12.SOURCE" => { type => "field", addr => 0x85080, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN13" => { type => "reg", addr => 0x85084, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN13.PAD_ENST" => { type => "field", addr => 0x85084, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN13.CONFIG" => { type => "field", addr => 0x85084, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN13.WAKEUP_ENABLE" => { type => "field", addr => 0x85084, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN13.INT_TYPE" => { type => "field", addr => 0x85084, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN13.PAD_PULL" => { type => "field", addr => 0x85084, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN13.PAD_STRENGTH" => { type => "field", addr => 0x85084, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN13.PAD_DRIVER" => { type => "field", addr => 0x85084, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN13.SOURCE" => { type => "field", addr => 0x85084, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN14" => { type => "reg", addr => 0x85088, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN14.PAD_ENST" => { type => "field", addr => 0x85088, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN14.CONFIG" => { type => "field", addr => 0x85088, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN14.WAKEUP_ENABLE" => { type => "field", addr => 0x85088, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN14.INT_TYPE" => { type => "field", addr => 0x85088, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN14.PAD_PULL" => { type => "field", addr => 0x85088, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN14.PAD_STRENGTH" => { type => "field", addr => 0x85088, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN14.PAD_DRIVER" => { type => "field", addr => 0x85088, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN14.SOURCE" => { type => "field", addr => 0x85088, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN15" => { type => "reg", addr => 0x8508c, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN15.PAD_ENST" => { type => "field", addr => 0x8508c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN15.CONFIG" => { type => "field", addr => 0x8508c, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN15.WAKEUP_ENABLE" => { type => "field", addr => 0x8508c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN15.INT_TYPE" => { type => "field", addr => 0x8508c, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN15.PAD_PULL" => { type => "field", addr => 0x8508c, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN15.PAD_STRENGTH" => { type => "field", addr => 0x8508c, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN15.PAD_DRIVER" => { type => "field", addr => 0x8508c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN15.SOURCE" => { type => "field", addr => 0x8508c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN16" => { type => "reg", addr => 0x85090, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN16.PAD_ENST" => { type => "field", addr => 0x85090, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN16.CONFIG" => { type => "field", addr => 0x85090, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN16.WAKEUP_ENABLE" => { type => "field", addr => 0x85090, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN16.INT_TYPE" => { type => "field", addr => 0x85090, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN16.PAD_PULL" => { type => "field", addr => 0x85090, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN16.PAD_STRENGTH" => { type => "field", addr => 0x85090, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN16.PAD_DRIVER" => { type => "field", addr => 0x85090, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN16.SOURCE" => { type => "field", addr => 0x85090, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN17" => { type => "reg", addr => 0x85094, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN17.PAD_ENST" => { type => "field", addr => 0x85094, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN17.CONFIG" => { type => "field", addr => 0x85094, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN17.WAKEUP_ENABLE" => { type => "field", addr => 0x85094, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN17.INT_TYPE" => { type => "field", addr => 0x85094, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN17.PAD_PULL" => { type => "field", addr => 0x85094, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN17.PAD_STRENGTH" => { type => "field", addr => 0x85094, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN17.PAD_DRIVER" => { type => "field", addr => 0x85094, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN17.SOURCE" => { type => "field", addr => 0x85094, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN18" => { type => "reg", addr => 0x85098, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN18.PAD_ENST" => { type => "field", addr => 0x85098, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN18.CONFIG" => { type => "field", addr => 0x85098, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN18.WAKEUP_ENABLE" => { type => "field", addr => 0x85098, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN18.INT_TYPE" => { type => "field", addr => 0x85098, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN18.PAD_PULL" => { type => "field", addr => 0x85098, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN18.PAD_STRENGTH" => { type => "field", addr => 0x85098, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN18.PAD_DRIVER" => { type => "field", addr => 0x85098, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN18.SOURCE" => { type => "field", addr => 0x85098, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN19" => { type => "reg", addr => 0x8509c, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN19.PAD_ENST" => { type => "field", addr => 0x8509c, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN19.CONFIG" => { type => "field", addr => 0x8509c, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN19.WAKEUP_ENABLE" => { type => "field", addr => 0x8509c, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN19.INT_TYPE" => { type => "field", addr => 0x8509c, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN19.PAD_PULL" => { type => "field", addr => 0x8509c, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN19.PAD_STRENGTH" => { type => "field", addr => 0x8509c, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN19.PAD_DRIVER" => { type => "field", addr => 0x8509c, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN19.SOURCE" => { type => "field", addr => 0x8509c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN20" => { type => "reg", addr => 0x850a0, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN20.PAD_ENST" => { type => "field", addr => 0x850a0, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN20.CONFIG" => { type => "field", addr => 0x850a0, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN20.WAKEUP_ENABLE" => { type => "field", addr => 0x850a0, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN20.INT_TYPE" => { type => "field", addr => 0x850a0, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN20.PAD_PULL" => { type => "field", addr => 0x850a0, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN20.PAD_STRENGTH" => { type => "field", addr => 0x850a0, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN20.PAD_DRIVER" => { type => "field", addr => 0x850a0, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN20.SOURCE" => { type => "field", addr => 0x850a0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN21" => { type => "reg", addr => 0x850a4, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN21.PAD_ENST" => { type => "field", addr => 0x850a4, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN21.CONFIG" => { type => "field", addr => 0x850a4, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN21.WAKEUP_ENABLE" => { type => "field", addr => 0x850a4, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN21.INT_TYPE" => { type => "field", addr => 0x850a4, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN21.PAD_PULL" => { type => "field", addr => 0x850a4, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN21.PAD_STRENGTH" => { type => "field", addr => 0x850a4, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN21.PAD_DRIVER" => { type => "field", addr => 0x850a4, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN21.SOURCE" => { type => "field", addr => 0x850a4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN22" => { type => "reg", addr => 0x850a8, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN22.PAD_ENST" => { type => "field", addr => 0x850a8, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN22.CONFIG" => { type => "field", addr => 0x850a8, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN22.WAKEUP_ENABLE" => { type => "field", addr => 0x850a8, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN22.INT_TYPE" => { type => "field", addr => 0x850a8, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN22.PAD_PULL" => { type => "field", addr => 0x850a8, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN22.PAD_STRENGTH" => { type => "field", addr => 0x850a8, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN22.PAD_DRIVER" => { type => "field", addr => 0x850a8, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN22.SOURCE" => { type => "field", addr => 0x850a8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN23" => { type => "reg", addr => 0x850ac, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN23.PAD_ENST" => { type => "field", addr => 0x850ac, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN23.CONFIG" => { type => "field", addr => 0x850ac, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN23.WAKEUP_ENABLE" => { type => "field", addr => 0x850ac, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN23.INT_TYPE" => { type => "field", addr => 0x850ac, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN23.PAD_PULL" => { type => "field", addr => 0x850ac, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN23.PAD_STRENGTH" => { type => "field", addr => 0x850ac, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN23.PAD_DRIVER" => { type => "field", addr => 0x850ac, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN23.SOURCE" => { type => "field", addr => 0x850ac, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN24" => { type => "reg", addr => 0x850b0, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN24.PAD_ENST" => { type => "field", addr => 0x850b0, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN24.CONFIG" => { type => "field", addr => 0x850b0, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN24.WAKEUP_ENABLE" => { type => "field", addr => 0x850b0, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN24.INT_TYPE" => { type => "field", addr => 0x850b0, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN24.PAD_PULL" => { type => "field", addr => 0x850b0, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN24.PAD_STRENGTH" => { type => "field", addr => 0x850b0, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN24.PAD_DRIVER" => { type => "field", addr => 0x850b0, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN24.SOURCE" => { type => "field", addr => 0x850b0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN25" => { type => "reg", addr => 0x850b4, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN25.PAD_ENST" => { type => "field", addr => 0x850b4, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN25.CONFIG" => { type => "field", addr => 0x850b4, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN25.WAKEUP_ENABLE" => { type => "field", addr => 0x850b4, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN25.INT_TYPE" => { type => "field", addr => 0x850b4, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN25.PAD_PULL" => { type => "field", addr => 0x850b4, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN25.PAD_STRENGTH" => { type => "field", addr => 0x850b4, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN25.PAD_DRIVER" => { type => "field", addr => 0x850b4, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN25.SOURCE" => { type => "field", addr => 0x850b4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN26" => { type => "reg", addr => 0x850b8, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN26.PAD_ENST" => { type => "field", addr => 0x850b8, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN26.CONFIG" => { type => "field", addr => 0x850b8, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN26.WAKEUP_ENABLE" => { type => "field", addr => 0x850b8, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN26.INT_TYPE" => { type => "field", addr => 0x850b8, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN26.PAD_PULL" => { type => "field", addr => 0x850b8, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PIN26.PAD_STRENGTH" => { type => "field", addr => 0x850b8, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN26.PAD_DRIVER" => { type => "field", addr => 0x850b8, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN26.SOURCE" => { type => "field", addr => 0x850b8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN27" => { type => "reg", addr => 0x850bc, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN27.PAD_ENST" => { type => "field", addr => 0x850bc, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN27.CONFIG" => { type => "field", addr => 0x850bc, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN27.WAKEUP_ENABLE" => { type => "field", addr => 0x850bc, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN27.INT_TYPE" => { type => "field", addr => 0x850bc, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN27.PAD_PULL" => { type => "field", addr => 0x850bc, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN27.PAD_STRENGTH" => { type => "field", addr => 0x850bc, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN27.PAD_DRIVER" => { type => "field", addr => 0x850bc, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN27.SOURCE" => { type => "field", addr => 0x850bc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN28" => { type => "reg", addr => 0x850c0, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN28.PAD_ENST" => { type => "field", addr => 0x850c0, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN28.CONFIG" => { type => "field", addr => 0x850c0, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN28.WAKEUP_ENABLE" => { type => "field", addr => 0x850c0, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN28.INT_TYPE" => { type => "field", addr => 0x850c0, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN28.PAD_PULL" => { type => "field", addr => 0x850c0, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN28.PAD_STRENGTH" => { type => "field", addr => 0x850c0, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN28.PAD_DRIVER" => { type => "field", addr => 0x850c0, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN28.SOURCE" => { type => "field", addr => 0x850c0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN29" => { type => "reg", addr => 0x850c4, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN29.PAD_ENST" => { type => "field", addr => 0x850c4, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN29.CONFIG" => { type => "field", addr => 0x850c4, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN29.WAKEUP_ENABLE" => { type => "field", addr => 0x850c4, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN29.INT_TYPE" => { type => "field", addr => 0x850c4, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN29.PAD_PULL" => { type => "field", addr => 0x850c4, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN29.PAD_STRENGTH" => { type => "field", addr => 0x850c4, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN29.PAD_DRIVER" => { type => "field", addr => 0x850c4, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN29.SOURCE" => { type => "field", addr => 0x850c4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN30" => { type => "reg", addr => 0x850c8, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN30.PAD_ENST" => { type => "field", addr => 0x850c8, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN30.CONFIG" => { type => "field", addr => 0x850c8, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN30.WAKEUP_ENABLE" => { type => "field", addr => 0x850c8, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN30.INT_TYPE" => { type => "field", addr => 0x850c8, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN30.PAD_PULL" => { type => "field", addr => 0x850c8, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN30.PAD_STRENGTH" => { type => "field", addr => 0x850c8, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN30.PAD_DRIVER" => { type => "field", addr => 0x850c8, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN30.SOURCE" => { type => "field", addr => 0x850c8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN31" => { type => "reg", addr => 0x850cc, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN31.PAD_ENST" => { type => "field", addr => 0x850cc, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN31.CONFIG" => { type => "field", addr => 0x850cc, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN31.WAKEUP_ENABLE" => { type => "field", addr => 0x850cc, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN31.INT_TYPE" => { type => "field", addr => 0x850cc, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN31.PAD_PULL" => { type => "field", addr => 0x850cc, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN31.PAD_STRENGTH" => { type => "field", addr => 0x850cc, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN31.PAD_DRIVER" => { type => "field", addr => 0x850cc, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN31.SOURCE" => { type => "field", addr => 0x850cc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN32" => { type => "reg", addr => 0x850d0, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN32.PAD_ENST" => { type => "field", addr => 0x850d0, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN32.CONFIG" => { type => "field", addr => 0x850d0, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN32.WAKEUP_ENABLE" => { type => "field", addr => 0x850d0, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN32.INT_TYPE" => { type => "field", addr => 0x850d0, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN32.PAD_PULL" => { type => "field", addr => 0x850d0, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN32.PAD_STRENGTH" => { type => "field", addr => 0x850d0, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN32.PAD_DRIVER" => { type => "field", addr => 0x850d0, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN32.SOURCE" => { type => "field", addr => 0x850d0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN33" => { type => "reg", addr => 0x850d4, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN33.PAD_ENST" => { type => "field", addr => 0x850d4, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN33.CONFIG" => { type => "field", addr => 0x850d4, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN33.WAKEUP_ENABLE" => { type => "field", addr => 0x850d4, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN33.INT_TYPE" => { type => "field", addr => 0x850d4, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN33.PAD_PULL" => { type => "field", addr => 0x850d4, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN33.PAD_STRENGTH" => { type => "field", addr => 0x850d4, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN33.PAD_DRIVER" => { type => "field", addr => 0x850d4, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN33.SOURCE" => { type => "field", addr => 0x850d4, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN34" => { type => "reg", addr => 0x850d8, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN34.PAD_ENST" => { type => "field", addr => 0x850d8, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN34.CONFIG" => { type => "field", addr => 0x850d8, width => 4, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN34.WAKEUP_ENABLE" => { type => "field", addr => 0x850d8, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN34.INT_TYPE" => { type => "field", addr => 0x850d8, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN34.PAD_PULL" => { type => "field", addr => 0x850d8, width => 2, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "WLAN_GPIO_PIN34.PAD_STRENGTH" => { type => "field", addr => 0x850d8, width => 2, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN34.PAD_DRIVER" => { type => "field", addr => 0x850d8, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN34.SOURCE" => { type => "field", addr => 0x850d8, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN35" => { type => "reg", addr => 0x850dc, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PIN35.WAKEUP_ENABLE" => { type => "field", addr => 0x850dc, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN35.INT_TYPE" => { type => "field", addr => 0x850dc, width => 3, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN35.PAD_DRIVER" => { type => "field", addr => 0x850dc, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PIN35.SOURCE" => { type => "field", addr => 0x850dc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WL_SOC_APB" => { type => "reg", addr => 0x850e0, width => 32, athEmulAttr => 0, acc => "RW" }, "WL_SOC_APB.TOGGLE" => { type => "field", addr => 0x850e0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_SIGMA_DELTA" => { type => "reg", addr => 0x850e4, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_SIGMA_DELTA.ENABLE" => { type => "field", addr => 0x850e4, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_SIGMA_DELTA.PRESCALAR" => { type => "field", addr => 0x850e4, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_SIGMA_DELTA.TARGET" => { type => "field", addr => 0x850e4, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WL_BOOTSTRAP" => { type => "reg", addr => 0x850e8, width => 32, athEmulAttr => 0, acc => "RO" }, "WL_BOOTSTRAP.LOAD_FIRMWARE_FROM_ATE" => { type => "field", addr => 0x850e8, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "WL_BOOTSTRAP.STATUS" => { type => "field", addr => 0x850e8, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "WL_BOOTSTRAP1" => { type => "reg", addr => 0x850ec, width => 32, athEmulAttr => 0, acc => "RO" }, "WL_BOOTSTRAP1.STATUS" => { type => "field", addr => 0x850ec, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "SOC_DEBUG" => { type => "reg", addr => 0x850f0, width => 32, athEmulAttr => 0, acc => "RW" }, "SOC_DEBUG.PCIE_DEBUG_SEL" => { type => "field", addr => 0x850f0, width => 6, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "SOC_DEBUG.SHIFT" => { type => "field", addr => 0x850f0, width => 3, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_DEBUG.GPIO_SEL" => { type => "field", addr => 0x850f0, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_DEBUG.CLOCK_SEL" => { type => "field", addr => 0x850f0, width => 5, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_DEBUG.SRC_SEL" => { type => "field", addr => 0x850f0, width => 3, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SOC_DEBUG.ENABLE" => { type => "field", addr => 0x850f0, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "SPDT_CONTROL" => { type => "reg", addr => 0x850f4, width => 32, athEmulAttr => 0, acc => "RW" }, "SPDT_CONTROL.RFSILENT_FORCE" => { type => "field", addr => 0x850f4, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "CLOCK_OBS_MUX" => { type => "reg", addr => 0x850f8, width => 32, athEmulAttr => 0, acc => "RW" }, "CLOCK_OBS_MUX.DIV_SEL" => { type => "field", addr => 0x850f8, width => 2, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "CLOCK_OBS_MUX.CLK_SEL" => { type => "field", addr => 0x850f8, width => 5, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "CLOCK_OBS_MUX.MASTER_SEL" => { type => "field", addr => 0x850f8, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "PCIE" => { type => "reg", addr => 0x850fc, width => 32, athEmulAttr => 0, acc => "RW" }, "PCIE.INT_TYPE" => { type => "field", addr => 0x850fc, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "PCIE.WAKEUP_TYPE" => { type => "field", addr => 0x850fc, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PCIE" => { type => "reg", addr => 0x85100, width => 32, athEmulAttr => 0, acc => "RW" }, "WLAN_GPIO_PCIE.RST_SHORT_ENST" => { type => "field", addr => 0x85100, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PCIE.WAKE_L_ENST" => { type => "field", addr => 0x85100, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PCIE.RST_L_ENST" => { type => "field", addr => 0x85100, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PCIE.CLKREQ_L_ENST" => { type => "field", addr => 0x85100, width => 1, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PCIE.RST_L_PAD_STRENGTH" => { type => "field", addr => 0x85100, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PCIE.WAKE_L_PAD_STRENGTH" => { type => "field", addr => 0x85100, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PCIE.CLKREQ_L_PAD_STRENGTH" => { type => "field", addr => 0x85100, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PCIE.RST_SHORT_PAD_PULL" => { type => "field", addr => 0x85100, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "WLAN_GPIO_PCIE.WAKE_L_PAD_PULL" => { type => "field", addr => 0x85100, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PCIE.CLKREQ_L_PAD_PULL" => { type => "field", addr => 0x85100, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "WLAN_GPIO_PCIE.RST_L_PAD_PULL" => { type => "field", addr => 0x85100, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "GPIO_SPARE0" => { type => "reg", addr => 0x85104, width => 32, athEmulAttr => 0, acc => "RW" }, "GPIO_SPARE0.BITS" => { type => "field", addr => 0x85104, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "GPIO_SPARE1" => { type => "reg", addr => 0x85108, width => 32, athEmulAttr => 0, acc => "RW" }, "GPIO_SPARE1.BITS" => { type => "field", addr => 0x85108, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "DEBUG_BUS" => { type => "reg", addr => 0x8510c, width => 32, athEmulAttr => 0, acc => "RO" }, "DEBUG_BUS.DATA" => { type => "field", addr => 0x8510c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, ################################################################### ## efuse_reg Register/Field definitions ################################################################### "EFUSE_WR_ENABLE_REG" => { type => "reg", addr => 0x86000, width => 32, athEmulAttr => 0, acc => "RW" }, "EFUSE_WR_ENABLE_REG.V" => { type => "field", addr => 0x86000, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "EFUSE_INT_ENABLE_REG" => { type => "reg", addr => 0x86004, width => 32, athEmulAttr => 0, acc => "RW" }, "EFUSE_INT_ENABLE_REG.V" => { type => "field", addr => 0x86004, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "EFUSE_INT_STATUS_REG" => { type => "reg", addr => 0x86008, width => 32, athEmulAttr => 0, acc => "RWOCLR" }, "EFUSE_INT_STATUS_REG.V" => { type => "field", addr => 0x86008, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RWOCLR", resetVal => 0 }, "BITMASK_WR_REG" => { type => "reg", addr => 0x8600c, width => 32, athEmulAttr => 0, acc => "RW" }, "BITMASK_WR_REG.V" => { type => "field", addr => 0x8600c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "VDDQ_SETTLE_TIME_REG" => { type => "reg", addr => 0x86010, width => 32, athEmulAttr => 0, acc => "RW" }, "VDDQ_SETTLE_TIME_REG.V" => { type => "field", addr => 0x86010, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 48 }, "VDDQ_HOLD_TIME_REG" => { type => "reg", addr => 0x86014, width => 32, athEmulAttr => 0, acc => "RW" }, "VDDQ_HOLD_TIME_REG.V" => { type => "field", addr => 0x86014, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "RD_STROBE_PW_REG" => { type => "reg", addr => 0x86018, width => 32, athEmulAttr => 0, acc => "RW" }, "RD_STROBE_PW_REG.V" => { type => "field", addr => 0x86018, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "PG_STROBE_PW_REG" => { type => "reg", addr => 0x8601c, width => 32, athEmulAttr => 0, acc => "RW" }, "PG_STROBE_PW_REG.V" => { type => "field", addr => 0x8601c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 97 }, "PGENB_SETUP_HOLD_TIME_REG" => { type => "reg", addr => 0x86020, width => 32, athEmulAttr => 0, acc => "RW" }, "PGENB_SETUP_HOLD_TIME_REG.V" => { type => "field", addr => 0x86020, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "STROBE_PULSE_INTERVAL_REG" => { type => "reg", addr => 0x86024, width => 32, athEmulAttr => 0, acc => "RW" }, "STROBE_PULSE_INTERVAL_REG.V" => { type => "field", addr => 0x86024, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "CSB_ADDR_LOAD_SETUP_HOLD_REG" => { type => "reg", addr => 0x86028, width => 32, athEmulAttr => 0, acc => "RW" }, "CSB_ADDR_LOAD_SETUP_HOLD_REG.V" => { type => "field", addr => 0x86028, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 1 }, "SUR_PD_CSB_REG" => { type => "reg", addr => 0x8602c, width => 32, athEmulAttr => 0, acc => "RW" }, "SUR_PD_CSB_REG.V" => { type => "field", addr => 0x8602c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 13 }, "SUP_PS_CSB_REG" => { type => "reg", addr => 0x86030, width => 32, athEmulAttr => 0, acc => "RW" }, "SUP_PS_CSB_REG.V" => { type => "field", addr => 0x86030, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "EFUSE_BUZY_STATUS_REG" => { type => "reg", addr => 0x86034, width => 32, athEmulAttr => 0, acc => "RO" }, "EFUSE_BUZY_STATUS_REG.V" => { type => "field", addr => 0x86034, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "EFUSE_INTF0" => { type => "reg", addr => 0x86800, width => 32, athEmulAttr => 0, acc => "RW", depth => 512, incr => 4 }, "EFUSE_INTF0.R" => { type => "field", addr => 0x86800, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "EFUSE_INTF1" => { type => "reg", addr => 0x87000, width => 32, athEmulAttr => 0, acc => "RW", depth => 512, incr => 4 }, "EFUSE_INTF1.R" => { type => "field", addr => 0x87000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, ################################################################### ## dbi_reg Register/Field definitions ################################################################### "DBI_WINDOW_reg" => { type => "reg", addr => 0x89000, width => 32, athEmulAttr => 0, acc => "RW", depth => 4096, incr => 4 }, "DBI_WINDOW_reg.DATA" => { type => "field", addr => 0x89000, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, ################################################################### ## pcie_phy_reg_csr Register/Field definitions ################################################################### "pcie_phy_reg_1" => { type => "reg", addr => 0x8d000, width => 32, athEmulAttr => 0, acc => "RW" }, "pcie_phy_reg_1.ForceRxEidle_0_EN" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.REV10_LoopBack_En" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.EnableClkReq" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.DataObsPrbsErr" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.serdes_en_lckdt" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.ClkObsSel" => { type => "field", addr => 0x8d000, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.DataObsEn" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.FuncTestRxClkInv" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.vco_fast" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "pcie_phy_reg_1.vco_slow" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "pcie_phy_reg_1.prbs_aa_enable" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.serdes_from_pad_or_reg" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.serdes_dis_rximp" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.serdes_disable" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.RxClkInv" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_1.ForceLoopBack" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.serdes_rx_eq" => { type => "field", addr => 0x8d000, width => 2, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_1.serdes_pll_disable_l1" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.serdes_power_save" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.serdes_cdr_bw" => { type => "field", addr => 0x8d000, width => 2, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_1.serdes_th_los" => { type => "field", addr => 0x8d000, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "pcie_phy_reg_1.serdes_en_deemp" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_1.serdes_sel_hsp" => { type => "field", addr => 0x8d000, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_1.s" => { type => "field", addr => 0x8d000, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_2" => { type => "reg", addr => 0x8d004, width => 32, athEmulAttr => 0, acc => "RW" }, "pcie_phy_reg_2.lckdt_out" => { type => "field", addr => 0x8d004, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "pcie_phy_reg_2.prbs_error_count" => { type => "field", addr => 0x8d004, width => 8, bitOffset => 23, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "pcie_phy_reg_2.sds_sdm_rxelecidle" => { type => "field", addr => 0x8d004, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "pcie_phy_reg_2.sds_sdm_rxdetected" => { type => "field", addr => 0x8d004, width => 1, bitOffset => 21, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "pcie_phy_reg_2.prbs_scramble" => { type => "field", addr => 0x8d004, width => 1, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_2.prbs_start" => { type => "field", addr => 0x8d004, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_2.prbs_ts_num" => { type => "field", addr => 0x8d004, width => 7, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x40 }, "pcie_phy_reg_2.TxDetRxOvrValue" => { type => "field", addr => 0x8d004, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_2.TxDetRxOvrEn" => { type => "field", addr => 0x8d004, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_2.CDRReadyTimer" => { type => "field", addr => 0x8d004, width => 4, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x7 }, "pcie_phy_reg_2.TxDetRxTargetDelay" => { type => "field", addr => 0x8d004, width => 5, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0xC }, "pcie_phy_reg_2.ForceDetect" => { type => "field", addr => 0x8d004, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3" => { type => "reg", addr => 0x8d008, width => 32, athEmulAttr => 0, acc => "RW" }, "pcie_phy_reg_3.serdes_rsv_7_4" => { type => "field", addr => 0x8d008, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3.serdes_th_dat" => { type => "field", addr => 0x8d008, width => 3, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "pcie_phy_reg_3.serdes_sel_los" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3.serdes_cdr_step" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 23, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3.serdes_en_refclk" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3.serdes_lpf_los" => { type => "field", addr => 0x8d008, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_3.serdes_cdr_rck_sel" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_3.serdes_offb" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_3.serdes_pll_bw" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3.serdes_cdr_dmt" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 15, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3.serdes_tx_amp" => { type => "field", addr => 0x8d008, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "pcie_phy_reg_3.serdes_rsv_3_0" => { type => "field", addr => 0x8d008, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "pcie_phy_reg_3.SPARE" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 7, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_3.en_beacongen" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3.txelecidle" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3.rx_det_req" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3.en_pll" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_3.en_lckdt" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_3.en_bufs_rx" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_3.en" => { type => "field", addr => 0x8d008, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_4" => { type => "reg", addr => 0x8d00c, width => 32, athEmulAttr => 0, acc => "RW" }, "pcie_phy_reg_4.clk_switch_wait_ext_value" => { type => "field", addr => 0x8d00c, width => 3, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_4.refclk_det_disable" => { type => "field", addr => 0x8d00c, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_4.refclk_wait_value" => { type => "field", addr => 0x8d00c, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x2 }, "pcie_phy_reg_4.clk_switch_wait_value" => { type => "field", addr => 0x8d00c, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x3c }, "pcie_phy_reg_4.pll_settle_time" => { type => "field", addr => 0x8d00c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x48 }, "pcie_phy_reg_5" => { type => "reg", addr => 0x8d010, width => 32, athEmulAttr => 0, acc => "RW" }, "pcie_phy_reg_5.EnableClkReq_prstn" => { type => "field", addr => 0x8d010, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_5.pll_fslck_time" => { type => "field", addr => 0x8d010, width => 12, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "pcie_phy_reg_5.reserve" => { type => "field", addr => 0x8d010, width => 2, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_5.txdetectrx_refclk_detect" => { type => "field", addr => 0x8d010, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_5.dis_txcm_perst_disable_n" => { type => "field", addr => 0x8d010, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_5.serdes_en_deemp" => { type => "field", addr => 0x8d010, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x3 }, "pcie_phy_reg_5.serdes_fslck_level" => { type => "field", addr => 0x8d010, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x5 }, "pcie_phy_reg_5.serdes_vcorng_ctrl" => { type => "field", addr => 0x8d010, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_5.serdes_en_steptx" => { type => "field", addr => 0x8d010, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_5.en_fast_pll_lock" => { type => "field", addr => 0x8d010, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_5.rx_signal_det_off" => { type => "field", addr => 0x8d010, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_6" => { type => "reg", addr => 0x8d014, width => 32, athEmulAttr => 0, acc => "RW" }, "pcie_phy_reg_6.reserve" => { type => "field", addr => 0x8d014, width => 18, bitOffset => 14, athEmulAttr => 0, acc => "RW", resetVal => 0x2c }, "pcie_phy_reg_6.lockdetect_rst_n" => { type => "field", addr => 0x8d014, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "pcie_phy_reg_6.en_bufs_rx_delay_enable" => { type => "field", addr => 0x8d014, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "pcie_phy_reg_6.en_bufs_rx_value" => { type => "field", addr => 0x8d014, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x38 }, }; my @addrMapStructs = ( "regMapStruct", "tiered_chn1_table_map_struct", "tiered_sm_table_map_struct", "tiered_chn_table_map_struct", "tiered_sm1_table_map_struct", ); use constant tierPortal => { "tiered_chn1_table_map_struct" => { addrPtr => 0x11494, dataPtr => 0x11498 }, "tiered_sm_table_map_struct" => { addrPtr => 0x10bf0, dataPtr => 0x10bf4 }, "tiered_chn_table_map_struct" => { addrPtr => 0x10494, dataPtr => 0x10498 }, "tiered_sm1_table_map_struct" => { addrPtr => 0x11bf0, dataPtr => 0x11bf4 }, }; use constant tiered_chn1_table_map_struct => { ################################################################### ## chn1_table_map Register/Field definitions ################################################################### "BB_paprd_power_at_am2am_cal_b1" => { type => "reg", addr => 0x80, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_power_at_am2am_cal_b1.paprd_power_at_am2am_cal_4_b1" => { type => "field", addr => 0x80, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_power_at_am2am_cal_b1.paprd_power_at_am2am_cal_3_b1" => { type => "field", addr => 0x80, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_power_at_am2am_cal_b1.paprd_power_at_am2am_cal_2_b1" => { type => "field", addr => 0x80, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_power_at_am2am_cal_b1.paprd_power_at_am2am_cal_1_b1" => { type => "field", addr => 0x80, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_power_at_am2am_cal_b1.paprd_power_at_am2am_cal_0_b1" => { type => "field", addr => 0x80, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_valid_obdb_b1" => { type => "reg", addr => 0x84, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_valid_obdb_b1.paprd_valid_obdb_4_b1" => { type => "field", addr => 0x84, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_paprd_valid_obdb_b1.paprd_valid_obdb_3_b1" => { type => "field", addr => 0x84, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_paprd_valid_obdb_b1.paprd_valid_obdb_2_b1" => { type => "field", addr => 0x84, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_paprd_valid_obdb_b1.paprd_valid_obdb_1_b1" => { type => "field", addr => 0x84, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_paprd_valid_obdb_b1.paprd_valid_obdb_0_b1" => { type => "field", addr => 0x84, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_chn1_tables_dummy_2" => { type => "reg", addr => 0x100, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chn1_tables_dummy_2.dummy2" => { type => "field", addr => 0x100, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcorr_txpath_coef_b1" => { type => "reg", addr => 0x890, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "BB_txiqcorr_txpath_coef_b1.txiqcorr_txpath_coef_chn1" => { type => "field", addr => 0x890, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcorr_rxpath_coef_b1" => { type => "reg", addr => 0x8d0, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "BB_txiqcorr_rxpath_coef_b1.txiqcorr_rxpath_coef_chn1" => { type => "field", addr => 0x8d0, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxiqcorr_rxpath_coef_b1" => { type => "reg", addr => 0x910, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "BB_rxiqcorr_rxpath_coef_b1.rxiqcorr_rxpath_coef_chn1" => { type => "field", addr => 0x910, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxiqcorr_txpath_coef_b1" => { type => "reg", addr => 0x950, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "BB_rxiqcorr_txpath_coef_b1.rxiqcorr_txpath_coef_chn1" => { type => "field", addr => 0x950, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b1" => { type => "reg", addr => 0xa40, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_iqcorr_idx_7_0_b1.rxcal_tx_iqcorr_idx_7_chn1" => { type => "field", addr => 0xa40, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b1.rxcal_tx_iqcorr_idx_6_chn1" => { type => "field", addr => 0xa40, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b1.rxcal_tx_iqcorr_idx_5_chn1" => { type => "field", addr => 0xa40, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b1.rxcal_tx_iqcorr_idx_4_chn1" => { type => "field", addr => 0xa40, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b1.rxcal_tx_iqcorr_idx_3_chn1" => { type => "field", addr => 0xa40, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b1.rxcal_tx_iqcorr_idx_2_chn1" => { type => "field", addr => 0xa40, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b1.rxcal_tx_iqcorr_idx_1_chn1" => { type => "field", addr => 0xa40, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b1.rxcal_tx_iqcorr_idx_0_chn1" => { type => "field", addr => 0xa40, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b1" => { type => "reg", addr => 0xa44, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_iqcorr_idx_15_8_b1.rxcal_tx_iqcorr_idx_15_chn1" => { type => "field", addr => 0xa44, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b1.rxcal_tx_iqcorr_idx_14_chn1" => { type => "field", addr => 0xa44, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b1.rxcal_tx_iqcorr_idx_13_chn1" => { type => "field", addr => 0xa44, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b1.rxcal_tx_iqcorr_idx_12_chn1" => { type => "field", addr => 0xa44, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b1.rxcal_tx_iqcorr_idx_11_chn1" => { type => "field", addr => 0xa44, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b1.rxcal_tx_iqcorr_idx_10_chn1" => { type => "field", addr => 0xa44, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b1.rxcal_tx_iqcorr_idx_9_chn1" => { type => "field", addr => 0xa44, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b1.rxcal_tx_iqcorr_idx_8_chn1" => { type => "field", addr => 0xa44, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b1" => { type => "reg", addr => 0xa48, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_iqcorr_idx_23_16_b1.rxcal_tx_iqcorr_idx_23_chn1" => { type => "field", addr => 0xa48, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b1.rxcal_tx_iqcorr_idx_22_chn1" => { type => "field", addr => 0xa48, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b1.rxcal_tx_iqcorr_idx_21_chn1" => { type => "field", addr => 0xa48, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b1.rxcal_tx_iqcorr_idx_20_chn1" => { type => "field", addr => 0xa48, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b1.rxcal_tx_iqcorr_idx_19_chn1" => { type => "field", addr => 0xa48, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b1.rxcal_tx_iqcorr_idx_18_chn1" => { type => "field", addr => 0xa48, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b1.rxcal_tx_iqcorr_idx_17_chn1" => { type => "field", addr => 0xa48, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b1.rxcal_tx_iqcorr_idx_16_chn1" => { type => "field", addr => 0xa48, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b1" => { type => "reg", addr => 0xa4c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_iqcorr_idx_31_24_b1.rxcal_tx_iqcorr_idx_31_chn1" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b1.rxcal_tx_iqcorr_idx_30_chn1" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b1.rxcal_tx_iqcorr_idx_29_chn1" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b1.rxcal_tx_iqcorr_idx_28_chn1" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b1.rxcal_tx_iqcorr_idx_27_chn1" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b1.rxcal_tx_iqcorr_idx_26_chn1" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b1.rxcal_tx_iqcorr_idx_25_chn1" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b1.rxcal_tx_iqcorr_idx_24_chn1" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_0_2_b1" => { type => "reg", addr => 0xa60, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_sm_sig_gain_table_0_2_b1.paprd_sm_sig_gain_2" => { type => "field", addr => 0xa60, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_0_2_b1.paprd_sm_sig_gain_1" => { type => "field", addr => 0xa60, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_0_2_b1.paprd_sm_sig_gain_0" => { type => "field", addr => 0xa60, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_3_5_b1" => { type => "reg", addr => 0xa64, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_sm_sig_gain_table_3_5_b1.paprd_sm_sig_gain_5" => { type => "field", addr => 0xa64, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_3_5_b1.paprd_sm_sig_gain_4" => { type => "field", addr => 0xa64, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_3_5_b1.paprd_sm_sig_gain_3" => { type => "field", addr => 0xa64, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_0_2_sec80_b1" => { type => "reg", addr => 0xa68, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_sm_sig_gain_table_0_2_sec80_b1.paprd_sm_sig_gain_sec80_2" => { type => "field", addr => 0xa68, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_0_2_sec80_b1.paprd_sm_sig_gain_sec80_1" => { type => "field", addr => 0xa68, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_0_2_sec80_b1.paprd_sm_sig_gain_sec80_0" => { type => "field", addr => 0xa68, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_peftbl_sel_b1" => { type => "reg", addr => 0xa6c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_peftbl_sel_b1.pef_half_rate_tb1_1" => { type => "field", addr => 0xa6c, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b1.pef_half_rate_tb0_1" => { type => "field", addr => 0xa6c, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b1.pef_table_sel_dpd5_b1" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b1.pef_table_sel_dpd4_b1" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b1.pef_table_sel_dpd3_b1" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b1.pef_table_sel_dpd2_b1" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b1.pef_table_sel_dpd1_b1" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b1.pef_table_sel_dpd0_b1" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set0_b1" => { type => "reg", addr => 0xa70, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set0_b1.tx_preemp_coef_tbl0_q_0_b1" => { type => "field", addr => 0xa70, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set0_b1.tx_preemp_coef_tbl0_i_0_b1" => { type => "field", addr => 0xa70, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set1_b1" => { type => "reg", addr => 0xa74, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set1_b1.tx_preemp_coef_tbl0_q_1_b1" => { type => "field", addr => 0xa74, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set1_b1.tx_preemp_coef_tbl0_i_1_b1" => { type => "field", addr => 0xa74, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set2_b1" => { type => "reg", addr => 0xa78, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set2_b1.tx_preemp_coef_tbl0_q_2_b1" => { type => "field", addr => 0xa78, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set2_b1.tx_preemp_coef_tbl0_i_2_b1" => { type => "field", addr => 0xa78, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set3_b1" => { type => "reg", addr => 0xa7c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set3_b1.tx_preemp_coef_tbl0_q_3_b1" => { type => "field", addr => 0xa7c, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set3_b1.tx_preemp_coef_tbl0_i_3_b1" => { type => "field", addr => 0xa7c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set4_b1" => { type => "reg", addr => 0xa80, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set4_b1.tx_preemp_coef_tbl0_q_4_b1" => { type => "field", addr => 0xa80, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set4_b1.tx_preemp_coef_tbl0_i_4_b1" => { type => "field", addr => 0xa80, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set5_b1" => { type => "reg", addr => 0xa84, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set5_b1.tx_preemp_coef_tbl0_q_5_b1" => { type => "field", addr => 0xa84, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set5_b1.tx_preemp_coef_tbl0_i_5_b1" => { type => "field", addr => 0xa84, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set6_b1" => { type => "reg", addr => 0xa88, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set6_b1.tx_preemp_coef_tbl0_q_6_b1" => { type => "field", addr => 0xa88, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set6_b1.tx_preemp_coef_tbl0_i_6_b1" => { type => "field", addr => 0xa88, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set7_b1" => { type => "reg", addr => 0xa8c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set7_b1.tx_preemp_coef_tbl0_q_7_b1" => { type => "field", addr => 0xa8c, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set7_b1.tx_preemp_coef_tbl0_i_7_b1" => { type => "field", addr => 0xa8c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set8_b1" => { type => "reg", addr => 0xa90, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set8_b1.tx_preemp_coef_tbl0_q_8_b1" => { type => "field", addr => 0xa90, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set8_b1.tx_preemp_coef_tbl0_i_8_b1" => { type => "field", addr => 0xa90, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set0_b1" => { type => "reg", addr => 0xa94, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set0_b1.tx_preemp_coef_tbl1_q_0_b1" => { type => "field", addr => 0xa94, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set0_b1.tx_preemp_coef_tbl1_i_0_b1" => { type => "field", addr => 0xa94, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set1_b1" => { type => "reg", addr => 0xa98, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set1_b1.tx_preemp_coef_tbl1_q_1_b1" => { type => "field", addr => 0xa98, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set1_b1.tx_preemp_coef_tbl1_i_1_b1" => { type => "field", addr => 0xa98, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set2_b1" => { type => "reg", addr => 0xa9c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set2_b1.tx_preemp_coef_tbl1_q_2_b1" => { type => "field", addr => 0xa9c, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set2_b1.tx_preemp_coef_tbl1_i_2_b1" => { type => "field", addr => 0xa9c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set3_b1" => { type => "reg", addr => 0xaa0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set3_b1.tx_preemp_coef_tbl1_q_3_b1" => { type => "field", addr => 0xaa0, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set3_b1.tx_preemp_coef_tbl1_i_3_b1" => { type => "field", addr => 0xaa0, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set4_b1" => { type => "reg", addr => 0xaa4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set4_b1.tx_preemp_coef_tbl1_q_4_b1" => { type => "field", addr => 0xaa4, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set4_b1.tx_preemp_coef_tbl1_i_4_b1" => { type => "field", addr => 0xaa4, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set5_b1" => { type => "reg", addr => 0xaa8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set5_b1.tx_preemp_coef_tbl1_q_5_b1" => { type => "field", addr => 0xaa8, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set5_b1.tx_preemp_coef_tbl1_i_5_b1" => { type => "field", addr => 0xaa8, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set6_b1" => { type => "reg", addr => 0xaac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set6_b1.tx_preemp_coef_tbl1_q_6_b1" => { type => "field", addr => 0xaac, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set6_b1.tx_preemp_coef_tbl1_i_6_b1" => { type => "field", addr => 0xaac, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set7_b1" => { type => "reg", addr => 0xab0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set7_b1.tx_preemp_coef_tbl1_q_7_b1" => { type => "field", addr => 0xab0, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set7_b1.tx_preemp_coef_tbl1_i_7_b1" => { type => "field", addr => 0xab0, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set8_b1" => { type => "reg", addr => 0xab4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set8_b1.tx_preemp_coef_tbl1_q_8_b1" => { type => "field", addr => 0xab4, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set8_b1.tx_preemp_coef_tbl1_i_8_b1" => { type => "field", addr => 0xab4, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_bw_table_dpdoff_b1" => { type => "reg", addr => 0xab8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_bw_table_dpdoff_b1.bw_table_2_bw80_sec80_1" => { type => "field", addr => 0xab8, width => 3, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_dpdoff_b1.bw_table_1_bw80_sec80_1" => { type => "field", addr => 0xab8, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_dpdoff_b1.bw_table_0_bw80_sec80_1" => { type => "field", addr => 0xab8, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_dpdoff_b1.bw_table_dpdoff_bw80_sec80_1" => { type => "field", addr => 0xab8, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_dpdoff_b1.bw_table_dpdoff_bw80_b1" => { type => "field", addr => 0xab8, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_dpdoff_b1.bw_table_dpdoff_bw40_b1" => { type => "field", addr => 0xab8, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_dpdoff_b1.bw_table_dpdoff_bw20_b1" => { type => "field", addr => 0xab8, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_dpdoff_b1.bw_table_dpdoff_bw10_b1" => { type => "field", addr => 0xab8, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_dpdoff_b1.bw_table_dpdoff_bw05_b1" => { type => "field", addr => 0xab8, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_1_0_b1" => { type => "reg", addr => 0xabc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_bw_table_1_0_b1.bw_table_1_bw80_b1" => { type => "field", addr => 0xabc, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_1_0_b1.bw_table_1_bw40_b1" => { type => "field", addr => 0xabc, width => 3, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_1_0_b1.bw_table_1_bw20_b1" => { type => "field", addr => 0xabc, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_1_0_b1.bw_table_1_bw10_b1" => { type => "field", addr => 0xabc, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_1_0_b1.bw_table_1_bw05_b1" => { type => "field", addr => 0xabc, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_1_0_b1.bw_table_0_bw80_b1" => { type => "field", addr => 0xabc, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_1_0_b1.bw_table_0_bw40_b1" => { type => "field", addr => 0xabc, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_1_0_b1.bw_table_0_bw20_b1" => { type => "field", addr => 0xabc, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_1_0_b1.bw_table_0_bw10_b1" => { type => "field", addr => 0xabc, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_1_0_b1.bw_table_0_bw05_b1" => { type => "field", addr => 0xabc, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_3_2_b1" => { type => "reg", addr => 0xac0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_bw_table_3_2_b1.bw_table_3_bw80_b1" => { type => "field", addr => 0xac0, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_3_2_b1.bw_table_3_bw40_b1" => { type => "field", addr => 0xac0, width => 3, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_3_2_b1.bw_table_3_bw20_b1" => { type => "field", addr => 0xac0, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_3_2_b1.bw_table_3_bw10_b1" => { type => "field", addr => 0xac0, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_3_2_b1.bw_table_3_bw05_b1" => { type => "field", addr => 0xac0, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_3_2_b1.bw_table_2_bw80_b1" => { type => "field", addr => 0xac0, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_3_2_b1.bw_table_2_bw40_b1" => { type => "field", addr => 0xac0, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_3_2_b1.bw_table_2_bw20_b1" => { type => "field", addr => 0xac0, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_3_2_b1.bw_table_2_bw10_b1" => { type => "field", addr => 0xac0, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_3_2_b1.bw_table_2_bw05_b1" => { type => "field", addr => 0xac0, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_5_4_b1" => { type => "reg", addr => 0xac4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_bw_table_5_4_b1.bw_table_5_bw80_b1" => { type => "field", addr => 0xac4, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_5_4_b1.bw_table_5_bw40_b1" => { type => "field", addr => 0xac4, width => 3, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_5_4_b1.bw_table_5_bw20_b1" => { type => "field", addr => 0xac4, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_5_4_b1.bw_table_5_bw10_b1" => { type => "field", addr => 0xac4, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_5_4_b1.bw_table_5_bw05_b1" => { type => "field", addr => 0xac4, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_5_4_b1.bw_table_4_bw80_b1" => { type => "field", addr => 0xac4, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_5_4_b1.bw_table_4_bw40_b1" => { type => "field", addr => 0xac4, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_5_4_b1.bw_table_4_bw20_b1" => { type => "field", addr => 0xac4, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_5_4_b1.bw_table_4_bw10_b1" => { type => "field", addr => 0xac4, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_5_4_b1.bw_table_4_bw05_b1" => { type => "field", addr => 0xac4, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_tx_notch_coef_b1" => { type => "reg", addr => 0xac8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_notch_coef_b1.tx_notch_coef_b1_1" => { type => "field", addr => 0xac8, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_coef_b1.tx_notch_coef_a2_1" => { type => "field", addr => 0xac8, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_coef_b1.tx_notch_coef_a1_1" => { type => "field", addr => 0xac8, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b1" => { type => "reg", addr => 0xacc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_notch_dpd_en_b1.paprd_notch_sel_dpd5_1" => { type => "field", addr => 0xacc, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b1.paprd_notch_sel_dpd4_1" => { type => "field", addr => 0xacc, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b1.paprd_notch_sel_dpd3_1" => { type => "field", addr => 0xacc, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b1.paprd_notch_sel_dpd2_1" => { type => "field", addr => 0xacc, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b1.paprd_notch_sel_dpd1_1" => { type => "field", addr => 0xacc, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b1.paprd_notch_sel_dpd0_1" => { type => "field", addr => 0xacc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_plybck_ctrl_0_b1" => { type => "reg", addr => 0xb00, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_plybck_ctrl_0_b1.tx_plybck_nsamples" => { type => "field", addr => 0xb00, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_0_b1.tx_plybck_start_addr" => { type => "field", addr => 0xb00, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_0_b1.tx_plybck_mix_disable" => { type => "field", addr => 0xb00, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_tx_plybck_ctrl_0_b1.tx_plybck_sw_start" => { type => "field", addr => 0xb00, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_0_b1.tx_plybck_dpd_train" => { type => "field", addr => 0xb00, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_0_b1.tx_plybck_rd_mode" => { type => "field", addr => 0xb00, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_0_b1.tx_plybck_s2_write" => { type => "field", addr => 0xb00, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_0_b1.tx_plybck_enable" => { type => "field", addr => 0xb00, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ibfcal_phasecorrection_chn1" => { type => "reg", addr => 0xb24, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_phasecorrection_chn1.ibfcal_phasecorr_pre_comp_q_1" => { type => "field", addr => 0xb24, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_phasecorrection_chn1.ibfcal_phasecorr_pre_comp_i_1" => { type => "field", addr => 0xb24, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 127 }, "BB_ibfcal_rffe_comp_g0_chn1" => { type => "reg", addr => 0xb28, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g0_chn1.ibfcal_comp_rffe_q_g0_xlna1_chn1" => { type => "field", addr => 0xb28, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g0_chn1.ibfcal_comp_rffe_i_g0_xlna1_chn1" => { type => "field", addr => 0xb28, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g0_chn1.ibfcal_comp_rffe_q_g0_xlna0_chn1" => { type => "field", addr => 0xb28, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g0_chn1.ibfcal_comp_rffe_i_g0_xlna0_chn1" => { type => "field", addr => 0xb28, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g1_chn1" => { type => "reg", addr => 0xb2c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g1_chn1.ibfcal_comp_rffe_q_g1_xlna1_chn1" => { type => "field", addr => 0xb2c, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g1_chn1.ibfcal_comp_rffe_i_g1_xlna1_chn1" => { type => "field", addr => 0xb2c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g1_chn1.ibfcal_comp_rffe_q_g1_xlna0_chn1" => { type => "field", addr => 0xb2c, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g1_chn1.ibfcal_comp_rffe_i_g1_xlna0_chn1" => { type => "field", addr => 0xb2c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g2_chn1" => { type => "reg", addr => 0xb30, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g2_chn1.ibfcal_comp_rffe_q_g2_xlna1_chn1" => { type => "field", addr => 0xb30, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g2_chn1.ibfcal_comp_rffe_i_g2_xlna1_chn1" => { type => "field", addr => 0xb30, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g2_chn1.ibfcal_comp_rffe_q_g2_xlna0_chn1" => { type => "field", addr => 0xb30, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g2_chn1.ibfcal_comp_rffe_i_g2_xlna0_chn1" => { type => "field", addr => 0xb30, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g3_chn1" => { type => "reg", addr => 0xb34, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g3_chn1.ibfcal_comp_rffe_q_g3_xlna1_chn1" => { type => "field", addr => 0xb34, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g3_chn1.ibfcal_comp_rffe_i_g3_xlna1_chn1" => { type => "field", addr => 0xb34, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g3_chn1.ibfcal_comp_rffe_q_g3_xlna0_chn1" => { type => "field", addr => 0xb34, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g3_chn1.ibfcal_comp_rffe_i_g3_xlna0_chn1" => { type => "field", addr => 0xb34, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g4_chn1" => { type => "reg", addr => 0xb38, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g4_chn1.ibfcal_comp_rffe_q_g4_xlna1_chn1" => { type => "field", addr => 0xb38, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g4_chn1.ibfcal_comp_rffe_i_g4_xlna1_chn1" => { type => "field", addr => 0xb38, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g4_chn1.ibfcal_comp_rffe_q_g4_xlna0_chn1" => { type => "field", addr => 0xb38, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g4_chn1.ibfcal_comp_rffe_i_g4_xlna0_chn1" => { type => "field", addr => 0xb38, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g5_chn1" => { type => "reg", addr => 0xb3c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g5_chn1.ibfcal_comp_rffe_q_g5_xlna1_chn1" => { type => "field", addr => 0xb3c, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g5_chn1.ibfcal_comp_rffe_i_g5_xlna1_chn1" => { type => "field", addr => 0xb3c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g5_chn1.ibfcal_comp_rffe_q_g5_xlna0_chn1" => { type => "field", addr => 0xb3c, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g5_chn1.ibfcal_comp_rffe_i_g5_xlna0_chn1" => { type => "field", addr => 0xb3c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g6_chn1" => { type => "reg", addr => 0xb40, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g6_chn1.ibfcal_comp_rffe_q_g6_xlna1_chn1" => { type => "field", addr => 0xb40, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g6_chn1.ibfcal_comp_rffe_i_g6_xlna1_chn1" => { type => "field", addr => 0xb40, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g6_chn1.ibfcal_comp_rffe_q_g6_xlna0_chn1" => { type => "field", addr => 0xb40, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g6_chn1.ibfcal_comp_rffe_i_g6_xlna0_chn1" => { type => "field", addr => 0xb40, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_normrx_rxiq_corr_coeff_b1" => { type => "reg", addr => 0xc00, width => 32, athEmulAttr => 0, acc => "RW", depth => 160, incr => 4 }, "BB_normrx_rxiq_corr_coeff_b1.normrx_iqc_coeff_table_chn1" => { type => "field", addr => 0xc00, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_mem_tab_b1" => { type => "reg", addr => 0xe80, width => 32, athEmulAttr => 0, acc => "RW", depth => 768, incr => 4 }, "BB_paprd_mem_tab_b1.paprd_mem" => { type => "field", addr => 0xe80, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_normtx_txiq_corr_coeff_b1" => { type => "reg", addr => 0x2ee0, width => 32, athEmulAttr => 0, acc => "RW", depth => 160, incr => 4 }, "BB_normtx_txiq_corr_coeff_b1.normtx_iqc_coeff_table_chn1" => { type => "field", addr => 0x2ee0, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chaninfo_tab_b1" => { type => "reg", addr => 0x3200, width => 32, athEmulAttr => 0, acc => "RW", depth => 256, incr => 4 }, "BB_chaninfo_tab_b1.chaninfo_word" => { type => "field", addr => 0x3200, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chn1_tables_dummy_1" => { type => "reg", addr => 0x8aac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chn1_tables_dummy_1.dummy1" => { type => "field", addr => 0x8aac, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, }; use constant tiered_sm_table_map_struct => { ################################################################### ## sm_table_map Register/Field definitions ################################################################### "BB_sm_tables_dummy1" => { type => "reg", addr => 0x0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sm_tables_dummy1.dummy1" => { type => "field", addr => 0x0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "BB_dc_dac_mem_b0" => { type => "reg", addr => 0x300, width => 32, athEmulAttr => 0, acc => "RW", depth => 52, incr => 4 }, "BB_dc_dac_mem_b0.dc_dac_setting" => { type => "field", addr => 0x300, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_txgain_sram" => { type => "reg", addr => 0x400, width => 32, athEmulAttr => 0, acc => "RW", depth => 96, incr => 4 }, "BB_tpc_txgain_sram.tpc_txgain_word" => { type => "field", addr => 0x400, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_plut_sram" => { type => "reg", addr => 0x580, width => 32, athEmulAttr => 0, acc => "RW", depth => 640, incr => 4 }, "BB_tpc_plut_sram.tpc_plut_word" => { type => "field", addr => 0x580, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_glut_sram" => { type => "reg", addr => 0xf80, width => 32, athEmulAttr => 0, acc => "RW", depth => 164, incr => 4 }, "BB_tpc_glut_sram.tpc_glut_word" => { type => "field", addr => 0xf80, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tpc_alut_sram" => { type => "reg", addr => 0x1210, width => 32, athEmulAttr => 0, acc => "RW", depth => 160, incr => 4 }, "BB_tpc_alut_sram.tpc_alut_word" => { type => "field", addr => 0x1210, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_0" => { type => "reg", addr => 0x1490, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_0.rxcal_tx_gain_table_0" => { type => "field", addr => 0x1490, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_1" => { type => "reg", addr => 0x1494, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_1.rxcal_tx_gain_table_1" => { type => "field", addr => 0x1494, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_2" => { type => "reg", addr => 0x1498, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_2.rxcal_tx_gain_table_2" => { type => "field", addr => 0x1498, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_3" => { type => "reg", addr => 0x149c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_3.rxcal_tx_gain_table_3" => { type => "field", addr => 0x149c, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_4" => { type => "reg", addr => 0x14a0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_4.rxcal_tx_gain_table_4" => { type => "field", addr => 0x14a0, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_5" => { type => "reg", addr => 0x14a4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_5.rxcal_tx_gain_table_5" => { type => "field", addr => 0x14a4, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_6" => { type => "reg", addr => 0x14a8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_6.rxcal_tx_gain_table_6" => { type => "field", addr => 0x14a8, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_7" => { type => "reg", addr => 0x14ac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_7.rxcal_tx_gain_table_7" => { type => "field", addr => 0x14ac, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_8" => { type => "reg", addr => 0x14b0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_8.rxcal_tx_gain_table_8" => { type => "field", addr => 0x14b0, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_9" => { type => "reg", addr => 0x14b4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_9.rxcal_tx_gain_table_9" => { type => "field", addr => 0x14b4, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_10" => { type => "reg", addr => 0x14b8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_10.rxcal_tx_gain_table_10" => { type => "field", addr => 0x14b8, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_11" => { type => "reg", addr => 0x14bc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_11.rxcal_tx_gain_table_11" => { type => "field", addr => 0x14bc, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_12" => { type => "reg", addr => 0x14c0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_12.rxcal_tx_gain_table_12" => { type => "field", addr => 0x14c0, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_13" => { type => "reg", addr => 0x14c4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_13.rxcal_tx_gain_table_13" => { type => "field", addr => 0x14c4, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_14" => { type => "reg", addr => 0x14c8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_14.rxcal_tx_gain_table_14" => { type => "field", addr => 0x14c8, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_15" => { type => "reg", addr => 0x14cc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_15.rxcal_tx_gain_table_15" => { type => "field", addr => 0x14cc, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_16" => { type => "reg", addr => 0x14d0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_16.rxcal_tx_gain_table_16" => { type => "field", addr => 0x14d0, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_17" => { type => "reg", addr => 0x14d4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_17.rxcal_tx_gain_table_17" => { type => "field", addr => 0x14d4, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_18" => { type => "reg", addr => 0x14d8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_18.rxcal_tx_gain_table_18" => { type => "field", addr => 0x14d8, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_19" => { type => "reg", addr => 0x14dc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_19.rxcal_tx_gain_table_19" => { type => "field", addr => 0x14dc, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_20" => { type => "reg", addr => 0x14e0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_20.rxcal_tx_gain_table_20" => { type => "field", addr => 0x14e0, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_21" => { type => "reg", addr => 0x14e4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_21.rxcal_tx_gain_table_21" => { type => "field", addr => 0x14e4, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_22" => { type => "reg", addr => 0x14e8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_22.rxcal_tx_gain_table_22" => { type => "field", addr => 0x14e8, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_23" => { type => "reg", addr => 0x14ec, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_23.rxcal_tx_gain_table_23" => { type => "field", addr => 0x14ec, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_24" => { type => "reg", addr => 0x14f0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_24.rxcal_tx_gain_table_24" => { type => "field", addr => 0x14f0, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_25" => { type => "reg", addr => 0x14f4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_25.rxcal_tx_gain_table_25" => { type => "field", addr => 0x14f4, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_26" => { type => "reg", addr => 0x14f8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_26.rxcal_tx_gain_table_26" => { type => "field", addr => 0x14f8, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_27" => { type => "reg", addr => 0x14fc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_27.rxcal_tx_gain_table_27" => { type => "field", addr => 0x14fc, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_28" => { type => "reg", addr => 0x1500, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_28.rxcal_tx_gain_table_28" => { type => "field", addr => 0x1500, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_29" => { type => "reg", addr => 0x1504, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_29.rxcal_tx_gain_table_29" => { type => "field", addr => 0x1504, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_30" => { type => "reg", addr => 0x1508, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_30.rxcal_tx_gain_table_30" => { type => "field", addr => 0x1508, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_gain_table_31" => { type => "reg", addr => 0x150c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_gain_table_31.rxcal_tx_gain_table_31" => { type => "field", addr => 0x150c, width => 21, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_0" => { type => "reg", addr => 0x1510, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_0.rxcal_gain_delta_db_table_0" => { type => "field", addr => 0x1510, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_0.rxcal_rx_gain_table_0" => { type => "field", addr => 0x1510, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_1" => { type => "reg", addr => 0x1514, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_1.rxcal_gain_delta_db_table_1" => { type => "field", addr => 0x1514, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_1.rxcal_rx_gain_table_1" => { type => "field", addr => 0x1514, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_2" => { type => "reg", addr => 0x1518, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_2.rxcal_gain_delta_db_table_2" => { type => "field", addr => 0x1518, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_2.rxcal_rx_gain_table_2" => { type => "field", addr => 0x1518, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_3" => { type => "reg", addr => 0x151c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_3.rxcal_gain_delta_db_table_3" => { type => "field", addr => 0x151c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_3.rxcal_rx_gain_table_3" => { type => "field", addr => 0x151c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_4" => { type => "reg", addr => 0x1520, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_4.rxcal_gain_delta_db_table_4" => { type => "field", addr => 0x1520, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_4.rxcal_rx_gain_table_4" => { type => "field", addr => 0x1520, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_5" => { type => "reg", addr => 0x1524, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_5.rxcal_gain_delta_db_table_5" => { type => "field", addr => 0x1524, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_5.rxcal_rx_gain_table_5" => { type => "field", addr => 0x1524, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_6" => { type => "reg", addr => 0x1528, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_6.rxcal_gain_delta_db_table_6" => { type => "field", addr => 0x1528, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_6.rxcal_rx_gain_table_6" => { type => "field", addr => 0x1528, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_7" => { type => "reg", addr => 0x152c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_7.rxcal_gain_delta_db_table_7" => { type => "field", addr => 0x152c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_7.rxcal_rx_gain_table_7" => { type => "field", addr => 0x152c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_8" => { type => "reg", addr => 0x1530, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_8.rxcal_gain_delta_db_table_8" => { type => "field", addr => 0x1530, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_8.rxcal_rx_gain_table_8" => { type => "field", addr => 0x1530, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_9" => { type => "reg", addr => 0x1534, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_9.rxcal_gain_delta_db_table_9" => { type => "field", addr => 0x1534, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_9.rxcal_rx_gain_table_9" => { type => "field", addr => 0x1534, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_10" => { type => "reg", addr => 0x1538, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_10.rxcal_gain_delta_db_table_10" => { type => "field", addr => 0x1538, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_10.rxcal_rx_gain_table_10" => { type => "field", addr => 0x1538, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_11" => { type => "reg", addr => 0x153c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_11.rxcal_gain_delta_db_table_11" => { type => "field", addr => 0x153c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_11.rxcal_rx_gain_table_11" => { type => "field", addr => 0x153c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_12" => { type => "reg", addr => 0x1540, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_12.rxcal_gain_delta_db_table_12" => { type => "field", addr => 0x1540, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_12.rxcal_rx_gain_table_12" => { type => "field", addr => 0x1540, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_13" => { type => "reg", addr => 0x1544, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_13.rxcal_gain_delta_db_table_13" => { type => "field", addr => 0x1544, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_13.rxcal_rx_gain_table_13" => { type => "field", addr => 0x1544, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_14" => { type => "reg", addr => 0x1548, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_14.rxcal_gain_delta_db_table_14" => { type => "field", addr => 0x1548, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_14.rxcal_rx_gain_table_14" => { type => "field", addr => 0x1548, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_15" => { type => "reg", addr => 0x154c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_rx_gain_table_15.rxcal_gain_delta_db_table_15" => { type => "field", addr => 0x154c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_rx_gain_table_15.rxcal_rx_gain_table_15" => { type => "field", addr => 0x154c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_sm_hc_preemp_lut" => { type => "reg", addr => 0x1550, width => 32, athEmulAttr => 0, acc => "RW", depth => 412, incr => 4 }, "BB_sm_hc_preemp_lut.sm_hc_preemp_lut_word" => { type => "field", addr => 0x1550, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_sm_tables_dummy2" => { type => "reg", addr => 0x1bc0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sm_tables_dummy2.dummy2" => { type => "field", addr => 0x1bc0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, }; use constant tiered_chn_table_map_struct => { ################################################################### ## chn_table_map Register/Field definitions ################################################################### "BB_paprd_power_at_am2am_cal_b0" => { type => "reg", addr => 0x80, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_power_at_am2am_cal_b0.paprd_power_at_am2am_cal_4_b0" => { type => "field", addr => 0x80, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_power_at_am2am_cal_b0.paprd_power_at_am2am_cal_3_b0" => { type => "field", addr => 0x80, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_power_at_am2am_cal_b0.paprd_power_at_am2am_cal_2_b0" => { type => "field", addr => 0x80, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_power_at_am2am_cal_b0.paprd_power_at_am2am_cal_1_b0" => { type => "field", addr => 0x80, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_power_at_am2am_cal_b0.paprd_power_at_am2am_cal_0_b0" => { type => "field", addr => 0x80, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_valid_obdb_b0" => { type => "reg", addr => 0x84, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_valid_obdb_b0.paprd_valid_obdb_4_b0" => { type => "field", addr => 0x84, width => 6, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_paprd_valid_obdb_b0.paprd_valid_obdb_3_b0" => { type => "field", addr => 0x84, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_paprd_valid_obdb_b0.paprd_valid_obdb_2_b0" => { type => "field", addr => 0x84, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_paprd_valid_obdb_b0.paprd_valid_obdb_1_b0" => { type => "field", addr => 0x84, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_paprd_valid_obdb_b0.paprd_valid_obdb_0_b0" => { type => "field", addr => 0x84, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x3f }, "BB_chn_tables_dummy_2" => { type => "reg", addr => 0x100, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chn_tables_dummy_2.dummy2" => { type => "field", addr => 0x100, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcorr_txpath_coef_b0" => { type => "reg", addr => 0x890, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "BB_txiqcorr_txpath_coef_b0.txiqcorr_txpath_coef_chn0" => { type => "field", addr => 0x890, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txiqcorr_rxpath_coef_b0" => { type => "reg", addr => 0x8d0, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "BB_txiqcorr_rxpath_coef_b0.txiqcorr_rxpath_coef_chn0" => { type => "field", addr => 0x8d0, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxiqcorr_rxpath_coef_b0" => { type => "reg", addr => 0x910, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "BB_rxiqcorr_rxpath_coef_b0.rxiqcorr_rxpath_coef_chn0" => { type => "field", addr => 0x910, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxiqcorr_txpath_coef_b0" => { type => "reg", addr => 0x950, width => 32, athEmulAttr => 0, acc => "RW", depth => 16, incr => 4 }, "BB_rxiqcorr_txpath_coef_b0.rxiqcorr_txpath_coef_chn0" => { type => "field", addr => 0x950, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b0" => { type => "reg", addr => 0xa40, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_iqcorr_idx_7_0_b0.rxcal_tx_iqcorr_idx_7_chn0" => { type => "field", addr => 0xa40, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b0.rxcal_tx_iqcorr_idx_6_chn0" => { type => "field", addr => 0xa40, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b0.rxcal_tx_iqcorr_idx_5_chn0" => { type => "field", addr => 0xa40, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b0.rxcal_tx_iqcorr_idx_4_chn0" => { type => "field", addr => 0xa40, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b0.rxcal_tx_iqcorr_idx_3_chn0" => { type => "field", addr => 0xa40, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b0.rxcal_tx_iqcorr_idx_2_chn0" => { type => "field", addr => 0xa40, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b0.rxcal_tx_iqcorr_idx_1_chn0" => { type => "field", addr => 0xa40, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_7_0_b0.rxcal_tx_iqcorr_idx_0_chn0" => { type => "field", addr => 0xa40, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b0" => { type => "reg", addr => 0xa44, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_iqcorr_idx_15_8_b0.rxcal_tx_iqcorr_idx_15_chn0" => { type => "field", addr => 0xa44, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b0.rxcal_tx_iqcorr_idx_14_chn0" => { type => "field", addr => 0xa44, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b0.rxcal_tx_iqcorr_idx_13_chn0" => { type => "field", addr => 0xa44, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b0.rxcal_tx_iqcorr_idx_12_chn0" => { type => "field", addr => 0xa44, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b0.rxcal_tx_iqcorr_idx_11_chn0" => { type => "field", addr => 0xa44, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b0.rxcal_tx_iqcorr_idx_10_chn0" => { type => "field", addr => 0xa44, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b0.rxcal_tx_iqcorr_idx_9_chn0" => { type => "field", addr => 0xa44, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_15_8_b0.rxcal_tx_iqcorr_idx_8_chn0" => { type => "field", addr => 0xa44, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b0" => { type => "reg", addr => 0xa48, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_iqcorr_idx_23_16_b0.rxcal_tx_iqcorr_idx_23_chn0" => { type => "field", addr => 0xa48, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b0.rxcal_tx_iqcorr_idx_22_chn0" => { type => "field", addr => 0xa48, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b0.rxcal_tx_iqcorr_idx_21_chn0" => { type => "field", addr => 0xa48, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b0.rxcal_tx_iqcorr_idx_20_chn0" => { type => "field", addr => 0xa48, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b0.rxcal_tx_iqcorr_idx_19_chn0" => { type => "field", addr => 0xa48, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b0.rxcal_tx_iqcorr_idx_18_chn0" => { type => "field", addr => 0xa48, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b0.rxcal_tx_iqcorr_idx_17_chn0" => { type => "field", addr => 0xa48, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_23_16_b0.rxcal_tx_iqcorr_idx_16_chn0" => { type => "field", addr => 0xa48, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b0" => { type => "reg", addr => 0xa4c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_rxcal_tx_iqcorr_idx_31_24_b0.rxcal_tx_iqcorr_idx_31_chn0" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b0.rxcal_tx_iqcorr_idx_30_chn0" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b0.rxcal_tx_iqcorr_idx_29_chn0" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b0.rxcal_tx_iqcorr_idx_28_chn0" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b0.rxcal_tx_iqcorr_idx_27_chn0" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b0.rxcal_tx_iqcorr_idx_26_chn0" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b0.rxcal_tx_iqcorr_idx_25_chn0" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_rxcal_tx_iqcorr_idx_31_24_b0.rxcal_tx_iqcorr_idx_24_chn0" => { type => "field", addr => 0xa4c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_7_0" => { type => "reg", addr => 0xa50, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txcal_rx_iqcorr_idx_7_0.txcal_rx_iqcorr_idx_7" => { type => "field", addr => 0xa50, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_7_0.txcal_rx_iqcorr_idx_6" => { type => "field", addr => 0xa50, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_7_0.txcal_rx_iqcorr_idx_5" => { type => "field", addr => 0xa50, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_7_0.txcal_rx_iqcorr_idx_4" => { type => "field", addr => 0xa50, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_7_0.txcal_rx_iqcorr_idx_3" => { type => "field", addr => 0xa50, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_7_0.txcal_rx_iqcorr_idx_2" => { type => "field", addr => 0xa50, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_7_0.txcal_rx_iqcorr_idx_1" => { type => "field", addr => 0xa50, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_7_0.txcal_rx_iqcorr_idx_0" => { type => "field", addr => 0xa50, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_15_8" => { type => "reg", addr => 0xa54, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txcal_rx_iqcorr_idx_15_8.txcal_rx_iqcorr_idx_15" => { type => "field", addr => 0xa54, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_15_8.txcal_rx_iqcorr_idx_14" => { type => "field", addr => 0xa54, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_15_8.txcal_rx_iqcorr_idx_13" => { type => "field", addr => 0xa54, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_15_8.txcal_rx_iqcorr_idx_12" => { type => "field", addr => 0xa54, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_15_8.txcal_rx_iqcorr_idx_11" => { type => "field", addr => 0xa54, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_15_8.txcal_rx_iqcorr_idx_10" => { type => "field", addr => 0xa54, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_15_8.txcal_rx_iqcorr_idx_9" => { type => "field", addr => 0xa54, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_15_8.txcal_rx_iqcorr_idx_8" => { type => "field", addr => 0xa54, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_23_16" => { type => "reg", addr => 0xa58, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txcal_rx_iqcorr_idx_23_16.txcal_rx_iqcorr_idx_23" => { type => "field", addr => 0xa58, width => 4, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_23_16.txcal_rx_iqcorr_idx_22" => { type => "field", addr => 0xa58, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_23_16.txcal_rx_iqcorr_idx_21" => { type => "field", addr => 0xa58, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_23_16.txcal_rx_iqcorr_idx_20" => { type => "field", addr => 0xa58, width => 4, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_23_16.txcal_rx_iqcorr_idx_19" => { type => "field", addr => 0xa58, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_23_16.txcal_rx_iqcorr_idx_18" => { type => "field", addr => 0xa58, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_23_16.txcal_rx_iqcorr_idx_17" => { type => "field", addr => 0xa58, width => 4, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_23_16.txcal_rx_iqcorr_idx_16" => { type => "field", addr => 0xa58, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_txcal_rx_iqcorr_idx_24" => { type => "reg", addr => 0xa5c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_txcal_rx_iqcorr_idx_24.txcal_rx_iqcorr_idx_24" => { type => "field", addr => 0xa5c, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_0_2_b0" => { type => "reg", addr => 0xa60, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_sm_sig_gain_table_0_2_b0.paprd_sm_sig_gain_2" => { type => "field", addr => 0xa60, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_0_2_b0.paprd_sm_sig_gain_1" => { type => "field", addr => 0xa60, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_0_2_b0.paprd_sm_sig_gain_0" => { type => "field", addr => 0xa60, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_3_5_b0" => { type => "reg", addr => 0xa64, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_sm_sig_gain_table_3_5_b0.paprd_sm_sig_gain_5" => { type => "field", addr => 0xa64, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_3_5_b0.paprd_sm_sig_gain_4" => { type => "field", addr => 0xa64, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_sm_sig_gain_table_3_5_b0.paprd_sm_sig_gain_3" => { type => "field", addr => 0xa64, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_peftbl_sel_b0" => { type => "reg", addr => 0xa6c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_peftbl_sel_b0.pef_half_rate_tb1_0" => { type => "field", addr => 0xa6c, width => 1, bitOffset => 13, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b0.pef_half_rate_tb0_0" => { type => "field", addr => 0xa6c, width => 1, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b0.pef_table_sel_dpd5_b0" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b0.pef_table_sel_dpd4_b0" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b0.pef_table_sel_dpd3_b0" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b0.pef_table_sel_dpd2_b0" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b0.pef_table_sel_dpd1_b0" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_peftbl_sel_b0.pef_table_sel_dpd0_b0" => { type => "field", addr => 0xa6c, width => 2, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set0_b0" => { type => "reg", addr => 0xa70, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set0_b0.tx_preemp_coef_tbl0_q_0_b0" => { type => "field", addr => 0xa70, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set0_b0.tx_preemp_coef_tbl0_i_0_b0" => { type => "field", addr => 0xa70, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set1_b0" => { type => "reg", addr => 0xa74, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set1_b0.tx_preemp_coef_tbl0_q_1_b0" => { type => "field", addr => 0xa74, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set1_b0.tx_preemp_coef_tbl0_i_1_b0" => { type => "field", addr => 0xa74, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set2_b0" => { type => "reg", addr => 0xa78, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set2_b0.tx_preemp_coef_tbl0_q_2_b0" => { type => "field", addr => 0xa78, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set2_b0.tx_preemp_coef_tbl0_i_2_b0" => { type => "field", addr => 0xa78, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set3_b0" => { type => "reg", addr => 0xa7c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set3_b0.tx_preemp_coef_tbl0_q_3_b0" => { type => "field", addr => 0xa7c, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set3_b0.tx_preemp_coef_tbl0_i_3_b0" => { type => "field", addr => 0xa7c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set4_b0" => { type => "reg", addr => 0xa80, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set4_b0.tx_preemp_coef_tbl0_q_4_b0" => { type => "field", addr => 0xa80, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set4_b0.tx_preemp_coef_tbl0_i_4_b0" => { type => "field", addr => 0xa80, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set5_b0" => { type => "reg", addr => 0xa84, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set5_b0.tx_preemp_coef_tbl0_q_5_b0" => { type => "field", addr => 0xa84, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set5_b0.tx_preemp_coef_tbl0_i_5_b0" => { type => "field", addr => 0xa84, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set6_b0" => { type => "reg", addr => 0xa88, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set6_b0.tx_preemp_coef_tbl0_q_6_b0" => { type => "field", addr => 0xa88, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set6_b0.tx_preemp_coef_tbl0_i_6_b0" => { type => "field", addr => 0xa88, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set7_b0" => { type => "reg", addr => 0xa8c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set7_b0.tx_preemp_coef_tbl0_q_7_b0" => { type => "field", addr => 0xa8c, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set7_b0.tx_preemp_coef_tbl0_i_7_b0" => { type => "field", addr => 0xa8c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set8_b0" => { type => "reg", addr => 0xa90, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl0_set8_b0.tx_preemp_coef_tbl0_q_8_b0" => { type => "field", addr => 0xa90, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl0_set8_b0.tx_preemp_coef_tbl0_i_8_b0" => { type => "field", addr => 0xa90, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set0_b0" => { type => "reg", addr => 0xa94, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set0_b0.tx_preemp_coef_tbl1_q_0_b0" => { type => "field", addr => 0xa94, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set0_b0.tx_preemp_coef_tbl1_i_0_b0" => { type => "field", addr => 0xa94, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set1_b0" => { type => "reg", addr => 0xa98, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set1_b0.tx_preemp_coef_tbl1_q_1_b0" => { type => "field", addr => 0xa98, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set1_b0.tx_preemp_coef_tbl1_i_1_b0" => { type => "field", addr => 0xa98, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set2_b0" => { type => "reg", addr => 0xa9c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set2_b0.tx_preemp_coef_tbl1_q_2_b0" => { type => "field", addr => 0xa9c, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set2_b0.tx_preemp_coef_tbl1_i_2_b0" => { type => "field", addr => 0xa9c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set3_b0" => { type => "reg", addr => 0xaa0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set3_b0.tx_preemp_coef_tbl1_q_3_b0" => { type => "field", addr => 0xaa0, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set3_b0.tx_preemp_coef_tbl1_i_3_b0" => { type => "field", addr => 0xaa0, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set4_b0" => { type => "reg", addr => 0xaa4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set4_b0.tx_preemp_coef_tbl1_q_4_b0" => { type => "field", addr => 0xaa4, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set4_b0.tx_preemp_coef_tbl1_i_4_b0" => { type => "field", addr => 0xaa4, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set5_b0" => { type => "reg", addr => 0xaa8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set5_b0.tx_preemp_coef_tbl1_q_5_b0" => { type => "field", addr => 0xaa8, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set5_b0.tx_preemp_coef_tbl1_i_5_b0" => { type => "field", addr => 0xaa8, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set6_b0" => { type => "reg", addr => 0xaac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set6_b0.tx_preemp_coef_tbl1_q_6_b0" => { type => "field", addr => 0xaac, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set6_b0.tx_preemp_coef_tbl1_i_6_b0" => { type => "field", addr => 0xaac, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set7_b0" => { type => "reg", addr => 0xab0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set7_b0.tx_preemp_coef_tbl1_q_7_b0" => { type => "field", addr => 0xab0, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set7_b0.tx_preemp_coef_tbl1_i_7_b0" => { type => "field", addr => 0xab0, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set8_b0" => { type => "reg", addr => 0xab4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_preemp_coef_tbl1_set8_b0.tx_preemp_coef_tbl1_q_8_b0" => { type => "field", addr => 0xab4, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_preemp_coef_tbl1_set8_b0.tx_preemp_coef_tbl1_i_8_b0" => { type => "field", addr => 0xab4, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_paprd_bw_table_dpdoff_b0" => { type => "reg", addr => 0xab8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_bw_table_dpdoff_b0.bw_table_dpdoff_bw80_b0" => { type => "field", addr => 0xab8, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_dpdoff_b0.bw_table_dpdoff_bw40_b0" => { type => "field", addr => 0xab8, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_dpdoff_b0.bw_table_dpdoff_bw20_b0" => { type => "field", addr => 0xab8, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_dpdoff_b0.bw_table_dpdoff_bw10_b0" => { type => "field", addr => 0xab8, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_dpdoff_b0.bw_table_dpdoff_bw05_b0" => { type => "field", addr => 0xab8, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_1_0_b0" => { type => "reg", addr => 0xabc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_bw_table_1_0_b0.bw_table_1_bw80_b0" => { type => "field", addr => 0xabc, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_1_0_b0.bw_table_1_bw40_b0" => { type => "field", addr => 0xabc, width => 3, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_1_0_b0.bw_table_1_bw20_b0" => { type => "field", addr => 0xabc, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_1_0_b0.bw_table_1_bw10_b0" => { type => "field", addr => 0xabc, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_1_0_b0.bw_table_1_bw05_b0" => { type => "field", addr => 0xabc, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_1_0_b0.bw_table_0_bw80_b0" => { type => "field", addr => 0xabc, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_1_0_b0.bw_table_0_bw40_b0" => { type => "field", addr => 0xabc, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_1_0_b0.bw_table_0_bw20_b0" => { type => "field", addr => 0xabc, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_1_0_b0.bw_table_0_bw10_b0" => { type => "field", addr => 0xabc, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_1_0_b0.bw_table_0_bw05_b0" => { type => "field", addr => 0xabc, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_3_2_b0" => { type => "reg", addr => 0xac0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_bw_table_3_2_b0.bw_table_3_bw80_b0" => { type => "field", addr => 0xac0, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_3_2_b0.bw_table_3_bw40_b0" => { type => "field", addr => 0xac0, width => 3, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_3_2_b0.bw_table_3_bw20_b0" => { type => "field", addr => 0xac0, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_3_2_b0.bw_table_3_bw10_b0" => { type => "field", addr => 0xac0, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_3_2_b0.bw_table_3_bw05_b0" => { type => "field", addr => 0xac0, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_3_2_b0.bw_table_2_bw80_b0" => { type => "field", addr => 0xac0, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_3_2_b0.bw_table_2_bw40_b0" => { type => "field", addr => 0xac0, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_3_2_b0.bw_table_2_bw20_b0" => { type => "field", addr => 0xac0, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_3_2_b0.bw_table_2_bw10_b0" => { type => "field", addr => 0xac0, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_3_2_b0.bw_table_2_bw05_b0" => { type => "field", addr => 0xac0, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_5_4_b0" => { type => "reg", addr => 0xac4, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_bw_table_5_4_b0.bw_table_5_bw80_b0" => { type => "field", addr => 0xac4, width => 3, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_5_4_b0.bw_table_5_bw40_b0" => { type => "field", addr => 0xac4, width => 3, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_5_4_b0.bw_table_5_bw20_b0" => { type => "field", addr => 0xac4, width => 3, bitOffset => 22, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_5_4_b0.bw_table_5_bw10_b0" => { type => "field", addr => 0xac4, width => 3, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_5_4_b0.bw_table_5_bw05_b0" => { type => "field", addr => 0xac4, width => 3, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_bw_table_5_4_b0.bw_table_4_bw80_b0" => { type => "field", addr => 0xac4, width => 3, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 3 }, "BB_paprd_bw_table_5_4_b0.bw_table_4_bw40_b0" => { type => "field", addr => 0xac4, width => 3, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_paprd_bw_table_5_4_b0.bw_table_4_bw20_b0" => { type => "field", addr => 0xac4, width => 3, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_paprd_bw_table_5_4_b0.bw_table_4_bw10_b0" => { type => "field", addr => 0xac4, width => 3, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_bw_table_5_4_b0.bw_table_4_bw05_b0" => { type => "field", addr => 0xac4, width => 3, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_tx_notch_coef_b0" => { type => "reg", addr => 0xac8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_notch_coef_b0.tx_notch_coef_b1_0" => { type => "field", addr => 0xac8, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_coef_b0.tx_notch_coef_a2_0" => { type => "field", addr => 0xac8, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_coef_b0.tx_notch_coef_a1_0" => { type => "field", addr => 0xac8, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b0" => { type => "reg", addr => 0xacc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_notch_dpd_en_b0.paprd_notch_sel_dpd5_0" => { type => "field", addr => 0xacc, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b0.paprd_notch_sel_dpd4_0" => { type => "field", addr => 0xacc, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b0.paprd_notch_sel_dpd3_0" => { type => "field", addr => 0xacc, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b0.paprd_notch_sel_dpd2_0" => { type => "field", addr => 0xacc, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b0.paprd_notch_sel_dpd1_0" => { type => "field", addr => 0xacc, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_notch_dpd_en_b0.paprd_notch_sel_dpd0_0" => { type => "field", addr => 0xacc, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_tx_plybck_ctrl_0_b0" => { type => "reg", addr => 0xb00, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_plybck_ctrl_0_b0.tx_plybck_nsamples" => { type => "field", addr => 0xb00, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "BB_tx_plybck_ctrl_0_b0.tx_plybck_start_addr" => { type => "field", addr => 0xb00, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "BB_tx_plybck_ctrl_0_b0.tx_plybck_mix_disable" => { type => "field", addr => 0xb00, width => 1, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_tx_plybck_ctrl_0_b0.tx_plybck_sw_start" => { type => "field", addr => 0xb00, width => 1, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_0_b0.tx_plybck_dpd_train" => { type => "field", addr => 0xb00, width => 1, bitOffset => 4, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_0_b0.tx_plybck_rd_mode" => { type => "field", addr => 0xb00, width => 2, bitOffset => 2, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_0_b0.tx_plybck_s2_write" => { type => "field", addr => 0xb00, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_0_b0.tx_plybck_enable" => { type => "field", addr => 0xb00, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_plybck_ctrl_1_b0" => { type => "reg", addr => 0xb04, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_plybck_ctrl_1_b0.tx_plybck_start_delay" => { type => "field", addr => 0xb04, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x01 }, "BB_ibfcal_cntl" => { type => "reg", addr => 0xb08, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_cntl.cf_ibfcal_force_idx_val" => { type => "field", addr => 0xb08, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_cntl.cf_ibfcal_force_idx_en" => { type => "field", addr => 0xb08, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ibfcal_cntl.cf_ibfcal_corr_start_idx" => { type => "field", addr => 0xb08, width => 7, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 48 }, "BB_ibfcal_cntl.cf_ibfcal_corr_len" => { type => "field", addr => 0xb08, width => 4, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 4 }, "BB_ibfcal_cntl.cf_ibfcal_num_corr_stages" => { type => "field", addr => 0xb08, width => 3, bitOffset => 5, athEmulAttr => 0, acc => "RW", resetVal => 5 }, "BB_ibfcal_cntl.cf_ibfcal_min_loopback_del" => { type => "field", addr => 0xb08, width => 5, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 03 }, "BB_ibfcal_stat_step1" => { type => "reg", addr => 0xb0c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_stat_step1.ibfcal_rx_gain_setting_step1" => { type => "field", addr => 0xb0c, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step1.ibfcal_phase_meas_step1" => { type => "field", addr => 0xb0c, width => 11, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step1.ibfcal_step1_done" => { type => "field", addr => 0xb0c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ibfcal_stat_step2" => { type => "reg", addr => 0xb10, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_stat_step2.ibfcal_rx_gain_setting_step2" => { type => "field", addr => 0xb10, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step2.ibfcal_phase_meas_step2" => { type => "field", addr => 0xb10, width => 11, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step2.ibfcal_step2_done" => { type => "field", addr => 0xb10, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ibfcal_stat_step3" => { type => "reg", addr => 0xb14, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_stat_step3.ibfcal_rx_gain_setting_step3" => { type => "field", addr => 0xb14, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step3.ibfcal_phase_meas_step3" => { type => "field", addr => 0xb14, width => 11, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step3.ibfcal_step3_done" => { type => "field", addr => 0xb14, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ibfcal_stat_step4" => { type => "reg", addr => 0xb18, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_stat_step4.ibfcal_rx_gain_setting_step4" => { type => "field", addr => 0xb18, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step4.ibfcal_phase_meas_step4" => { type => "field", addr => 0xb18, width => 11, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step4.ibfcal_step4_done" => { type => "field", addr => 0xb18, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ibfcal_stat_step5" => { type => "reg", addr => 0xb1c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_stat_step5.ibfcal_rx_gain_setting_step5" => { type => "field", addr => 0xb1c, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step5.ibfcal_phase_meas_step5" => { type => "field", addr => 0xb1c, width => 11, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step5.ibfcal_step5_done" => { type => "field", addr => 0xb1c, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ibfcal_stat_step6" => { type => "reg", addr => 0xb20, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_stat_step6.ibfcal_rx_gain_setting_step6" => { type => "field", addr => 0xb20, width => 8, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step6.ibfcal_phase_meas_step6" => { type => "field", addr => 0xb20, width => 11, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0 }, "BB_ibfcal_stat_step6.ibfcal_step6_done" => { type => "field", addr => 0xb20, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_ibfcal_phasecorrection_chn0" => { type => "reg", addr => 0xb24, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_phasecorrection_chn0.ibfcal_phasecorr_pre_comp_q_0" => { type => "field", addr => 0xb24, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_phasecorrection_chn0.ibfcal_phasecorr_pre_comp_i_0" => { type => "field", addr => 0xb24, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 127 }, "BB_ibfcal_rffe_comp_g0_chn0" => { type => "reg", addr => 0xb28, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g0_chn0.ibfcal_comp_rffe_q_g0_xlna1_chn0" => { type => "field", addr => 0xb28, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g0_chn0.ibfcal_comp_rffe_i_g0_xlna1_chn0" => { type => "field", addr => 0xb28, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g0_chn0.ibfcal_comp_rffe_q_g0_xlna0_chn0" => { type => "field", addr => 0xb28, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g0_chn0.ibfcal_comp_rffe_i_g0_xlna0_chn0" => { type => "field", addr => 0xb28, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g1_chn0" => { type => "reg", addr => 0xb2c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g1_chn0.ibfcal_comp_rffe_q_g1_xlna1_chn0" => { type => "field", addr => 0xb2c, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g1_chn0.ibfcal_comp_rffe_i_g1_xlna1_chn0" => { type => "field", addr => 0xb2c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g1_chn0.ibfcal_comp_rffe_q_g1_xlna0_chn0" => { type => "field", addr => 0xb2c, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g1_chn0.ibfcal_comp_rffe_i_g1_xlna0_chn0" => { type => "field", addr => 0xb2c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g2_chn0" => { type => "reg", addr => 0xb30, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g2_chn0.ibfcal_comp_rffe_q_g2_xlna1_chn0" => { type => "field", addr => 0xb30, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g2_chn0.ibfcal_comp_rffe_i_g2_xlna1_chn0" => { type => "field", addr => 0xb30, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g2_chn0.ibfcal_comp_rffe_q_g2_xlna0_chn0" => { type => "field", addr => 0xb30, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g2_chn0.ibfcal_comp_rffe_i_g2_xlna0_chn0" => { type => "field", addr => 0xb30, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g3_chn0" => { type => "reg", addr => 0xb34, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g3_chn0.ibfcal_comp_rffe_q_g3_xlna1_chn0" => { type => "field", addr => 0xb34, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g3_chn0.ibfcal_comp_rffe_i_g3_xlna1_chn0" => { type => "field", addr => 0xb34, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g3_chn0.ibfcal_comp_rffe_q_g3_xlna0_chn0" => { type => "field", addr => 0xb34, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g3_chn0.ibfcal_comp_rffe_i_g3_xlna0_chn0" => { type => "field", addr => 0xb34, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g4_chn0" => { type => "reg", addr => 0xb38, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g4_chn0.ibfcal_comp_rffe_q_g4_xlna1_chn0" => { type => "field", addr => 0xb38, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g4_chn0.ibfcal_comp_rffe_i_g4_xlna1_chn0" => { type => "field", addr => 0xb38, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g4_chn0.ibfcal_comp_rffe_q_g4_xlna0_chn0" => { type => "field", addr => 0xb38, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g4_chn0.ibfcal_comp_rffe_i_g4_xlna0_chn0" => { type => "field", addr => 0xb38, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g5_chn0" => { type => "reg", addr => 0xb3c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g5_chn0.ibfcal_comp_rffe_q_g5_xlna1_chn0" => { type => "field", addr => 0xb3c, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g5_chn0.ibfcal_comp_rffe_i_g5_xlna1_chn0" => { type => "field", addr => 0xb3c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g5_chn0.ibfcal_comp_rffe_q_g5_xlna0_chn0" => { type => "field", addr => 0xb3c, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g5_chn0.ibfcal_comp_rffe_i_g5_xlna0_chn0" => { type => "field", addr => 0xb3c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g6_chn0" => { type => "reg", addr => 0xb40, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_rffe_comp_g6_chn0.ibfcal_comp_rffe_q_g6_xlna1_chn0" => { type => "field", addr => 0xb40, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g6_chn0.ibfcal_comp_rffe_i_g6_xlna1_chn0" => { type => "field", addr => 0xb40, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_rffe_comp_g6_chn0.ibfcal_comp_rffe_q_g6_xlna0_chn0" => { type => "field", addr => 0xb40, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_rffe_comp_g6_chn0.ibfcal_comp_rffe_i_g6_xlna0_chn0" => { type => "field", addr => 0xb40, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_gm_tia_comp_g1" => { type => "reg", addr => 0xb44, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_gm_tia_comp_g1.ibfcal_comp_tia_q_g1" => { type => "field", addr => 0xb44, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_gm_tia_comp_g1.ibfcal_comp_tia_i_g1" => { type => "field", addr => 0xb44, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_gm_tia_comp_g1.ibfcal_comp_gm_q_g1" => { type => "field", addr => 0xb44, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_gm_tia_comp_g1.ibfcal_comp_gm_i_g1" => { type => "field", addr => 0xb44, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_gm_tia_comp_g2" => { type => "reg", addr => 0xb48, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_gm_tia_comp_g2.ibfcal_comp_tia_q_g2" => { type => "field", addr => 0xb48, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_gm_tia_comp_g2.ibfcal_comp_tia_i_g2" => { type => "field", addr => 0xb48, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_gm_tia_comp_g2.ibfcal_comp_gm_q_g2" => { type => "field", addr => 0xb48, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_gm_tia_comp_g2.ibfcal_comp_gm_i_g2" => { type => "field", addr => 0xb48, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_gm_tia_comp_g3" => { type => "reg", addr => 0xb4c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_ibfcal_gm_tia_comp_g3.ibfcal_comp_tia_q_g3" => { type => "field", addr => 0xb4c, width => 6, bitOffset => 18, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_gm_tia_comp_g3.ibfcal_comp_tia_i_g3" => { type => "field", addr => 0xb4c, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_ibfcal_gm_tia_comp_g3.ibfcal_comp_gm_q_g3" => { type => "field", addr => 0xb4c, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0 }, "BB_ibfcal_gm_tia_comp_g3.ibfcal_comp_gm_i_g3" => { type => "field", addr => 0xb4c, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 31 }, "BB_normrx_rxiq_corr_coeff_b0" => { type => "reg", addr => 0xc00, width => 32, athEmulAttr => 0, acc => "RW", depth => 160, incr => 4 }, "BB_normrx_rxiq_corr_coeff_b0.normrx_iqc_coeff_table_chn0" => { type => "field", addr => 0xc00, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_mem_tab_b0" => { type => "reg", addr => 0xe80, width => 32, athEmulAttr => 0, acc => "RW", depth => 768, incr => 4 }, "BB_paprd_mem_tab_b0.paprd_mem" => { type => "field", addr => 0xe80, width => 24, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_adcsat" => { type => "reg", addr => 0x23fc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_adcsat.paprd_adcsat_thrl" => { type => "field", addr => 0x23fc, width => 9, bitOffset => 21, athEmulAttr => 0, acc => "RW", resetVal => 0x101 }, "BB_paprd_train_adcsat.paprd_adcsat_thrh" => { type => "field", addr => 0x23fc, width => 9, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 254 }, "BB_paprd_train_adcsat.paprd_adcsat_icount" => { type => "field", addr => 0x23fc, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 16 }, "BB_paprd_train_adcsat.paprd_adcsat_num_thr" => { type => "field", addr => 0x23fc, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 6 }, "BB_paprd_trainer_cntl1" => { type => "reg", addr => 0x2400, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_trainer_cntl1.cf_paprd_train_mode" => { type => "field", addr => 0x2400, width => 1, bitOffset => 31, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl1.cf_paprd_train_segment" => { type => "field", addr => 0x2400, width => 1, bitOffset => 30, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl1.cf_paprd_enable_adc_fifo" => { type => "field", addr => 0x2400, width => 1, bitOffset => 27, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl1.cf_paprd_forced_fine_idx" => { type => "field", addr => 0x2400, width => 2, bitOffset => 25, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl1.cf_paprd_forced_coarse_idx" => { type => "field", addr => 0x2400, width => 5, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl1.cf_paprd_corr_force" => { type => "field", addr => 0x2400, width => 1, bitOffset => 19, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl1.cf_paprd_adc_shift" => { type => "field", addr => 0x2400, width => 2, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl1.cf_paprd_dc_corr_enable" => { type => "field", addr => 0x2400, width => 1, bitOffset => 11, athEmulAttr => 0, acc => "RW", resetVal => 0x1 }, "BB_paprd_trainer_cntl1.cf_paprd_tx_gain_force" => { type => "field", addr => 0x2400, width => 1, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl1.cf_paprd_rx_bb_gain_force" => { type => "field", addr => 0x2400, width => 1, bitOffset => 9, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl1.cf_paprd_iqcorr_enable" => { type => "field", addr => 0x2400, width => 1, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl1.cf_paprd_agc2_settling" => { type => "field", addr => 0x2400, width => 7, bitOffset => 1, athEmulAttr => 0, acc => "RW", resetVal => 28 }, "BB_paprd_trainer_cntl1.cf_paprd_train_enable" => { type => "field", addr => 0x2400, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl2" => { type => "reg", addr => 0x2404, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_trainer_cntl2.cf_paprd_init_rx_bb_gain" => { type => "field", addr => 0x2404, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x89 }, "BB_paprd_trainer_cntl3" => { type => "reg", addr => 0x2408, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_trainer_cntl3.cf_paprd_bbtxmix_disable" => { type => "field", addr => 0x2408, width => 1, bitOffset => 29, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl3.cf_paprd_dbg_en" => { type => "field", addr => 0x2408, width => 1, bitOffset => 28, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl3.cf_paprd_fine_corr_len" => { type => "field", addr => 0x2408, width => 4, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_paprd_trainer_cntl3.cf_paprd_coarse_corr_len" => { type => "field", addr => 0x2408, width => 4, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 2 }, "BB_paprd_trainer_cntl3.cf_paprd_num_corr_stages" => { type => "field", addr => 0x2408, width => 3, bitOffset => 17, athEmulAttr => 0, acc => "RW", resetVal => 7 }, "BB_paprd_trainer_cntl3.cf_paprd_min_loopback_del" => { type => "field", addr => 0x2408, width => 5, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 03 }, "BB_paprd_trainer_cntl3.cf_paprd_quick_drop" => { type => "field", addr => 0x2408, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x3D }, "BB_paprd_trainer_cntl4" => { type => "reg", addr => 0x240c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_trainer_cntl4.cf_paprd_agc2_max_gain" => { type => "field", addr => 0x240c, width => 6, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 42 }, "BB_paprd_trainer_cntl4.cf_paprd_num_train_samples" => { type => "field", addr => 0x240c, width => 10, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 64 }, "BB_paprd_trainer_cntl4.cf_paprd_safety_delta" => { type => "field", addr => 0x240c, width => 4, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_cntl4.cf_paprd_min_corr" => { type => "field", addr => 0x240c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 400 }, "BB_paprd_trainer_stat1" => { type => "reg", addr => 0x2410, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_trainer_stat1.paprd_agc2_sized" => { type => "field", addr => 0x2410, width => 1, bitOffset => 18, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_trainer_stat1.paprd_agc2_pwr" => { type => "field", addr => 0x2410, width => 8, bitOffset => 10, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_trainer_stat1.paprd_rx_gain_idx" => { type => "field", addr => 0x2410, width => 6, bitOffset => 4, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_trainer_stat1.paprd_train_active" => { type => "field", addr => 0x2410, width => 1, bitOffset => 3, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_trainer_stat1.paprd_corr_err" => { type => "field", addr => 0x2410, width => 1, bitOffset => 2, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_trainer_stat1.paprd_train_incomplete" => { type => "field", addr => 0x2410, width => 1, bitOffset => 1, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_trainer_stat1.paprd_train_done" => { type => "field", addr => 0x2410, width => 1, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_trainer_stat2" => { type => "reg", addr => 0x2414, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_trainer_stat2.paprd_coarse_val" => { type => "field", addr => 0x2414, width => 16, bitOffset => 16, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_trainer_stat2.paprd_fine_val" => { type => "field", addr => 0x2414, width => 16, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_trainer_stat3" => { type => "reg", addr => 0x2418, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_trainer_stat3.paprd_coarse_idx" => { type => "field", addr => 0x2418, width => 5, bitOffset => 22, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_trainer_stat3.paprd_fine_idx" => { type => "field", addr => 0x2418, width => 2, bitOffset => 20, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_trainer_stat3.paprd_train_samples_cnt" => { type => "field", addr => 0x2418, width => 20, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_train_gain_set0" => { type => "reg", addr => 0x241c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set0.paprd_gain_tbl_2" => { type => "field", addr => 0x241c, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set0.paprd_gain_tbl_1" => { type => "field", addr => 0x241c, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set0.paprd_gain_tbl_0" => { type => "field", addr => 0x241c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set1" => { type => "reg", addr => 0x2420, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set1.paprd_gain_tbl_5" => { type => "field", addr => 0x2420, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set1.paprd_gain_tbl_4" => { type => "field", addr => 0x2420, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set1.paprd_gain_tbl_3" => { type => "field", addr => 0x2420, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set2" => { type => "reg", addr => 0x2424, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set2.paprd_gain_tbl_8" => { type => "field", addr => 0x2424, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set2.paprd_gain_tbl_7" => { type => "field", addr => 0x2424, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set2.paprd_gain_tbl_6" => { type => "field", addr => 0x2424, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set3" => { type => "reg", addr => 0x2428, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set3.paprd_gain_tbl_11" => { type => "field", addr => 0x2428, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set3.paprd_gain_tbl_10" => { type => "field", addr => 0x2428, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set3.paprd_gain_tbl_9" => { type => "field", addr => 0x2428, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set4" => { type => "reg", addr => 0x242c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set4.paprd_gain_tbl_14" => { type => "field", addr => 0x242c, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set4.paprd_gain_tbl_13" => { type => "field", addr => 0x242c, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set4.paprd_gain_tbl_12" => { type => "field", addr => 0x242c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set5" => { type => "reg", addr => 0x2430, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set5.paprd_gain_tbl_17" => { type => "field", addr => 0x2430, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set5.paprd_gain_tbl_16" => { type => "field", addr => 0x2430, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set5.paprd_gain_tbl_15" => { type => "field", addr => 0x2430, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set6" => { type => "reg", addr => 0x2434, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set6.paprd_gain_tbl_20" => { type => "field", addr => 0x2434, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set6.paprd_gain_tbl_19" => { type => "field", addr => 0x2434, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set6.paprd_gain_tbl_18" => { type => "field", addr => 0x2434, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set7" => { type => "reg", addr => 0x2438, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set7.paprd_gain_tbl_23" => { type => "field", addr => 0x2438, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set7.paprd_gain_tbl_22" => { type => "field", addr => 0x2438, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set7.paprd_gain_tbl_21" => { type => "field", addr => 0x2438, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set8" => { type => "reg", addr => 0x243c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set8.paprd_gain_tbl_26" => { type => "field", addr => 0x243c, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set8.paprd_gain_tbl_25" => { type => "field", addr => 0x243c, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set8.paprd_gain_tbl_24" => { type => "field", addr => 0x243c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_idx_set0" => { type => "reg", addr => 0x2440, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_idx_set0.paprd_gain_idx_0" => { type => "field", addr => 0x2440, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_idx_set1" => { type => "reg", addr => 0x2444, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_idx_set1.paprd_gain_idx_1" => { type => "field", addr => 0x2444, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_idx_set2" => { type => "reg", addr => 0x2448, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_idx_set2.paprd_gain_idx_2" => { type => "field", addr => 0x2448, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_idx_set3" => { type => "reg", addr => 0x244c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_idx_set3.paprd_gain_idx_3" => { type => "field", addr => 0x244c, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_agc0" => { type => "reg", addr => 0x2450, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_agc0.consec_gain_change" => { type => "field", addr => 0x2450, width => 4, bitOffset => 26, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_agc0.consec_pwr_low_cnt" => { type => "field", addr => 0x2450, width => 2, bitOffset => 24, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_agc0.paprd_pwr_weak" => { type => "field", addr => 0x2450, width => 8, bitOffset => 16, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_agc0.paprd_pwr_low" => { type => "field", addr => 0x2450, width => 8, bitOffset => 8, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_agc0.paprd_pwr_high" => { type => "field", addr => 0x2450, width => 8, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_agc1" => { type => "reg", addr => 0x2454, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_agc1.target_lvl_weak_db" => { type => "field", addr => 0x2454, width => 6, bitOffset => 12, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_agc1.target_lvl_low_db" => { type => "field", addr => 0x2454, width => 6, bitOffset => 6, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_agc1.target_lvl_hi_db" => { type => "field", addr => 0x2454, width => 6, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_qchk_acc_0" => { type => "reg", addr => 0x2458, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_train_qchk_acc_0.paprd_qchk_acc_0" => { type => "field", addr => 0x2458, width => 25, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_acc_1" => { type => "reg", addr => 0x245c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_train_qchk_acc_1.paprd_qchk_acc_1" => { type => "field", addr => 0x245c, width => 25, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_acc_2" => { type => "reg", addr => 0x2460, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_train_qchk_acc_2.paprd_qchk_acc_2" => { type => "field", addr => 0x2460, width => 25, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_acc_3" => { type => "reg", addr => 0x2464, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_train_qchk_acc_3.paprd_qchk_acc_3" => { type => "field", addr => 0x2464, width => 25, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_data_0" => { type => "reg", addr => 0x2468, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_train_qchk_data_0.paprd_qchk_max_0" => { type => "field", addr => 0x2468, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_data_0.paprd_qchk_min_0" => { type => "field", addr => 0x2468, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_data_1" => { type => "reg", addr => 0x246c, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_train_qchk_data_1.paprd_qchk_max_1" => { type => "field", addr => 0x246c, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_data_1.paprd_qchk_min_1" => { type => "field", addr => 0x246c, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_data_2" => { type => "reg", addr => 0x2470, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_train_qchk_data_2.paprd_qchk_max_2" => { type => "field", addr => 0x2470, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_data_2.paprd_qchk_min_2" => { type => "field", addr => 0x2470, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_data_3" => { type => "reg", addr => 0x2474, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_train_qchk_data_3.paprd_qchk_max_3" => { type => "field", addr => 0x2474, width => 12, bitOffset => 12, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_qchk_data_3.paprd_qchk_min_3" => { type => "field", addr => 0x2474, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_mem" => { type => "reg", addr => 0x2478, width => 32, athEmulAttr => 0, acc => "RO", depth => 384, incr => 4 }, "BB_paprd_train_mem.paprd_trn_data" => { type => "field", addr => 0x2478, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => 0x0 }, "BB_paprd_train_gain_set9" => { type => "reg", addr => 0x2af8, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set9.paprd_gain_tbl_29" => { type => "field", addr => 0x2af8, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set9.paprd_gain_tbl_28" => { type => "field", addr => 0x2af8, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set9.paprd_gain_tbl_27" => { type => "field", addr => 0x2af8, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set10" => { type => "reg", addr => 0x2afc, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set10.paprd_gain_tbl_32" => { type => "field", addr => 0x2afc, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set10.paprd_gain_tbl_31" => { type => "field", addr => 0x2afc, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set10.paprd_gain_tbl_30" => { type => "field", addr => 0x2afc, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set11" => { type => "reg", addr => 0x2b00, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set11.paprd_gain_tbl_35" => { type => "field", addr => 0x2b00, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set11.paprd_gain_tbl_34" => { type => "field", addr => 0x2b00, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set11.paprd_gain_tbl_33" => { type => "field", addr => 0x2b00, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set12" => { type => "reg", addr => 0x2b04, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set12.paprd_gain_tbl_38" => { type => "field", addr => 0x2b04, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set12.paprd_gain_tbl_37" => { type => "field", addr => 0x2b04, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set12.paprd_gain_tbl_36" => { type => "field", addr => 0x2b04, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set13" => { type => "reg", addr => 0x2b08, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set13.paprd_gain_tbl_41" => { type => "field", addr => 0x2b08, width => 10, bitOffset => 20, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set13.paprd_gain_tbl_40" => { type => "field", addr => 0x2b08, width => 10, bitOffset => 10, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set13.paprd_gain_tbl_39" => { type => "field", addr => 0x2b08, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_set14" => { type => "reg", addr => 0x2b0c, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_set14.paprd_gain_tbl_42" => { type => "field", addr => 0x2b0c, width => 10, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_idx_set4" => { type => "reg", addr => 0x2b10, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_idx_set4.paprd_gain_idx_4" => { type => "field", addr => 0x2b10, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_gain_idx_set5" => { type => "reg", addr => 0x2b14, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_paprd_train_gain_idx_set5.paprd_gain_idx_5" => { type => "field", addr => 0x2b14, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_normtx_txiq_corr_coeff_b0" => { type => "reg", addr => 0x2ee0, width => 32, athEmulAttr => 0, acc => "RW", depth => 160, incr => 4 }, "BB_normtx_txiq_corr_coeff_b0.normtx_iqc_coeff_table_chn0" => { type => "field", addr => 0x2ee0, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_paprd_train_dc_est" => { type => "reg", addr => 0x31b0, width => 32, athEmulAttr => 0, acc => "RO" }, "BB_paprd_train_dc_est.paprd_dc_est_q" => { type => "field", addr => 0x31b0, width => 11, bitOffset => 11, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_paprd_train_dc_est.paprd_dc_est_i" => { type => "field", addr => 0x31b0, width => 11, bitOffset => 0, athEmulAttr => 0, acc => "RO", resetVal => "NL" }, "BB_chaninfo_tab_b0" => { type => "reg", addr => 0x3200, width => 32, athEmulAttr => 0, acc => "RW", depth => 256, incr => 4 }, "BB_chaninfo_tab_b0.chaninfo_word" => { type => "field", addr => 0x3200, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_fir_coeff_mem" => { type => "reg", addr => 0x36b0, width => 32, athEmulAttr => 0, acc => "RW", depth => 280, incr => 4 }, "BB_tx_fir_coeff_mem.tx_fir_coeff" => { type => "field", addr => 0x36b0, width => 28, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_tx_fir_cntl" => { type => "reg", addr => 0x3b10, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_tx_fir_cntl.tx_fir_mcs_thr" => { type => "field", addr => 0x3b10, width => 4, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chn_dc_notch_fd_01_mem" => { type => "reg", addr => 0x3b14, width => 32, athEmulAttr => 0, acc => "RW", depth => 256, incr => 4 }, "BB_chn_dc_notch_fd_01_mem.dc_notch_fd_coeff" => { type => "field", addr => 0x3b14, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chn_dc_notch_fd_23_mem" => { type => "reg", addr => 0x3f14, width => 32, athEmulAttr => 0, acc => "RW", depth => 256, incr => 4 }, "BB_chn_dc_notch_fd_23_mem.dc_notch_fd_coeff" => { type => "field", addr => 0x3f14, width => 12, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_chn_tables_dummy_1" => { type => "reg", addr => 0x8aac, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_chn_tables_dummy_1.dummy1" => { type => "field", addr => 0x8aac, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, }; use constant tiered_sm1_table_map_struct => { ################################################################### ## sm1_table_map Register/Field definitions ################################################################### "BB_sm1_tables_dummy1" => { type => "reg", addr => 0x0, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sm1_tables_dummy1.dummy1" => { type => "field", addr => 0x0, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "BB_dc_dac_mem_b1" => { type => "reg", addr => 0x300, width => 32, athEmulAttr => 0, acc => "RW", depth => 52, incr => 4 }, "BB_dc_dac_mem_b1.dc_dac_setting" => { type => "field", addr => 0x300, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => 0x0 }, "BB_sm1_hc_preemp_lut" => { type => "reg", addr => 0x1300, width => 32, athEmulAttr => 0, acc => "RW", depth => 412, incr => 4 }, "BB_sm1_hc_preemp_lut.sm1_hc_preemp_lut_word" => { type => "field", addr => 0x1300, width => 18, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, "BB_sm1_tables_dummy2" => { type => "reg", addr => 0x1970, width => 32, athEmulAttr => 0, acc => "RW" }, "BB_sm1_tables_dummy2.dummy2" => { type => "field", addr => 0x1970, width => 32, bitOffset => 0, athEmulAttr => 0, acc => "RW", resetVal => "NL" }, }; use constant EMULATION => 0; use constant SILICON_FULL_SPEED => 1; use constant SILICON_HALF_SPEED => 2; use constant SILICON_QTR_SPEED => 3; use constant DKSIM => 4; use constant MODE_2G_HT20 => 0; use constant MODE_2G_HT40 => 1; use constant MODE_5G_HT20 => 2; use constant MODE_5G_HT40 => 3; use constant MODE_2G_LEGACY => 4; use constant MODE_5G_LEGACY => 5; use constant NUM_NON_TIER_STRUCTS => 2; # Hash to hold reverse reference. Keys are addresses and values are Reg names. my %refRegMapStruct = '%'; # Hash to hold Field names for a given register. my %refFldMapStruct = '@'; my @tierRefs; my $VERBOSE = 0; my $SINGLE_STEP = 0; #------------------------------------------------------------------------------------------- # Register Class #------------------------------------------------------------------------------------------- sub new { my ($class, $type) = @_; my $self = {}; bless $self, $class; if ($type == EMULATION) { unshift (@addrMapStructs, "regMapStructEmul"); } else { unshift (@addrMapStructs, "regMapStructAna"); } for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { my $path = eval $addrMapStructs[$i]; push(@tierRefs, $path); my $map = $addrMapStructs[$i]; foreach my $name (keys %{$path}) { if ($path->{$name}->{type} eq "reg") { my $depth = (exists $path->{$name}->{depth}) ? $path->{$name}->{depth} : 0; my $addr = $path->{$name}->{addr}; my $arg; if ($depth > 0) { for my $j (0 .. ($depth-1)) { my $reg = $name."[".$j."]"; my $arg = ($i >= NUM_NON_TIER_STRUCTS) ? $self->tierPortal->{$map}->{addrPtr}.".".$addr : $addr; $self->athDie("Error! Duplicate Register Map Address found for $name in RegAccess.pm\n") if exists $self->{refRegMapStruct}->{$arg}; $self->{refRegMapStruct}->{$arg}=$reg; $addr = $addr + ($path->{$name}->{incr}); } } else { my $arg = ($i >= NUM_NON_TIER_STRUCTS) ? $self->tierPortal->{$map}->{addrPtr}.".".$addr : $addr; $self->athDie("Error! Duplicate Register Map Address found for $name in RegAccess.pm\n") if exists $self->{refRegMapStruct}->{$arg}; $self->{refRegMapStruct}->{$arg}=$name; } } if ($path->{$name}->{type} eq "field") { my @rfields = split(/\./, $name); my $tname = @rfields[0]; push (@{$self->{refFldMapStruct}->{@rfields[0]}}, $name); } } } # foreach my $name (keys %{$self->{refFldMapStruct}}) { # print "$name %%%%%%%%%%%%% @{$self->{refFldMapStruct}->{$name}}\n"; # } # foreach my $name (keys %{$self->{refRegMapStruct}}) { # printf("%s -- %s\n", $name, $self->{refRegMapStruct}->{$name}); # } return $self; } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Register Write Subroutine # Args : handle - pointer to register class # name - register/field name # value - write value #------------------------------------------------------------------------------------------- sub regWr { my ($self, $name, $value) = @_; my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } $self->athDie("Error! Register/field name $name not found in RegAccess.pm\n") if !defined $path; if ($path->{acc} eq "RO") { warn "Warning ! Write to Register/Field $name which is read-only"; #return 1; } my $reg_val; if ($path->{$name}->{type} ne "reg") { my $reg_msk = ~((2**$path->{$name}->{width} - 1) << $path->{$name}->{bitOffset}); if ($inTier) { main::reg_write($self->tierPortal->{$map}->{addrPtr}, $path->{$name}->{addr}); $reg_val = main::reg_read($self->tierPortal->{$map}->{dataPtr}) & $reg_msk; } else { $reg_val = main::reg_read($path->{$name}->{addr}) & $reg_msk; } $value = ($value & (2**$path->{$name}->{width} - 1)) << $path->{$name}->{bitOffset}; $value = $reg_val | $value; } if ($inTier) { main::reg_write($self->tierPortal->{$map}->{addrPtr}, $path->{$name}->{addr}); main::reg_write($self->tierPortal->{$map}->{dataPtr}, $value); } else { main::reg_write($path->{$name}->{addr}, $value); } return 1; } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Register Read Subroutine # Args : handle - pointer to register class # name - register/field name # returns 32 bit read value #------------------------------------------------------------------------------------------- sub regRd { my ($self, $name) = @_; my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } $self->athDie("Error! Register/field name $name not found in RegAccess.pm\n") if !defined $path; if ($path->{$name}->{acc} eq "WO") { warn "Warning ! Read from Register/Field $name which is write-only. Read data may be incorrect"; } my $reg_val; if ($inTier) { main::reg_write($self->tierPortal->{$map}->{addrPtr}, $path->{$name}->{addr}); $reg_val = main::reg_read($self->tierPortal->{$map}->{dataPtr}); } else { $reg_val = main::reg_read($path->{$name}->{addr}); } if ($path->{$name}->{type} ne "reg") { $reg_val = $reg_val >> $path->{$name}->{bitOffset}; $reg_val = $reg_val & (2**$path->{$name}->{width} - 1); } return $reg_val; } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Routine returns address from Register name # Args : handle - pointer to register class # address - address of required register #------------------------------------------------------------------------------------------- sub regNameFromAddr { my ($self, $addr) = @_; if (exists $self->{refRegMapStruct}->{$addr}) { return $self->{refRegMapStruct}->{$addr}; } else { return 0; } } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Routine to display breakup of a register value by it's fields # Args : handle - pointer to register class # address - numerical address of the register # value - 32 bit value whose breakup is required. #------------------------------------------------------------------------------------------- sub decipherAddrVal { my ($self, $addr, $value, $fhandle) = @_; my $taddr = $addr; $self->athDie("Error! Register Map Address $taddr not found\n") if !exists $self->{refRegMapStruct}->{$addr}; my $name = $self->{refRegMapStruct}->{$addr}; $name =~ s/\[[0-9]+]//; # remove array index to retrive fields my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } print " --------------------------------------------------------\n"; if ($inTier) { my @sa = split(/\./, $addr); printf (" TIER Register breakup for Portal Addr - 0x%08x Addr - 0x%08x, Value = 0x%08x\n", $sa[0], $sa[1], $value); } else { printf (" Register breakup for Addr - 0x%08x, Value = 0x%08x\n", $addr, $value); } print " --------------------------------------------------------\n"; printf (" Register Name - %s\n", $name); printf (" Register Fields - \n"); if ($fhandle) { print $fhandle " --------------------------------------------------------\n"; if ($inTier) { my @sa = split(/\./, $addr); printf (fhandle " TIER Register breakup for Portal Addr - 0x%08x Addr - 0x%08x, Value = 0x%08x\n", $sa[0], $sa[1], $value); } else { printf ($fhandle " Register breakup for Addr - 0x%08x, Value = 0x%08x\n", $addr, $value); } print $fhandle " --------------------------------------------------------\n"; printf ($fhandle " Register Name - %s\n", $name); printf ($fhandle " Register Fields - \n"); } my $reg_val; foreach my $nm (sort { $path->{$a}->{bitOffset} <=> $path->{$b}->{bitOffset} }(@{$self->{refFldMapStruct}->{$name}}) ) { $reg_val = $value >> $path->{$nm}->{bitOffset}; $reg_val = $reg_val & (2**$path->{$nm}->{width} - 1); printf (" %-40s[%d:%d] = 0x%x\n", $nm, $path->{$nm}->{bitOffset} + $path->{$nm}->{width} - 1,$path->{$nm}->{bitOffset},$reg_val); if ($fhandle) { printf ($fhandle " %-40s[%d:%d] = 0x%x\n", $nm, $path->{$nm}->{bitOffset} + $path->{$nm}->{width} - 1,$path->{$nm}->{bitOffset},$reg_val); } } print " --------------------------------------------------------\n"; if ($fhandle) { print $fhandle " --------------------------------------------------------\n"; } return 1; } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Routine to display breakup of a register value by it's fields. Same as the routine above # except that the name of the register is specified and it's value is read from the chip. # Args : handle - pointer to register class # name - name of the register #------------------------------------------------------------------------------------------- sub dispRegContents { my ($self, $name, $fhandle) = @_; my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } if ($inTier) { $self->decipherAddrVal($self->tierPortal->{$map}->{addrPtr}.".".$path->{$name}->{addr}, $self->regRd($name), $fhandle); } else { $self->decipherAddrVal($path->{$name}->{addr}, $self->regRd($name), $fhandle); } return 1; } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Routine to display breakup of a register value by it's fields. Same as the routine above # except that the name of the register is specified and it's value is read from the chip. # Args : handle - pointer to register class # name - name of the register #------------------------------------------------------------------------------------------- sub viewRegContents { my ($self, $name,$value) = @_; my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } if ($inTier) { $self->decipherAddrVal($self->tierPortal->{$map}->{addrPtr}.".".$path->{$name}->{addr}, $value); } else { $self->decipherAddrVal($path->{$name}->{addr}, $value); } return 1; } #------------------------------------------------------------------------------------------- # Routine to return a 32 bit offset and masked value, given a register field and field value # Args : handle - pointer to register class # name - name of the field # value - value of the field #------------------------------------------------------------------------------------------- sub retFldVal { my ($self, $name, $reg_val) = @_; my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } $self->athDie( "Error! Register/field name $name not found in RegAccess.pm\n") if !exists $path->{$name}; return ($reg_val << $path->{$name}->{bitOffset}); } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Routine to do table/memory writes # Args : handle - pointer to register class # name - name of the register (no fields allowed) # offset - offset from the starting address location of the table/memory # value - 32 bit value to be written #------------------------------------------------------------------------------------------- sub tableWr { my ($self, $name, $offset, $value) = @_; my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } $self->athDie( "Error! Register name $name not found in RegAccess.pm\n") if !exists $path->{$name}; $self->athDie( "Error! Cannot do a table access by field\n") if ($path->{$name}->{type} ne "reg"); $self->athDie( "Error! Register name $name does not have a \"depth\" specification\n") if !exists $path->{$name}->{depth}; if ($path->{$name}->{acc} eq "RO") { warn "Warning ! Write to Register/Field $name which is read-only. No write performed"; return 1; } if ($inTier) { main::reg_write($self->tierPortal->{$map}->{addrPtr}, $path->{$name}->{addr} + ($offset * 4)); main::reg_write($self->tierPortal->{$map}->{dataPtr}, $value); } else { main::reg_write($path->{$name}->{addr} + ($offset * 4), $value); } return 1; } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Routine to do table/memory reads # Args : handle - pointer to register class # name - name of the register (no fields allowed) # offset - offset from the starting address location of the table/memory #------------------------------------------------------------------------------------------- sub tableRd { my ($self, $name, $offset) = @_; my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } $self->athDie( "Error! Register name $name not found in RegAccess.pm\n") if !exists $path->{$name}; $self->athDie( "Error! Cannot do a table access by field\n") if ($path->{$name}->{type} ne "reg"); $self->athDie( "Error! Register name $name does not have a \"depth\" specification\n") if !exists $path->{$name}->{depth}; my $value; if ($inTier) { main::reg_write($self->tierPortal->{$map}->{addrPtr}, $path->{$name}->{addr} + ($offset * 4)); $value = main::reg_read($self->tierPortal->{$map}->{dataPtr}); } else { $value = main::reg_read($path->{$name}->{addr} + ($offset * 4)); } return $value; } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Routine to poll a register/field # Args : handle - pointer to register class # name - name of register/field # numPolls - number of times the register/field needs to be read before timing out # waitTime - wait time in each poll # value - register/field value for which to wait (turning true) #------------------------------------------------------------------------------------------- sub regPoll { my ($self, $name, $numPolls, $waitTime, $value) = @_; my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } $self->athDie( "Error! Register/field name $name not found in RegAccess.pm\n") if !exists $path->{$name}->{addr}; if ($path->{$name}->{acc} eq "WO") { warn "Warning ! Poll from Register/Field $name which is write-only. Read data may be incorrect"; } my $timeout = $numPolls; my $reg_val; if ($inTier) { main::reg_write($self->tierPortal->{$map}->{addrPtr}, $path->{$name}->{addr}); $reg_val = main::reg_read($self->tierPortal->{$map}->{dataPtr}); if ($path->{$name}->{type} ne "reg") { $reg_val = $reg_val >> $path->{$name}->{bitOffset}; $reg_val = $reg_val & (2**$path->{$name}->{width} - 1); } printf (" Polling on %s for value 0x%-x. Starting Value : 0x%-x\n", $name, $value, $reg_val); while (($timeout > 0) && ($reg_val != $value)) { main::reg_write($self->tierPortal->{$map}->{addrPtr}, $path->{$name}->{addr}); $reg_val = main::reg_read($self->tierPortal->{$map}->{dataPtr}); if ($path->{$name}->{type} ne "reg") { $reg_val = $reg_val >> $path->{$name}->{bitOffset}; $reg_val = $reg_val & (2**$path->{$name}->{width} - 1); } if ($waitTime > 0) { main::wait_on_time($waitTime); } $timeout--; } } else { $reg_val = main::reg_read($path->{$name}->{addr}); if ($path->{$name}->{type} ne "reg") { $reg_val = $reg_val >> $path->{$name}->{bitOffset}; $reg_val = $reg_val & (2**$path->{$name}->{width} - 1); } printf (" Polling on %s for value 0x%-x. Starting Value : 0x%-x\n", $name, $value, $reg_val); while (($timeout > 0) && ($reg_val != $value)) { $reg_val = main::reg_read($path->{$name}->{addr}); if ($path->{$name}->{type} ne "reg") { $reg_val = $reg_val >> $path->{$name}->{bitOffset}; $reg_val = $reg_val & (2**$path->{$name}->{width} - 1); } if ($waitTime > 0) { main::wait_on_time($waitTime); } $timeout--; } } $self->athDie( " Error ! Polling timed out on $name after $numPolls reads\n") if ($timeout == 0); printf (" Polling on %s complete.\n", $name); } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Routine to program initialization arrays. # This routine will accept an array of fields and construct 32 bit register values to be # programmed one shot into the chip. This avoids read-modify-write (as in regRd) since # some of the BB registers have this programming requirement. # NOTES : # 1) The routine requires *ALL* fields for a given register to be specified in the array. # 2) The order of writes is determined by any field of a given register encountered FIRST # as it scans the array # e.g. if the array is ([ reg0.field0, 0x0], # [ reg0.field1, 0x1], # [ reg0.field2, 0x1], # [ reg1.field0, 0x1], # [ reg0.field3, 0x1], # [ reg4.field1, 0x1], # ..... # then the routine will scan the entire array and write in the sequence reg0, reg1, reg4 # Args : handle - pointer to register class # var - array passed ** BY REFERENCE ** # dispMode - If 1, displays each register name and value while programming #------------------------------------------------------------------------------------------- sub arrayProg { my ($self, $arr, $dispMode) = @_; $self->enhArrayProg($arr, 1, $dispMode); } #------------------------------------------------------------------------------------------- #------------------------------------------------------------------------------------------- # Enhanced Routine to program initialization arrays. # This routine will accept an array of fields and construct 32 bit register values to be # programmed one shot into the chip. This avoids read-modify-write (as in regRd) since # some of the BB registers have this programming requirement. # NOTES : # 1) The routine requires *ALL* fields for a given register to be specified in the array. # 2) The order of writes is determined by any field of a given register encountered FIRST # as it scans the array # e.g. if the array is ([ reg0.field0, 0x0], # [ reg0.field1, 0x1], # [ reg0.field2, 0x1], # [ reg1.field0, 0x1], # [ reg0.field3, 0x1], # [ reg4.field1, 0x1], # ..... # then the routine will scan the entire array and write in the sequence reg0, reg1, reg4 # Args : handle - pointer to register class # # var - array passed ** BY REFERENCE ** # # arrInd - Index in the array from which values have to be used. For e.g. # pass 2 for 2G-HT20 values in the array below. # @proArr = ( # Name common 2G-HT20 # ["name0", 0x1, 0x2], # ["name1", 0x1, 0x2], # ["name2", 0x1, 0x2], # ..... # ["nameN", 0x1, 0x2], # ); # !!NOTE!! : You cannot pass 0 or >2 as index in the e.g. above # # dispMode - If 1, displays each register name and value while programming #------------------------------------------------------------------------------------------- sub enhArrayProg { my ($self, $arr, $arrInd, $dispMode, $wait_on_time) = @_; my %hStruct; printf (" Starting Array Initialization...\n"); for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { my $path = $tierRefs[$i]; my $map = $addrMapStructs[$i]; foreach my $name (keys %{$path}) { if ($path->{$name}->{type} eq "field") { my @rfields = split(/\./, $name); my $reg = $rfields[$#rfields - 1]; my $depth = 0; if (exists $path->{$name}->{depth}) { $depth = $path->{$name}->{depth}; } my $addr = $path->{$name}->{addr}; if ($depth > 0) { for my $j (0 .. ($depth-1)) { $reg .= "[".$j."]"; $hStruct{$reg}{$name} = undef; $hStruct{$reg}{"populated"} = 0; if ($i > 0) { $hStruct{$reg}{"addr"} = $self->tierPortal->{$map}->{addrPtr}.".".$addr; } else { $hStruct{$reg}{"addr"} = $addr; } $addr += 4; } } else { $hStruct{$reg}{$name} = undef; $hStruct{$reg}{"populated"} = 0; if ($i > 0) { $hStruct{$reg}{"addr"} = $self->tierPortal->{$map}->{addrPtr}.".".$addr; } else { $hStruct{$reg}{"addr"} = $addr; } } } } } for (my $i = 0; $i <= $#{$arr}; $i++) { my @tA = @{$arr}; my $name = $tA[$i][0]; my @tArr1 = split(/\./, $name); my @tArr2 = split(/[\[\]]/, $tArr1[0]); my $reg = $tArr1[0]; if ($#tArr2 > 0) { $name = $tArr2[0].".".$tArr1[1]; } my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } $self->athDie("iniArrayProg Error! No value defined at Index $arrInd for $reg\n") if ($tA[$i][$arrInd] eq undef); $self->athDie("iniArrayProg Error! Cannot use Index argument of 0 which corresponds to Field name\n") if ($arrInd == 0); $self->athDie("iniArrayProg Error! Register/field name $name not found in RegAccess.pm\n") if !exists $path->{$name}; if ($path->{$name}->{type} ne "field") { $self->athDie("iniArrayProg Error! Name $name specified in initialization array is not a field. Currently, arrayProg supports field specifications only. Please break up the programming into field values.\n"); } $hStruct{$reg}{$name} = $tA[$i][$arrInd]; if (!$hStruct{$reg}{"populated"}) { $hStruct{$reg}{"populated"} = 1; $hStruct{$reg}{"locInd"} = $i; } } foreach my $elm (sort { $hStruct{$a}{"locInd"} <=> $hStruct{$b}{"locInd"} }(keys %hStruct)) { if ($hStruct{$elm}{"populated"}) { $hStruct{$elm}{"regVal"} = 0; foreach my $name (keys %{$hStruct{$elm}}) { my $map; my $path; my $inTier = 0; for (my $i = 0; $i < ($#addrMapStructs+1); $i++) { if (exists $tierRefs[$i]->{$name}) { $path = $tierRefs[$i]; $map = $addrMapStructs[$i]; $inTier = 1 if ($i >= NUM_NON_TIER_STRUCTS); } } if ($hStruct{$elm}{$name} eq undef) { $self->athDie("iniArrayProg Error! During initialization, field $name in $elm is not populated. Please specify *all* fields in the register\n"); } else { my $tval = $hStruct{$elm}{$name} & (2**$path->{$name}->{width} - 1); $hStruct{$elm}{"regVal"} = $hStruct{$elm}{"regVal"} | ($tval << $path->{$name}->{bitOffset}); } } my @tArr1 = split(/\./, $elm); my @tArr2 = split(/[\[\]]/, $tArr1[0]); if ($#tArr2 > 0) { $self->tableWr($tArr2[0], $tArr2[1], $hStruct{$elm}{"regVal"}); } else { if(defined $wait_on_time) { printf(" wait_on_time = $wait_on_time\n"); main::wait_on_time($wait_on_time); } $self->regWr($elm, $hStruct{$elm}{"regVal"}); } printf (" %-40s <= 0x%08x\n", $elm , $hStruct{$elm}{"regVal"}) if $dispMode; } } printf (" End of Array Initialization...\n"); } #------------------------------------------------------------------------------------------- sub athDie { my ($self, $errMsg) = @_; if ($::TARGET == 4) { # DKSIM print "$errMsg"; } else { die "$errMsg"; } } sub athPause { printf("Press a key to continue\n"); if($::TARGET == DKSIM) { printf("Continuing as Simulation Env ..\n"); } else { getc(); } } 1;