/*
 * Copyright (c) 2015 Qualcomm Atheros, Inc.
 * All Rights Reserved.
 * Qualcomm Atheros Confidential and Proprietary.
 */

#ifndef __REG_TIERED_SM1_TABLE_MAP_MACRO_H__
#define __REG_TIERED_SM1_TABLE_MAP_MACRO_H__


/* macros for BlueprintGlobalNameSpace::sm1_tables_dummy1 */
#ifndef __SM1_TABLES_DUMMY1_MACRO__
#define __SM1_TABLES_DUMMY1_MACRO__

/* macros for field dummy1 */
#define SM1_TABLES_DUMMY1__DUMMY1__SHIFT                                      0
#define SM1_TABLES_DUMMY1__DUMMY1__WIDTH                                     32
#define SM1_TABLES_DUMMY1__DUMMY1__MASK                             0xffffffffU
#define SM1_TABLES_DUMMY1__DUMMY1__READ(src)     (u_int32_t)(src) & 0xffffffffU
#define SM1_TABLES_DUMMY1__DUMMY1__WRITE(src)  ((u_int32_t)(src) & 0xffffffffU)
#define SM1_TABLES_DUMMY1__DUMMY1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define SM1_TABLES_DUMMY1__DUMMY1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define SM1_TABLES_DUMMY1__TYPE                                       u_int32_t
#define SM1_TABLES_DUMMY1__READ                                     0xffffffffU
#define SM1_TABLES_DUMMY1__WRITE                                    0xffffffffU

#endif /* __SM1_TABLES_DUMMY1_MACRO__ */


/* macros for sm1_table_map.BB_sm1_tables_dummy1 */
#define INST_SM1_TABLE_MAP__BB_SM1_TABLES_DUMMY1__NUM                         1

/* macros for BlueprintGlobalNameSpace::dc_dac_mem_b1 */
#ifndef __DC_DAC_MEM_B1_MACRO__
#define __DC_DAC_MEM_B1_MACRO__

/* macros for field dc_dac_setting */
#define DC_DAC_MEM_B1__DC_DAC_SETTING__SHIFT                                  0
#define DC_DAC_MEM_B1__DC_DAC_SETTING__WIDTH                                 32
#define DC_DAC_MEM_B1__DC_DAC_SETTING__MASK                         0xffffffffU
#define DC_DAC_MEM_B1__DC_DAC_SETTING__READ(src) (u_int32_t)(src) & 0xffffffffU
#define DC_DAC_MEM_B1__DC_DAC_SETTING__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define DC_DAC_MEM_B1__DC_DAC_SETTING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define DC_DAC_MEM_B1__DC_DAC_SETTING__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define DC_DAC_MEM_B1__TYPE                                           u_int32_t
#define DC_DAC_MEM_B1__READ                                         0xffffffffU
#define DC_DAC_MEM_B1__WRITE                                        0xffffffffU

#endif /* __DC_DAC_MEM_B1_MACRO__ */


/* macros for sm1_table_map.BB_dc_dac_mem_b1 */
#define INST_SM1_TABLE_MAP__BB_DC_DAC_MEM_B1__NUM                            52

/* macros for BlueprintGlobalNameSpace::sm1_hc_preemp_lut */
#ifndef __SM1_HC_PREEMP_LUT_MACRO__
#define __SM1_HC_PREEMP_LUT_MACRO__

/* macros for field sm1_hc_preemp_lut_word */
#define SM1_HC_PREEMP_LUT__SM1_HC_PREEMP_LUT_WORD__SHIFT                      0
#define SM1_HC_PREEMP_LUT__SM1_HC_PREEMP_LUT_WORD__WIDTH                     18
#define SM1_HC_PREEMP_LUT__SM1_HC_PREEMP_LUT_WORD__MASK             0x0003ffffU
#define SM1_HC_PREEMP_LUT__SM1_HC_PREEMP_LUT_WORD__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define SM1_HC_PREEMP_LUT__SM1_HC_PREEMP_LUT_WORD__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define SM1_HC_PREEMP_LUT__SM1_HC_PREEMP_LUT_WORD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define SM1_HC_PREEMP_LUT__SM1_HC_PREEMP_LUT_WORD__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define SM1_HC_PREEMP_LUT__TYPE                                       u_int32_t
#define SM1_HC_PREEMP_LUT__READ                                     0x0003ffffU
#define SM1_HC_PREEMP_LUT__WRITE                                    0x0003ffffU

#endif /* __SM1_HC_PREEMP_LUT_MACRO__ */


/* macros for sm1_table_map.BB_sm1_hc_preemp_lut */
#define INST_SM1_TABLE_MAP__BB_SM1_HC_PREEMP_LUT__NUM                       412

/* macros for BlueprintGlobalNameSpace::sm1_tables_dummy2 */
#ifndef __SM1_TABLES_DUMMY2_MACRO__
#define __SM1_TABLES_DUMMY2_MACRO__

/* macros for field dummy2 */
#define SM1_TABLES_DUMMY2__DUMMY2__SHIFT                                      0
#define SM1_TABLES_DUMMY2__DUMMY2__WIDTH                                     32
#define SM1_TABLES_DUMMY2__DUMMY2__MASK                             0xffffffffU
#define SM1_TABLES_DUMMY2__DUMMY2__READ(src)     (u_int32_t)(src) & 0xffffffffU
#define SM1_TABLES_DUMMY2__DUMMY2__WRITE(src)  ((u_int32_t)(src) & 0xffffffffU)
#define SM1_TABLES_DUMMY2__DUMMY2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define SM1_TABLES_DUMMY2__DUMMY2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define SM1_TABLES_DUMMY2__TYPE                                       u_int32_t
#define SM1_TABLES_DUMMY2__READ                                     0xffffffffU
#define SM1_TABLES_DUMMY2__WRITE                                    0xffffffffU

#endif /* __SM1_TABLES_DUMMY2_MACRO__ */


/* macros for sm1_table_map.BB_sm1_tables_dummy2 */
#define INST_SM1_TABLE_MAP__BB_SM1_TABLES_DUMMY2__NUM                         1
#define RFILE_INST_SM1_TABLE_MAP__NUM                                         1

#define TIERED_SM1_TABLE_MAP__VERSION \
                    "/prj/qca/chips/besra/1.0/shanghai-qca/dev_01/tyzhang/tyzhang_besra_chip/chips/besra/1.0/ip/athr/wifi/besra/shared/scripts/perllib/Pinfo.pm\n\
                    /prj/qca/chips/besra/1.0/shanghai-qca/dev_01/tyzhang/tyzhang_besra_chip/chips/besra/1.0/ip/athr/wifi/besra/shared/xml/bin/ath_ansic.pm\n\
                    /prj/qca/chips/besra/1.0/shanghai-qca/dev_01/tyzhang/tyzhang_besra_chip/chips/besra/1.0/src/chip_top/design/blueprint/chip_top_reg.rdl\n\
                    /prj/qca/chips/besra/1.0/shanghai-qca/dev_01/tyzhang/tyzhang_besra_chip/chips/besra/1.0/src/chip_top/design/blueprint/chip_top_reg_common_signals.rdl\n\
                    /prj/qca/chips/besra/1.0/shanghai-qca/dev_01/tyzhang/tyzhang_besra_chip/chips/besra/1.0/src/chip_top/design/blueprint/srcs/sm1_table_map.rdl"
#endif /* __REG_TIERED_SM1_TABLE_MAP_MACRO_H__ */