/* * Copyright (c) 2015 Qualcomm Atheros, Inc. * All Rights Reserved. * Qualcomm Atheros Confidential and Proprietary. */ #ifndef _PHY_CHN2_REG_MAP_H_ #define _PHY_CHN2_REG_MAP_H_ #ifndef __PHY_CHN2_REG_MAP_BASE_ADDRESS #define __PHY_CHN2_REG_MAP_BASE_ADDRESS (0x12400) #endif // 0x88 (PHY_BB_PRE_EMPHASIS_BW20_B2) #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_NEG_BW20_2_LSB 15 #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_NEG_BW20_2_MSB 29 #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_NEG_BW20_2_MASK 0x3fff8000 #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_NEG_BW20_2_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_NEG_BW20_2_MASK) >> PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_NEG_BW20_2_LSB) #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_NEG_BW20_2_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_NEG_BW20_2_LSB) & PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_NEG_BW20_2_MASK) #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_NEG_BW20_2_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_POS_BW20_2_LSB 0 #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_POS_BW20_2_MSB 14 #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_POS_BW20_2_MASK 0x7fff #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_POS_BW20_2_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_POS_BW20_2_MASK) >> PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_POS_BW20_2_LSB) #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_POS_BW20_2_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_POS_BW20_2_LSB) & PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_POS_BW20_2_MASK) #define PHY_BB_PRE_EMPHASIS_BW20_B2_PRE_EMP_DB_POS_BW20_2_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW20_B2_ADDRESS (0x88 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_PRE_EMPHASIS_BW20_B2_RSTMASK 0x3fffffff #define PHY_BB_PRE_EMPHASIS_BW20_B2_RESET 0x0 // 0x8c (PHY_BB_PRE_EMPHASIS_BW40_B2) #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_NEG_BW40_2_LSB 15 #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_NEG_BW40_2_MSB 29 #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_NEG_BW40_2_MASK 0x3fff8000 #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_NEG_BW40_2_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_NEG_BW40_2_MASK) >> PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_NEG_BW40_2_LSB) #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_NEG_BW40_2_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_NEG_BW40_2_LSB) & PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_NEG_BW40_2_MASK) #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_NEG_BW40_2_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_POS_BW40_2_LSB 0 #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_POS_BW40_2_MSB 14 #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_POS_BW40_2_MASK 0x7fff #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_POS_BW40_2_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_POS_BW40_2_MASK) >> PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_POS_BW40_2_LSB) #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_POS_BW40_2_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_POS_BW40_2_LSB) & PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_POS_BW40_2_MASK) #define PHY_BB_PRE_EMPHASIS_BW40_B2_PRE_EMP_DB_POS_BW40_2_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW40_B2_ADDRESS (0x8c + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_PRE_EMPHASIS_BW40_B2_RSTMASK 0x3fffffff #define PHY_BB_PRE_EMPHASIS_BW40_B2_RESET 0x0 // 0x90 (PHY_BB_PRE_EMPHASIS_BW80_B2) #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_NEG_BW80_2_LSB 15 #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_NEG_BW80_2_MSB 29 #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_NEG_BW80_2_MASK 0x3fff8000 #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_NEG_BW80_2_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_NEG_BW80_2_MASK) >> PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_NEG_BW80_2_LSB) #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_NEG_BW80_2_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_NEG_BW80_2_LSB) & PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_NEG_BW80_2_MASK) #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_NEG_BW80_2_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_POS_BW80_2_LSB 0 #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_POS_BW80_2_MSB 14 #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_POS_BW80_2_MASK 0x7fff #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_POS_BW80_2_GET(x) (((x) & PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_POS_BW80_2_MASK) >> PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_POS_BW80_2_LSB) #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_POS_BW80_2_SET(x) (((0 | (x)) << PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_POS_BW80_2_LSB) & PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_POS_BW80_2_MASK) #define PHY_BB_PRE_EMPHASIS_BW80_B2_PRE_EMP_DB_POS_BW80_2_RESET 0x0 #define PHY_BB_PRE_EMPHASIS_BW80_B2_ADDRESS (0x90 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_PRE_EMPHASIS_BW80_B2_RSTMASK 0x3fffffff #define PHY_BB_PRE_EMPHASIS_BW80_B2_RESET 0x0 // 0x94 (PHY_BB_CHN2_TABLES_INTF_ADDR) #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_ADDR_AUTO_INCR_LSB 31 #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_ADDR_AUTO_INCR_MSB 31 #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_ADDR_AUTO_INCR_MASK 0x80000000 #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_ADDR_AUTO_INCR_GET(x) (((x) & PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_ADDR_AUTO_INCR_MASK) >> PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_ADDR_AUTO_INCR_LSB) #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_ADDR_AUTO_INCR_SET(x) (((0 | (x)) << PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_ADDR_AUTO_INCR_LSB) & PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_ADDR_AUTO_INCR_MASK) #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_ADDR_AUTO_INCR_RESET 0x0 #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_TABLES_ADDR_LSB 2 #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_TABLES_ADDR_MSB 17 #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_TABLES_ADDR_MASK 0x3fffc #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_TABLES_ADDR_GET(x) (((x) & PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_TABLES_ADDR_MASK) >> PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_TABLES_ADDR_LSB) #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_TABLES_ADDR_SET(x) (((0 | (x)) << PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_TABLES_ADDR_LSB) & PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_TABLES_ADDR_MASK) #define PHY_BB_CHN2_TABLES_INTF_ADDR_CHN2_TABLES_ADDR_RESET 0x0 #define PHY_BB_CHN2_TABLES_INTF_ADDR_ADDRESS (0x94 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHN2_TABLES_INTF_ADDR_RSTMASK 0x8003fffc #define PHY_BB_CHN2_TABLES_INTF_ADDR_RESET 0x0 // 0x98 (PHY_BB_CHN2_TABLES_INTF_DATA) #define PHY_BB_CHN2_TABLES_INTF_DATA_CHN2_TABLES_DATA_LSB 0 #define PHY_BB_CHN2_TABLES_INTF_DATA_CHN2_TABLES_DATA_MSB 31 #define PHY_BB_CHN2_TABLES_INTF_DATA_CHN2_TABLES_DATA_MASK 0xffffffff #define PHY_BB_CHN2_TABLES_INTF_DATA_CHN2_TABLES_DATA_GET(x) (((x) & PHY_BB_CHN2_TABLES_INTF_DATA_CHN2_TABLES_DATA_MASK) >> PHY_BB_CHN2_TABLES_INTF_DATA_CHN2_TABLES_DATA_LSB) #define PHY_BB_CHN2_TABLES_INTF_DATA_CHN2_TABLES_DATA_SET(x) (((0 | (x)) << PHY_BB_CHN2_TABLES_INTF_DATA_CHN2_TABLES_DATA_LSB) & PHY_BB_CHN2_TABLES_INTF_DATA_CHN2_TABLES_DATA_MASK) #define PHY_BB_CHN2_TABLES_INTF_DATA_CHN2_TABLES_DATA_RESET 0x0 #define PHY_BB_CHN2_TABLES_INTF_DATA_ADDRESS (0x98 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHN2_TABLES_INTF_DATA_RSTMASK 0xffffffff #define PHY_BB_CHN2_TABLES_INTF_DATA_RESET 0x0 // 0xa8 (PHY_BB_SPUR_REPORT_B2) #define PHY_BB_SPUR_REPORT_B2_POWER_WITH_SPUR_REMOVED_2_LSB 16 #define PHY_BB_SPUR_REPORT_B2_POWER_WITH_SPUR_REMOVED_2_MSB 31 #define PHY_BB_SPUR_REPORT_B2_POWER_WITH_SPUR_REMOVED_2_MASK 0xffff0000 #define PHY_BB_SPUR_REPORT_B2_POWER_WITH_SPUR_REMOVED_2_GET(x) (((x) & PHY_BB_SPUR_REPORT_B2_POWER_WITH_SPUR_REMOVED_2_MASK) >> PHY_BB_SPUR_REPORT_B2_POWER_WITH_SPUR_REMOVED_2_LSB) #define PHY_BB_SPUR_REPORT_B2_POWER_WITH_SPUR_REMOVED_2_SET(x) (((0 | (x)) << PHY_BB_SPUR_REPORT_B2_POWER_WITH_SPUR_REMOVED_2_LSB) & PHY_BB_SPUR_REPORT_B2_POWER_WITH_SPUR_REMOVED_2_MASK) #define PHY_BB_SPUR_REPORT_B2_POWER_WITH_SPUR_REMOVED_2_RESET 0x0 #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_Q_2_LSB 8 #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_Q_2_MSB 15 #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_Q_2_MASK 0xff00 #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_Q_2_GET(x) (((x) & PHY_BB_SPUR_REPORT_B2_SPUR_EST_Q_2_MASK) >> PHY_BB_SPUR_REPORT_B2_SPUR_EST_Q_2_LSB) #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_Q_2_SET(x) (((0 | (x)) << PHY_BB_SPUR_REPORT_B2_SPUR_EST_Q_2_LSB) & PHY_BB_SPUR_REPORT_B2_SPUR_EST_Q_2_MASK) #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_Q_2_RESET 0x0 #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_I_2_LSB 0 #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_I_2_MSB 7 #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_I_2_MASK 0xff #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_I_2_GET(x) (((x) & PHY_BB_SPUR_REPORT_B2_SPUR_EST_I_2_MASK) >> PHY_BB_SPUR_REPORT_B2_SPUR_EST_I_2_LSB) #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_I_2_SET(x) (((0 | (x)) << PHY_BB_SPUR_REPORT_B2_SPUR_EST_I_2_LSB) & PHY_BB_SPUR_REPORT_B2_SPUR_EST_I_2_MASK) #define PHY_BB_SPUR_REPORT_B2_SPUR_EST_I_2_RESET 0x0 #define PHY_BB_SPUR_REPORT_B2_ADDRESS (0xa8 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPUR_REPORT_B2_RSTMASK 0xffffffff #define PHY_BB_SPUR_REPORT_B2_RESET 0x0 // 0xc0 (PHY_BB_IQ_ADC_MEAS_0_B2) #define PHY_BB_IQ_ADC_MEAS_0_B2_GAIN_DC_IQ_CAL_MEAS_0_2_LSB 0 #define PHY_BB_IQ_ADC_MEAS_0_B2_GAIN_DC_IQ_CAL_MEAS_0_2_MSB 31 #define PHY_BB_IQ_ADC_MEAS_0_B2_GAIN_DC_IQ_CAL_MEAS_0_2_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_0_B2_GAIN_DC_IQ_CAL_MEAS_0_2_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_0_B2_GAIN_DC_IQ_CAL_MEAS_0_2_MASK) >> PHY_BB_IQ_ADC_MEAS_0_B2_GAIN_DC_IQ_CAL_MEAS_0_2_LSB) #define PHY_BB_IQ_ADC_MEAS_0_B2_GAIN_DC_IQ_CAL_MEAS_0_2_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_0_B2_GAIN_DC_IQ_CAL_MEAS_0_2_LSB) & PHY_BB_IQ_ADC_MEAS_0_B2_GAIN_DC_IQ_CAL_MEAS_0_2_MASK) #define PHY_BB_IQ_ADC_MEAS_0_B2_GAIN_DC_IQ_CAL_MEAS_0_2_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_0_B2_ADDRESS (0xc0 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_0_B2_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_0_B2_RESET 0x0 // 0xc4 (PHY_BB_IQ_ADC_MEAS_1_B2) #define PHY_BB_IQ_ADC_MEAS_1_B2_GAIN_DC_IQ_CAL_MEAS_1_2_LSB 0 #define PHY_BB_IQ_ADC_MEAS_1_B2_GAIN_DC_IQ_CAL_MEAS_1_2_MSB 31 #define PHY_BB_IQ_ADC_MEAS_1_B2_GAIN_DC_IQ_CAL_MEAS_1_2_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_1_B2_GAIN_DC_IQ_CAL_MEAS_1_2_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_1_B2_GAIN_DC_IQ_CAL_MEAS_1_2_MASK) >> PHY_BB_IQ_ADC_MEAS_1_B2_GAIN_DC_IQ_CAL_MEAS_1_2_LSB) #define PHY_BB_IQ_ADC_MEAS_1_B2_GAIN_DC_IQ_CAL_MEAS_1_2_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_1_B2_GAIN_DC_IQ_CAL_MEAS_1_2_LSB) & PHY_BB_IQ_ADC_MEAS_1_B2_GAIN_DC_IQ_CAL_MEAS_1_2_MASK) #define PHY_BB_IQ_ADC_MEAS_1_B2_GAIN_DC_IQ_CAL_MEAS_1_2_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_1_B2_ADDRESS (0xc4 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_1_B2_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_1_B2_RESET 0x0 // 0xc8 (PHY_BB_IQ_ADC_MEAS_2_B2) #define PHY_BB_IQ_ADC_MEAS_2_B2_GAIN_DC_IQ_CAL_MEAS_2_2_LSB 0 #define PHY_BB_IQ_ADC_MEAS_2_B2_GAIN_DC_IQ_CAL_MEAS_2_2_MSB 31 #define PHY_BB_IQ_ADC_MEAS_2_B2_GAIN_DC_IQ_CAL_MEAS_2_2_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_2_B2_GAIN_DC_IQ_CAL_MEAS_2_2_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_2_B2_GAIN_DC_IQ_CAL_MEAS_2_2_MASK) >> PHY_BB_IQ_ADC_MEAS_2_B2_GAIN_DC_IQ_CAL_MEAS_2_2_LSB) #define PHY_BB_IQ_ADC_MEAS_2_B2_GAIN_DC_IQ_CAL_MEAS_2_2_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_2_B2_GAIN_DC_IQ_CAL_MEAS_2_2_LSB) & PHY_BB_IQ_ADC_MEAS_2_B2_GAIN_DC_IQ_CAL_MEAS_2_2_MASK) #define PHY_BB_IQ_ADC_MEAS_2_B2_GAIN_DC_IQ_CAL_MEAS_2_2_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_2_B2_ADDRESS (0xc8 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_2_B2_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_2_B2_RESET 0x0 // 0xcc (PHY_BB_IQ_ADC_MEAS_3_B2) #define PHY_BB_IQ_ADC_MEAS_3_B2_GAIN_DC_IQ_CAL_MEAS_3_2_LSB 0 #define PHY_BB_IQ_ADC_MEAS_3_B2_GAIN_DC_IQ_CAL_MEAS_3_2_MSB 31 #define PHY_BB_IQ_ADC_MEAS_3_B2_GAIN_DC_IQ_CAL_MEAS_3_2_MASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_3_B2_GAIN_DC_IQ_CAL_MEAS_3_2_GET(x) (((x) & PHY_BB_IQ_ADC_MEAS_3_B2_GAIN_DC_IQ_CAL_MEAS_3_2_MASK) >> PHY_BB_IQ_ADC_MEAS_3_B2_GAIN_DC_IQ_CAL_MEAS_3_2_LSB) #define PHY_BB_IQ_ADC_MEAS_3_B2_GAIN_DC_IQ_CAL_MEAS_3_2_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_MEAS_3_B2_GAIN_DC_IQ_CAL_MEAS_3_2_LSB) & PHY_BB_IQ_ADC_MEAS_3_B2_GAIN_DC_IQ_CAL_MEAS_3_2_MASK) #define PHY_BB_IQ_ADC_MEAS_3_B2_GAIN_DC_IQ_CAL_MEAS_3_2_RESET 0x0 #define PHY_BB_IQ_ADC_MEAS_3_B2_ADDRESS (0xcc + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_MEAS_3_B2_RSTMASK 0xffffffff #define PHY_BB_IQ_ADC_MEAS_3_B2_RESET 0x0 // 0xd0 (PHY_BB_TX_PHASE_RAMP_B2) #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ALPHA_2_LSB 17 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ALPHA_2_MSB 24 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ALPHA_2_MASK 0x1fe0000 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ALPHA_2_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ALPHA_2_MASK) >> PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ALPHA_2_LSB) #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ALPHA_2_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ALPHA_2_LSB) & PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ALPHA_2_MASK) #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ALPHA_2_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_INIT_2_LSB 7 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_INIT_2_MSB 16 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_INIT_2_MASK 0x1ff80 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_INIT_2_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_INIT_2_MASK) >> PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_INIT_2_LSB) #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_INIT_2_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_INIT_2_LSB) & PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_INIT_2_MASK) #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_INIT_2_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_BIAS_2_LSB 1 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_BIAS_2_MSB 6 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_BIAS_2_MASK 0x7e #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_BIAS_2_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_BIAS_2_MASK) >> PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_BIAS_2_LSB) #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_BIAS_2_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_BIAS_2_LSB) & PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_BIAS_2_MASK) #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_BIAS_2_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ENABLE_2_LSB 0 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ENABLE_2_MSB 0 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ENABLE_2_MASK 0x1 #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ENABLE_2_GET(x) (((x) & PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ENABLE_2_MASK) >> PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ENABLE_2_LSB) #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ENABLE_2_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ENABLE_2_LSB) & PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ENABLE_2_MASK) #define PHY_BB_TX_PHASE_RAMP_B2_CF_PHASE_RAMP_ENABLE_2_RESET 0x0 #define PHY_BB_TX_PHASE_RAMP_B2_ADDRESS (0xd0 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_TX_PHASE_RAMP_B2_RSTMASK 0x1ffffff #define PHY_BB_TX_PHASE_RAMP_B2_RESET 0x0 // 0xd4 (PHY_BB_ADC_GAIN_CORR_B2) #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_I_COEFF_2_LSB 9 #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_I_COEFF_2_MSB 17 #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_I_COEFF_2_MASK 0x3fe00 #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_I_COEFF_2_GET(x) (((x) & PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_I_COEFF_2_MASK) >> PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_I_COEFF_2_LSB) #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_I_COEFF_2_SET(x) (((0 | (x)) << PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_I_COEFF_2_LSB) & PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_I_COEFF_2_MASK) #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_I_COEFF_2_RESET 0x20 #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_Q_COEFF_2_LSB 0 #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_Q_COEFF_2_MSB 8 #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_Q_COEFF_2_MASK 0x1ff #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_Q_COEFF_2_GET(x) (((x) & PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_Q_COEFF_2_MASK) >> PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_Q_COEFF_2_LSB) #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_Q_COEFF_2_SET(x) (((0 | (x)) << PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_Q_COEFF_2_LSB) & PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_Q_COEFF_2_MASK) #define PHY_BB_ADC_GAIN_CORR_B2_ADC_GAIN_CORR_Q_COEFF_2_RESET 0x20 #define PHY_BB_ADC_GAIN_CORR_B2_ADDRESS (0xd4 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_ADC_GAIN_CORR_B2_RSTMASK 0x3ffff #define PHY_BB_ADC_GAIN_CORR_B2_RESET 0x4020 // 0xd8 (PHY_BB_ADC_DC_CORR_B2) #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_I_COEFF_2_LSB 9 #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_I_COEFF_2_MSB 17 #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_I_COEFF_2_MASK 0x3fe00 #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_I_COEFF_2_GET(x) (((x) & PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_I_COEFF_2_MASK) >> PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_I_COEFF_2_LSB) #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_I_COEFF_2_SET(x) (((0 | (x)) << PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_I_COEFF_2_LSB) & PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_I_COEFF_2_MASK) #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_I_COEFF_2_RESET 0x0 #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_Q_COEFF_2_LSB 0 #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_Q_COEFF_2_MSB 8 #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_Q_COEFF_2_MASK 0x1ff #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_Q_COEFF_2_GET(x) (((x) & PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_Q_COEFF_2_MASK) >> PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_Q_COEFF_2_LSB) #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_Q_COEFF_2_SET(x) (((0 | (x)) << PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_Q_COEFF_2_LSB) & PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_Q_COEFF_2_MASK) #define PHY_BB_ADC_DC_CORR_B2_ADC_DC_CORR_Q_COEFF_2_RESET 0x0 #define PHY_BB_ADC_DC_CORR_B2_ADDRESS (0xd8 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_ADC_DC_CORR_B2_RSTMASK 0x3ffff #define PHY_BB_ADC_DC_CORR_B2_RESET 0x0 // 0xe0 (PHY_BB_RX_IQ_CORR_LOOPBACK_B2) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_I_COFF_2_LSB 9 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_I_COFF_2_MSB 17 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_I_COFF_2_MASK 0x3fe00 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_I_COFF_2_GET(x) (((x) & PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_I_COFF_2_MASK) >> PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_I_COFF_2_LSB) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_I_COFF_2_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_I_COFF_2_LSB) & PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_I_COFF_2_MASK) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_I_COFF_2_RESET 0x0 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_Q_COFF_2_LSB 0 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_Q_COFF_2_MSB 8 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_Q_COFF_2_MASK 0x1ff #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_Q_COFF_2_GET(x) (((x) & PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_Q_COFF_2_MASK) >> PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_Q_COFF_2_LSB) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_Q_COFF_2_SET(x) (((0 | (x)) << PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_Q_COFF_2_LSB) & PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_Q_COFF_2_MASK) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_LOOPBACK_IQCORR_Q_Q_COFF_2_RESET 0x0 #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_ADDRESS (0xe0 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_RSTMASK 0x3ffff #define PHY_BB_RX_IQ_CORR_LOOPBACK_B2_RESET 0x0 // 0xf0 (PHY_BB_PAPRD_CTRL0_B2) #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_VALID_GAIN_5_0_2_LSB 2 #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_VALID_GAIN_5_0_2_MSB 31 #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_VALID_GAIN_5_0_2_MASK 0xfffffffc #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_VALID_GAIN_5_0_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL0_B2_PAPRD_VALID_GAIN_5_0_2_MASK) >> PHY_BB_PAPRD_CTRL0_B2_PAPRD_VALID_GAIN_5_0_2_LSB) #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_VALID_GAIN_5_0_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL0_B2_PAPRD_VALID_GAIN_5_0_2_LSB) & PHY_BB_PAPRD_CTRL0_B2_PAPRD_VALID_GAIN_5_0_2_MASK) #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_VALID_GAIN_5_0_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_LSB 0 #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_MSB 0 #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_MASK 0x1 #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_MASK) >> PHY_BB_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_LSB) #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_LSB) & PHY_BB_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_MASK) #define PHY_BB_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL0_B2_ADDRESS (0xf0 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_CTRL0_B2_RSTMASK 0xfffffffd #define PHY_BB_PAPRD_CTRL0_B2_RESET 0x0 // 0xf4 (PHY_BB_PAPRD_CTRL1_B2) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TRAINER_IANDQ_SEL_2_LSB 29 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TRAINER_IANDQ_SEL_2_MSB 29 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TRAINER_IANDQ_SEL_2_MASK 0x20000000 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TRAINER_IANDQ_SEL_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B2_PAPRD_TRAINER_IANDQ_SEL_2_MASK) >> PHY_BB_PAPRD_CTRL1_B2_PAPRD_TRAINER_IANDQ_SEL_2_LSB) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TRAINER_IANDQ_SEL_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B2_PAPRD_TRAINER_IANDQ_SEL_2_LSB) & PHY_BB_PAPRD_CTRL1_B2_PAPRD_TRAINER_IANDQ_SEL_2_MASK) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TRAINER_IANDQ_SEL_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MIN_2_LSB 8 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MIN_2_MSB 13 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MIN_2_MASK 0x3f00 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MIN_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MIN_2_MASK) >> PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MIN_2_LSB) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MIN_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MIN_2_LSB) & PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MIN_2_MASK) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MIN_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MAX_2_LSB 2 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MAX_2_MSB 7 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MAX_2_MASK 0xfc #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MAX_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MAX_2_MASK) >> PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MAX_2_LSB) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MAX_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MAX_2_LSB) & PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MAX_2_MASK) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_TARGET_PWR_MAX_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2PM_ENABLE_2_LSB 1 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2PM_ENABLE_2_MSB 1 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2PM_ENABLE_2_MASK 0x2 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2PM_ENABLE_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2PM_ENABLE_2_MASK) >> PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2PM_ENABLE_2_LSB) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2PM_ENABLE_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2PM_ENABLE_2_LSB) & PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2PM_ENABLE_2_MASK) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2PM_ENABLE_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2AM_ENABLE_2_LSB 0 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2AM_ENABLE_2_MSB 0 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2AM_ENABLE_2_MASK 0x1 #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2AM_ENABLE_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2AM_ENABLE_2_MASK) >> PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2AM_ENABLE_2_LSB) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2AM_ENABLE_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2AM_ENABLE_2_LSB) & PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2AM_ENABLE_2_MASK) #define PHY_BB_PAPRD_CTRL1_B2_PAPRD_ADAPTIVE_AM2AM_ENABLE_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL1_B2_ADDRESS (0xf4 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_CTRL1_B2_RSTMASK 0x20003fff #define PHY_BB_PAPRD_CTRL1_B2_RESET 0x0 // 0xf8 (PHY_BB_PAPRD_CTRL2_B2) #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_MAG_THRSH_2_LSB 27 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_MAG_THRSH_2_MSB 31 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_MAG_THRSH_2_MASK 0xf8000000 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_MAG_THRSH_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B2_PAPRD_MAG_THRSH_2_MASK) >> PHY_BB_PAPRD_CTRL2_B2_PAPRD_MAG_THRSH_2_LSB) #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_MAG_THRSH_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B2_PAPRD_MAG_THRSH_2_LSB) & PHY_BB_PAPRD_CTRL2_B2_PAPRD_MAG_THRSH_2_MASK) #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_MAG_THRSH_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_TABLE_RFBMODE_2_LSB 24 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_TABLE_RFBMODE_2_MSB 26 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_TABLE_RFBMODE_2_MASK 0x7000000 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_TABLE_RFBMODE_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B2_PAPRD_TABLE_RFBMODE_2_MASK) >> PHY_BB_PAPRD_CTRL2_B2_PAPRD_TABLE_RFBMODE_2_LSB) #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_TABLE_RFBMODE_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B2_PAPRD_TABLE_RFBMODE_2_LSB) & PHY_BB_PAPRD_CTRL2_B2_PAPRD_TABLE_RFBMODE_2_MASK) #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_TABLE_RFBMODE_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_ADAPTIVE_TABLE_VALID_2_LSB 18 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_ADAPTIVE_TABLE_VALID_2_MSB 23 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_ADAPTIVE_TABLE_VALID_2_MASK 0xfc0000 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_ADAPTIVE_TABLE_VALID_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B2_PAPRD_ADAPTIVE_TABLE_VALID_2_MASK) >> PHY_BB_PAPRD_CTRL2_B2_PAPRD_ADAPTIVE_TABLE_VALID_2_LSB) #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_ADAPTIVE_TABLE_VALID_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B2_PAPRD_ADAPTIVE_TABLE_VALID_2_LSB) & PHY_BB_PAPRD_CTRL2_B2_PAPRD_ADAPTIVE_TABLE_VALID_2_MASK) #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_ADAPTIVE_TABLE_VALID_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_VALID_PA_SETTING_2_LSB 0 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_VALID_PA_SETTING_2_MSB 17 #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_VALID_PA_SETTING_2_MASK 0x3ffff #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_VALID_PA_SETTING_2_GET(x) (((x) & PHY_BB_PAPRD_CTRL2_B2_PAPRD_VALID_PA_SETTING_2_MASK) >> PHY_BB_PAPRD_CTRL2_B2_PAPRD_VALID_PA_SETTING_2_LSB) #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_VALID_PA_SETTING_2_SET(x) (((0 | (x)) << PHY_BB_PAPRD_CTRL2_B2_PAPRD_VALID_PA_SETTING_2_LSB) & PHY_BB_PAPRD_CTRL2_B2_PAPRD_VALID_PA_SETTING_2_MASK) #define PHY_BB_PAPRD_CTRL2_B2_PAPRD_VALID_PA_SETTING_2_RESET 0x0 #define PHY_BB_PAPRD_CTRL2_B2_ADDRESS (0xf8 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_CTRL2_B2_RSTMASK 0xffffffff #define PHY_BB_PAPRD_CTRL2_B2_RESET 0x0 // 0x150 (PHY_BB_FDTG_SS0_DATA_B2) #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_IM_2_LSB 24 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_IM_2_MSB 31 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_IM_2_MASK 0xff000000 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_IM_2_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_IM_2_MASK) >> PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_IM_2_LSB) #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_IM_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_IM_2_LSB) & PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_IM_2_MASK) #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_IM_2_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_RE_2_LSB 16 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_RE_2_MSB 23 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_RE_2_MASK 0xff0000 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_RE_2_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_RE_2_MASK) >> PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_RE_2_LSB) #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_RE_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_RE_2_LSB) & PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_RE_2_MASK) #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_B_DATA_RE_2_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_IM_2_LSB 8 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_IM_2_MSB 15 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_IM_2_MASK 0xff00 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_IM_2_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_IM_2_MASK) >> PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_IM_2_LSB) #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_IM_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_IM_2_LSB) & PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_IM_2_MASK) #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_IM_2_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_RE_2_LSB 0 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_RE_2_MSB 7 #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_RE_2_MASK 0xff #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_RE_2_GET(x) (((x) & PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_RE_2_MASK) >> PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_RE_2_LSB) #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_RE_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_RE_2_LSB) & PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_RE_2_MASK) #define PHY_BB_FDTG_SS0_DATA_B2_FDTG_SS0_A_DATA_RE_2_RESET 0x0 #define PHY_BB_FDTG_SS0_DATA_B2_ADDRESS (0x150 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS0_DATA_B2_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS0_DATA_B2_RESET 0x0 // 0x154 (PHY_BB_FDTG_SS1_DATA_B2) #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_IM_2_LSB 24 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_IM_2_MSB 31 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_IM_2_MASK 0xff000000 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_IM_2_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_IM_2_MASK) >> PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_IM_2_LSB) #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_IM_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_IM_2_LSB) & PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_IM_2_MASK) #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_IM_2_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_RE_2_LSB 16 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_RE_2_MSB 23 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_RE_2_MASK 0xff0000 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_RE_2_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_RE_2_MASK) >> PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_RE_2_LSB) #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_RE_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_RE_2_LSB) & PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_RE_2_MASK) #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_B_DATA_RE_2_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_IM_2_LSB 8 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_IM_2_MSB 15 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_IM_2_MASK 0xff00 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_IM_2_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_IM_2_MASK) >> PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_IM_2_LSB) #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_IM_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_IM_2_LSB) & PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_IM_2_MASK) #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_IM_2_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_RE_2_LSB 0 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_RE_2_MSB 7 #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_RE_2_MASK 0xff #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_RE_2_GET(x) (((x) & PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_RE_2_MASK) >> PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_RE_2_LSB) #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_RE_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_RE_2_LSB) & PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_RE_2_MASK) #define PHY_BB_FDTG_SS1_DATA_B2_FDTG_SS1_A_DATA_RE_2_RESET 0x0 #define PHY_BB_FDTG_SS1_DATA_B2_ADDRESS (0x154 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS1_DATA_B2_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS1_DATA_B2_RESET 0x0 // 0x158 (PHY_BB_FDTG_SS2_DATA_B2) #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_IM_2_LSB 24 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_IM_2_MSB 31 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_IM_2_MASK 0xff000000 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_IM_2_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_IM_2_MASK) >> PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_IM_2_LSB) #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_IM_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_IM_2_LSB) & PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_IM_2_MASK) #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_IM_2_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_RE_2_LSB 16 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_RE_2_MSB 23 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_RE_2_MASK 0xff0000 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_RE_2_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_RE_2_MASK) >> PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_RE_2_LSB) #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_RE_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_RE_2_LSB) & PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_RE_2_MASK) #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_B_DATA_RE_2_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_IM_2_LSB 8 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_IM_2_MSB 15 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_IM_2_MASK 0xff00 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_IM_2_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_IM_2_MASK) >> PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_IM_2_LSB) #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_IM_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_IM_2_LSB) & PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_IM_2_MASK) #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_IM_2_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_RE_2_LSB 0 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_RE_2_MSB 7 #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_RE_2_MASK 0xff #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_RE_2_GET(x) (((x) & PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_RE_2_MASK) >> PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_RE_2_LSB) #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_RE_2_SET(x) (((0 | (x)) << PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_RE_2_LSB) & PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_RE_2_MASK) #define PHY_BB_FDTG_SS2_DATA_B2_FDTG_SS2_A_DATA_RE_2_RESET 0x0 #define PHY_BB_FDTG_SS2_DATA_B2_ADDRESS (0x158 + __PHY_CHN2_REG_MAP_BASE_ADDRESS) #define PHY_BB_FDTG_SS2_DATA_B2_RSTMASK 0xffffffff #define PHY_BB_FDTG_SS2_DATA_B2_RESET 0x0 #endif /* _PHY_CHN2_REG_MAP_H_ */