/* * Copyright (c) 2015 Qualcomm Atheros, Inc. * All Rights Reserved. * Qualcomm Atheros Confidential and Proprietary. */ #ifndef _CHN1_RBIST_REGFILE_H_ #define _CHN1_RBIST_REGFILE_H_ #ifndef __CHN1_RBIST_REGFILE_BASE_ADDRESS #define __CHN1_RBIST_REGFILE_BASE_ADDRESS (0x466c0) #endif // 0x0 (CHN1_RBIST_CNTRL) #define CHN1_RBIST_CNTRL_ATE_RX_ADC_SAMPLE_CONTROL_LSB 22 #define CHN1_RBIST_CNTRL_ATE_RX_ADC_SAMPLE_CONTROL_MSB 23 #define CHN1_RBIST_CNTRL_ATE_RX_ADC_SAMPLE_CONTROL_MASK 0xc00000 #define CHN1_RBIST_CNTRL_ATE_RX_ADC_SAMPLE_CONTROL_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_RX_ADC_SAMPLE_CONTROL_MASK) >> CHN1_RBIST_CNTRL_ATE_RX_ADC_SAMPLE_CONTROL_LSB) #define CHN1_RBIST_CNTRL_ATE_RX_ADC_SAMPLE_CONTROL_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_RX_ADC_SAMPLE_CONTROL_LSB) & CHN1_RBIST_CNTRL_ATE_RX_ADC_SAMPLE_CONTROL_MASK) #define CHN1_RBIST_CNTRL_ATE_RX_ADC_SAMPLE_CONTROL_RESET 0x3 #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_POWER_MEASUREMENT_LSB 21 #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_POWER_MEASUREMENT_MSB 21 #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_POWER_MEASUREMENT_MASK 0x200000 #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_POWER_MEASUREMENT_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_POWER_MEASUREMENT_MASK) >> CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_POWER_MEASUREMENT_LSB) #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_POWER_MEASUREMENT_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_POWER_MEASUREMENT_LSB) & CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_POWER_MEASUREMENT_MASK) #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_POWER_MEASUREMENT_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_LSB 17 #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_MSB 20 #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_MASK 0x1e0000 #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_MASK) >> CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_LSB) #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_LSB) & CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_MASK) #define CHN1_RBIST_CNTRL_ATE_RX_DC_INTERLEAVE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16 #define CHN1_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16 #define CHN1_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x10000 #define CHN1_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_RBIST_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15 #define CHN1_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15 #define CHN1_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x8000 #define CHN1_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK) >> CHN1_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB) #define CHN1_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB) & CHN1_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK) #define CHN1_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14 #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14 #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x4000 #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13 #define CHN1_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13 #define CHN1_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x2000 #define CHN1_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12 #define CHN1_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12 #define CHN1_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x1000 #define CHN1_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11 #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11 #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x800 #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10 #define CHN1_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10 #define CHN1_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x400 #define CHN1_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9 #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9 #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x200 #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8 #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8 #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x100 #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK) >> CHN1_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB) #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB) & CHN1_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK) #define CHN1_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x80 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK) >> CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB) & CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x40 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK) >> CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB) & CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x20 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK) >> CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB) & CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x10 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK) >> CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB) & CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x8 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x4 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x2 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x1 #define CHN1_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & CHN1_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK) >> CHN1_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((0 | (x)) << CHN1_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB) & CHN1_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK) #define CHN1_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_RESET 0x0 #define CHN1_RBIST_CNTRL_ADDRESS (0x0 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_RBIST_CNTRL_RSTMASK 0xffffff #define CHN1_RBIST_CNTRL_RESET 0xc00000 // 0x4 (CHN1_TX_DC_OFFSET) #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16 #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 27 #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0xfff0000 #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK) >> CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB) #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((0 | (x)) << CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB) & CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK) #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_RESET 0x0 #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0 #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 11 #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0xfff #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK) >> CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB) #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((0 | (x)) << CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB) & CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK) #define CHN1_TX_DC_OFFSET_ATE_TONEGEN_DC_I_RESET 0x0 #define CHN1_TX_DC_OFFSET_ADDRESS (0x4 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_TX_DC_OFFSET_RSTMASK 0xfff0fff #define CHN1_TX_DC_OFFSET_RESET 0x0 // 0x8 (CHN1_TX_TONEGEN0) #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 31 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0xff000000 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK) >> CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB) #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((0 | (x)) << CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB) & CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK) #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_RESET 0x0 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_LSB 16 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_MSB 18 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_MASK 0x70000 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_GET(x) (((x) & CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_MASK) >> CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_LSB) #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_SET(x) (((0 | (x)) << CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_LSB) & CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_MASK) #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_RESET 0x0 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_LSB 8 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_MSB 11 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_MASK 0xf00 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_GET(x) (((x) & CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_MASK) >> CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_LSB) #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_SET(x) (((0 | (x)) << CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_LSB) & CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_MASK) #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_RESET 0x0 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 7 #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0xff #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK) >> CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB) #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((0 | (x)) << CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB) & CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK) #define CHN1_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_RESET 0x0 #define CHN1_TX_TONEGEN0_ADDRESS (0x8 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_TX_TONEGEN0_RSTMASK 0xff070fff #define CHN1_TX_TONEGEN0_RESET 0x0 // 0xc (CHN1_TX_TONEGEN1) #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 31 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0xff000000 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK) >> CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB) #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((0 | (x)) << CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB) & CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK) #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_RESET 0x0 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_1DB_LSB 16 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_1DB_MSB 18 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_1DB_MASK 0x70000 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_1DB_GET(x) (((x) & CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_1DB_MASK) >> CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_1DB_LSB) #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_1DB_SET(x) (((0 | (x)) << CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_1DB_LSB) & CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_1DB_MASK) #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_1DB_RESET 0x0 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_6DB_LSB 8 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_6DB_MSB 11 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_6DB_MASK 0xf00 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_6DB_GET(x) (((x) & CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_6DB_MASK) >> CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_6DB_LSB) #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_6DB_SET(x) (((0 | (x)) << CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_6DB_LSB) & CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_6DB_MASK) #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_BACKOFF_6DB_RESET 0x0 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 7 #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0xff #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK) >> CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB) #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((0 | (x)) << CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB) & CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK) #define CHN1_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_RESET 0x0 #define CHN1_TX_TONEGEN1_ADDRESS (0xc + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_TX_TONEGEN1_RSTMASK 0xff070fff #define CHN1_TX_TONEGEN1_RESET 0x0 // 0x10 (CHN1_TX_LFTONEGEN0) #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 31 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0xff000000 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK) >> CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB) #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((0 | (x)) << CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB) & CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK) #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_RESET 0xa #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_LSB 16 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_MSB 18 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_MASK 0x70000 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_GET(x) (((x) & CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_MASK) >> CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_LSB) #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_SET(x) (((0 | (x)) << CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_LSB) & CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_MASK) #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_1DB_RESET 0x0 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_LSB 8 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_MSB 11 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_MASK 0xf00 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_GET(x) (((x) & CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_MASK) >> CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_LSB) #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_SET(x) (((0 | (x)) << CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_LSB) & CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_MASK) #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_BACKOFF_6DB_RESET 0x0 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 7 #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0xff #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK) >> CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB) #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((0 | (x)) << CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB) & CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK) #define CHN1_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_RESET 0x0 #define CHN1_TX_LFTONEGEN0_ADDRESS (0x10 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_TX_LFTONEGEN0_RSTMASK 0xff070fff #define CHN1_TX_LFTONEGEN0_RESET 0xa000000 // 0x14 (CHN1_TX_LINEAR_RAMP_I) #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24 #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29 #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK) >> CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB) #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((0 | (x)) << CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB) & CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK) #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_RESET 0x0 #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x3ff000 #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK) >> CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB) #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((0 | (x)) << CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB) & CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK) #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_RESET 0x0 #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0 #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 11 #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0xfff #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK) >> CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB) #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((0 | (x)) << CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB) & CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK) #define CHN1_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_RESET 0x0 #define CHN1_TX_LINEAR_RAMP_I_ADDRESS (0x14 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_TX_LINEAR_RAMP_I_RSTMASK 0x3f3fffff #define CHN1_TX_LINEAR_RAMP_I_RESET 0x0 // 0x18 (CHN1_TX_LINEAR_RAMP_Q) #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24 #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29 #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK) >> CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB) #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((0 | (x)) << CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB) & CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK) #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_RESET 0x0 #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x3ff000 #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK) >> CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB) #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((0 | (x)) << CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB) & CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK) #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_RESET 0x0 #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0 #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 11 #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0xfff #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK) >> CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB) #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((0 | (x)) << CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB) & CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK) #define CHN1_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_RESET 0x0 #define CHN1_TX_LINEAR_RAMP_Q_ADDRESS (0x18 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_TX_LINEAR_RAMP_Q_RSTMASK 0x3f3fffff #define CHN1_TX_LINEAR_RAMP_Q_RESET 0x0 // 0x1c (CHN1_TX_PRBS_MAG) #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16 #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25 #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x3ff0000 #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK) >> CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB) #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((0 | (x)) << CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB) & CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK) #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_RESET 0x0 #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0 #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9 #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x3ff #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK) >> CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB) #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((0 | (x)) << CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB) & CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK) #define CHN1_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_RESET 0x0 #define CHN1_TX_PRBS_MAG_ADDRESS (0x1c + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_TX_PRBS_MAG_RSTMASK 0x3ff03ff #define CHN1_TX_PRBS_MAG_RESET 0x0 // 0x20 (CHN1_TX_PRBS_SEED_I) #define CHN1_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0 #define CHN1_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30 #define CHN1_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff #define CHN1_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & CHN1_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK) >> CHN1_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB) #define CHN1_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((0 | (x)) << CHN1_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB) & CHN1_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK) #define CHN1_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_RESET 0x1 #define CHN1_TX_PRBS_SEED_I_ADDRESS (0x20 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_TX_PRBS_SEED_I_RSTMASK 0x7fffffff #define CHN1_TX_PRBS_SEED_I_RESET 0x1 // 0x24 (CHN1_TX_PRBS_SEED_Q) #define CHN1_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0 #define CHN1_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30 #define CHN1_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff #define CHN1_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & CHN1_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK) >> CHN1_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB) #define CHN1_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((0 | (x)) << CHN1_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB) & CHN1_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK) #define CHN1_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_RESET 0x1 #define CHN1_TX_PRBS_SEED_Q_ADDRESS (0x24 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_TX_PRBS_SEED_Q_RSTMASK 0x7fffffff #define CHN1_TX_PRBS_SEED_Q_RESET 0x1 // 0x28 (CHN1_CMAC_DC_CANCEL) #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16 #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25 #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x3ff0000 #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK) >> CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB) #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((0 | (x)) << CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB) & CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK) #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_RESET 0x0 #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0 #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9 #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x3ff #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK) >> CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB) #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((0 | (x)) << CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB) & CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK) #define CHN1_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_RESET 0x0 #define CHN1_CMAC_DC_CANCEL_ADDRESS (0x28 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_DC_CANCEL_RSTMASK 0x3ff03ff #define CHN1_CMAC_DC_CANCEL_RESET 0x0 // 0x2c (CHN1_CMAC_DC_OFFSET) #define CHN1_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0 #define CHN1_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3 #define CHN1_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0xf #define CHN1_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & CHN1_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK) >> CHN1_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB) #define CHN1_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((0 | (x)) << CHN1_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB) & CHN1_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK) #define CHN1_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_RESET 0x0 #define CHN1_CMAC_DC_OFFSET_ADDRESS (0x2c + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_DC_OFFSET_RSTMASK 0xf #define CHN1_CMAC_DC_OFFSET_RESET 0x0 // 0x30 (CHN1_CMAC_CORR) #define CHN1_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8 #define CHN1_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 14 #define CHN1_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x7f00 #define CHN1_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & CHN1_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK) >> CHN1_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB) #define CHN1_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((0 | (x)) << CHN1_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB) & CHN1_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK) #define CHN1_CMAC_CORR_ATE_CMAC_CORR_FREQ_RESET 0x0 #define CHN1_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0 #define CHN1_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4 #define CHN1_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x1f #define CHN1_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & CHN1_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK) >> CHN1_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB) #define CHN1_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((0 | (x)) << CHN1_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB) & CHN1_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK) #define CHN1_CMAC_CORR_ATE_CMAC_CORR_CYCLES_RESET 0x0 #define CHN1_CMAC_CORR_ADDRESS (0x30 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_CORR_RSTMASK 0x7f1f #define CHN1_CMAC_CORR_RESET 0x0 // 0x34 (CHN1_CMAC_POWER) #define CHN1_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0 #define CHN1_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3 #define CHN1_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0xf #define CHN1_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & CHN1_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK) >> CHN1_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB) #define CHN1_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((0 | (x)) << CHN1_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB) & CHN1_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK) #define CHN1_CMAC_POWER_ATE_CMAC_POWER_CYCLES_RESET 0x0 #define CHN1_CMAC_POWER_ADDRESS (0x34 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_POWER_RSTMASK 0xf #define CHN1_CMAC_POWER_RESET 0x0 // 0x38 (CHN1_CMAC_CROSS_CORR) #define CHN1_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0 #define CHN1_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3 #define CHN1_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0xf #define CHN1_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & CHN1_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK) >> CHN1_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB) #define CHN1_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((0 | (x)) << CHN1_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB) & CHN1_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK) #define CHN1_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_RESET 0x0 #define CHN1_CMAC_CROSS_CORR_ADDRESS (0x38 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_CROSS_CORR_RSTMASK 0xf #define CHN1_CMAC_CROSS_CORR_RESET 0x0 // 0x3c (CHN1_CMAC_I2Q2) #define CHN1_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0 #define CHN1_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3 #define CHN1_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0xf #define CHN1_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & CHN1_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK) >> CHN1_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB) #define CHN1_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((0 | (x)) << CHN1_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB) & CHN1_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK) #define CHN1_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_RESET 0x0 #define CHN1_CMAC_I2Q2_ADDRESS (0x3c + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_I2Q2_RSTMASK 0xf #define CHN1_CMAC_I2Q2_RESET 0x0 // 0x40 (CHN1_CMAC_POWER_HPF) #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4 #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7 #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0xf0 #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK) >> CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB) #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((0 | (x)) << CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB) & CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK) #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_RESET 0xa #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0 #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3 #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0xf #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK) >> CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB) #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((0 | (x)) << CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB) & CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK) #define CHN1_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_RESET 0x0 #define CHN1_CMAC_POWER_HPF_ADDRESS (0x40 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_POWER_HPF_RSTMASK 0xff #define CHN1_CMAC_POWER_HPF_RESET 0xa0 // 0x44 (CHN1_RXDAC_SET1) #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16 #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19 #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0xf0000 #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & CHN1_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK) >> CHN1_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB) #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((0 | (x)) << CHN1_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB) & CHN1_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK) #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_RESET 0xc #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8 #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13 #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x3f00 #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & CHN1_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK) >> CHN1_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB) #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((0 | (x)) << CHN1_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB) & CHN1_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK) #define CHN1_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_RESET 0x0 #define CHN1_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4 #define CHN1_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4 #define CHN1_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x10 #define CHN1_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & CHN1_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK) >> CHN1_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB) #define CHN1_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((0 | (x)) << CHN1_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB) & CHN1_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK) #define CHN1_RXDAC_SET1_ATE_RXDAC_HI_GAIN_RESET 0x0 #define CHN1_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0 #define CHN1_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1 #define CHN1_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x3 #define CHN1_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & CHN1_RXDAC_SET1_ATE_RXDAC_MUX_MASK) >> CHN1_RXDAC_SET1_ATE_RXDAC_MUX_LSB) #define CHN1_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((0 | (x)) << CHN1_RXDAC_SET1_ATE_RXDAC_MUX_LSB) & CHN1_RXDAC_SET1_ATE_RXDAC_MUX_MASK) #define CHN1_RXDAC_SET1_ATE_RXDAC_MUX_RESET 0x0 #define CHN1_RXDAC_SET1_ADDRESS (0x44 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_RXDAC_SET1_RSTMASK 0xf3f13 #define CHN1_RXDAC_SET1_RESET 0xc0000 // 0x48 (CHN1_RXDAC_SET2) #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24 #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 31 #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0xff000000 #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & CHN1_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK) >> CHN1_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB) #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((0 | (x)) << CHN1_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB) & CHN1_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK) #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_LOW_RESET 0x14 #define CHN1_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16 #define CHN1_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 23 #define CHN1_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0xff0000 #define CHN1_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & CHN1_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK) >> CHN1_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB) #define CHN1_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((0 | (x)) << CHN1_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB) & CHN1_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK) #define CHN1_RXDAC_SET2_ATE_RXDAC_I_LOW_RESET 0x2 #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8 #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 15 #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0xff00 #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & CHN1_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK) >> CHN1_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB) #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((0 | (x)) << CHN1_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB) & CHN1_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK) #define CHN1_RXDAC_SET2_ATE_RXDAC_Q_HI_RESET 0x14 #define CHN1_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0 #define CHN1_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 7 #define CHN1_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0xff #define CHN1_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & CHN1_RXDAC_SET2_ATE_RXDAC_I_HI_MASK) >> CHN1_RXDAC_SET2_ATE_RXDAC_I_HI_LSB) #define CHN1_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((0 | (x)) << CHN1_RXDAC_SET2_ATE_RXDAC_I_HI_LSB) & CHN1_RXDAC_SET2_ATE_RXDAC_I_HI_MASK) #define CHN1_RXDAC_SET2_ATE_RXDAC_I_HI_RESET 0x2 #define CHN1_RXDAC_SET2_ADDRESS (0x48 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_RXDAC_SET2_RSTMASK 0xffffffff #define CHN1_RXDAC_SET2_RESET 0x14021402 // 0x4c (CHN1_RXDAC_LONG_SHIFT) #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8 #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 15 #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0xff00 #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK) >> CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB) #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((0 | (x)) << CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB) & CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK) #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_RESET 0x14 #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0 #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 7 #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0xff #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK) >> CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB) #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((0 | (x)) << CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB) & CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK) #define CHN1_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_RESET 0x2 #define CHN1_RXDAC_LONG_SHIFT_ADDRESS (0x4c + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_RXDAC_LONG_SHIFT_RSTMASK 0xffff #define CHN1_RXDAC_LONG_SHIFT_RESET 0x1402 // 0x50 (CHN1_CMAC_RESULTS_I) #define CHN1_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0 #define CHN1_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31 #define CHN1_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff #define CHN1_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & CHN1_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK) >> CHN1_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB) #define CHN1_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((0 | (x)) << CHN1_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB) & CHN1_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK) #define CHN1_CMAC_RESULTS_I_ATE_CMAC_RESULTS_RESET 0x0 #define CHN1_CMAC_RESULTS_I_ADDRESS (0x50 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_RESULTS_I_RSTMASK 0xffffffff #define CHN1_CMAC_RESULTS_I_RESET 0x0 // 0x54 (CHN1_CMAC_RESULTS_Q) #define CHN1_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0 #define CHN1_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31 #define CHN1_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff #define CHN1_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & CHN1_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK) >> CHN1_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB) #define CHN1_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((0 | (x)) << CHN1_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB) & CHN1_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK) #define CHN1_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_RESET 0x0 #define CHN1_CMAC_RESULTS_Q_ADDRESS (0x54 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_RESULTS_Q_RSTMASK 0xffffffff #define CHN1_CMAC_RESULTS_Q_RESET 0x0 // 0x58 (CHN1_CMAC_RESULTS_1_I) #define CHN1_CMAC_RESULTS_1_I_ATE_CMAC_RESULTS_LSB 0 #define CHN1_CMAC_RESULTS_1_I_ATE_CMAC_RESULTS_MSB 31 #define CHN1_CMAC_RESULTS_1_I_ATE_CMAC_RESULTS_MASK 0xffffffff #define CHN1_CMAC_RESULTS_1_I_ATE_CMAC_RESULTS_GET(x) (((x) & CHN1_CMAC_RESULTS_1_I_ATE_CMAC_RESULTS_MASK) >> CHN1_CMAC_RESULTS_1_I_ATE_CMAC_RESULTS_LSB) #define CHN1_CMAC_RESULTS_1_I_ATE_CMAC_RESULTS_SET(x) (((0 | (x)) << CHN1_CMAC_RESULTS_1_I_ATE_CMAC_RESULTS_LSB) & CHN1_CMAC_RESULTS_1_I_ATE_CMAC_RESULTS_MASK) #define CHN1_CMAC_RESULTS_1_I_ATE_CMAC_RESULTS_RESET 0x0 #define CHN1_CMAC_RESULTS_1_I_ADDRESS (0x58 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_RESULTS_1_I_RSTMASK 0xffffffff #define CHN1_CMAC_RESULTS_1_I_RESET 0x0 // 0x5c (CHN1_CMAC_RESULTS_1_Q) #define CHN1_CMAC_RESULTS_1_Q_ATE_CMAC_RESULTS_LSB 0 #define CHN1_CMAC_RESULTS_1_Q_ATE_CMAC_RESULTS_MSB 31 #define CHN1_CMAC_RESULTS_1_Q_ATE_CMAC_RESULTS_MASK 0xffffffff #define CHN1_CMAC_RESULTS_1_Q_ATE_CMAC_RESULTS_GET(x) (((x) & CHN1_CMAC_RESULTS_1_Q_ATE_CMAC_RESULTS_MASK) >> CHN1_CMAC_RESULTS_1_Q_ATE_CMAC_RESULTS_LSB) #define CHN1_CMAC_RESULTS_1_Q_ATE_CMAC_RESULTS_SET(x) (((0 | (x)) << CHN1_CMAC_RESULTS_1_Q_ATE_CMAC_RESULTS_LSB) & CHN1_CMAC_RESULTS_1_Q_ATE_CMAC_RESULTS_MASK) #define CHN1_CMAC_RESULTS_1_Q_ATE_CMAC_RESULTS_RESET 0x0 #define CHN1_CMAC_RESULTS_1_Q_ADDRESS (0x5c + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_RESULTS_1_Q_RSTMASK 0xffffffff #define CHN1_CMAC_RESULTS_1_Q_RESET 0x0 // 0x60 (CHN1_CMAC_DC_CANCEL_1) #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_Q_LSB 16 #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_Q_MSB 25 #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_Q_MASK 0x3ff0000 #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_Q_MASK) >> CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_Q_LSB) #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_Q_SET(x) (((0 | (x)) << CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_Q_LSB) & CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_Q_MASK) #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_Q_RESET 0x0 #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_I_LSB 0 #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_I_MSB 9 #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_I_MASK 0x3ff #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_I_MASK) >> CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_I_LSB) #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_I_SET(x) (((0 | (x)) << CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_I_LSB) & CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_I_MASK) #define CHN1_CMAC_DC_CANCEL_1_ATE_CMAC_DC_CANCEL_I_RESET 0x0 #define CHN1_CMAC_DC_CANCEL_1_ADDRESS (0x60 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_DC_CANCEL_1_RSTMASK 0x3ff03ff #define CHN1_CMAC_DC_CANCEL_1_RESET 0x0 // 0x64 (CHN1_CMAC_GAIN_COMP) #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_ENABLE_LSB 31 #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_ENABLE_MSB 31 #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_ENABLE_MASK 0x80000000 #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_ENABLE_GET(x) (((x) & CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_ENABLE_MASK) >> CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_ENABLE_LSB) #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_ENABLE_SET(x) (((0 | (x)) << CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_ENABLE_LSB) & CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_ENABLE_MASK) #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_ENABLE_RESET 0x0 #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_Q_LSB 16 #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_Q_MSB 24 #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_Q_MASK 0x1ff0000 #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_Q_GET(x) (((x) & CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_Q_MASK) >> CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_Q_LSB) #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_Q_SET(x) (((0 | (x)) << CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_Q_LSB) & CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_Q_MASK) #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_Q_RESET 0x20 #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_I_LSB 0 #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_I_MSB 8 #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_I_MASK 0x1ff #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_I_GET(x) (((x) & CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_I_MASK) >> CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_I_LSB) #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_I_SET(x) (((0 | (x)) << CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_I_LSB) & CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_I_MASK) #define CHN1_CMAC_GAIN_COMP_ATE_CMAC_GAIN_COMP_I_RESET 0x20 #define CHN1_CMAC_GAIN_COMP_ADDRESS (0x64 + __CHN1_RBIST_REGFILE_BASE_ADDRESS) #define CHN1_CMAC_GAIN_COMP_RSTMASK 0x81ff01ff #define CHN1_CMAC_GAIN_COMP_RESET 0x200020 #endif /* _CHN1_RBIST_REGFILE_H_ */