/* * Copyright (c) 2014 Qualcomm Atheros, Inc. * All Rights Reserved. * Qualcomm Atheros Confidential and Proprietary. */ // ------------------------------------------------------------------ // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. // $ATH_LICENSE_HOSTSDK0_C$ // ------------------------------------------------------------------ //=================================================================== // Author(s): ="Atheros" //=================================================================== #ifdef WLAN_HEADERS #include "hw/wifi_top_reg_map.h" #define INT_STATUS_HF_TIMER_MSB WIFICMN_LF_HF_WDT_INT_STATUS_HF_TIMER_MSB #define INT_STATUS_HF_TIMER_LSB WIFICMN_LF_HF_WDT_INT_STATUS_HF_TIMER_LSB #define INT_STATUS_HF_TIMER_MASK WIFICMN_LF_HF_WDT_INT_STATUS_HF_TIMER_MASK #define INT_STATUS_HF_TIMER_GET(x) WIFICMN_LF_HF_WDT_INT_STATUS_HF_TIMER_GET(x) #define INT_STATUS_HF_TIMER_SET(x) WIFICMN_LF_HF_WDT_INT_STATUS_HF_TIMER_SET(x) #define INT_STATUS_LF_TIMER3_MSB WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER3_MSB #define INT_STATUS_LF_TIMER3_LSB WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER3_LSB #define INT_STATUS_LF_TIMER3_MASK WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER3_MASK #define INT_STATUS_LF_TIMER3_GET(x) WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER3_GET(x) #define INT_STATUS_LF_TIMER3_SET(x) WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER3_SET(x) #define INT_STATUS_LF_TIMER2_MSB WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER2_MSB #define INT_STATUS_LF_TIMER2_LSB WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER2_LSB #define INT_STATUS_LF_TIMER2_MASK WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER2_MASK #define INT_STATUS_LF_TIMER2_GET(x) WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER2_GET(x) #define INT_STATUS_LF_TIMER2_SET(x) WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER2_SET(x) #define INT_STATUS_LF_TIMER1_MSB WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER1_MSB #define INT_STATUS_LF_TIMER1_LSB WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER1_LSB #define INT_STATUS_LF_TIMER1_MASK WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER1_MASK #define INT_STATUS_LF_TIMER1_GET(x) WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER1_GET(x) #define INT_STATUS_LF_TIMER1_SET(x) WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER1_SET(x) #define INT_STATUS_LF_TIMER0_MSB WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER0_MSB #define INT_STATUS_LF_TIMER0_LSB WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER0_LSB #define INT_STATUS_LF_TIMER0_MASK WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER0_MASK #define INT_STATUS_LF_TIMER0_GET(x) WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER0_GET(x) #define INT_STATUS_LF_TIMER0_SET(x) WIFICMN_LF_HF_WDT_INT_STATUS_LF_TIMER0_SET(x) #define WIFICMN_ISR_S1_TBTT_TIMER_TRIGGER_MASK 0x00000001 #define WIFICMN_ISR_S1_DBA_TIMER_TRIGGER_MASK 0x00000002 #define WIFICMN_ISR_S1_SBA_TIMER_TRIGGER_MASK 0x00000004 #define WIFICMN_ISR_S1_HCF_TIMER_TRIGGER_MASK 0x00000008 #define WIFICMN_ISR_S1_TIM_TIMER_TRIGGER_MASK 0x00000010 #define WIFICMN_ISR_S1_DTIM_TIMER_TRIGGER_MASK 0x00000020 #define WIFICMN_ISR_S1_QUIET_TIMER_TRIGGER_MASK 0x00000040 #define WIFICMN_ISR_S1_NDP_TIMER_TRIGGER_MASK 0x00000080 #define WIFICMN_ISR_S1_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 #define WIFICMN_ISR_S1_GENERIC_TIMER2_TRIGGER_LSB 8 #define WIFICMN_ISR_S1_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i)) #define WIFICMN_ISR_S1_TIMER_OVERFLOW_MASK 0x00010000 #define WIFICMN_ISR_S1_DBA_TIMER_THRESHOLD_MASK 0x00020000 #define WIFICMN_ISR_S1_SBA_TIMER_THRESHOLD_MASK 0x00040000 #define WIFICMN_ISR_S1_HCF_TIMER_THRESHOLD_MASK 0x00080000 #define WIFICMN_ISR_S1_TIM_TIMER_THRESHOLD_MASK 0x00100000 #define WIFICMN_ISR_S1_DTIM_TIMER_THRESHOLD_MASK 0x00200000 #define WIFICMN_ISR_S1_QUIET_TIMER_THRESHOLD_MASK 0x00400000 #define WIFICMN_ISR_S1_NDP_TIMER_THRESHOLD_MASK 0x00800000 #define WIFICMN_ISR_S1_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 #define WIFICMN_ISR_S1_GENERIC_TIMER2_THRESHOLD_LSB 24 #define WIFICMN_ISR_S1_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) #define WIFICMN_IMR_S1_TBTT_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_TBTT_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_DBA_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_DBA_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_SBA_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_SBA_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_HCF_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_HCF_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_TIM_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_TIM_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_DTIM_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_DTIM_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_QUIET_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_QUIET_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_NDP_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_NDP_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_GENERIC_TIMER2_TRIGGER_MASK WIFICMN_ISR_S1_GENERIC_TIMER2_TRIGGER_MASK #define WIFICMN_IMR_S1_GENERIC_TIMER2_TRIGGER_LSB WIFICMN_ISR_S1_GENERIC_TIMER2_TRIGGER_LSB #define WIFICMN_IMR_S1_GENERIC_TIMER2_TRIGGER(_i) WIFICMN_ISR_S1_GENERIC_TIMER2_TRIGGER(_i) #define WIFICMN_IMR_S1_TIMER_OVERFLOW_MASK WIFICMN_ISR_S1_TIMER_OVERFLOW_MASK #define WIFICMN_IMR_S1_DBA_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_DBA_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_SBA_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_SBA_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_HCF_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_HCF_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_TIM_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_TIM_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_DTIM_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_DTIM_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_QUIET_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_QUIET_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_NDP_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_NDP_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_GENERIC_TIMER2_THRESHOLD_MASK WIFICMN_ISR_S1_GENERIC_TIMER2_THRESHOLD_MASK #define WIFICMN_IMR_S1_GENERIC_TIMER2_THRESHOLD_LSB WIFICMN_ISR_S1_GENERIC_TIMER2_THRESHOLD_LSB #define WIFICMN_IMR_S1_GENERIC_TIMER2_THRESHOLD(_i) WIFICMN_ISR_S1_GENERIC_TIMER2_THRESHOLD(_i) #define WIFICMN_ISR_S1_TBTT2_TIMER_TRIGGER_MASK 0x00000100 #define WIFICMN_ISR_S1_TIM2_TIMER_TRIGGER_MASK 0x00000200 #define WIFICMN_ISR_S1_DTIM2_TIMER_TRIGGER_MASK 0x00000400 #define WIFICMN_ISR_S1_QUIET2_TIMER_TRIGGER_MASK 0x00000800 #define WIFICMN_ISR_S1_NDP2_TIMER_TRIGGER_MASK 0x00001000 #define WIFICMN_ISR_S1_SWFDA_TIMER_TRIGGER_MASK 0x00002000 #define WIFICMN_IMR_S1_TBTT2_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_TBTT2_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_TIM2_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_TIM2_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_DTIM2_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_DTIM2_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_QUIET2_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_QUIET2_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_NDP2_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_NDP2_TIMER_TRIGGER_MASK #define WIFICMN_IMR_S1_SWFDA_TIMER_TRIGGER_MASK WIFICMN_ISR_S1_SWFDA_TIMER_TRIGGER_MASK #define WIFICMN_ISR_S1_TIMER2_OVERFLOW_MASK 0x01000000 #define WIFICMN_ISR_S1_TIM2_TIMER_THRESHOLD_MASK 0x02000000 #define WIFICMN_ISR_S1_DTIM2_TIMER_THRESHOLD_MASK 0x04000000 #define WIFICMN_ISR_S1_QUIET2_TIMER_THRESHOLD_MASK 0x08000000 #define WIFICMN_ISR_S1_NDP2_TIMER_THRESHOLD_MASK 0x10000000 #define WIFICMN_ISR_S1_SWFDA_TIMER_THRESHOLD_MASK 0x20000000 #define WIFICMN_IMR_S1_TIMER2_OVERFLOW_MASK WIFICMN_ISR_S1_TIMER2_OVERFLOW_MASK #define WIFICMN_IMR_S1_TIM2_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_TIM2_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_DTIM2_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_DTIM2_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_QUIET2_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_QUIET2_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_NDP2_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_NDP2_TIMER_THRESHOLD_MASK #define WIFICMN_IMR_S1_SWFDA_TIMER_THRESHOLD_MASK WIFICMN_ISR_S1_SWFDA_TIMER_THRESHOLD_MASK #endif /* WLAN_HEADERS */