// Copyright (c) 2013 Qualcomm Atheros, Inc. All rights reserved. // $ATH_LICENSE_HW_HDR_C$ // // DO NOT EDIT! This file is automatically generated // These definitions are tied to a particular hardware layout #ifndef _PPDU_SS_11AC_SU_INFO_H_ #define _PPDU_SS_11AC_SU_INFO_H_ #if !defined(__ASSEMBLER__) #endif // ################ START SUMMARY ################# // // Dword Fields // 0 struct l_sig_a l_sig_a_bw20; // 1 struct l_sig_a l_sig_a_bw40; // 2 struct l_sig_a l_sig_a_bw80; // 3-4 struct vht_sig_a vht_sig_a_bw20; // 5-6 struct vht_sig_a vht_sig_a_bw40; // 7-8 struct vht_sig_a vht_sig_a_bw80; // 9 struct vht_sig_b_su20 vht_sig_b_bw20; // 10 struct vht_sig_b_mac_su40 vht_sig_b_bw40; // 11 struct vht_sig_b_mac_su80 vht_sig_b_bw80; // 12 struct tx_service tx_service_bw20; // 13 struct tx_service tx_service_bw40; // 14 struct tx_service tx_service_bw80; // 17-15 struct tx_pcu_info tx_pcu_info_bw20; // 20-18 struct tx_pcu_info tx_pcu_info_bw40; // 23-21 struct tx_pcu_info tx_pcu_info_bw80; // 24 duration_bw20[15:0], duration_bw40[31:16] // 25 duration_bw80[15:0], set_fc_more_data_bw20[16], set_fc_more_data_bw40[17], set_fc_more_data_bw80[18], set_fc_pwr_mgt[19], set_qc_eosp_bw20[20], set_qc_eosp_bw40[21], set_qc_eosp_bw80[22], reserved_25[31:23] // 26 pcu_data_threshold_20[3:0], pcu_data_threshold_40[7:4], pcu_data_threshold_80[11:8], reserved[31:12] // // ################ END SUMMARY ################# #define NUM_OF_DWORDS_PPDU_SS_11AC_SU_INFO 27 struct ppdu_ss_11ac_su_info { struct l_sig_a l_sig_a_bw20; struct l_sig_a l_sig_a_bw40; struct l_sig_a l_sig_a_bw80; struct vht_sig_a vht_sig_a_bw20; struct vht_sig_a vht_sig_a_bw40; struct vht_sig_a vht_sig_a_bw80; struct vht_sig_b_su20 vht_sig_b_bw20; struct vht_sig_b_mac_su40 vht_sig_b_bw40; struct vht_sig_b_mac_su80 vht_sig_b_bw80; struct tx_service tx_service_bw20; struct tx_service tx_service_bw40; struct tx_service tx_service_bw80; struct tx_pcu_info tx_pcu_info_bw20; struct tx_pcu_info tx_pcu_info_bw40; struct tx_pcu_info tx_pcu_info_bw80; volatile uint32_t duration_bw20 : 16, //[15:0] duration_bw40 : 16; //[31:16] volatile uint32_t duration_bw80 : 16, //[15:0] set_fc_more_data_bw20 : 1, //[16] set_fc_more_data_bw40 : 1, //[17] set_fc_more_data_bw80 : 1, //[18] set_fc_pwr_mgt : 1, //[19] set_qc_eosp_bw20 : 1, //[20] set_qc_eosp_bw40 : 1, //[21] set_qc_eosp_bw80 : 1, //[22] reserved_25 : 9; //[31:23] volatile uint32_t pcu_data_threshold_20 : 4, //[3:0] pcu_data_threshold_40 : 4, //[7:4] pcu_data_threshold_80 : 4, //[11:8] reserved : 20; //[31:12] }; /* struct l_sig_a l_sig_a_bw20 This field has exactly the same contents as the L_SIG_A TLV (without the tag/length word) struct l_sig_a l_sig_a_bw40 This field has exactly the same contents as the L_SIG_A TLV (without the tag/length word) struct l_sig_a l_sig_a_bw80 This field has exactly the same contents as the L_SIG_A TLV (without the tag/length word) struct vht_sig_a vht_sig_a_bw20 VHT_SIG_A field setting for 20 MHz transmission This field has exactly the same contents as the VHT_SIG_A TLV (without the tag/length word) struct vht_sig_a vht_sig_a_bw40 VHT_SIG_A field setting for 40 MHz transmission This field has exactly the same contents as the VHT_SIG_A TLV (without the tag/length word) struct vht_sig_a vht_sig_a_bw80 VHT_SIG_A field setting for 40 MHz transmission This field has exactly the same contents as the VHT_SIG_A TLV (without the tag/length word) struct vht_sig_b_su20 vht_sig_b_bw20 VHT_SIG_B field setting for 20 MHz transmission This field has exactly the same contents as the VHT_SIG_B_SU20 TLV (without the tag/length word) struct vht_sig_b_mac_su40 vht_sig_b_bw40 VHT_SIG_B field setting for 40 MHz transmission This field has exactly the same contents as the VHT_SIG_B_SU40 TLV (without the tag/length word) struct vht_sig_b_mac_su80 vht_sig_b_bw80 VHT_SIG_B field setting for 40 MHz transmission This field has exactly the same contents as the VHT_SIG_B_SU80 TLV (without the tag/length word) struct tx_service tx_service_bw20 HT SERVICE field setting for 20 MHz transmission This field has exactly the same contents as the TX_SERVICE TLV (without the tag/length word) struct tx_service tx_service_bw40 HT SERVICE field setting for 40 MHz transmission This field has exactly the same contents as the TX_SERVICE TLV (without the tag/length word) struct tx_service tx_service_bw80 HT SERVICE field setting for 80 MHz transmission This field has exactly the same contents as the TX_SERVICE TLV (without the tag/length word) struct tx_pcu_info tx_pcu_info_bw20 Info for tx_pcu for 20 MHz BW struct tx_pcu_info tx_pcu_info_bw40 Info for tx_pcu for 40 MHz BW struct tx_pcu_info tx_pcu_info_bw80 Info for tx_pcu for 80 MHz BW duration_bw20 Duration field value to be inserted in the MPDUs when transmitting at 20 MHz BW. duration_bw40 Duration field value to be inserted in the MPDUs when transmitting at 40 MHz BW duration_bw80 Duration field value to be inserted in the MPDUs when transmitting at 80 MHz BW set_fc_more_data_bw20 For 20 MHz Bandwidth: When set, the TX PCU will set the more data bit in the Frame Control field for the transmitted frames. set_fc_more_data_bw40 For 40 MHz Bandwidth: When set, the TX PCU will set the more data bit in the Frame Control field for the transmitted frames. set_fc_more_data_bw80 For 80 MHz Bandwidth: When set, the TX PCU will set the more data bit in the Frame Control field for the transmitted frames. set_fc_pwr_mgt When set, the TX PCU will set the power management bit in the Frame Control field for the transmitted frames. This will only be set for the SW generated path. set_qc_eosp_bw20 For 20 MHz Bandwidth: When set, the PCU will set the eosp bit in the QoS Control field for the transmitted frames. set_qc_eosp_bw40 For 40 MHz Bandwidth: When set, the PCU will set the eosp bit in the QoS Control field for the transmitted frames. set_qc_eosp_bw80 For 80 MHz Bandwidth: When set, the PCU will set the eosp bit in the QoS Control field for the transmitted frames. reserved_25 Reserved: Generator should set to 0, consumer shall ignore pcu_data_threshold_20 Field only used in case of 20 MHz transmission. The minimum amount of MPDU data present in the TX PCU buffer, before TX PCU allows this MPDU data to transfer to the PHY. This threshold prevents or reduces data underrun conditions during an MPDU transmission. If an entire MPDU frame is present in the TX PCU buffer that is smaller than this threshold value, this threshold is ignored, and MPDU data transfer to the PHY is allowed to start. In units of 256 bytes, except for value 0xF, which means that only when the entire frame is present in the TX PCU buffer, the transmission is allowed to start. pcu_data_threshold_40 Field only used in case of 40 MHz transmission. The minimum amount of MPDU data present in the TX PCU buffer, before TX PCU allows this MPDU data to transfer to the PHY. This threshold prevents or reduces data underrun conditions during an MPDU transmission. If an entire MPDU frame is present in the TX PCU buffer that is smaller than this threshold value, this threshold is ignored, and MPDU data transfer to the PHY is allowed to start. In units of 256 bytes, except for value 0xF, which means that only when the entire frame is present in the TX PCU buffer, the transmission is allowed to start. pcu_data_threshold_80 Field only used in case of 80 MHz transmission. The minimum amount of MPDU data present in the TX PCU buffer, before TX PCU allows this MPDU data to transfer to the PHY. This threshold prevents or reduces data underrun conditions during an MPDU transmission. If an entire MPDU frame is present in the TX PCU buffer that is smaller than this threshold value, this threshold is ignored, and MPDU data transfer to the PHY is allowed to start. In units of 256 bytes, except for value 0xF, which means that only when the entire frame is present in the TX PCU buffer, the transmission is allowed to start. reserved Reserved: Generator should set to 0, consumer shall ignore */ #define PPDU_SS_11AC_SU_INFO_0_L_SIG_A_L_SIG_A_BW20_OFFSET 0x00000000 #define PPDU_SS_11AC_SU_INFO_0_L_SIG_A_L_SIG_A_BW20_LSB 12 #define PPDU_SS_11AC_SU_INFO_0_L_SIG_A_L_SIG_A_BW20_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_1_L_SIG_A_L_SIG_A_BW40_OFFSET 0x00000004 #define PPDU_SS_11AC_SU_INFO_1_L_SIG_A_L_SIG_A_BW40_LSB 12 #define PPDU_SS_11AC_SU_INFO_1_L_SIG_A_L_SIG_A_BW40_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_2_L_SIG_A_L_SIG_A_BW80_OFFSET 0x00000008 #define PPDU_SS_11AC_SU_INFO_2_L_SIG_A_L_SIG_A_BW80_LSB 12 #define PPDU_SS_11AC_SU_INFO_2_L_SIG_A_L_SIG_A_BW80_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_3_VHT_SIG_A_VHT_SIG_A_BW20_OFFSET 0x0000000c #define PPDU_SS_11AC_SU_INFO_3_VHT_SIG_A_VHT_SIG_A_BW20_LSB 12 #define PPDU_SS_11AC_SU_INFO_3_VHT_SIG_A_VHT_SIG_A_BW20_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_4_VHT_SIG_A_VHT_SIG_A_BW20_OFFSET 0x00000010 #define PPDU_SS_11AC_SU_INFO_4_VHT_SIG_A_VHT_SIG_A_BW20_LSB 12 #define PPDU_SS_11AC_SU_INFO_4_VHT_SIG_A_VHT_SIG_A_BW20_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_5_VHT_SIG_A_VHT_SIG_A_BW40_OFFSET 0x00000014 #define PPDU_SS_11AC_SU_INFO_5_VHT_SIG_A_VHT_SIG_A_BW40_LSB 12 #define PPDU_SS_11AC_SU_INFO_5_VHT_SIG_A_VHT_SIG_A_BW40_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_6_VHT_SIG_A_VHT_SIG_A_BW40_OFFSET 0x00000018 #define PPDU_SS_11AC_SU_INFO_6_VHT_SIG_A_VHT_SIG_A_BW40_LSB 12 #define PPDU_SS_11AC_SU_INFO_6_VHT_SIG_A_VHT_SIG_A_BW40_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_7_VHT_SIG_A_VHT_SIG_A_BW80_OFFSET 0x0000001c #define PPDU_SS_11AC_SU_INFO_7_VHT_SIG_A_VHT_SIG_A_BW80_LSB 12 #define PPDU_SS_11AC_SU_INFO_7_VHT_SIG_A_VHT_SIG_A_BW80_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_8_VHT_SIG_A_VHT_SIG_A_BW80_OFFSET 0x00000020 #define PPDU_SS_11AC_SU_INFO_8_VHT_SIG_A_VHT_SIG_A_BW80_LSB 12 #define PPDU_SS_11AC_SU_INFO_8_VHT_SIG_A_VHT_SIG_A_BW80_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_9_VHT_SIG_B_SU20_VHT_SIG_B_BW20_OFFSET 0x00000024 #define PPDU_SS_11AC_SU_INFO_9_VHT_SIG_B_SU20_VHT_SIG_B_BW20_LSB 12 #define PPDU_SS_11AC_SU_INFO_9_VHT_SIG_B_SU20_VHT_SIG_B_BW20_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_10_VHT_SIG_B_MAC_SU40_VHT_SIG_B_BW40_OFFSET 0x00000028 #define PPDU_SS_11AC_SU_INFO_10_VHT_SIG_B_MAC_SU40_VHT_SIG_B_BW40_LSB 12 #define PPDU_SS_11AC_SU_INFO_10_VHT_SIG_B_MAC_SU40_VHT_SIG_B_BW40_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_11_VHT_SIG_B_MAC_SU80_VHT_SIG_B_BW80_OFFSET 0x0000002c #define PPDU_SS_11AC_SU_INFO_11_VHT_SIG_B_MAC_SU80_VHT_SIG_B_BW80_LSB 12 #define PPDU_SS_11AC_SU_INFO_11_VHT_SIG_B_MAC_SU80_VHT_SIG_B_BW80_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_12_TX_SERVICE_TX_SERVICE_BW20_OFFSET 0x00000030 #define PPDU_SS_11AC_SU_INFO_12_TX_SERVICE_TX_SERVICE_BW20_LSB 12 #define PPDU_SS_11AC_SU_INFO_12_TX_SERVICE_TX_SERVICE_BW20_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_13_TX_SERVICE_TX_SERVICE_BW40_OFFSET 0x00000034 #define PPDU_SS_11AC_SU_INFO_13_TX_SERVICE_TX_SERVICE_BW40_LSB 12 #define PPDU_SS_11AC_SU_INFO_13_TX_SERVICE_TX_SERVICE_BW40_MASK 0xffffffff #define PPDU_SS_11AC_SU_INFO_14_TX_SERVICE_TX_SERVICE_BW80_OFFSET 0x00000038 #define PPDU_SS_11AC_SU_INFO_14_TX_SERVICE_TX_SERVICE_BW80_LSB 12 #define PPDU_SS_11AC_SU_INFO_14_TX_SERVICE_TX_SERVICE_BW80_MASK 0xffffffff /* Description PPDU_SS_11AC_SU_INFO_24_DURATION_BW20 Duration field value to be inserted in the MPDUs when transmitting at 20 MHz BW. */ #define PPDU_SS_11AC_SU_INFO_24_DURATION_BW20_OFFSET 0x00000060 #define PPDU_SS_11AC_SU_INFO_24_DURATION_BW20_LSB 0 #define PPDU_SS_11AC_SU_INFO_24_DURATION_BW20_MASK 0x0000ffff /* Description PPDU_SS_11AC_SU_INFO_24_DURATION_BW40 Duration field value to be inserted in the MPDUs when transmitting at 40 MHz BW */ #define PPDU_SS_11AC_SU_INFO_24_DURATION_BW40_OFFSET 0x00000060 #define PPDU_SS_11AC_SU_INFO_24_DURATION_BW40_LSB 16 #define PPDU_SS_11AC_SU_INFO_24_DURATION_BW40_MASK 0xffff0000 /* Description PPDU_SS_11AC_SU_INFO_25_DURATION_BW80 Duration field value to be inserted in the MPDUs when transmitting at 80 MHz BW */ #define PPDU_SS_11AC_SU_INFO_25_DURATION_BW80_OFFSET 0x00000064 #define PPDU_SS_11AC_SU_INFO_25_DURATION_BW80_LSB 0 #define PPDU_SS_11AC_SU_INFO_25_DURATION_BW80_MASK 0x0000ffff /* Description PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW20 For 20 MHz Bandwidth: When set, the TX PCU will set the more data bit in the Frame Control field for the transmitted frames. */ #define PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW20_OFFSET 0x00000064 #define PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW20_LSB 16 #define PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW20_MASK 0x00010000 /* Description PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW40 For 40 MHz Bandwidth: When set, the TX PCU will set the more data bit in the Frame Control field for the transmitted frames. */ #define PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW40_OFFSET 0x00000064 #define PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW40_LSB 17 #define PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW40_MASK 0x00020000 /* Description PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW80 For 80 MHz Bandwidth: When set, the TX PCU will set the more data bit in the Frame Control field for the transmitted frames. */ #define PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW80_OFFSET 0x00000064 #define PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW80_LSB 18 #define PPDU_SS_11AC_SU_INFO_25_SET_FC_MORE_DATA_BW80_MASK 0x00040000 /* Description PPDU_SS_11AC_SU_INFO_25_SET_FC_PWR_MGT When set, the TX PCU will set the power management bit in the Frame Control field for the transmitted frames. This will only be set for the SW generated path. */ #define PPDU_SS_11AC_SU_INFO_25_SET_FC_PWR_MGT_OFFSET 0x00000064 #define PPDU_SS_11AC_SU_INFO_25_SET_FC_PWR_MGT_LSB 19 #define PPDU_SS_11AC_SU_INFO_25_SET_FC_PWR_MGT_MASK 0x00080000 /* Description PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW20 For 20 MHz Bandwidth: When set, the PCU will set the eosp bit in the QoS Control field for the transmitted frames. */ #define PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW20_OFFSET 0x00000064 #define PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW20_LSB 20 #define PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW20_MASK 0x00100000 /* Description PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW40 For 40 MHz Bandwidth: When set, the PCU will set the eosp bit in the QoS Control field for the transmitted frames. */ #define PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW40_OFFSET 0x00000064 #define PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW40_LSB 21 #define PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW40_MASK 0x00200000 /* Description PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW80 For 80 MHz Bandwidth: When set, the PCU will set the eosp bit in the QoS Control field for the transmitted frames. */ #define PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW80_OFFSET 0x00000064 #define PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW80_LSB 22 #define PPDU_SS_11AC_SU_INFO_25_SET_QC_EOSP_BW80_MASK 0x00400000 /* Description PPDU_SS_11AC_SU_INFO_25_RESERVED_25 Reserved: Generator should set to 0, consumer shall ignore */ #define PPDU_SS_11AC_SU_INFO_25_RESERVED_25_OFFSET 0x00000064 #define PPDU_SS_11AC_SU_INFO_25_RESERVED_25_LSB 23 #define PPDU_SS_11AC_SU_INFO_25_RESERVED_25_MASK 0xff800000 /* Description PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_20 Field only used in case of 20 MHz transmission. The minimum amount of MPDU data present in the TX PCU buffer, before TX PCU allows this MPDU data to transfer to the PHY. This threshold prevents or reduces data underrun conditions during an MPDU transmission. If an entire MPDU frame is present in the TX PCU buffer that is smaller than this threshold value, this threshold is ignored, and MPDU data transfer to the PHY is allowed to start. In units of 256 bytes, except for value 0xF, which means that only when the entire frame is present in the TX PCU buffer, the transmission is allowed to start. */ #define PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_20_OFFSET 0x00000068 #define PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_20_LSB 0 #define PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_20_MASK 0x0000000f /* Description PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_40 Field only used in case of 40 MHz transmission. The minimum amount of MPDU data present in the TX PCU buffer, before TX PCU allows this MPDU data to transfer to the PHY. This threshold prevents or reduces data underrun conditions during an MPDU transmission. If an entire MPDU frame is present in the TX PCU buffer that is smaller than this threshold value, this threshold is ignored, and MPDU data transfer to the PHY is allowed to start. In units of 256 bytes, except for value 0xF, which means that only when the entire frame is present in the TX PCU buffer, the transmission is allowed to start. */ #define PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_40_OFFSET 0x00000068 #define PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_40_LSB 4 #define PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_40_MASK 0x000000f0 /* Description PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_80 Field only used in case of 80 MHz transmission. The minimum amount of MPDU data present in the TX PCU buffer, before TX PCU allows this MPDU data to transfer to the PHY. This threshold prevents or reduces data underrun conditions during an MPDU transmission. If an entire MPDU frame is present in the TX PCU buffer that is smaller than this threshold value, this threshold is ignored, and MPDU data transfer to the PHY is allowed to start. In units of 256 bytes, except for value 0xF, which means that only when the entire frame is present in the TX PCU buffer, the transmission is allowed to start. */ #define PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_80_OFFSET 0x00000068 #define PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_80_LSB 8 #define PPDU_SS_11AC_SU_INFO_26_PCU_DATA_THRESHOLD_80_MASK 0x00000f00 /* Description PPDU_SS_11AC_SU_INFO_26_RESERVED Reserved: Generator should set to 0, consumer shall ignore */ #define PPDU_SS_11AC_SU_INFO_26_RESERVED_OFFSET 0x00000068 #define PPDU_SS_11AC_SU_INFO_26_RESERVED_LSB 12 #define PPDU_SS_11AC_SU_INFO_26_RESERVED_MASK 0xfffff000 #endif // _PPDU_SS_11AC_SU_INFO_H_