// Copyright (c) 2013 Qualcomm Atheros, Inc. All rights reserved. // $ATH_LICENSE_HW_HDR_C$ // // DO NOT EDIT! This file is automatically generated // These definitions are tied to a particular hardware layout #ifndef _PPDU_SS_11A_INFO_H_ #define _PPDU_SS_11A_INFO_H_ #if !defined(__ASSEMBLER__) #endif // ################ START SUMMARY ################# // // Dword Fields // 0 struct l_sig_a l_sig_a_bw20; // 1 struct tx_service tx_service_bw20; // 2 duration_bw20[15:0], set_fc_more_data[16], set_fc_pwr_mgt[17], set_qc_eosp[18], pcu_data_threshold[22:19], reserved[31:23] // // ################ END SUMMARY ################# #define NUM_OF_DWORDS_PPDU_SS_11A_INFO 3 struct ppdu_ss_11a_info { struct l_sig_a l_sig_a_bw20; struct tx_service tx_service_bw20; volatile uint32_t duration_bw20 : 16, //[15:0] set_fc_more_data : 1, //[16] set_fc_pwr_mgt : 1, //[17] set_qc_eosp : 1, //[18] pcu_data_threshold : 4, //[22:19] reserved : 9; //[31:23] }; /* struct l_sig_a l_sig_a_bw20 This field has exactly the same contents as the L_SIG_B TLV (without the tag/length word). When this is generated based on the PDG_RESPONSE from the TXPCU, this field may correspond to 20, 40, or 80 MHz response frame depending on bandwidth field in the PDG_RESPONSE. struct tx_service tx_service_bw20 This field has exactly the same contents as the TX_SERVICE TLV (without the tag/length word). When this is generated based on the PDG_RESPONSE from the TXPCU, this field may correspond to 20, 40, or 80 MHz response frame depending on bandwidth field in the PDG_RESPONSE. duration_bw20 Duration field value to be inserted in the MPDUs. When this is generated based on the PDG_RESPONSE from the TXPCU, this field may correspond to 20, 40, or 80 MHz response frame depending on bandwidth field in the PDG_RESPONSE. set_fc_more_data For user0 frames only When set, the TX PCU will set the more data bit in the Frame Control field for the transmitted frames. set_fc_pwr_mgt For user0 frames only When set, the TX PCU will set the power management bit in the Frame Control field for the transmitted frames. This will only be set for the SW generated path. set_qc_eosp For user0 frames only When set, the PCU will set the eosp bit in the QoS Control field for the transmitted frames. pcu_data_threshold The minimum amount of MPDU data present in the TX PCU buffer, before TX PCU allows this MPDU data to transfer to the PHY. This threshold prevents or reduces data underrun conditions during an MPDU transmission. If an entire MPDU frame is present in the TX PCU buffer that is smaller than this threshold value, this threshold is ignored, and MPDU data transfer to the PHY is allowed to start. In units of 256 bytes, except for value 0xF, which means that only when the entire frame is present in the TX PCU buffer, the transmission is allowed to start. reserved */ #define PPDU_SS_11A_INFO_0_L_SIG_A_L_SIG_A_BW20_OFFSET 0x00000000 #define PPDU_SS_11A_INFO_0_L_SIG_A_L_SIG_A_BW20_LSB 23 #define PPDU_SS_11A_INFO_0_L_SIG_A_L_SIG_A_BW20_MASK 0xffffffff #define PPDU_SS_11A_INFO_1_TX_SERVICE_TX_SERVICE_BW20_OFFSET 0x00000004 #define PPDU_SS_11A_INFO_1_TX_SERVICE_TX_SERVICE_BW20_LSB 23 #define PPDU_SS_11A_INFO_1_TX_SERVICE_TX_SERVICE_BW20_MASK 0xffffffff /* Description PPDU_SS_11A_INFO_2_DURATION_BW20 Duration field value to be inserted in the MPDUs. When this is generated based on the PDG_RESPONSE from the TXPCU, this field may correspond to 20, 40, or 80 MHz response frame depending on bandwidth field in the PDG_RESPONSE. */ #define PPDU_SS_11A_INFO_2_DURATION_BW20_OFFSET 0x00000008 #define PPDU_SS_11A_INFO_2_DURATION_BW20_LSB 0 #define PPDU_SS_11A_INFO_2_DURATION_BW20_MASK 0x0000ffff /* Description PPDU_SS_11A_INFO_2_SET_FC_MORE_DATA For user0 frames only When set, the TX PCU will set the more data bit in the Frame Control field for the transmitted frames. */ #define PPDU_SS_11A_INFO_2_SET_FC_MORE_DATA_OFFSET 0x00000008 #define PPDU_SS_11A_INFO_2_SET_FC_MORE_DATA_LSB 16 #define PPDU_SS_11A_INFO_2_SET_FC_MORE_DATA_MASK 0x00010000 /* Description PPDU_SS_11A_INFO_2_SET_FC_PWR_MGT For user0 frames only When set, the TX PCU will set the power management bit in the Frame Control field for the transmitted frames. This will only be set for the SW generated path. */ #define PPDU_SS_11A_INFO_2_SET_FC_PWR_MGT_OFFSET 0x00000008 #define PPDU_SS_11A_INFO_2_SET_FC_PWR_MGT_LSB 17 #define PPDU_SS_11A_INFO_2_SET_FC_PWR_MGT_MASK 0x00020000 /* Description PPDU_SS_11A_INFO_2_SET_QC_EOSP For user0 frames only When set, the PCU will set the eosp bit in the QoS Control field for the transmitted frames. */ #define PPDU_SS_11A_INFO_2_SET_QC_EOSP_OFFSET 0x00000008 #define PPDU_SS_11A_INFO_2_SET_QC_EOSP_LSB 18 #define PPDU_SS_11A_INFO_2_SET_QC_EOSP_MASK 0x00040000 /* Description PPDU_SS_11A_INFO_2_PCU_DATA_THRESHOLD The minimum amount of MPDU data present in the TX PCU buffer, before TX PCU allows this MPDU data to transfer to the PHY. This threshold prevents or reduces data underrun conditions during an MPDU transmission. If an entire MPDU frame is present in the TX PCU buffer that is smaller than this threshold value, this threshold is ignored, and MPDU data transfer to the PHY is allowed to start. In units of 256 bytes, except for value 0xF, which means that only when the entire frame is present in the TX PCU buffer, the transmission is allowed to start. */ #define PPDU_SS_11A_INFO_2_PCU_DATA_THRESHOLD_OFFSET 0x00000008 #define PPDU_SS_11A_INFO_2_PCU_DATA_THRESHOLD_LSB 19 #define PPDU_SS_11A_INFO_2_PCU_DATA_THRESHOLD_MASK 0x00780000 /* Description PPDU_SS_11A_INFO_2_RESERVED */ #define PPDU_SS_11A_INFO_2_RESERVED_OFFSET 0x00000008 #define PPDU_SS_11A_INFO_2_RESERVED_LSB 23 #define PPDU_SS_11A_INFO_2_RESERVED_MASK 0xff800000 #endif // _PPDU_SS_11A_INFO_H_