// // ----------------------------------------------------------------------------- // Copyright (c) 2011-2014 Qualcomm Atheros, Inc. All rights reserved. // ----------------------------------------------------------------------------- // FILE : sm_table_map.h // DESCRIPTION : Software Header File for WiFi 2.0 // THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT // ----------------------------------------------------------------------------- // #ifndef _SM_TABLE_MAP_H_ #define _SM_TABLE_MAP_H_ #ifndef __SM_TABLE_MAP_BASE_ADDRESS #define __SM_TABLE_MAP_BASE_ADDRESS (0x0) #endif // 0x0 (BB_SM_TABLES_DUMMY1) #define BB_SM_TABLES_DUMMY1_DUMMY1_LSB 0 #define BB_SM_TABLES_DUMMY1_DUMMY1_MSB 31 #define BB_SM_TABLES_DUMMY1_DUMMY1_MASK 0xffffffff #define BB_SM_TABLES_DUMMY1_DUMMY1_GET(x) (((x) & BB_SM_TABLES_DUMMY1_DUMMY1_MASK) >> BB_SM_TABLES_DUMMY1_DUMMY1_LSB) #define BB_SM_TABLES_DUMMY1_DUMMY1_SET(x) (((0 | (x)) << BB_SM_TABLES_DUMMY1_DUMMY1_LSB) & BB_SM_TABLES_DUMMY1_DUMMY1_MASK) #define BB_SM_TABLES_DUMMY1_DUMMY1_RESET 0x0 #define BB_SM_TABLES_DUMMY1_ADDRESS (0x0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_TABLES_DUMMY1_RSTMASK 0xffffffff #define BB_SM_TABLES_DUMMY1_RESET 0x0 // 0x300 (BB_DC_DAC_MEM_B0) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_RESET 0x0 #define BB_DC_DAC_MEM_B0_ADDRESS (0x300 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_RESET 0x0 // 0x300 (BB_DC_DAC_MEM_B0_0) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_0_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_0_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_0_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_0_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_0_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_0_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_0_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_0_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_0_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_0_RESET 0x0 #define BB_DC_DAC_MEM_B0_0_ADDRESS (0x300 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_0_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_0_RESET 0x0 // 0x304 (BB_DC_DAC_MEM_B0_1) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_1_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_1_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_1_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_1_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_1_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_1_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_1_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_1_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_1_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_1_RESET 0x0 #define BB_DC_DAC_MEM_B0_1_ADDRESS (0x304 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_1_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_1_RESET 0x0 // 0x308 (BB_DC_DAC_MEM_B0_2) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_2_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_2_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_2_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_2_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_2_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_2_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_2_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_2_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_2_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_2_RESET 0x0 #define BB_DC_DAC_MEM_B0_2_ADDRESS (0x308 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_2_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_2_RESET 0x0 // 0x30c (BB_DC_DAC_MEM_B0_3) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_3_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_3_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_3_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_3_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_3_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_3_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_3_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_3_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_3_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_3_RESET 0x0 #define BB_DC_DAC_MEM_B0_3_ADDRESS (0x30c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_3_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_3_RESET 0x0 // 0x310 (BB_DC_DAC_MEM_B0_4) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_4_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_4_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_4_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_4_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_4_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_4_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_4_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_4_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_4_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_4_RESET 0x0 #define BB_DC_DAC_MEM_B0_4_ADDRESS (0x310 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_4_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_4_RESET 0x0 // 0x314 (BB_DC_DAC_MEM_B0_5) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_5_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_5_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_5_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_5_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_5_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_5_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_5_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_5_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_5_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_5_RESET 0x0 #define BB_DC_DAC_MEM_B0_5_ADDRESS (0x314 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_5_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_5_RESET 0x0 // 0x318 (BB_DC_DAC_MEM_B0_6) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_6_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_6_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_6_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_6_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_6_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_6_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_6_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_6_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_6_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_6_RESET 0x0 #define BB_DC_DAC_MEM_B0_6_ADDRESS (0x318 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_6_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_6_RESET 0x0 // 0x31c (BB_DC_DAC_MEM_B0_7) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_7_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_7_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_7_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_7_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_7_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_7_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_7_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_7_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_7_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_7_RESET 0x0 #define BB_DC_DAC_MEM_B0_7_ADDRESS (0x31c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_7_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_7_RESET 0x0 // 0x320 (BB_DC_DAC_MEM_B0_8) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_8_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_8_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_8_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_8_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_8_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_8_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_8_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_8_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_8_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_8_RESET 0x0 #define BB_DC_DAC_MEM_B0_8_ADDRESS (0x320 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_8_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_8_RESET 0x0 // 0x324 (BB_DC_DAC_MEM_B0_9) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_9_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_9_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_9_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_9_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_9_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_9_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_9_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_9_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_9_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_9_RESET 0x0 #define BB_DC_DAC_MEM_B0_9_ADDRESS (0x324 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_9_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_9_RESET 0x0 // 0x328 (BB_DC_DAC_MEM_B0_10) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_10_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_10_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_10_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_10_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_10_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_10_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_10_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_10_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_10_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_10_RESET 0x0 #define BB_DC_DAC_MEM_B0_10_ADDRESS (0x328 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_10_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_10_RESET 0x0 // 0x32c (BB_DC_DAC_MEM_B0_11) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_11_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_11_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_11_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_11_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_11_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_11_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_11_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_11_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_11_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_11_RESET 0x0 #define BB_DC_DAC_MEM_B0_11_ADDRESS (0x32c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_11_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_11_RESET 0x0 // 0x330 (BB_DC_DAC_MEM_B0_12) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_12_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_12_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_12_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_12_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_12_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_12_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_12_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_12_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_12_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_12_RESET 0x0 #define BB_DC_DAC_MEM_B0_12_ADDRESS (0x330 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_12_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_12_RESET 0x0 // 0x334 (BB_DC_DAC_MEM_B0_13) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_13_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_13_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_13_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_13_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_13_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_13_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_13_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_13_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_13_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_13_RESET 0x0 #define BB_DC_DAC_MEM_B0_13_ADDRESS (0x334 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_13_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_13_RESET 0x0 // 0x338 (BB_DC_DAC_MEM_B0_14) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_14_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_14_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_14_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_14_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_14_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_14_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_14_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_14_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_14_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_14_RESET 0x0 #define BB_DC_DAC_MEM_B0_14_ADDRESS (0x338 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_14_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_14_RESET 0x0 // 0x33c (BB_DC_DAC_MEM_B0_15) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_15_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_15_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_15_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_15_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_15_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_15_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_15_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_15_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_15_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_15_RESET 0x0 #define BB_DC_DAC_MEM_B0_15_ADDRESS (0x33c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_15_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_15_RESET 0x0 // 0x340 (BB_DC_DAC_MEM_B0_16) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_16_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_16_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_16_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_16_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_16_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_16_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_16_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_16_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_16_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_16_RESET 0x0 #define BB_DC_DAC_MEM_B0_16_ADDRESS (0x340 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_16_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_16_RESET 0x0 // 0x344 (BB_DC_DAC_MEM_B0_17) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_17_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_17_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_17_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_17_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_17_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_17_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_17_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_17_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_17_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_17_RESET 0x0 #define BB_DC_DAC_MEM_B0_17_ADDRESS (0x344 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_17_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_17_RESET 0x0 // 0x348 (BB_DC_DAC_MEM_B0_18) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_18_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_18_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_18_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_18_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_18_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_18_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_18_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_18_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_18_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_18_RESET 0x0 #define BB_DC_DAC_MEM_B0_18_ADDRESS (0x348 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_18_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_18_RESET 0x0 // 0x34c (BB_DC_DAC_MEM_B0_19) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_19_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_19_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_19_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_19_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_19_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_19_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_19_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_19_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_19_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_19_RESET 0x0 #define BB_DC_DAC_MEM_B0_19_ADDRESS (0x34c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_19_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_19_RESET 0x0 // 0x350 (BB_DC_DAC_MEM_B0_20) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_20_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_20_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_20_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_20_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_20_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_20_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_20_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_20_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_20_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_20_RESET 0x0 #define BB_DC_DAC_MEM_B0_20_ADDRESS (0x350 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_20_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_20_RESET 0x0 // 0x354 (BB_DC_DAC_MEM_B0_21) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_21_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_21_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_21_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_21_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_21_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_21_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_21_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_21_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_21_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_21_RESET 0x0 #define BB_DC_DAC_MEM_B0_21_ADDRESS (0x354 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_21_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_21_RESET 0x0 // 0x358 (BB_DC_DAC_MEM_B0_22) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_22_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_22_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_22_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_22_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_22_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_22_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_22_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_22_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_22_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_22_RESET 0x0 #define BB_DC_DAC_MEM_B0_22_ADDRESS (0x358 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_22_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_22_RESET 0x0 // 0x35c (BB_DC_DAC_MEM_B0_23) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_23_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_23_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_23_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_23_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_23_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_23_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_23_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_23_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_23_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_23_RESET 0x0 #define BB_DC_DAC_MEM_B0_23_ADDRESS (0x35c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_23_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_23_RESET 0x0 // 0x360 (BB_DC_DAC_MEM_B0_24) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_24_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_24_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_24_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_24_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_24_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_24_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_24_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_24_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_24_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_24_RESET 0x0 #define BB_DC_DAC_MEM_B0_24_ADDRESS (0x360 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_24_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_24_RESET 0x0 // 0x364 (BB_DC_DAC_MEM_B0_25) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_25_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_25_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_25_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_25_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_25_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_25_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_25_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_25_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_25_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_25_RESET 0x0 #define BB_DC_DAC_MEM_B0_25_ADDRESS (0x364 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_25_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_25_RESET 0x0 // 0x368 (BB_DC_DAC_MEM_B0_26) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_26_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_26_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_26_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_26_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_26_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_26_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_26_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_26_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_26_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_26_RESET 0x0 #define BB_DC_DAC_MEM_B0_26_ADDRESS (0x368 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_26_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_26_RESET 0x0 // 0x36c (BB_DC_DAC_MEM_B0_27) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_27_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_27_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_27_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_27_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_27_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_27_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_27_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_27_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_27_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_27_RESET 0x0 #define BB_DC_DAC_MEM_B0_27_ADDRESS (0x36c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_27_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_27_RESET 0x0 // 0x370 (BB_DC_DAC_MEM_B0_28) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_28_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_28_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_28_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_28_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_28_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_28_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_28_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_28_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_28_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_28_RESET 0x0 #define BB_DC_DAC_MEM_B0_28_ADDRESS (0x370 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_28_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_28_RESET 0x0 // 0x374 (BB_DC_DAC_MEM_B0_29) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_29_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_29_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_29_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_29_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_29_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_29_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_29_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_29_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_29_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_29_RESET 0x0 #define BB_DC_DAC_MEM_B0_29_ADDRESS (0x374 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_29_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_29_RESET 0x0 // 0x378 (BB_DC_DAC_MEM_B0_30) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_30_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_30_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_30_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_30_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_30_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_30_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_30_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_30_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_30_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_30_RESET 0x0 #define BB_DC_DAC_MEM_B0_30_ADDRESS (0x378 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_30_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_30_RESET 0x0 // 0x37c (BB_DC_DAC_MEM_B0_31) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_31_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_31_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_31_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_31_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_31_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_31_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_31_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_31_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_31_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_31_RESET 0x0 #define BB_DC_DAC_MEM_B0_31_ADDRESS (0x37c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_31_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_31_RESET 0x0 // 0x380 (BB_DC_DAC_MEM_B0_32) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_32_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_32_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_32_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_32_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_32_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_32_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_32_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_32_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_32_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_32_RESET 0x0 #define BB_DC_DAC_MEM_B0_32_ADDRESS (0x380 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_32_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_32_RESET 0x0 // 0x384 (BB_DC_DAC_MEM_B0_33) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_33_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_33_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_33_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_33_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_33_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_33_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_33_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_33_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_33_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_33_RESET 0x0 #define BB_DC_DAC_MEM_B0_33_ADDRESS (0x384 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_33_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_33_RESET 0x0 // 0x388 (BB_DC_DAC_MEM_B0_34) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_34_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_34_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_34_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_34_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_34_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_34_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_34_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_34_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_34_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_34_RESET 0x0 #define BB_DC_DAC_MEM_B0_34_ADDRESS (0x388 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_34_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_34_RESET 0x0 // 0x38c (BB_DC_DAC_MEM_B0_35) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_35_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_35_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_35_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_35_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_35_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_35_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_35_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_35_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_35_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_35_RESET 0x0 #define BB_DC_DAC_MEM_B0_35_ADDRESS (0x38c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_35_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_35_RESET 0x0 // 0x390 (BB_DC_DAC_MEM_B0_36) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_36_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_36_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_36_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_36_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_36_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_36_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_36_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_36_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_36_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_36_RESET 0x0 #define BB_DC_DAC_MEM_B0_36_ADDRESS (0x390 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_36_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_36_RESET 0x0 // 0x394 (BB_DC_DAC_MEM_B0_37) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_37_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_37_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_37_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_37_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_37_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_37_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_37_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_37_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_37_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_37_RESET 0x0 #define BB_DC_DAC_MEM_B0_37_ADDRESS (0x394 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_37_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_37_RESET 0x0 // 0x398 (BB_DC_DAC_MEM_B0_38) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_38_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_38_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_38_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_38_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_38_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_38_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_38_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_38_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_38_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_38_RESET 0x0 #define BB_DC_DAC_MEM_B0_38_ADDRESS (0x398 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_38_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_38_RESET 0x0 // 0x39c (BB_DC_DAC_MEM_B0_39) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_39_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_39_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_39_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_39_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_39_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_39_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_39_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_39_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_39_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_39_RESET 0x0 #define BB_DC_DAC_MEM_B0_39_ADDRESS (0x39c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_39_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_39_RESET 0x0 // 0x3a0 (BB_DC_DAC_MEM_B0_40) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_40_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_40_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_40_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_40_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_40_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_40_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_40_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_40_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_40_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_40_RESET 0x0 #define BB_DC_DAC_MEM_B0_40_ADDRESS (0x3a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_40_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_40_RESET 0x0 // 0x3a4 (BB_DC_DAC_MEM_B0_41) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_41_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_41_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_41_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_41_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_41_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_41_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_41_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_41_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_41_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_41_RESET 0x0 #define BB_DC_DAC_MEM_B0_41_ADDRESS (0x3a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_41_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_41_RESET 0x0 // 0x3a8 (BB_DC_DAC_MEM_B0_42) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_42_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_42_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_42_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_42_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_42_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_42_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_42_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_42_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_42_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_42_RESET 0x0 #define BB_DC_DAC_MEM_B0_42_ADDRESS (0x3a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_42_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_42_RESET 0x0 // 0x3ac (BB_DC_DAC_MEM_B0_43) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_43_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_43_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_43_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_43_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_43_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_43_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_43_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_43_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_43_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_43_RESET 0x0 #define BB_DC_DAC_MEM_B0_43_ADDRESS (0x3ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_43_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_43_RESET 0x0 // 0x3b0 (BB_DC_DAC_MEM_B0_44) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_44_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_44_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_44_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_44_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_44_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_44_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_44_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_44_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_44_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_44_RESET 0x0 #define BB_DC_DAC_MEM_B0_44_ADDRESS (0x3b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_44_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_44_RESET 0x0 // 0x3b4 (BB_DC_DAC_MEM_B0_45) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_45_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_45_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_45_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_45_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_45_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_45_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_45_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_45_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_45_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_45_RESET 0x0 #define BB_DC_DAC_MEM_B0_45_ADDRESS (0x3b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_45_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_45_RESET 0x0 // 0x3b8 (BB_DC_DAC_MEM_B0_46) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_46_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_46_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_46_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_46_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_46_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_46_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_46_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_46_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_46_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_46_RESET 0x0 #define BB_DC_DAC_MEM_B0_46_ADDRESS (0x3b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_46_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_46_RESET 0x0 // 0x3bc (BB_DC_DAC_MEM_B0_47) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_47_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_47_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_47_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_47_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_47_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_47_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_47_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_47_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_47_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_47_RESET 0x0 #define BB_DC_DAC_MEM_B0_47_ADDRESS (0x3bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_47_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_47_RESET 0x0 // 0x3c0 (BB_DC_DAC_MEM_B0_48) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_48_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_48_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_48_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_48_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_48_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_48_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_48_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_48_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_48_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_48_RESET 0x0 #define BB_DC_DAC_MEM_B0_48_ADDRESS (0x3c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_48_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_48_RESET 0x0 // 0x3c4 (BB_DC_DAC_MEM_B0_49) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_49_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_49_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_49_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_49_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_49_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_49_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_49_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_49_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_49_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_49_RESET 0x0 #define BB_DC_DAC_MEM_B0_49_ADDRESS (0x3c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_49_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_49_RESET 0x0 // 0x3c8 (BB_DC_DAC_MEM_B0_50) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_50_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_50_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_50_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_50_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_50_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_50_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_50_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_50_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_50_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_50_RESET 0x0 #define BB_DC_DAC_MEM_B0_50_ADDRESS (0x3c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_50_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_50_RESET 0x0 // 0x3cc (BB_DC_DAC_MEM_B0_51) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_51_LSB 0 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_51_MSB 31 #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_51_MASK 0xffffffff #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_51_GET(x) (((x) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_51_MASK) >> BB_DC_DAC_MEM_B0_DC_DAC_SETTING_51_LSB) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_51_SET(x) (((0 | (x)) << BB_DC_DAC_MEM_B0_DC_DAC_SETTING_51_LSB) & BB_DC_DAC_MEM_B0_DC_DAC_SETTING_51_MASK) #define BB_DC_DAC_MEM_B0_DC_DAC_SETTING_51_RESET 0x0 #define BB_DC_DAC_MEM_B0_51_ADDRESS (0x3cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_DC_DAC_MEM_B0_51_RSTMASK 0xffffffff #define BB_DC_DAC_MEM_B0_51_RESET 0x0 // 0x400 (BB_TPC_TXGAIN_SRAM) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_ADDRESS (0x400 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_RESET 0x0 // 0x400 (BB_TPC_TXGAIN_SRAM_0) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_0_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_0_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_0_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_0_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_0_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_0_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_0_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_0_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_0_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_0_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_0_ADDRESS (0x400 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_0_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_0_RESET 0x0 // 0x404 (BB_TPC_TXGAIN_SRAM_1) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_1_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_1_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_1_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_1_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_1_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_1_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_1_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_1_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_1_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_1_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_1_ADDRESS (0x404 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_1_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_1_RESET 0x0 // 0x408 (BB_TPC_TXGAIN_SRAM_2) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_2_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_2_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_2_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_2_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_2_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_2_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_2_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_2_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_2_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_2_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_2_ADDRESS (0x408 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_2_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_2_RESET 0x0 // 0x40c (BB_TPC_TXGAIN_SRAM_3) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_3_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_3_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_3_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_3_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_3_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_3_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_3_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_3_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_3_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_3_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_3_ADDRESS (0x40c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_3_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_3_RESET 0x0 // 0x410 (BB_TPC_TXGAIN_SRAM_4) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_4_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_4_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_4_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_4_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_4_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_4_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_4_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_4_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_4_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_4_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_4_ADDRESS (0x410 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_4_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_4_RESET 0x0 // 0x414 (BB_TPC_TXGAIN_SRAM_5) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_5_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_5_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_5_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_5_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_5_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_5_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_5_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_5_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_5_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_5_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_5_ADDRESS (0x414 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_5_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_5_RESET 0x0 // 0x418 (BB_TPC_TXGAIN_SRAM_6) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_6_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_6_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_6_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_6_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_6_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_6_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_6_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_6_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_6_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_6_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_6_ADDRESS (0x418 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_6_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_6_RESET 0x0 // 0x41c (BB_TPC_TXGAIN_SRAM_7) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_7_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_7_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_7_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_7_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_7_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_7_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_7_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_7_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_7_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_7_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_7_ADDRESS (0x41c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_7_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_7_RESET 0x0 // 0x420 (BB_TPC_TXGAIN_SRAM_8) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_8_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_8_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_8_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_8_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_8_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_8_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_8_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_8_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_8_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_8_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_8_ADDRESS (0x420 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_8_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_8_RESET 0x0 // 0x424 (BB_TPC_TXGAIN_SRAM_9) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_9_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_9_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_9_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_9_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_9_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_9_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_9_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_9_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_9_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_9_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_9_ADDRESS (0x424 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_9_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_9_RESET 0x0 // 0x428 (BB_TPC_TXGAIN_SRAM_10) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_10_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_10_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_10_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_10_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_10_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_10_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_10_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_10_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_10_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_10_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_10_ADDRESS (0x428 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_10_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_10_RESET 0x0 // 0x42c (BB_TPC_TXGAIN_SRAM_11) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_11_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_11_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_11_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_11_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_11_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_11_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_11_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_11_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_11_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_11_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_11_ADDRESS (0x42c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_11_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_11_RESET 0x0 // 0x430 (BB_TPC_TXGAIN_SRAM_12) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_12_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_12_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_12_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_12_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_12_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_12_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_12_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_12_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_12_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_12_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_12_ADDRESS (0x430 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_12_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_12_RESET 0x0 // 0x434 (BB_TPC_TXGAIN_SRAM_13) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_13_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_13_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_13_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_13_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_13_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_13_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_13_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_13_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_13_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_13_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_13_ADDRESS (0x434 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_13_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_13_RESET 0x0 // 0x438 (BB_TPC_TXGAIN_SRAM_14) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_14_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_14_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_14_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_14_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_14_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_14_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_14_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_14_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_14_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_14_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_14_ADDRESS (0x438 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_14_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_14_RESET 0x0 // 0x43c (BB_TPC_TXGAIN_SRAM_15) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_15_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_15_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_15_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_15_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_15_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_15_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_15_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_15_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_15_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_15_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_15_ADDRESS (0x43c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_15_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_15_RESET 0x0 // 0x440 (BB_TPC_TXGAIN_SRAM_16) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_16_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_16_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_16_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_16_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_16_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_16_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_16_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_16_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_16_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_16_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_16_ADDRESS (0x440 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_16_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_16_RESET 0x0 // 0x444 (BB_TPC_TXGAIN_SRAM_17) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_17_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_17_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_17_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_17_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_17_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_17_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_17_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_17_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_17_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_17_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_17_ADDRESS (0x444 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_17_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_17_RESET 0x0 // 0x448 (BB_TPC_TXGAIN_SRAM_18) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_18_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_18_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_18_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_18_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_18_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_18_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_18_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_18_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_18_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_18_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_18_ADDRESS (0x448 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_18_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_18_RESET 0x0 // 0x44c (BB_TPC_TXGAIN_SRAM_19) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_19_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_19_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_19_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_19_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_19_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_19_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_19_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_19_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_19_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_19_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_19_ADDRESS (0x44c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_19_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_19_RESET 0x0 // 0x450 (BB_TPC_TXGAIN_SRAM_20) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_20_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_20_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_20_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_20_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_20_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_20_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_20_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_20_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_20_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_20_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_20_ADDRESS (0x450 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_20_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_20_RESET 0x0 // 0x454 (BB_TPC_TXGAIN_SRAM_21) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_21_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_21_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_21_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_21_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_21_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_21_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_21_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_21_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_21_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_21_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_21_ADDRESS (0x454 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_21_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_21_RESET 0x0 // 0x458 (BB_TPC_TXGAIN_SRAM_22) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_22_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_22_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_22_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_22_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_22_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_22_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_22_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_22_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_22_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_22_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_22_ADDRESS (0x458 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_22_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_22_RESET 0x0 // 0x45c (BB_TPC_TXGAIN_SRAM_23) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_23_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_23_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_23_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_23_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_23_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_23_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_23_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_23_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_23_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_23_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_23_ADDRESS (0x45c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_23_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_23_RESET 0x0 // 0x460 (BB_TPC_TXGAIN_SRAM_24) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_24_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_24_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_24_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_24_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_24_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_24_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_24_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_24_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_24_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_24_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_24_ADDRESS (0x460 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_24_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_24_RESET 0x0 // 0x464 (BB_TPC_TXGAIN_SRAM_25) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_25_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_25_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_25_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_25_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_25_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_25_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_25_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_25_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_25_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_25_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_25_ADDRESS (0x464 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_25_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_25_RESET 0x0 // 0x468 (BB_TPC_TXGAIN_SRAM_26) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_26_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_26_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_26_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_26_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_26_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_26_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_26_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_26_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_26_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_26_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_26_ADDRESS (0x468 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_26_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_26_RESET 0x0 // 0x46c (BB_TPC_TXGAIN_SRAM_27) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_27_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_27_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_27_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_27_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_27_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_27_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_27_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_27_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_27_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_27_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_27_ADDRESS (0x46c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_27_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_27_RESET 0x0 // 0x470 (BB_TPC_TXGAIN_SRAM_28) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_28_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_28_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_28_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_28_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_28_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_28_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_28_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_28_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_28_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_28_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_28_ADDRESS (0x470 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_28_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_28_RESET 0x0 // 0x474 (BB_TPC_TXGAIN_SRAM_29) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_29_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_29_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_29_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_29_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_29_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_29_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_29_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_29_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_29_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_29_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_29_ADDRESS (0x474 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_29_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_29_RESET 0x0 // 0x478 (BB_TPC_TXGAIN_SRAM_30) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_30_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_30_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_30_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_30_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_30_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_30_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_30_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_30_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_30_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_30_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_30_ADDRESS (0x478 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_30_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_30_RESET 0x0 // 0x47c (BB_TPC_TXGAIN_SRAM_31) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_31_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_31_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_31_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_31_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_31_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_31_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_31_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_31_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_31_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_31_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_31_ADDRESS (0x47c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_31_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_31_RESET 0x0 // 0x480 (BB_TPC_TXGAIN_SRAM_32) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_32_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_32_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_32_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_32_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_32_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_32_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_32_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_32_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_32_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_32_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_32_ADDRESS (0x480 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_32_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_32_RESET 0x0 // 0x484 (BB_TPC_TXGAIN_SRAM_33) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_33_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_33_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_33_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_33_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_33_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_33_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_33_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_33_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_33_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_33_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_33_ADDRESS (0x484 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_33_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_33_RESET 0x0 // 0x488 (BB_TPC_TXGAIN_SRAM_34) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_34_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_34_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_34_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_34_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_34_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_34_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_34_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_34_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_34_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_34_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_34_ADDRESS (0x488 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_34_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_34_RESET 0x0 // 0x48c (BB_TPC_TXGAIN_SRAM_35) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_35_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_35_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_35_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_35_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_35_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_35_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_35_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_35_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_35_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_35_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_35_ADDRESS (0x48c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_35_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_35_RESET 0x0 // 0x490 (BB_TPC_TXGAIN_SRAM_36) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_36_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_36_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_36_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_36_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_36_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_36_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_36_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_36_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_36_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_36_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_36_ADDRESS (0x490 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_36_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_36_RESET 0x0 // 0x494 (BB_TPC_TXGAIN_SRAM_37) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_37_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_37_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_37_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_37_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_37_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_37_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_37_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_37_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_37_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_37_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_37_ADDRESS (0x494 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_37_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_37_RESET 0x0 // 0x498 (BB_TPC_TXGAIN_SRAM_38) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_38_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_38_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_38_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_38_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_38_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_38_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_38_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_38_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_38_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_38_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_38_ADDRESS (0x498 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_38_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_38_RESET 0x0 // 0x49c (BB_TPC_TXGAIN_SRAM_39) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_39_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_39_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_39_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_39_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_39_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_39_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_39_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_39_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_39_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_39_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_39_ADDRESS (0x49c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_39_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_39_RESET 0x0 // 0x4a0 (BB_TPC_TXGAIN_SRAM_40) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_40_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_40_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_40_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_40_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_40_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_40_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_40_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_40_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_40_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_40_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_40_ADDRESS (0x4a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_40_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_40_RESET 0x0 // 0x4a4 (BB_TPC_TXGAIN_SRAM_41) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_41_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_41_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_41_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_41_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_41_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_41_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_41_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_41_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_41_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_41_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_41_ADDRESS (0x4a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_41_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_41_RESET 0x0 // 0x4a8 (BB_TPC_TXGAIN_SRAM_42) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_42_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_42_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_42_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_42_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_42_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_42_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_42_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_42_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_42_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_42_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_42_ADDRESS (0x4a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_42_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_42_RESET 0x0 // 0x4ac (BB_TPC_TXGAIN_SRAM_43) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_43_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_43_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_43_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_43_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_43_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_43_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_43_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_43_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_43_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_43_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_43_ADDRESS (0x4ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_43_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_43_RESET 0x0 // 0x4b0 (BB_TPC_TXGAIN_SRAM_44) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_44_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_44_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_44_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_44_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_44_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_44_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_44_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_44_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_44_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_44_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_44_ADDRESS (0x4b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_44_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_44_RESET 0x0 // 0x4b4 (BB_TPC_TXGAIN_SRAM_45) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_45_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_45_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_45_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_45_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_45_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_45_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_45_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_45_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_45_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_45_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_45_ADDRESS (0x4b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_45_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_45_RESET 0x0 // 0x4b8 (BB_TPC_TXGAIN_SRAM_46) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_46_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_46_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_46_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_46_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_46_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_46_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_46_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_46_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_46_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_46_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_46_ADDRESS (0x4b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_46_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_46_RESET 0x0 // 0x4bc (BB_TPC_TXGAIN_SRAM_47) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_47_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_47_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_47_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_47_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_47_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_47_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_47_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_47_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_47_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_47_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_47_ADDRESS (0x4bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_47_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_47_RESET 0x0 // 0x4c0 (BB_TPC_TXGAIN_SRAM_48) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_48_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_48_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_48_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_48_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_48_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_48_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_48_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_48_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_48_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_48_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_48_ADDRESS (0x4c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_48_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_48_RESET 0x0 // 0x4c4 (BB_TPC_TXGAIN_SRAM_49) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_49_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_49_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_49_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_49_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_49_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_49_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_49_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_49_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_49_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_49_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_49_ADDRESS (0x4c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_49_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_49_RESET 0x0 // 0x4c8 (BB_TPC_TXGAIN_SRAM_50) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_50_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_50_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_50_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_50_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_50_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_50_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_50_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_50_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_50_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_50_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_50_ADDRESS (0x4c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_50_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_50_RESET 0x0 // 0x4cc (BB_TPC_TXGAIN_SRAM_51) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_51_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_51_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_51_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_51_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_51_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_51_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_51_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_51_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_51_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_51_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_51_ADDRESS (0x4cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_51_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_51_RESET 0x0 // 0x4d0 (BB_TPC_TXGAIN_SRAM_52) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_52_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_52_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_52_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_52_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_52_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_52_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_52_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_52_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_52_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_52_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_52_ADDRESS (0x4d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_52_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_52_RESET 0x0 // 0x4d4 (BB_TPC_TXGAIN_SRAM_53) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_53_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_53_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_53_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_53_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_53_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_53_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_53_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_53_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_53_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_53_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_53_ADDRESS (0x4d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_53_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_53_RESET 0x0 // 0x4d8 (BB_TPC_TXGAIN_SRAM_54) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_54_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_54_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_54_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_54_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_54_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_54_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_54_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_54_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_54_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_54_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_54_ADDRESS (0x4d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_54_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_54_RESET 0x0 // 0x4dc (BB_TPC_TXGAIN_SRAM_55) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_55_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_55_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_55_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_55_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_55_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_55_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_55_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_55_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_55_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_55_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_55_ADDRESS (0x4dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_55_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_55_RESET 0x0 // 0x4e0 (BB_TPC_TXGAIN_SRAM_56) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_56_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_56_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_56_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_56_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_56_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_56_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_56_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_56_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_56_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_56_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_56_ADDRESS (0x4e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_56_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_56_RESET 0x0 // 0x4e4 (BB_TPC_TXGAIN_SRAM_57) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_57_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_57_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_57_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_57_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_57_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_57_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_57_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_57_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_57_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_57_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_57_ADDRESS (0x4e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_57_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_57_RESET 0x0 // 0x4e8 (BB_TPC_TXGAIN_SRAM_58) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_58_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_58_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_58_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_58_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_58_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_58_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_58_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_58_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_58_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_58_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_58_ADDRESS (0x4e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_58_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_58_RESET 0x0 // 0x4ec (BB_TPC_TXGAIN_SRAM_59) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_59_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_59_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_59_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_59_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_59_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_59_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_59_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_59_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_59_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_59_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_59_ADDRESS (0x4ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_59_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_59_RESET 0x0 // 0x4f0 (BB_TPC_TXGAIN_SRAM_60) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_60_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_60_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_60_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_60_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_60_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_60_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_60_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_60_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_60_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_60_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_60_ADDRESS (0x4f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_60_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_60_RESET 0x0 // 0x4f4 (BB_TPC_TXGAIN_SRAM_61) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_61_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_61_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_61_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_61_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_61_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_61_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_61_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_61_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_61_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_61_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_61_ADDRESS (0x4f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_61_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_61_RESET 0x0 // 0x4f8 (BB_TPC_TXGAIN_SRAM_62) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_62_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_62_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_62_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_62_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_62_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_62_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_62_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_62_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_62_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_62_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_62_ADDRESS (0x4f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_62_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_62_RESET 0x0 // 0x4fc (BB_TPC_TXGAIN_SRAM_63) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_63_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_63_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_63_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_63_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_63_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_63_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_63_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_63_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_63_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_63_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_63_ADDRESS (0x4fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_63_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_63_RESET 0x0 // 0x500 (BB_TPC_TXGAIN_SRAM_64) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_64_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_64_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_64_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_64_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_64_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_64_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_64_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_64_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_64_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_64_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_64_ADDRESS (0x500 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_64_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_64_RESET 0x0 // 0x504 (BB_TPC_TXGAIN_SRAM_65) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_65_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_65_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_65_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_65_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_65_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_65_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_65_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_65_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_65_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_65_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_65_ADDRESS (0x504 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_65_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_65_RESET 0x0 // 0x508 (BB_TPC_TXGAIN_SRAM_66) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_66_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_66_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_66_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_66_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_66_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_66_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_66_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_66_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_66_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_66_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_66_ADDRESS (0x508 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_66_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_66_RESET 0x0 // 0x50c (BB_TPC_TXGAIN_SRAM_67) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_67_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_67_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_67_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_67_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_67_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_67_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_67_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_67_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_67_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_67_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_67_ADDRESS (0x50c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_67_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_67_RESET 0x0 // 0x510 (BB_TPC_TXGAIN_SRAM_68) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_68_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_68_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_68_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_68_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_68_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_68_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_68_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_68_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_68_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_68_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_68_ADDRESS (0x510 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_68_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_68_RESET 0x0 // 0x514 (BB_TPC_TXGAIN_SRAM_69) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_69_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_69_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_69_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_69_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_69_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_69_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_69_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_69_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_69_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_69_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_69_ADDRESS (0x514 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_69_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_69_RESET 0x0 // 0x518 (BB_TPC_TXGAIN_SRAM_70) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_70_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_70_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_70_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_70_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_70_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_70_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_70_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_70_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_70_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_70_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_70_ADDRESS (0x518 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_70_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_70_RESET 0x0 // 0x51c (BB_TPC_TXGAIN_SRAM_71) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_71_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_71_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_71_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_71_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_71_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_71_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_71_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_71_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_71_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_71_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_71_ADDRESS (0x51c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_71_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_71_RESET 0x0 // 0x520 (BB_TPC_TXGAIN_SRAM_72) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_72_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_72_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_72_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_72_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_72_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_72_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_72_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_72_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_72_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_72_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_72_ADDRESS (0x520 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_72_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_72_RESET 0x0 // 0x524 (BB_TPC_TXGAIN_SRAM_73) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_73_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_73_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_73_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_73_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_73_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_73_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_73_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_73_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_73_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_73_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_73_ADDRESS (0x524 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_73_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_73_RESET 0x0 // 0x528 (BB_TPC_TXGAIN_SRAM_74) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_74_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_74_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_74_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_74_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_74_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_74_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_74_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_74_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_74_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_74_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_74_ADDRESS (0x528 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_74_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_74_RESET 0x0 // 0x52c (BB_TPC_TXGAIN_SRAM_75) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_75_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_75_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_75_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_75_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_75_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_75_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_75_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_75_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_75_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_75_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_75_ADDRESS (0x52c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_75_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_75_RESET 0x0 // 0x530 (BB_TPC_TXGAIN_SRAM_76) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_76_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_76_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_76_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_76_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_76_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_76_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_76_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_76_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_76_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_76_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_76_ADDRESS (0x530 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_76_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_76_RESET 0x0 // 0x534 (BB_TPC_TXGAIN_SRAM_77) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_77_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_77_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_77_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_77_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_77_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_77_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_77_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_77_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_77_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_77_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_77_ADDRESS (0x534 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_77_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_77_RESET 0x0 // 0x538 (BB_TPC_TXGAIN_SRAM_78) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_78_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_78_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_78_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_78_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_78_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_78_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_78_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_78_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_78_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_78_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_78_ADDRESS (0x538 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_78_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_78_RESET 0x0 // 0x53c (BB_TPC_TXGAIN_SRAM_79) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_79_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_79_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_79_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_79_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_79_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_79_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_79_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_79_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_79_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_79_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_79_ADDRESS (0x53c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_79_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_79_RESET 0x0 // 0x540 (BB_TPC_TXGAIN_SRAM_80) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_80_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_80_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_80_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_80_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_80_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_80_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_80_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_80_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_80_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_80_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_80_ADDRESS (0x540 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_80_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_80_RESET 0x0 // 0x544 (BB_TPC_TXGAIN_SRAM_81) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_81_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_81_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_81_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_81_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_81_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_81_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_81_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_81_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_81_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_81_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_81_ADDRESS (0x544 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_81_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_81_RESET 0x0 // 0x548 (BB_TPC_TXGAIN_SRAM_82) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_82_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_82_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_82_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_82_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_82_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_82_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_82_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_82_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_82_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_82_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_82_ADDRESS (0x548 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_82_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_82_RESET 0x0 // 0x54c (BB_TPC_TXGAIN_SRAM_83) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_83_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_83_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_83_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_83_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_83_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_83_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_83_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_83_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_83_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_83_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_83_ADDRESS (0x54c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_83_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_83_RESET 0x0 // 0x550 (BB_TPC_TXGAIN_SRAM_84) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_84_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_84_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_84_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_84_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_84_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_84_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_84_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_84_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_84_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_84_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_84_ADDRESS (0x550 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_84_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_84_RESET 0x0 // 0x554 (BB_TPC_TXGAIN_SRAM_85) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_85_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_85_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_85_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_85_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_85_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_85_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_85_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_85_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_85_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_85_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_85_ADDRESS (0x554 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_85_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_85_RESET 0x0 // 0x558 (BB_TPC_TXGAIN_SRAM_86) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_86_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_86_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_86_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_86_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_86_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_86_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_86_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_86_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_86_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_86_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_86_ADDRESS (0x558 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_86_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_86_RESET 0x0 // 0x55c (BB_TPC_TXGAIN_SRAM_87) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_87_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_87_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_87_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_87_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_87_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_87_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_87_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_87_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_87_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_87_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_87_ADDRESS (0x55c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_87_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_87_RESET 0x0 // 0x560 (BB_TPC_TXGAIN_SRAM_88) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_88_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_88_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_88_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_88_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_88_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_88_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_88_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_88_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_88_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_88_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_88_ADDRESS (0x560 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_88_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_88_RESET 0x0 // 0x564 (BB_TPC_TXGAIN_SRAM_89) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_89_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_89_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_89_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_89_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_89_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_89_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_89_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_89_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_89_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_89_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_89_ADDRESS (0x564 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_89_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_89_RESET 0x0 // 0x568 (BB_TPC_TXGAIN_SRAM_90) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_90_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_90_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_90_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_90_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_90_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_90_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_90_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_90_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_90_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_90_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_90_ADDRESS (0x568 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_90_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_90_RESET 0x0 // 0x56c (BB_TPC_TXGAIN_SRAM_91) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_91_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_91_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_91_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_91_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_91_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_91_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_91_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_91_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_91_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_91_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_91_ADDRESS (0x56c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_91_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_91_RESET 0x0 // 0x570 (BB_TPC_TXGAIN_SRAM_92) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_92_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_92_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_92_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_92_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_92_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_92_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_92_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_92_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_92_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_92_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_92_ADDRESS (0x570 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_92_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_92_RESET 0x0 // 0x574 (BB_TPC_TXGAIN_SRAM_93) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_93_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_93_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_93_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_93_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_93_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_93_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_93_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_93_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_93_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_93_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_93_ADDRESS (0x574 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_93_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_93_RESET 0x0 // 0x578 (BB_TPC_TXGAIN_SRAM_94) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_94_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_94_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_94_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_94_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_94_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_94_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_94_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_94_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_94_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_94_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_94_ADDRESS (0x578 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_94_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_94_RESET 0x0 // 0x57c (BB_TPC_TXGAIN_SRAM_95) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_95_LSB 0 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_95_MSB 19 #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_95_MASK 0xfffff #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_95_GET(x) (((x) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_95_MASK) >> BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_95_LSB) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_95_SET(x) (((0 | (x)) << BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_95_LSB) & BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_95_MASK) #define BB_TPC_TXGAIN_SRAM_TPC_TXGAIN_WORD_95_RESET 0x0 #define BB_TPC_TXGAIN_SRAM_95_ADDRESS (0x57c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_TXGAIN_SRAM_95_RSTMASK 0xfffff #define BB_TPC_TXGAIN_SRAM_95_RESET 0x0 // 0x580 (BB_TPC_PLUT_SRAM) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_RESET 0x0 #define BB_TPC_PLUT_SRAM_ADDRESS (0x580 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_RESET 0x0 // 0x580 (BB_TPC_PLUT_SRAM_0) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_0_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_0_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_0_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_0_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_0_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_0_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_0_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_0_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_0_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_0_RESET 0x0 #define BB_TPC_PLUT_SRAM_0_ADDRESS (0x580 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_0_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_0_RESET 0x0 // 0x584 (BB_TPC_PLUT_SRAM_1) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_1_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_1_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_1_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_1_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_1_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_1_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_1_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_1_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_1_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_1_RESET 0x0 #define BB_TPC_PLUT_SRAM_1_ADDRESS (0x584 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_1_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_1_RESET 0x0 // 0x588 (BB_TPC_PLUT_SRAM_2) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_2_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_2_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_2_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_2_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_2_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_2_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_2_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_2_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_2_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_2_RESET 0x0 #define BB_TPC_PLUT_SRAM_2_ADDRESS (0x588 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_2_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_2_RESET 0x0 // 0x58c (BB_TPC_PLUT_SRAM_3) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_3_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_3_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_3_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_3_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_3_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_3_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_3_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_3_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_3_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_3_RESET 0x0 #define BB_TPC_PLUT_SRAM_3_ADDRESS (0x58c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_3_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_3_RESET 0x0 // 0x590 (BB_TPC_PLUT_SRAM_4) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_4_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_4_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_4_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_4_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_4_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_4_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_4_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_4_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_4_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_4_RESET 0x0 #define BB_TPC_PLUT_SRAM_4_ADDRESS (0x590 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_4_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_4_RESET 0x0 // 0x594 (BB_TPC_PLUT_SRAM_5) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_5_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_5_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_5_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_5_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_5_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_5_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_5_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_5_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_5_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_5_RESET 0x0 #define BB_TPC_PLUT_SRAM_5_ADDRESS (0x594 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_5_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_5_RESET 0x0 // 0x598 (BB_TPC_PLUT_SRAM_6) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_6_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_6_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_6_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_6_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_6_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_6_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_6_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_6_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_6_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_6_RESET 0x0 #define BB_TPC_PLUT_SRAM_6_ADDRESS (0x598 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_6_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_6_RESET 0x0 // 0x59c (BB_TPC_PLUT_SRAM_7) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_7_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_7_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_7_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_7_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_7_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_7_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_7_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_7_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_7_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_7_RESET 0x0 #define BB_TPC_PLUT_SRAM_7_ADDRESS (0x59c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_7_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_7_RESET 0x0 // 0x5a0 (BB_TPC_PLUT_SRAM_8) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_8_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_8_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_8_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_8_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_8_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_8_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_8_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_8_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_8_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_8_RESET 0x0 #define BB_TPC_PLUT_SRAM_8_ADDRESS (0x5a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_8_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_8_RESET 0x0 // 0x5a4 (BB_TPC_PLUT_SRAM_9) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_9_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_9_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_9_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_9_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_9_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_9_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_9_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_9_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_9_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_9_RESET 0x0 #define BB_TPC_PLUT_SRAM_9_ADDRESS (0x5a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_9_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_9_RESET 0x0 // 0x5a8 (BB_TPC_PLUT_SRAM_10) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_10_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_10_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_10_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_10_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_10_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_10_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_10_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_10_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_10_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_10_RESET 0x0 #define BB_TPC_PLUT_SRAM_10_ADDRESS (0x5a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_10_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_10_RESET 0x0 // 0x5ac (BB_TPC_PLUT_SRAM_11) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_11_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_11_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_11_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_11_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_11_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_11_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_11_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_11_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_11_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_11_RESET 0x0 #define BB_TPC_PLUT_SRAM_11_ADDRESS (0x5ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_11_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_11_RESET 0x0 // 0x5b0 (BB_TPC_PLUT_SRAM_12) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_12_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_12_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_12_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_12_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_12_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_12_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_12_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_12_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_12_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_12_RESET 0x0 #define BB_TPC_PLUT_SRAM_12_ADDRESS (0x5b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_12_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_12_RESET 0x0 // 0x5b4 (BB_TPC_PLUT_SRAM_13) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_13_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_13_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_13_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_13_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_13_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_13_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_13_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_13_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_13_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_13_RESET 0x0 #define BB_TPC_PLUT_SRAM_13_ADDRESS (0x5b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_13_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_13_RESET 0x0 // 0x5b8 (BB_TPC_PLUT_SRAM_14) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_14_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_14_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_14_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_14_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_14_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_14_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_14_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_14_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_14_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_14_RESET 0x0 #define BB_TPC_PLUT_SRAM_14_ADDRESS (0x5b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_14_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_14_RESET 0x0 // 0x5bc (BB_TPC_PLUT_SRAM_15) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_15_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_15_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_15_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_15_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_15_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_15_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_15_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_15_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_15_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_15_RESET 0x0 #define BB_TPC_PLUT_SRAM_15_ADDRESS (0x5bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_15_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_15_RESET 0x0 // 0x5c0 (BB_TPC_PLUT_SRAM_16) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_16_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_16_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_16_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_16_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_16_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_16_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_16_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_16_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_16_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_16_RESET 0x0 #define BB_TPC_PLUT_SRAM_16_ADDRESS (0x5c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_16_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_16_RESET 0x0 // 0x5c4 (BB_TPC_PLUT_SRAM_17) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_17_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_17_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_17_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_17_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_17_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_17_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_17_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_17_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_17_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_17_RESET 0x0 #define BB_TPC_PLUT_SRAM_17_ADDRESS (0x5c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_17_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_17_RESET 0x0 // 0x5c8 (BB_TPC_PLUT_SRAM_18) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_18_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_18_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_18_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_18_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_18_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_18_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_18_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_18_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_18_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_18_RESET 0x0 #define BB_TPC_PLUT_SRAM_18_ADDRESS (0x5c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_18_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_18_RESET 0x0 // 0x5cc (BB_TPC_PLUT_SRAM_19) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_19_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_19_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_19_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_19_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_19_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_19_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_19_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_19_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_19_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_19_RESET 0x0 #define BB_TPC_PLUT_SRAM_19_ADDRESS (0x5cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_19_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_19_RESET 0x0 // 0x5d0 (BB_TPC_PLUT_SRAM_20) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_20_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_20_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_20_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_20_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_20_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_20_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_20_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_20_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_20_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_20_RESET 0x0 #define BB_TPC_PLUT_SRAM_20_ADDRESS (0x5d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_20_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_20_RESET 0x0 // 0x5d4 (BB_TPC_PLUT_SRAM_21) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_21_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_21_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_21_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_21_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_21_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_21_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_21_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_21_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_21_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_21_RESET 0x0 #define BB_TPC_PLUT_SRAM_21_ADDRESS (0x5d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_21_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_21_RESET 0x0 // 0x5d8 (BB_TPC_PLUT_SRAM_22) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_22_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_22_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_22_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_22_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_22_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_22_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_22_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_22_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_22_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_22_RESET 0x0 #define BB_TPC_PLUT_SRAM_22_ADDRESS (0x5d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_22_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_22_RESET 0x0 // 0x5dc (BB_TPC_PLUT_SRAM_23) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_23_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_23_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_23_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_23_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_23_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_23_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_23_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_23_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_23_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_23_RESET 0x0 #define BB_TPC_PLUT_SRAM_23_ADDRESS (0x5dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_23_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_23_RESET 0x0 // 0x5e0 (BB_TPC_PLUT_SRAM_24) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_24_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_24_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_24_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_24_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_24_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_24_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_24_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_24_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_24_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_24_RESET 0x0 #define BB_TPC_PLUT_SRAM_24_ADDRESS (0x5e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_24_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_24_RESET 0x0 // 0x5e4 (BB_TPC_PLUT_SRAM_25) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_25_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_25_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_25_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_25_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_25_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_25_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_25_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_25_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_25_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_25_RESET 0x0 #define BB_TPC_PLUT_SRAM_25_ADDRESS (0x5e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_25_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_25_RESET 0x0 // 0x5e8 (BB_TPC_PLUT_SRAM_26) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_26_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_26_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_26_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_26_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_26_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_26_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_26_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_26_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_26_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_26_RESET 0x0 #define BB_TPC_PLUT_SRAM_26_ADDRESS (0x5e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_26_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_26_RESET 0x0 // 0x5ec (BB_TPC_PLUT_SRAM_27) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_27_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_27_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_27_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_27_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_27_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_27_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_27_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_27_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_27_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_27_RESET 0x0 #define BB_TPC_PLUT_SRAM_27_ADDRESS (0x5ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_27_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_27_RESET 0x0 // 0x5f0 (BB_TPC_PLUT_SRAM_28) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_28_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_28_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_28_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_28_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_28_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_28_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_28_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_28_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_28_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_28_RESET 0x0 #define BB_TPC_PLUT_SRAM_28_ADDRESS (0x5f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_28_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_28_RESET 0x0 // 0x5f4 (BB_TPC_PLUT_SRAM_29) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_29_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_29_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_29_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_29_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_29_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_29_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_29_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_29_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_29_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_29_RESET 0x0 #define BB_TPC_PLUT_SRAM_29_ADDRESS (0x5f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_29_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_29_RESET 0x0 // 0x5f8 (BB_TPC_PLUT_SRAM_30) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_30_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_30_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_30_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_30_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_30_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_30_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_30_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_30_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_30_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_30_RESET 0x0 #define BB_TPC_PLUT_SRAM_30_ADDRESS (0x5f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_30_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_30_RESET 0x0 // 0x5fc (BB_TPC_PLUT_SRAM_31) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_31_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_31_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_31_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_31_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_31_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_31_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_31_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_31_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_31_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_31_RESET 0x0 #define BB_TPC_PLUT_SRAM_31_ADDRESS (0x5fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_31_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_31_RESET 0x0 // 0x600 (BB_TPC_PLUT_SRAM_32) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_32_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_32_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_32_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_32_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_32_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_32_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_32_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_32_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_32_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_32_RESET 0x0 #define BB_TPC_PLUT_SRAM_32_ADDRESS (0x600 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_32_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_32_RESET 0x0 // 0x604 (BB_TPC_PLUT_SRAM_33) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_33_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_33_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_33_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_33_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_33_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_33_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_33_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_33_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_33_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_33_RESET 0x0 #define BB_TPC_PLUT_SRAM_33_ADDRESS (0x604 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_33_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_33_RESET 0x0 // 0x608 (BB_TPC_PLUT_SRAM_34) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_34_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_34_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_34_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_34_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_34_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_34_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_34_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_34_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_34_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_34_RESET 0x0 #define BB_TPC_PLUT_SRAM_34_ADDRESS (0x608 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_34_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_34_RESET 0x0 // 0x60c (BB_TPC_PLUT_SRAM_35) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_35_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_35_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_35_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_35_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_35_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_35_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_35_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_35_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_35_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_35_RESET 0x0 #define BB_TPC_PLUT_SRAM_35_ADDRESS (0x60c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_35_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_35_RESET 0x0 // 0x610 (BB_TPC_PLUT_SRAM_36) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_36_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_36_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_36_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_36_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_36_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_36_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_36_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_36_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_36_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_36_RESET 0x0 #define BB_TPC_PLUT_SRAM_36_ADDRESS (0x610 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_36_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_36_RESET 0x0 // 0x614 (BB_TPC_PLUT_SRAM_37) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_37_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_37_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_37_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_37_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_37_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_37_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_37_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_37_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_37_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_37_RESET 0x0 #define BB_TPC_PLUT_SRAM_37_ADDRESS (0x614 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_37_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_37_RESET 0x0 // 0x618 (BB_TPC_PLUT_SRAM_38) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_38_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_38_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_38_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_38_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_38_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_38_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_38_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_38_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_38_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_38_RESET 0x0 #define BB_TPC_PLUT_SRAM_38_ADDRESS (0x618 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_38_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_38_RESET 0x0 // 0x61c (BB_TPC_PLUT_SRAM_39) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_39_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_39_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_39_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_39_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_39_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_39_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_39_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_39_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_39_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_39_RESET 0x0 #define BB_TPC_PLUT_SRAM_39_ADDRESS (0x61c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_39_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_39_RESET 0x0 // 0x620 (BB_TPC_PLUT_SRAM_40) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_40_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_40_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_40_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_40_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_40_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_40_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_40_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_40_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_40_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_40_RESET 0x0 #define BB_TPC_PLUT_SRAM_40_ADDRESS (0x620 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_40_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_40_RESET 0x0 // 0x624 (BB_TPC_PLUT_SRAM_41) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_41_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_41_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_41_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_41_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_41_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_41_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_41_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_41_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_41_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_41_RESET 0x0 #define BB_TPC_PLUT_SRAM_41_ADDRESS (0x624 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_41_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_41_RESET 0x0 // 0x628 (BB_TPC_PLUT_SRAM_42) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_42_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_42_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_42_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_42_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_42_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_42_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_42_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_42_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_42_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_42_RESET 0x0 #define BB_TPC_PLUT_SRAM_42_ADDRESS (0x628 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_42_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_42_RESET 0x0 // 0x62c (BB_TPC_PLUT_SRAM_43) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_43_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_43_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_43_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_43_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_43_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_43_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_43_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_43_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_43_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_43_RESET 0x0 #define BB_TPC_PLUT_SRAM_43_ADDRESS (0x62c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_43_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_43_RESET 0x0 // 0x630 (BB_TPC_PLUT_SRAM_44) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_44_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_44_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_44_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_44_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_44_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_44_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_44_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_44_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_44_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_44_RESET 0x0 #define BB_TPC_PLUT_SRAM_44_ADDRESS (0x630 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_44_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_44_RESET 0x0 // 0x634 (BB_TPC_PLUT_SRAM_45) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_45_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_45_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_45_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_45_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_45_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_45_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_45_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_45_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_45_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_45_RESET 0x0 #define BB_TPC_PLUT_SRAM_45_ADDRESS (0x634 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_45_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_45_RESET 0x0 // 0x638 (BB_TPC_PLUT_SRAM_46) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_46_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_46_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_46_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_46_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_46_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_46_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_46_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_46_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_46_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_46_RESET 0x0 #define BB_TPC_PLUT_SRAM_46_ADDRESS (0x638 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_46_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_46_RESET 0x0 // 0x63c (BB_TPC_PLUT_SRAM_47) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_47_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_47_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_47_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_47_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_47_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_47_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_47_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_47_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_47_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_47_RESET 0x0 #define BB_TPC_PLUT_SRAM_47_ADDRESS (0x63c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_47_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_47_RESET 0x0 // 0x640 (BB_TPC_PLUT_SRAM_48) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_48_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_48_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_48_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_48_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_48_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_48_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_48_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_48_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_48_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_48_RESET 0x0 #define BB_TPC_PLUT_SRAM_48_ADDRESS (0x640 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_48_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_48_RESET 0x0 // 0x644 (BB_TPC_PLUT_SRAM_49) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_49_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_49_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_49_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_49_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_49_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_49_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_49_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_49_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_49_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_49_RESET 0x0 #define BB_TPC_PLUT_SRAM_49_ADDRESS (0x644 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_49_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_49_RESET 0x0 // 0x648 (BB_TPC_PLUT_SRAM_50) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_50_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_50_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_50_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_50_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_50_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_50_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_50_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_50_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_50_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_50_RESET 0x0 #define BB_TPC_PLUT_SRAM_50_ADDRESS (0x648 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_50_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_50_RESET 0x0 // 0x64c (BB_TPC_PLUT_SRAM_51) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_51_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_51_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_51_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_51_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_51_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_51_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_51_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_51_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_51_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_51_RESET 0x0 #define BB_TPC_PLUT_SRAM_51_ADDRESS (0x64c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_51_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_51_RESET 0x0 // 0x650 (BB_TPC_PLUT_SRAM_52) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_52_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_52_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_52_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_52_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_52_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_52_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_52_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_52_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_52_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_52_RESET 0x0 #define BB_TPC_PLUT_SRAM_52_ADDRESS (0x650 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_52_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_52_RESET 0x0 // 0x654 (BB_TPC_PLUT_SRAM_53) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_53_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_53_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_53_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_53_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_53_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_53_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_53_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_53_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_53_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_53_RESET 0x0 #define BB_TPC_PLUT_SRAM_53_ADDRESS (0x654 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_53_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_53_RESET 0x0 // 0x658 (BB_TPC_PLUT_SRAM_54) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_54_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_54_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_54_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_54_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_54_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_54_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_54_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_54_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_54_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_54_RESET 0x0 #define BB_TPC_PLUT_SRAM_54_ADDRESS (0x658 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_54_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_54_RESET 0x0 // 0x65c (BB_TPC_PLUT_SRAM_55) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_55_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_55_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_55_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_55_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_55_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_55_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_55_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_55_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_55_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_55_RESET 0x0 #define BB_TPC_PLUT_SRAM_55_ADDRESS (0x65c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_55_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_55_RESET 0x0 // 0x660 (BB_TPC_PLUT_SRAM_56) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_56_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_56_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_56_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_56_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_56_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_56_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_56_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_56_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_56_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_56_RESET 0x0 #define BB_TPC_PLUT_SRAM_56_ADDRESS (0x660 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_56_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_56_RESET 0x0 // 0x664 (BB_TPC_PLUT_SRAM_57) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_57_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_57_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_57_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_57_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_57_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_57_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_57_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_57_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_57_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_57_RESET 0x0 #define BB_TPC_PLUT_SRAM_57_ADDRESS (0x664 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_57_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_57_RESET 0x0 // 0x668 (BB_TPC_PLUT_SRAM_58) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_58_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_58_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_58_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_58_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_58_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_58_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_58_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_58_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_58_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_58_RESET 0x0 #define BB_TPC_PLUT_SRAM_58_ADDRESS (0x668 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_58_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_58_RESET 0x0 // 0x66c (BB_TPC_PLUT_SRAM_59) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_59_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_59_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_59_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_59_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_59_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_59_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_59_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_59_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_59_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_59_RESET 0x0 #define BB_TPC_PLUT_SRAM_59_ADDRESS (0x66c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_59_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_59_RESET 0x0 // 0x670 (BB_TPC_PLUT_SRAM_60) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_60_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_60_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_60_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_60_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_60_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_60_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_60_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_60_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_60_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_60_RESET 0x0 #define BB_TPC_PLUT_SRAM_60_ADDRESS (0x670 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_60_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_60_RESET 0x0 // 0x674 (BB_TPC_PLUT_SRAM_61) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_61_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_61_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_61_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_61_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_61_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_61_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_61_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_61_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_61_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_61_RESET 0x0 #define BB_TPC_PLUT_SRAM_61_ADDRESS (0x674 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_61_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_61_RESET 0x0 // 0x678 (BB_TPC_PLUT_SRAM_62) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_62_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_62_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_62_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_62_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_62_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_62_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_62_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_62_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_62_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_62_RESET 0x0 #define BB_TPC_PLUT_SRAM_62_ADDRESS (0x678 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_62_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_62_RESET 0x0 // 0x67c (BB_TPC_PLUT_SRAM_63) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_63_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_63_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_63_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_63_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_63_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_63_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_63_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_63_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_63_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_63_RESET 0x0 #define BB_TPC_PLUT_SRAM_63_ADDRESS (0x67c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_63_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_63_RESET 0x0 // 0x680 (BB_TPC_PLUT_SRAM_64) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_64_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_64_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_64_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_64_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_64_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_64_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_64_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_64_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_64_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_64_RESET 0x0 #define BB_TPC_PLUT_SRAM_64_ADDRESS (0x680 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_64_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_64_RESET 0x0 // 0x684 (BB_TPC_PLUT_SRAM_65) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_65_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_65_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_65_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_65_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_65_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_65_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_65_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_65_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_65_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_65_RESET 0x0 #define BB_TPC_PLUT_SRAM_65_ADDRESS (0x684 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_65_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_65_RESET 0x0 // 0x688 (BB_TPC_PLUT_SRAM_66) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_66_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_66_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_66_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_66_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_66_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_66_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_66_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_66_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_66_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_66_RESET 0x0 #define BB_TPC_PLUT_SRAM_66_ADDRESS (0x688 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_66_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_66_RESET 0x0 // 0x68c (BB_TPC_PLUT_SRAM_67) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_67_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_67_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_67_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_67_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_67_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_67_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_67_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_67_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_67_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_67_RESET 0x0 #define BB_TPC_PLUT_SRAM_67_ADDRESS (0x68c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_67_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_67_RESET 0x0 // 0x690 (BB_TPC_PLUT_SRAM_68) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_68_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_68_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_68_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_68_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_68_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_68_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_68_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_68_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_68_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_68_RESET 0x0 #define BB_TPC_PLUT_SRAM_68_ADDRESS (0x690 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_68_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_68_RESET 0x0 // 0x694 (BB_TPC_PLUT_SRAM_69) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_69_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_69_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_69_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_69_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_69_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_69_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_69_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_69_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_69_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_69_RESET 0x0 #define BB_TPC_PLUT_SRAM_69_ADDRESS (0x694 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_69_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_69_RESET 0x0 // 0x698 (BB_TPC_PLUT_SRAM_70) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_70_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_70_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_70_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_70_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_70_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_70_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_70_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_70_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_70_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_70_RESET 0x0 #define BB_TPC_PLUT_SRAM_70_ADDRESS (0x698 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_70_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_70_RESET 0x0 // 0x69c (BB_TPC_PLUT_SRAM_71) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_71_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_71_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_71_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_71_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_71_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_71_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_71_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_71_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_71_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_71_RESET 0x0 #define BB_TPC_PLUT_SRAM_71_ADDRESS (0x69c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_71_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_71_RESET 0x0 // 0x6a0 (BB_TPC_PLUT_SRAM_72) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_72_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_72_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_72_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_72_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_72_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_72_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_72_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_72_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_72_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_72_RESET 0x0 #define BB_TPC_PLUT_SRAM_72_ADDRESS (0x6a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_72_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_72_RESET 0x0 // 0x6a4 (BB_TPC_PLUT_SRAM_73) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_73_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_73_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_73_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_73_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_73_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_73_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_73_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_73_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_73_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_73_RESET 0x0 #define BB_TPC_PLUT_SRAM_73_ADDRESS (0x6a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_73_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_73_RESET 0x0 // 0x6a8 (BB_TPC_PLUT_SRAM_74) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_74_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_74_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_74_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_74_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_74_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_74_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_74_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_74_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_74_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_74_RESET 0x0 #define BB_TPC_PLUT_SRAM_74_ADDRESS (0x6a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_74_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_74_RESET 0x0 // 0x6ac (BB_TPC_PLUT_SRAM_75) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_75_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_75_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_75_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_75_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_75_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_75_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_75_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_75_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_75_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_75_RESET 0x0 #define BB_TPC_PLUT_SRAM_75_ADDRESS (0x6ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_75_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_75_RESET 0x0 // 0x6b0 (BB_TPC_PLUT_SRAM_76) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_76_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_76_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_76_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_76_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_76_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_76_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_76_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_76_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_76_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_76_RESET 0x0 #define BB_TPC_PLUT_SRAM_76_ADDRESS (0x6b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_76_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_76_RESET 0x0 // 0x6b4 (BB_TPC_PLUT_SRAM_77) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_77_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_77_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_77_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_77_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_77_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_77_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_77_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_77_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_77_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_77_RESET 0x0 #define BB_TPC_PLUT_SRAM_77_ADDRESS (0x6b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_77_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_77_RESET 0x0 // 0x6b8 (BB_TPC_PLUT_SRAM_78) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_78_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_78_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_78_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_78_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_78_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_78_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_78_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_78_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_78_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_78_RESET 0x0 #define BB_TPC_PLUT_SRAM_78_ADDRESS (0x6b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_78_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_78_RESET 0x0 // 0x6bc (BB_TPC_PLUT_SRAM_79) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_79_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_79_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_79_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_79_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_79_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_79_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_79_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_79_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_79_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_79_RESET 0x0 #define BB_TPC_PLUT_SRAM_79_ADDRESS (0x6bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_79_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_79_RESET 0x0 // 0x6c0 (BB_TPC_PLUT_SRAM_80) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_80_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_80_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_80_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_80_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_80_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_80_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_80_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_80_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_80_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_80_RESET 0x0 #define BB_TPC_PLUT_SRAM_80_ADDRESS (0x6c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_80_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_80_RESET 0x0 // 0x6c4 (BB_TPC_PLUT_SRAM_81) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_81_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_81_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_81_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_81_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_81_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_81_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_81_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_81_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_81_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_81_RESET 0x0 #define BB_TPC_PLUT_SRAM_81_ADDRESS (0x6c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_81_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_81_RESET 0x0 // 0x6c8 (BB_TPC_PLUT_SRAM_82) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_82_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_82_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_82_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_82_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_82_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_82_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_82_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_82_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_82_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_82_RESET 0x0 #define BB_TPC_PLUT_SRAM_82_ADDRESS (0x6c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_82_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_82_RESET 0x0 // 0x6cc (BB_TPC_PLUT_SRAM_83) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_83_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_83_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_83_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_83_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_83_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_83_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_83_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_83_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_83_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_83_RESET 0x0 #define BB_TPC_PLUT_SRAM_83_ADDRESS (0x6cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_83_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_83_RESET 0x0 // 0x6d0 (BB_TPC_PLUT_SRAM_84) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_84_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_84_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_84_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_84_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_84_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_84_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_84_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_84_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_84_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_84_RESET 0x0 #define BB_TPC_PLUT_SRAM_84_ADDRESS (0x6d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_84_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_84_RESET 0x0 // 0x6d4 (BB_TPC_PLUT_SRAM_85) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_85_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_85_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_85_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_85_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_85_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_85_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_85_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_85_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_85_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_85_RESET 0x0 #define BB_TPC_PLUT_SRAM_85_ADDRESS (0x6d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_85_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_85_RESET 0x0 // 0x6d8 (BB_TPC_PLUT_SRAM_86) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_86_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_86_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_86_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_86_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_86_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_86_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_86_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_86_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_86_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_86_RESET 0x0 #define BB_TPC_PLUT_SRAM_86_ADDRESS (0x6d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_86_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_86_RESET 0x0 // 0x6dc (BB_TPC_PLUT_SRAM_87) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_87_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_87_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_87_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_87_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_87_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_87_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_87_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_87_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_87_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_87_RESET 0x0 #define BB_TPC_PLUT_SRAM_87_ADDRESS (0x6dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_87_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_87_RESET 0x0 // 0x6e0 (BB_TPC_PLUT_SRAM_88) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_88_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_88_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_88_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_88_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_88_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_88_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_88_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_88_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_88_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_88_RESET 0x0 #define BB_TPC_PLUT_SRAM_88_ADDRESS (0x6e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_88_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_88_RESET 0x0 // 0x6e4 (BB_TPC_PLUT_SRAM_89) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_89_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_89_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_89_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_89_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_89_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_89_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_89_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_89_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_89_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_89_RESET 0x0 #define BB_TPC_PLUT_SRAM_89_ADDRESS (0x6e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_89_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_89_RESET 0x0 // 0x6e8 (BB_TPC_PLUT_SRAM_90) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_90_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_90_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_90_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_90_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_90_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_90_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_90_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_90_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_90_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_90_RESET 0x0 #define BB_TPC_PLUT_SRAM_90_ADDRESS (0x6e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_90_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_90_RESET 0x0 // 0x6ec (BB_TPC_PLUT_SRAM_91) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_91_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_91_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_91_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_91_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_91_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_91_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_91_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_91_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_91_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_91_RESET 0x0 #define BB_TPC_PLUT_SRAM_91_ADDRESS (0x6ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_91_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_91_RESET 0x0 // 0x6f0 (BB_TPC_PLUT_SRAM_92) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_92_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_92_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_92_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_92_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_92_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_92_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_92_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_92_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_92_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_92_RESET 0x0 #define BB_TPC_PLUT_SRAM_92_ADDRESS (0x6f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_92_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_92_RESET 0x0 // 0x6f4 (BB_TPC_PLUT_SRAM_93) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_93_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_93_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_93_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_93_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_93_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_93_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_93_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_93_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_93_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_93_RESET 0x0 #define BB_TPC_PLUT_SRAM_93_ADDRESS (0x6f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_93_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_93_RESET 0x0 // 0x6f8 (BB_TPC_PLUT_SRAM_94) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_94_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_94_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_94_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_94_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_94_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_94_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_94_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_94_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_94_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_94_RESET 0x0 #define BB_TPC_PLUT_SRAM_94_ADDRESS (0x6f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_94_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_94_RESET 0x0 // 0x6fc (BB_TPC_PLUT_SRAM_95) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_95_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_95_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_95_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_95_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_95_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_95_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_95_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_95_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_95_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_95_RESET 0x0 #define BB_TPC_PLUT_SRAM_95_ADDRESS (0x6fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_95_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_95_RESET 0x0 // 0x700 (BB_TPC_PLUT_SRAM_96) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_96_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_96_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_96_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_96_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_96_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_96_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_96_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_96_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_96_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_96_RESET 0x0 #define BB_TPC_PLUT_SRAM_96_ADDRESS (0x700 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_96_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_96_RESET 0x0 // 0x704 (BB_TPC_PLUT_SRAM_97) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_97_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_97_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_97_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_97_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_97_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_97_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_97_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_97_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_97_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_97_RESET 0x0 #define BB_TPC_PLUT_SRAM_97_ADDRESS (0x704 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_97_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_97_RESET 0x0 // 0x708 (BB_TPC_PLUT_SRAM_98) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_98_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_98_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_98_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_98_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_98_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_98_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_98_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_98_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_98_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_98_RESET 0x0 #define BB_TPC_PLUT_SRAM_98_ADDRESS (0x708 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_98_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_98_RESET 0x0 // 0x70c (BB_TPC_PLUT_SRAM_99) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_99_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_99_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_99_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_99_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_99_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_99_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_99_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_99_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_99_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_99_RESET 0x0 #define BB_TPC_PLUT_SRAM_99_ADDRESS (0x70c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_99_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_99_RESET 0x0 // 0x710 (BB_TPC_PLUT_SRAM_100) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_100_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_100_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_100_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_100_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_100_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_100_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_100_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_100_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_100_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_100_RESET 0x0 #define BB_TPC_PLUT_SRAM_100_ADDRESS (0x710 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_100_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_100_RESET 0x0 // 0x714 (BB_TPC_PLUT_SRAM_101) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_101_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_101_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_101_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_101_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_101_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_101_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_101_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_101_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_101_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_101_RESET 0x0 #define BB_TPC_PLUT_SRAM_101_ADDRESS (0x714 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_101_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_101_RESET 0x0 // 0x718 (BB_TPC_PLUT_SRAM_102) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_102_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_102_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_102_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_102_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_102_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_102_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_102_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_102_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_102_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_102_RESET 0x0 #define BB_TPC_PLUT_SRAM_102_ADDRESS (0x718 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_102_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_102_RESET 0x0 // 0x71c (BB_TPC_PLUT_SRAM_103) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_103_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_103_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_103_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_103_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_103_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_103_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_103_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_103_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_103_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_103_RESET 0x0 #define BB_TPC_PLUT_SRAM_103_ADDRESS (0x71c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_103_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_103_RESET 0x0 // 0x720 (BB_TPC_PLUT_SRAM_104) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_104_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_104_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_104_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_104_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_104_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_104_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_104_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_104_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_104_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_104_RESET 0x0 #define BB_TPC_PLUT_SRAM_104_ADDRESS (0x720 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_104_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_104_RESET 0x0 // 0x724 (BB_TPC_PLUT_SRAM_105) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_105_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_105_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_105_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_105_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_105_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_105_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_105_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_105_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_105_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_105_RESET 0x0 #define BB_TPC_PLUT_SRAM_105_ADDRESS (0x724 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_105_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_105_RESET 0x0 // 0x728 (BB_TPC_PLUT_SRAM_106) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_106_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_106_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_106_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_106_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_106_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_106_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_106_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_106_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_106_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_106_RESET 0x0 #define BB_TPC_PLUT_SRAM_106_ADDRESS (0x728 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_106_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_106_RESET 0x0 // 0x72c (BB_TPC_PLUT_SRAM_107) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_107_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_107_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_107_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_107_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_107_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_107_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_107_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_107_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_107_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_107_RESET 0x0 #define BB_TPC_PLUT_SRAM_107_ADDRESS (0x72c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_107_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_107_RESET 0x0 // 0x730 (BB_TPC_PLUT_SRAM_108) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_108_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_108_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_108_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_108_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_108_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_108_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_108_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_108_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_108_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_108_RESET 0x0 #define BB_TPC_PLUT_SRAM_108_ADDRESS (0x730 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_108_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_108_RESET 0x0 // 0x734 (BB_TPC_PLUT_SRAM_109) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_109_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_109_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_109_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_109_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_109_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_109_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_109_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_109_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_109_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_109_RESET 0x0 #define BB_TPC_PLUT_SRAM_109_ADDRESS (0x734 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_109_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_109_RESET 0x0 // 0x738 (BB_TPC_PLUT_SRAM_110) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_110_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_110_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_110_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_110_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_110_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_110_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_110_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_110_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_110_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_110_RESET 0x0 #define BB_TPC_PLUT_SRAM_110_ADDRESS (0x738 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_110_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_110_RESET 0x0 // 0x73c (BB_TPC_PLUT_SRAM_111) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_111_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_111_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_111_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_111_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_111_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_111_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_111_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_111_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_111_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_111_RESET 0x0 #define BB_TPC_PLUT_SRAM_111_ADDRESS (0x73c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_111_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_111_RESET 0x0 // 0x740 (BB_TPC_PLUT_SRAM_112) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_112_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_112_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_112_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_112_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_112_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_112_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_112_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_112_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_112_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_112_RESET 0x0 #define BB_TPC_PLUT_SRAM_112_ADDRESS (0x740 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_112_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_112_RESET 0x0 // 0x744 (BB_TPC_PLUT_SRAM_113) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_113_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_113_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_113_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_113_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_113_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_113_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_113_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_113_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_113_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_113_RESET 0x0 #define BB_TPC_PLUT_SRAM_113_ADDRESS (0x744 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_113_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_113_RESET 0x0 // 0x748 (BB_TPC_PLUT_SRAM_114) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_114_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_114_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_114_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_114_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_114_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_114_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_114_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_114_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_114_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_114_RESET 0x0 #define BB_TPC_PLUT_SRAM_114_ADDRESS (0x748 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_114_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_114_RESET 0x0 // 0x74c (BB_TPC_PLUT_SRAM_115) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_115_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_115_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_115_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_115_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_115_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_115_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_115_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_115_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_115_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_115_RESET 0x0 #define BB_TPC_PLUT_SRAM_115_ADDRESS (0x74c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_115_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_115_RESET 0x0 // 0x750 (BB_TPC_PLUT_SRAM_116) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_116_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_116_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_116_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_116_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_116_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_116_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_116_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_116_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_116_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_116_RESET 0x0 #define BB_TPC_PLUT_SRAM_116_ADDRESS (0x750 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_116_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_116_RESET 0x0 // 0x754 (BB_TPC_PLUT_SRAM_117) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_117_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_117_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_117_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_117_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_117_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_117_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_117_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_117_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_117_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_117_RESET 0x0 #define BB_TPC_PLUT_SRAM_117_ADDRESS (0x754 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_117_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_117_RESET 0x0 // 0x758 (BB_TPC_PLUT_SRAM_118) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_118_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_118_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_118_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_118_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_118_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_118_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_118_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_118_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_118_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_118_RESET 0x0 #define BB_TPC_PLUT_SRAM_118_ADDRESS (0x758 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_118_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_118_RESET 0x0 // 0x75c (BB_TPC_PLUT_SRAM_119) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_119_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_119_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_119_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_119_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_119_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_119_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_119_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_119_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_119_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_119_RESET 0x0 #define BB_TPC_PLUT_SRAM_119_ADDRESS (0x75c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_119_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_119_RESET 0x0 // 0x760 (BB_TPC_PLUT_SRAM_120) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_120_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_120_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_120_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_120_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_120_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_120_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_120_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_120_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_120_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_120_RESET 0x0 #define BB_TPC_PLUT_SRAM_120_ADDRESS (0x760 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_120_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_120_RESET 0x0 // 0x764 (BB_TPC_PLUT_SRAM_121) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_121_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_121_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_121_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_121_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_121_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_121_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_121_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_121_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_121_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_121_RESET 0x0 #define BB_TPC_PLUT_SRAM_121_ADDRESS (0x764 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_121_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_121_RESET 0x0 // 0x768 (BB_TPC_PLUT_SRAM_122) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_122_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_122_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_122_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_122_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_122_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_122_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_122_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_122_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_122_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_122_RESET 0x0 #define BB_TPC_PLUT_SRAM_122_ADDRESS (0x768 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_122_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_122_RESET 0x0 // 0x76c (BB_TPC_PLUT_SRAM_123) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_123_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_123_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_123_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_123_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_123_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_123_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_123_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_123_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_123_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_123_RESET 0x0 #define BB_TPC_PLUT_SRAM_123_ADDRESS (0x76c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_123_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_123_RESET 0x0 // 0x770 (BB_TPC_PLUT_SRAM_124) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_124_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_124_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_124_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_124_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_124_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_124_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_124_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_124_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_124_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_124_RESET 0x0 #define BB_TPC_PLUT_SRAM_124_ADDRESS (0x770 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_124_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_124_RESET 0x0 // 0x774 (BB_TPC_PLUT_SRAM_125) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_125_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_125_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_125_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_125_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_125_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_125_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_125_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_125_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_125_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_125_RESET 0x0 #define BB_TPC_PLUT_SRAM_125_ADDRESS (0x774 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_125_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_125_RESET 0x0 // 0x778 (BB_TPC_PLUT_SRAM_126) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_126_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_126_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_126_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_126_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_126_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_126_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_126_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_126_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_126_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_126_RESET 0x0 #define BB_TPC_PLUT_SRAM_126_ADDRESS (0x778 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_126_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_126_RESET 0x0 // 0x77c (BB_TPC_PLUT_SRAM_127) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_127_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_127_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_127_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_127_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_127_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_127_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_127_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_127_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_127_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_127_RESET 0x0 #define BB_TPC_PLUT_SRAM_127_ADDRESS (0x77c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_127_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_127_RESET 0x0 // 0x780 (BB_TPC_PLUT_SRAM_128) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_128_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_128_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_128_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_128_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_128_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_128_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_128_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_128_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_128_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_128_RESET 0x0 #define BB_TPC_PLUT_SRAM_128_ADDRESS (0x780 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_128_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_128_RESET 0x0 // 0x784 (BB_TPC_PLUT_SRAM_129) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_129_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_129_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_129_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_129_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_129_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_129_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_129_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_129_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_129_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_129_RESET 0x0 #define BB_TPC_PLUT_SRAM_129_ADDRESS (0x784 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_129_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_129_RESET 0x0 // 0x788 (BB_TPC_PLUT_SRAM_130) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_130_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_130_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_130_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_130_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_130_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_130_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_130_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_130_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_130_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_130_RESET 0x0 #define BB_TPC_PLUT_SRAM_130_ADDRESS (0x788 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_130_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_130_RESET 0x0 // 0x78c (BB_TPC_PLUT_SRAM_131) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_131_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_131_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_131_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_131_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_131_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_131_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_131_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_131_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_131_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_131_RESET 0x0 #define BB_TPC_PLUT_SRAM_131_ADDRESS (0x78c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_131_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_131_RESET 0x0 // 0x790 (BB_TPC_PLUT_SRAM_132) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_132_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_132_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_132_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_132_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_132_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_132_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_132_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_132_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_132_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_132_RESET 0x0 #define BB_TPC_PLUT_SRAM_132_ADDRESS (0x790 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_132_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_132_RESET 0x0 // 0x794 (BB_TPC_PLUT_SRAM_133) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_133_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_133_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_133_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_133_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_133_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_133_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_133_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_133_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_133_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_133_RESET 0x0 #define BB_TPC_PLUT_SRAM_133_ADDRESS (0x794 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_133_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_133_RESET 0x0 // 0x798 (BB_TPC_PLUT_SRAM_134) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_134_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_134_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_134_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_134_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_134_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_134_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_134_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_134_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_134_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_134_RESET 0x0 #define BB_TPC_PLUT_SRAM_134_ADDRESS (0x798 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_134_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_134_RESET 0x0 // 0x79c (BB_TPC_PLUT_SRAM_135) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_135_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_135_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_135_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_135_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_135_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_135_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_135_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_135_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_135_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_135_RESET 0x0 #define BB_TPC_PLUT_SRAM_135_ADDRESS (0x79c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_135_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_135_RESET 0x0 // 0x7a0 (BB_TPC_PLUT_SRAM_136) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_136_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_136_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_136_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_136_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_136_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_136_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_136_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_136_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_136_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_136_RESET 0x0 #define BB_TPC_PLUT_SRAM_136_ADDRESS (0x7a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_136_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_136_RESET 0x0 // 0x7a4 (BB_TPC_PLUT_SRAM_137) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_137_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_137_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_137_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_137_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_137_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_137_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_137_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_137_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_137_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_137_RESET 0x0 #define BB_TPC_PLUT_SRAM_137_ADDRESS (0x7a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_137_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_137_RESET 0x0 // 0x7a8 (BB_TPC_PLUT_SRAM_138) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_138_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_138_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_138_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_138_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_138_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_138_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_138_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_138_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_138_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_138_RESET 0x0 #define BB_TPC_PLUT_SRAM_138_ADDRESS (0x7a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_138_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_138_RESET 0x0 // 0x7ac (BB_TPC_PLUT_SRAM_139) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_139_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_139_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_139_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_139_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_139_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_139_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_139_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_139_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_139_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_139_RESET 0x0 #define BB_TPC_PLUT_SRAM_139_ADDRESS (0x7ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_139_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_139_RESET 0x0 // 0x7b0 (BB_TPC_PLUT_SRAM_140) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_140_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_140_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_140_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_140_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_140_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_140_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_140_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_140_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_140_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_140_RESET 0x0 #define BB_TPC_PLUT_SRAM_140_ADDRESS (0x7b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_140_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_140_RESET 0x0 // 0x7b4 (BB_TPC_PLUT_SRAM_141) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_141_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_141_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_141_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_141_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_141_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_141_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_141_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_141_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_141_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_141_RESET 0x0 #define BB_TPC_PLUT_SRAM_141_ADDRESS (0x7b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_141_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_141_RESET 0x0 // 0x7b8 (BB_TPC_PLUT_SRAM_142) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_142_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_142_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_142_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_142_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_142_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_142_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_142_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_142_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_142_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_142_RESET 0x0 #define BB_TPC_PLUT_SRAM_142_ADDRESS (0x7b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_142_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_142_RESET 0x0 // 0x7bc (BB_TPC_PLUT_SRAM_143) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_143_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_143_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_143_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_143_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_143_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_143_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_143_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_143_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_143_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_143_RESET 0x0 #define BB_TPC_PLUT_SRAM_143_ADDRESS (0x7bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_143_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_143_RESET 0x0 // 0x7c0 (BB_TPC_PLUT_SRAM_144) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_144_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_144_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_144_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_144_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_144_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_144_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_144_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_144_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_144_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_144_RESET 0x0 #define BB_TPC_PLUT_SRAM_144_ADDRESS (0x7c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_144_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_144_RESET 0x0 // 0x7c4 (BB_TPC_PLUT_SRAM_145) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_145_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_145_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_145_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_145_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_145_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_145_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_145_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_145_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_145_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_145_RESET 0x0 #define BB_TPC_PLUT_SRAM_145_ADDRESS (0x7c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_145_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_145_RESET 0x0 // 0x7c8 (BB_TPC_PLUT_SRAM_146) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_146_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_146_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_146_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_146_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_146_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_146_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_146_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_146_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_146_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_146_RESET 0x0 #define BB_TPC_PLUT_SRAM_146_ADDRESS (0x7c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_146_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_146_RESET 0x0 // 0x7cc (BB_TPC_PLUT_SRAM_147) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_147_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_147_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_147_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_147_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_147_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_147_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_147_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_147_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_147_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_147_RESET 0x0 #define BB_TPC_PLUT_SRAM_147_ADDRESS (0x7cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_147_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_147_RESET 0x0 // 0x7d0 (BB_TPC_PLUT_SRAM_148) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_148_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_148_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_148_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_148_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_148_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_148_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_148_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_148_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_148_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_148_RESET 0x0 #define BB_TPC_PLUT_SRAM_148_ADDRESS (0x7d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_148_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_148_RESET 0x0 // 0x7d4 (BB_TPC_PLUT_SRAM_149) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_149_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_149_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_149_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_149_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_149_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_149_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_149_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_149_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_149_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_149_RESET 0x0 #define BB_TPC_PLUT_SRAM_149_ADDRESS (0x7d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_149_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_149_RESET 0x0 // 0x7d8 (BB_TPC_PLUT_SRAM_150) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_150_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_150_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_150_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_150_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_150_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_150_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_150_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_150_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_150_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_150_RESET 0x0 #define BB_TPC_PLUT_SRAM_150_ADDRESS (0x7d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_150_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_150_RESET 0x0 // 0x7dc (BB_TPC_PLUT_SRAM_151) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_151_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_151_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_151_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_151_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_151_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_151_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_151_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_151_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_151_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_151_RESET 0x0 #define BB_TPC_PLUT_SRAM_151_ADDRESS (0x7dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_151_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_151_RESET 0x0 // 0x7e0 (BB_TPC_PLUT_SRAM_152) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_152_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_152_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_152_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_152_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_152_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_152_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_152_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_152_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_152_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_152_RESET 0x0 #define BB_TPC_PLUT_SRAM_152_ADDRESS (0x7e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_152_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_152_RESET 0x0 // 0x7e4 (BB_TPC_PLUT_SRAM_153) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_153_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_153_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_153_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_153_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_153_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_153_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_153_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_153_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_153_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_153_RESET 0x0 #define BB_TPC_PLUT_SRAM_153_ADDRESS (0x7e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_153_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_153_RESET 0x0 // 0x7e8 (BB_TPC_PLUT_SRAM_154) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_154_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_154_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_154_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_154_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_154_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_154_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_154_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_154_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_154_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_154_RESET 0x0 #define BB_TPC_PLUT_SRAM_154_ADDRESS (0x7e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_154_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_154_RESET 0x0 // 0x7ec (BB_TPC_PLUT_SRAM_155) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_155_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_155_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_155_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_155_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_155_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_155_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_155_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_155_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_155_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_155_RESET 0x0 #define BB_TPC_PLUT_SRAM_155_ADDRESS (0x7ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_155_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_155_RESET 0x0 // 0x7f0 (BB_TPC_PLUT_SRAM_156) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_156_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_156_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_156_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_156_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_156_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_156_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_156_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_156_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_156_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_156_RESET 0x0 #define BB_TPC_PLUT_SRAM_156_ADDRESS (0x7f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_156_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_156_RESET 0x0 // 0x7f4 (BB_TPC_PLUT_SRAM_157) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_157_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_157_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_157_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_157_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_157_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_157_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_157_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_157_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_157_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_157_RESET 0x0 #define BB_TPC_PLUT_SRAM_157_ADDRESS (0x7f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_157_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_157_RESET 0x0 // 0x7f8 (BB_TPC_PLUT_SRAM_158) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_158_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_158_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_158_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_158_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_158_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_158_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_158_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_158_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_158_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_158_RESET 0x0 #define BB_TPC_PLUT_SRAM_158_ADDRESS (0x7f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_158_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_158_RESET 0x0 // 0x7fc (BB_TPC_PLUT_SRAM_159) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_159_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_159_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_159_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_159_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_159_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_159_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_159_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_159_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_159_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_159_RESET 0x0 #define BB_TPC_PLUT_SRAM_159_ADDRESS (0x7fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_159_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_159_RESET 0x0 // 0x800 (BB_TPC_PLUT_SRAM_160) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_160_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_160_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_160_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_160_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_160_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_160_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_160_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_160_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_160_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_160_RESET 0x0 #define BB_TPC_PLUT_SRAM_160_ADDRESS (0x800 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_160_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_160_RESET 0x0 // 0x804 (BB_TPC_PLUT_SRAM_161) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_161_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_161_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_161_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_161_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_161_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_161_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_161_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_161_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_161_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_161_RESET 0x0 #define BB_TPC_PLUT_SRAM_161_ADDRESS (0x804 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_161_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_161_RESET 0x0 // 0x808 (BB_TPC_PLUT_SRAM_162) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_162_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_162_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_162_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_162_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_162_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_162_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_162_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_162_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_162_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_162_RESET 0x0 #define BB_TPC_PLUT_SRAM_162_ADDRESS (0x808 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_162_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_162_RESET 0x0 // 0x80c (BB_TPC_PLUT_SRAM_163) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_163_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_163_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_163_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_163_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_163_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_163_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_163_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_163_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_163_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_163_RESET 0x0 #define BB_TPC_PLUT_SRAM_163_ADDRESS (0x80c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_163_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_163_RESET 0x0 // 0x810 (BB_TPC_PLUT_SRAM_164) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_164_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_164_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_164_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_164_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_164_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_164_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_164_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_164_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_164_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_164_RESET 0x0 #define BB_TPC_PLUT_SRAM_164_ADDRESS (0x810 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_164_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_164_RESET 0x0 // 0x814 (BB_TPC_PLUT_SRAM_165) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_165_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_165_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_165_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_165_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_165_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_165_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_165_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_165_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_165_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_165_RESET 0x0 #define BB_TPC_PLUT_SRAM_165_ADDRESS (0x814 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_165_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_165_RESET 0x0 // 0x818 (BB_TPC_PLUT_SRAM_166) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_166_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_166_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_166_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_166_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_166_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_166_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_166_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_166_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_166_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_166_RESET 0x0 #define BB_TPC_PLUT_SRAM_166_ADDRESS (0x818 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_166_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_166_RESET 0x0 // 0x81c (BB_TPC_PLUT_SRAM_167) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_167_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_167_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_167_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_167_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_167_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_167_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_167_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_167_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_167_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_167_RESET 0x0 #define BB_TPC_PLUT_SRAM_167_ADDRESS (0x81c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_167_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_167_RESET 0x0 // 0x820 (BB_TPC_PLUT_SRAM_168) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_168_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_168_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_168_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_168_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_168_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_168_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_168_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_168_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_168_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_168_RESET 0x0 #define BB_TPC_PLUT_SRAM_168_ADDRESS (0x820 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_168_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_168_RESET 0x0 // 0x824 (BB_TPC_PLUT_SRAM_169) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_169_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_169_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_169_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_169_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_169_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_169_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_169_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_169_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_169_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_169_RESET 0x0 #define BB_TPC_PLUT_SRAM_169_ADDRESS (0x824 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_169_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_169_RESET 0x0 // 0x828 (BB_TPC_PLUT_SRAM_170) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_170_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_170_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_170_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_170_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_170_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_170_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_170_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_170_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_170_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_170_RESET 0x0 #define BB_TPC_PLUT_SRAM_170_ADDRESS (0x828 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_170_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_170_RESET 0x0 // 0x82c (BB_TPC_PLUT_SRAM_171) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_171_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_171_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_171_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_171_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_171_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_171_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_171_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_171_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_171_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_171_RESET 0x0 #define BB_TPC_PLUT_SRAM_171_ADDRESS (0x82c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_171_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_171_RESET 0x0 // 0x830 (BB_TPC_PLUT_SRAM_172) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_172_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_172_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_172_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_172_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_172_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_172_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_172_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_172_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_172_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_172_RESET 0x0 #define BB_TPC_PLUT_SRAM_172_ADDRESS (0x830 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_172_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_172_RESET 0x0 // 0x834 (BB_TPC_PLUT_SRAM_173) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_173_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_173_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_173_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_173_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_173_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_173_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_173_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_173_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_173_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_173_RESET 0x0 #define BB_TPC_PLUT_SRAM_173_ADDRESS (0x834 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_173_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_173_RESET 0x0 // 0x838 (BB_TPC_PLUT_SRAM_174) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_174_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_174_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_174_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_174_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_174_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_174_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_174_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_174_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_174_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_174_RESET 0x0 #define BB_TPC_PLUT_SRAM_174_ADDRESS (0x838 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_174_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_174_RESET 0x0 // 0x83c (BB_TPC_PLUT_SRAM_175) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_175_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_175_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_175_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_175_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_175_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_175_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_175_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_175_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_175_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_175_RESET 0x0 #define BB_TPC_PLUT_SRAM_175_ADDRESS (0x83c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_175_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_175_RESET 0x0 // 0x840 (BB_TPC_PLUT_SRAM_176) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_176_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_176_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_176_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_176_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_176_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_176_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_176_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_176_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_176_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_176_RESET 0x0 #define BB_TPC_PLUT_SRAM_176_ADDRESS (0x840 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_176_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_176_RESET 0x0 // 0x844 (BB_TPC_PLUT_SRAM_177) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_177_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_177_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_177_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_177_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_177_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_177_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_177_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_177_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_177_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_177_RESET 0x0 #define BB_TPC_PLUT_SRAM_177_ADDRESS (0x844 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_177_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_177_RESET 0x0 // 0x848 (BB_TPC_PLUT_SRAM_178) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_178_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_178_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_178_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_178_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_178_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_178_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_178_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_178_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_178_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_178_RESET 0x0 #define BB_TPC_PLUT_SRAM_178_ADDRESS (0x848 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_178_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_178_RESET 0x0 // 0x84c (BB_TPC_PLUT_SRAM_179) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_179_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_179_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_179_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_179_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_179_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_179_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_179_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_179_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_179_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_179_RESET 0x0 #define BB_TPC_PLUT_SRAM_179_ADDRESS (0x84c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_179_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_179_RESET 0x0 // 0x850 (BB_TPC_PLUT_SRAM_180) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_180_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_180_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_180_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_180_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_180_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_180_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_180_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_180_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_180_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_180_RESET 0x0 #define BB_TPC_PLUT_SRAM_180_ADDRESS (0x850 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_180_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_180_RESET 0x0 // 0x854 (BB_TPC_PLUT_SRAM_181) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_181_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_181_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_181_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_181_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_181_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_181_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_181_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_181_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_181_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_181_RESET 0x0 #define BB_TPC_PLUT_SRAM_181_ADDRESS (0x854 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_181_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_181_RESET 0x0 // 0x858 (BB_TPC_PLUT_SRAM_182) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_182_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_182_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_182_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_182_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_182_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_182_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_182_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_182_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_182_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_182_RESET 0x0 #define BB_TPC_PLUT_SRAM_182_ADDRESS (0x858 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_182_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_182_RESET 0x0 // 0x85c (BB_TPC_PLUT_SRAM_183) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_183_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_183_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_183_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_183_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_183_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_183_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_183_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_183_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_183_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_183_RESET 0x0 #define BB_TPC_PLUT_SRAM_183_ADDRESS (0x85c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_183_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_183_RESET 0x0 // 0x860 (BB_TPC_PLUT_SRAM_184) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_184_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_184_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_184_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_184_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_184_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_184_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_184_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_184_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_184_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_184_RESET 0x0 #define BB_TPC_PLUT_SRAM_184_ADDRESS (0x860 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_184_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_184_RESET 0x0 // 0x864 (BB_TPC_PLUT_SRAM_185) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_185_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_185_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_185_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_185_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_185_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_185_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_185_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_185_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_185_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_185_RESET 0x0 #define BB_TPC_PLUT_SRAM_185_ADDRESS (0x864 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_185_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_185_RESET 0x0 // 0x868 (BB_TPC_PLUT_SRAM_186) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_186_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_186_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_186_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_186_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_186_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_186_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_186_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_186_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_186_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_186_RESET 0x0 #define BB_TPC_PLUT_SRAM_186_ADDRESS (0x868 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_186_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_186_RESET 0x0 // 0x86c (BB_TPC_PLUT_SRAM_187) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_187_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_187_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_187_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_187_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_187_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_187_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_187_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_187_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_187_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_187_RESET 0x0 #define BB_TPC_PLUT_SRAM_187_ADDRESS (0x86c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_187_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_187_RESET 0x0 // 0x870 (BB_TPC_PLUT_SRAM_188) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_188_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_188_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_188_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_188_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_188_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_188_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_188_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_188_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_188_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_188_RESET 0x0 #define BB_TPC_PLUT_SRAM_188_ADDRESS (0x870 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_188_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_188_RESET 0x0 // 0x874 (BB_TPC_PLUT_SRAM_189) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_189_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_189_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_189_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_189_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_189_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_189_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_189_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_189_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_189_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_189_RESET 0x0 #define BB_TPC_PLUT_SRAM_189_ADDRESS (0x874 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_189_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_189_RESET 0x0 // 0x878 (BB_TPC_PLUT_SRAM_190) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_190_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_190_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_190_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_190_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_190_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_190_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_190_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_190_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_190_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_190_RESET 0x0 #define BB_TPC_PLUT_SRAM_190_ADDRESS (0x878 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_190_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_190_RESET 0x0 // 0x87c (BB_TPC_PLUT_SRAM_191) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_191_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_191_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_191_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_191_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_191_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_191_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_191_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_191_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_191_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_191_RESET 0x0 #define BB_TPC_PLUT_SRAM_191_ADDRESS (0x87c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_191_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_191_RESET 0x0 // 0x880 (BB_TPC_PLUT_SRAM_192) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_192_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_192_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_192_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_192_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_192_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_192_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_192_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_192_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_192_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_192_RESET 0x0 #define BB_TPC_PLUT_SRAM_192_ADDRESS (0x880 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_192_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_192_RESET 0x0 // 0x884 (BB_TPC_PLUT_SRAM_193) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_193_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_193_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_193_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_193_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_193_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_193_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_193_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_193_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_193_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_193_RESET 0x0 #define BB_TPC_PLUT_SRAM_193_ADDRESS (0x884 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_193_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_193_RESET 0x0 // 0x888 (BB_TPC_PLUT_SRAM_194) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_194_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_194_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_194_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_194_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_194_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_194_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_194_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_194_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_194_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_194_RESET 0x0 #define BB_TPC_PLUT_SRAM_194_ADDRESS (0x888 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_194_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_194_RESET 0x0 // 0x88c (BB_TPC_PLUT_SRAM_195) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_195_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_195_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_195_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_195_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_195_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_195_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_195_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_195_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_195_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_195_RESET 0x0 #define BB_TPC_PLUT_SRAM_195_ADDRESS (0x88c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_195_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_195_RESET 0x0 // 0x890 (BB_TPC_PLUT_SRAM_196) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_196_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_196_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_196_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_196_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_196_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_196_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_196_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_196_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_196_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_196_RESET 0x0 #define BB_TPC_PLUT_SRAM_196_ADDRESS (0x890 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_196_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_196_RESET 0x0 // 0x894 (BB_TPC_PLUT_SRAM_197) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_197_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_197_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_197_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_197_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_197_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_197_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_197_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_197_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_197_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_197_RESET 0x0 #define BB_TPC_PLUT_SRAM_197_ADDRESS (0x894 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_197_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_197_RESET 0x0 // 0x898 (BB_TPC_PLUT_SRAM_198) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_198_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_198_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_198_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_198_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_198_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_198_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_198_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_198_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_198_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_198_RESET 0x0 #define BB_TPC_PLUT_SRAM_198_ADDRESS (0x898 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_198_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_198_RESET 0x0 // 0x89c (BB_TPC_PLUT_SRAM_199) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_199_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_199_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_199_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_199_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_199_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_199_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_199_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_199_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_199_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_199_RESET 0x0 #define BB_TPC_PLUT_SRAM_199_ADDRESS (0x89c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_199_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_199_RESET 0x0 // 0x8a0 (BB_TPC_PLUT_SRAM_200) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_200_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_200_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_200_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_200_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_200_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_200_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_200_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_200_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_200_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_200_RESET 0x0 #define BB_TPC_PLUT_SRAM_200_ADDRESS (0x8a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_200_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_200_RESET 0x0 // 0x8a4 (BB_TPC_PLUT_SRAM_201) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_201_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_201_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_201_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_201_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_201_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_201_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_201_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_201_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_201_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_201_RESET 0x0 #define BB_TPC_PLUT_SRAM_201_ADDRESS (0x8a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_201_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_201_RESET 0x0 // 0x8a8 (BB_TPC_PLUT_SRAM_202) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_202_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_202_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_202_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_202_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_202_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_202_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_202_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_202_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_202_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_202_RESET 0x0 #define BB_TPC_PLUT_SRAM_202_ADDRESS (0x8a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_202_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_202_RESET 0x0 // 0x8ac (BB_TPC_PLUT_SRAM_203) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_203_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_203_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_203_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_203_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_203_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_203_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_203_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_203_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_203_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_203_RESET 0x0 #define BB_TPC_PLUT_SRAM_203_ADDRESS (0x8ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_203_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_203_RESET 0x0 // 0x8b0 (BB_TPC_PLUT_SRAM_204) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_204_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_204_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_204_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_204_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_204_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_204_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_204_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_204_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_204_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_204_RESET 0x0 #define BB_TPC_PLUT_SRAM_204_ADDRESS (0x8b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_204_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_204_RESET 0x0 // 0x8b4 (BB_TPC_PLUT_SRAM_205) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_205_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_205_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_205_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_205_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_205_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_205_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_205_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_205_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_205_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_205_RESET 0x0 #define BB_TPC_PLUT_SRAM_205_ADDRESS (0x8b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_205_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_205_RESET 0x0 // 0x8b8 (BB_TPC_PLUT_SRAM_206) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_206_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_206_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_206_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_206_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_206_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_206_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_206_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_206_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_206_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_206_RESET 0x0 #define BB_TPC_PLUT_SRAM_206_ADDRESS (0x8b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_206_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_206_RESET 0x0 // 0x8bc (BB_TPC_PLUT_SRAM_207) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_207_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_207_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_207_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_207_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_207_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_207_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_207_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_207_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_207_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_207_RESET 0x0 #define BB_TPC_PLUT_SRAM_207_ADDRESS (0x8bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_207_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_207_RESET 0x0 // 0x8c0 (BB_TPC_PLUT_SRAM_208) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_208_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_208_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_208_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_208_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_208_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_208_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_208_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_208_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_208_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_208_RESET 0x0 #define BB_TPC_PLUT_SRAM_208_ADDRESS (0x8c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_208_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_208_RESET 0x0 // 0x8c4 (BB_TPC_PLUT_SRAM_209) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_209_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_209_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_209_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_209_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_209_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_209_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_209_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_209_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_209_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_209_RESET 0x0 #define BB_TPC_PLUT_SRAM_209_ADDRESS (0x8c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_209_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_209_RESET 0x0 // 0x8c8 (BB_TPC_PLUT_SRAM_210) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_210_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_210_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_210_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_210_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_210_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_210_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_210_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_210_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_210_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_210_RESET 0x0 #define BB_TPC_PLUT_SRAM_210_ADDRESS (0x8c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_210_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_210_RESET 0x0 // 0x8cc (BB_TPC_PLUT_SRAM_211) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_211_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_211_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_211_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_211_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_211_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_211_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_211_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_211_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_211_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_211_RESET 0x0 #define BB_TPC_PLUT_SRAM_211_ADDRESS (0x8cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_211_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_211_RESET 0x0 // 0x8d0 (BB_TPC_PLUT_SRAM_212) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_212_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_212_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_212_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_212_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_212_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_212_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_212_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_212_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_212_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_212_RESET 0x0 #define BB_TPC_PLUT_SRAM_212_ADDRESS (0x8d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_212_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_212_RESET 0x0 // 0x8d4 (BB_TPC_PLUT_SRAM_213) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_213_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_213_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_213_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_213_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_213_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_213_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_213_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_213_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_213_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_213_RESET 0x0 #define BB_TPC_PLUT_SRAM_213_ADDRESS (0x8d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_213_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_213_RESET 0x0 // 0x8d8 (BB_TPC_PLUT_SRAM_214) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_214_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_214_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_214_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_214_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_214_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_214_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_214_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_214_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_214_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_214_RESET 0x0 #define BB_TPC_PLUT_SRAM_214_ADDRESS (0x8d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_214_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_214_RESET 0x0 // 0x8dc (BB_TPC_PLUT_SRAM_215) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_215_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_215_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_215_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_215_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_215_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_215_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_215_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_215_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_215_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_215_RESET 0x0 #define BB_TPC_PLUT_SRAM_215_ADDRESS (0x8dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_215_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_215_RESET 0x0 // 0x8e0 (BB_TPC_PLUT_SRAM_216) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_216_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_216_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_216_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_216_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_216_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_216_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_216_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_216_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_216_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_216_RESET 0x0 #define BB_TPC_PLUT_SRAM_216_ADDRESS (0x8e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_216_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_216_RESET 0x0 // 0x8e4 (BB_TPC_PLUT_SRAM_217) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_217_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_217_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_217_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_217_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_217_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_217_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_217_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_217_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_217_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_217_RESET 0x0 #define BB_TPC_PLUT_SRAM_217_ADDRESS (0x8e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_217_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_217_RESET 0x0 // 0x8e8 (BB_TPC_PLUT_SRAM_218) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_218_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_218_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_218_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_218_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_218_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_218_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_218_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_218_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_218_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_218_RESET 0x0 #define BB_TPC_PLUT_SRAM_218_ADDRESS (0x8e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_218_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_218_RESET 0x0 // 0x8ec (BB_TPC_PLUT_SRAM_219) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_219_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_219_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_219_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_219_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_219_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_219_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_219_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_219_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_219_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_219_RESET 0x0 #define BB_TPC_PLUT_SRAM_219_ADDRESS (0x8ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_219_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_219_RESET 0x0 // 0x8f0 (BB_TPC_PLUT_SRAM_220) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_220_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_220_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_220_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_220_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_220_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_220_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_220_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_220_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_220_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_220_RESET 0x0 #define BB_TPC_PLUT_SRAM_220_ADDRESS (0x8f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_220_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_220_RESET 0x0 // 0x8f4 (BB_TPC_PLUT_SRAM_221) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_221_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_221_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_221_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_221_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_221_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_221_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_221_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_221_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_221_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_221_RESET 0x0 #define BB_TPC_PLUT_SRAM_221_ADDRESS (0x8f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_221_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_221_RESET 0x0 // 0x8f8 (BB_TPC_PLUT_SRAM_222) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_222_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_222_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_222_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_222_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_222_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_222_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_222_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_222_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_222_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_222_RESET 0x0 #define BB_TPC_PLUT_SRAM_222_ADDRESS (0x8f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_222_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_222_RESET 0x0 // 0x8fc (BB_TPC_PLUT_SRAM_223) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_223_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_223_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_223_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_223_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_223_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_223_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_223_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_223_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_223_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_223_RESET 0x0 #define BB_TPC_PLUT_SRAM_223_ADDRESS (0x8fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_223_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_223_RESET 0x0 // 0x900 (BB_TPC_PLUT_SRAM_224) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_224_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_224_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_224_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_224_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_224_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_224_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_224_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_224_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_224_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_224_RESET 0x0 #define BB_TPC_PLUT_SRAM_224_ADDRESS (0x900 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_224_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_224_RESET 0x0 // 0x904 (BB_TPC_PLUT_SRAM_225) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_225_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_225_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_225_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_225_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_225_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_225_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_225_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_225_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_225_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_225_RESET 0x0 #define BB_TPC_PLUT_SRAM_225_ADDRESS (0x904 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_225_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_225_RESET 0x0 // 0x908 (BB_TPC_PLUT_SRAM_226) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_226_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_226_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_226_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_226_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_226_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_226_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_226_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_226_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_226_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_226_RESET 0x0 #define BB_TPC_PLUT_SRAM_226_ADDRESS (0x908 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_226_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_226_RESET 0x0 // 0x90c (BB_TPC_PLUT_SRAM_227) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_227_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_227_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_227_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_227_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_227_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_227_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_227_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_227_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_227_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_227_RESET 0x0 #define BB_TPC_PLUT_SRAM_227_ADDRESS (0x90c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_227_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_227_RESET 0x0 // 0x910 (BB_TPC_PLUT_SRAM_228) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_228_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_228_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_228_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_228_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_228_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_228_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_228_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_228_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_228_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_228_RESET 0x0 #define BB_TPC_PLUT_SRAM_228_ADDRESS (0x910 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_228_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_228_RESET 0x0 // 0x914 (BB_TPC_PLUT_SRAM_229) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_229_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_229_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_229_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_229_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_229_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_229_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_229_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_229_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_229_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_229_RESET 0x0 #define BB_TPC_PLUT_SRAM_229_ADDRESS (0x914 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_229_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_229_RESET 0x0 // 0x918 (BB_TPC_PLUT_SRAM_230) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_230_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_230_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_230_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_230_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_230_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_230_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_230_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_230_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_230_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_230_RESET 0x0 #define BB_TPC_PLUT_SRAM_230_ADDRESS (0x918 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_230_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_230_RESET 0x0 // 0x91c (BB_TPC_PLUT_SRAM_231) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_231_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_231_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_231_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_231_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_231_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_231_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_231_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_231_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_231_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_231_RESET 0x0 #define BB_TPC_PLUT_SRAM_231_ADDRESS (0x91c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_231_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_231_RESET 0x0 // 0x920 (BB_TPC_PLUT_SRAM_232) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_232_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_232_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_232_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_232_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_232_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_232_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_232_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_232_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_232_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_232_RESET 0x0 #define BB_TPC_PLUT_SRAM_232_ADDRESS (0x920 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_232_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_232_RESET 0x0 // 0x924 (BB_TPC_PLUT_SRAM_233) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_233_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_233_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_233_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_233_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_233_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_233_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_233_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_233_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_233_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_233_RESET 0x0 #define BB_TPC_PLUT_SRAM_233_ADDRESS (0x924 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_233_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_233_RESET 0x0 // 0x928 (BB_TPC_PLUT_SRAM_234) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_234_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_234_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_234_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_234_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_234_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_234_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_234_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_234_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_234_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_234_RESET 0x0 #define BB_TPC_PLUT_SRAM_234_ADDRESS (0x928 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_234_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_234_RESET 0x0 // 0x92c (BB_TPC_PLUT_SRAM_235) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_235_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_235_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_235_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_235_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_235_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_235_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_235_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_235_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_235_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_235_RESET 0x0 #define BB_TPC_PLUT_SRAM_235_ADDRESS (0x92c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_235_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_235_RESET 0x0 // 0x930 (BB_TPC_PLUT_SRAM_236) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_236_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_236_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_236_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_236_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_236_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_236_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_236_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_236_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_236_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_236_RESET 0x0 #define BB_TPC_PLUT_SRAM_236_ADDRESS (0x930 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_236_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_236_RESET 0x0 // 0x934 (BB_TPC_PLUT_SRAM_237) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_237_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_237_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_237_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_237_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_237_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_237_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_237_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_237_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_237_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_237_RESET 0x0 #define BB_TPC_PLUT_SRAM_237_ADDRESS (0x934 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_237_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_237_RESET 0x0 // 0x938 (BB_TPC_PLUT_SRAM_238) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_238_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_238_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_238_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_238_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_238_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_238_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_238_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_238_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_238_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_238_RESET 0x0 #define BB_TPC_PLUT_SRAM_238_ADDRESS (0x938 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_238_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_238_RESET 0x0 // 0x93c (BB_TPC_PLUT_SRAM_239) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_239_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_239_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_239_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_239_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_239_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_239_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_239_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_239_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_239_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_239_RESET 0x0 #define BB_TPC_PLUT_SRAM_239_ADDRESS (0x93c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_239_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_239_RESET 0x0 // 0x940 (BB_TPC_PLUT_SRAM_240) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_240_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_240_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_240_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_240_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_240_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_240_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_240_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_240_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_240_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_240_RESET 0x0 #define BB_TPC_PLUT_SRAM_240_ADDRESS (0x940 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_240_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_240_RESET 0x0 // 0x944 (BB_TPC_PLUT_SRAM_241) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_241_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_241_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_241_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_241_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_241_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_241_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_241_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_241_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_241_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_241_RESET 0x0 #define BB_TPC_PLUT_SRAM_241_ADDRESS (0x944 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_241_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_241_RESET 0x0 // 0x948 (BB_TPC_PLUT_SRAM_242) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_242_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_242_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_242_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_242_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_242_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_242_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_242_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_242_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_242_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_242_RESET 0x0 #define BB_TPC_PLUT_SRAM_242_ADDRESS (0x948 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_242_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_242_RESET 0x0 // 0x94c (BB_TPC_PLUT_SRAM_243) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_243_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_243_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_243_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_243_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_243_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_243_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_243_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_243_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_243_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_243_RESET 0x0 #define BB_TPC_PLUT_SRAM_243_ADDRESS (0x94c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_243_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_243_RESET 0x0 // 0x950 (BB_TPC_PLUT_SRAM_244) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_244_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_244_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_244_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_244_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_244_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_244_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_244_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_244_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_244_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_244_RESET 0x0 #define BB_TPC_PLUT_SRAM_244_ADDRESS (0x950 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_244_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_244_RESET 0x0 // 0x954 (BB_TPC_PLUT_SRAM_245) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_245_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_245_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_245_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_245_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_245_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_245_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_245_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_245_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_245_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_245_RESET 0x0 #define BB_TPC_PLUT_SRAM_245_ADDRESS (0x954 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_245_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_245_RESET 0x0 // 0x958 (BB_TPC_PLUT_SRAM_246) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_246_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_246_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_246_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_246_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_246_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_246_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_246_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_246_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_246_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_246_RESET 0x0 #define BB_TPC_PLUT_SRAM_246_ADDRESS (0x958 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_246_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_246_RESET 0x0 // 0x95c (BB_TPC_PLUT_SRAM_247) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_247_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_247_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_247_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_247_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_247_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_247_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_247_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_247_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_247_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_247_RESET 0x0 #define BB_TPC_PLUT_SRAM_247_ADDRESS (0x95c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_247_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_247_RESET 0x0 // 0x960 (BB_TPC_PLUT_SRAM_248) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_248_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_248_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_248_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_248_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_248_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_248_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_248_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_248_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_248_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_248_RESET 0x0 #define BB_TPC_PLUT_SRAM_248_ADDRESS (0x960 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_248_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_248_RESET 0x0 // 0x964 (BB_TPC_PLUT_SRAM_249) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_249_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_249_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_249_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_249_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_249_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_249_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_249_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_249_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_249_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_249_RESET 0x0 #define BB_TPC_PLUT_SRAM_249_ADDRESS (0x964 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_249_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_249_RESET 0x0 // 0x968 (BB_TPC_PLUT_SRAM_250) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_250_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_250_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_250_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_250_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_250_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_250_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_250_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_250_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_250_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_250_RESET 0x0 #define BB_TPC_PLUT_SRAM_250_ADDRESS (0x968 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_250_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_250_RESET 0x0 // 0x96c (BB_TPC_PLUT_SRAM_251) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_251_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_251_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_251_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_251_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_251_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_251_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_251_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_251_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_251_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_251_RESET 0x0 #define BB_TPC_PLUT_SRAM_251_ADDRESS (0x96c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_251_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_251_RESET 0x0 // 0x970 (BB_TPC_PLUT_SRAM_252) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_252_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_252_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_252_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_252_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_252_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_252_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_252_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_252_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_252_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_252_RESET 0x0 #define BB_TPC_PLUT_SRAM_252_ADDRESS (0x970 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_252_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_252_RESET 0x0 // 0x974 (BB_TPC_PLUT_SRAM_253) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_253_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_253_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_253_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_253_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_253_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_253_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_253_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_253_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_253_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_253_RESET 0x0 #define BB_TPC_PLUT_SRAM_253_ADDRESS (0x974 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_253_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_253_RESET 0x0 // 0x978 (BB_TPC_PLUT_SRAM_254) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_254_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_254_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_254_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_254_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_254_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_254_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_254_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_254_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_254_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_254_RESET 0x0 #define BB_TPC_PLUT_SRAM_254_ADDRESS (0x978 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_254_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_254_RESET 0x0 // 0x97c (BB_TPC_PLUT_SRAM_255) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_255_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_255_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_255_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_255_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_255_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_255_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_255_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_255_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_255_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_255_RESET 0x0 #define BB_TPC_PLUT_SRAM_255_ADDRESS (0x97c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_255_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_255_RESET 0x0 // 0x980 (BB_TPC_PLUT_SRAM_256) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_256_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_256_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_256_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_256_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_256_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_256_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_256_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_256_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_256_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_256_RESET 0x0 #define BB_TPC_PLUT_SRAM_256_ADDRESS (0x980 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_256_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_256_RESET 0x0 // 0x984 (BB_TPC_PLUT_SRAM_257) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_257_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_257_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_257_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_257_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_257_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_257_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_257_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_257_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_257_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_257_RESET 0x0 #define BB_TPC_PLUT_SRAM_257_ADDRESS (0x984 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_257_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_257_RESET 0x0 // 0x988 (BB_TPC_PLUT_SRAM_258) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_258_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_258_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_258_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_258_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_258_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_258_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_258_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_258_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_258_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_258_RESET 0x0 #define BB_TPC_PLUT_SRAM_258_ADDRESS (0x988 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_258_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_258_RESET 0x0 // 0x98c (BB_TPC_PLUT_SRAM_259) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_259_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_259_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_259_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_259_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_259_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_259_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_259_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_259_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_259_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_259_RESET 0x0 #define BB_TPC_PLUT_SRAM_259_ADDRESS (0x98c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_259_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_259_RESET 0x0 // 0x990 (BB_TPC_PLUT_SRAM_260) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_260_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_260_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_260_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_260_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_260_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_260_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_260_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_260_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_260_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_260_RESET 0x0 #define BB_TPC_PLUT_SRAM_260_ADDRESS (0x990 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_260_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_260_RESET 0x0 // 0x994 (BB_TPC_PLUT_SRAM_261) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_261_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_261_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_261_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_261_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_261_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_261_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_261_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_261_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_261_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_261_RESET 0x0 #define BB_TPC_PLUT_SRAM_261_ADDRESS (0x994 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_261_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_261_RESET 0x0 // 0x998 (BB_TPC_PLUT_SRAM_262) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_262_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_262_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_262_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_262_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_262_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_262_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_262_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_262_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_262_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_262_RESET 0x0 #define BB_TPC_PLUT_SRAM_262_ADDRESS (0x998 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_262_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_262_RESET 0x0 // 0x99c (BB_TPC_PLUT_SRAM_263) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_263_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_263_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_263_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_263_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_263_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_263_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_263_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_263_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_263_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_263_RESET 0x0 #define BB_TPC_PLUT_SRAM_263_ADDRESS (0x99c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_263_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_263_RESET 0x0 // 0x9a0 (BB_TPC_PLUT_SRAM_264) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_264_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_264_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_264_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_264_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_264_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_264_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_264_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_264_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_264_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_264_RESET 0x0 #define BB_TPC_PLUT_SRAM_264_ADDRESS (0x9a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_264_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_264_RESET 0x0 // 0x9a4 (BB_TPC_PLUT_SRAM_265) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_265_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_265_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_265_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_265_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_265_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_265_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_265_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_265_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_265_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_265_RESET 0x0 #define BB_TPC_PLUT_SRAM_265_ADDRESS (0x9a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_265_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_265_RESET 0x0 // 0x9a8 (BB_TPC_PLUT_SRAM_266) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_266_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_266_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_266_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_266_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_266_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_266_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_266_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_266_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_266_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_266_RESET 0x0 #define BB_TPC_PLUT_SRAM_266_ADDRESS (0x9a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_266_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_266_RESET 0x0 // 0x9ac (BB_TPC_PLUT_SRAM_267) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_267_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_267_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_267_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_267_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_267_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_267_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_267_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_267_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_267_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_267_RESET 0x0 #define BB_TPC_PLUT_SRAM_267_ADDRESS (0x9ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_267_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_267_RESET 0x0 // 0x9b0 (BB_TPC_PLUT_SRAM_268) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_268_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_268_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_268_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_268_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_268_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_268_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_268_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_268_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_268_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_268_RESET 0x0 #define BB_TPC_PLUT_SRAM_268_ADDRESS (0x9b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_268_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_268_RESET 0x0 // 0x9b4 (BB_TPC_PLUT_SRAM_269) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_269_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_269_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_269_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_269_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_269_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_269_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_269_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_269_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_269_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_269_RESET 0x0 #define BB_TPC_PLUT_SRAM_269_ADDRESS (0x9b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_269_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_269_RESET 0x0 // 0x9b8 (BB_TPC_PLUT_SRAM_270) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_270_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_270_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_270_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_270_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_270_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_270_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_270_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_270_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_270_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_270_RESET 0x0 #define BB_TPC_PLUT_SRAM_270_ADDRESS (0x9b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_270_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_270_RESET 0x0 // 0x9bc (BB_TPC_PLUT_SRAM_271) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_271_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_271_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_271_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_271_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_271_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_271_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_271_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_271_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_271_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_271_RESET 0x0 #define BB_TPC_PLUT_SRAM_271_ADDRESS (0x9bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_271_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_271_RESET 0x0 // 0x9c0 (BB_TPC_PLUT_SRAM_272) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_272_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_272_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_272_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_272_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_272_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_272_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_272_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_272_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_272_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_272_RESET 0x0 #define BB_TPC_PLUT_SRAM_272_ADDRESS (0x9c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_272_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_272_RESET 0x0 // 0x9c4 (BB_TPC_PLUT_SRAM_273) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_273_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_273_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_273_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_273_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_273_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_273_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_273_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_273_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_273_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_273_RESET 0x0 #define BB_TPC_PLUT_SRAM_273_ADDRESS (0x9c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_273_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_273_RESET 0x0 // 0x9c8 (BB_TPC_PLUT_SRAM_274) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_274_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_274_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_274_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_274_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_274_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_274_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_274_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_274_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_274_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_274_RESET 0x0 #define BB_TPC_PLUT_SRAM_274_ADDRESS (0x9c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_274_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_274_RESET 0x0 // 0x9cc (BB_TPC_PLUT_SRAM_275) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_275_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_275_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_275_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_275_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_275_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_275_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_275_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_275_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_275_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_275_RESET 0x0 #define BB_TPC_PLUT_SRAM_275_ADDRESS (0x9cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_275_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_275_RESET 0x0 // 0x9d0 (BB_TPC_PLUT_SRAM_276) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_276_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_276_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_276_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_276_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_276_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_276_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_276_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_276_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_276_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_276_RESET 0x0 #define BB_TPC_PLUT_SRAM_276_ADDRESS (0x9d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_276_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_276_RESET 0x0 // 0x9d4 (BB_TPC_PLUT_SRAM_277) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_277_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_277_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_277_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_277_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_277_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_277_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_277_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_277_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_277_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_277_RESET 0x0 #define BB_TPC_PLUT_SRAM_277_ADDRESS (0x9d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_277_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_277_RESET 0x0 // 0x9d8 (BB_TPC_PLUT_SRAM_278) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_278_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_278_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_278_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_278_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_278_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_278_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_278_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_278_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_278_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_278_RESET 0x0 #define BB_TPC_PLUT_SRAM_278_ADDRESS (0x9d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_278_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_278_RESET 0x0 // 0x9dc (BB_TPC_PLUT_SRAM_279) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_279_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_279_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_279_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_279_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_279_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_279_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_279_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_279_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_279_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_279_RESET 0x0 #define BB_TPC_PLUT_SRAM_279_ADDRESS (0x9dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_279_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_279_RESET 0x0 // 0x9e0 (BB_TPC_PLUT_SRAM_280) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_280_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_280_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_280_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_280_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_280_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_280_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_280_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_280_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_280_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_280_RESET 0x0 #define BB_TPC_PLUT_SRAM_280_ADDRESS (0x9e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_280_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_280_RESET 0x0 // 0x9e4 (BB_TPC_PLUT_SRAM_281) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_281_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_281_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_281_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_281_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_281_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_281_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_281_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_281_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_281_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_281_RESET 0x0 #define BB_TPC_PLUT_SRAM_281_ADDRESS (0x9e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_281_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_281_RESET 0x0 // 0x9e8 (BB_TPC_PLUT_SRAM_282) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_282_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_282_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_282_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_282_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_282_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_282_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_282_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_282_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_282_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_282_RESET 0x0 #define BB_TPC_PLUT_SRAM_282_ADDRESS (0x9e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_282_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_282_RESET 0x0 // 0x9ec (BB_TPC_PLUT_SRAM_283) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_283_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_283_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_283_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_283_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_283_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_283_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_283_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_283_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_283_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_283_RESET 0x0 #define BB_TPC_PLUT_SRAM_283_ADDRESS (0x9ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_283_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_283_RESET 0x0 // 0x9f0 (BB_TPC_PLUT_SRAM_284) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_284_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_284_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_284_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_284_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_284_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_284_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_284_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_284_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_284_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_284_RESET 0x0 #define BB_TPC_PLUT_SRAM_284_ADDRESS (0x9f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_284_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_284_RESET 0x0 // 0x9f4 (BB_TPC_PLUT_SRAM_285) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_285_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_285_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_285_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_285_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_285_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_285_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_285_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_285_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_285_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_285_RESET 0x0 #define BB_TPC_PLUT_SRAM_285_ADDRESS (0x9f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_285_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_285_RESET 0x0 // 0x9f8 (BB_TPC_PLUT_SRAM_286) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_286_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_286_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_286_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_286_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_286_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_286_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_286_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_286_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_286_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_286_RESET 0x0 #define BB_TPC_PLUT_SRAM_286_ADDRESS (0x9f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_286_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_286_RESET 0x0 // 0x9fc (BB_TPC_PLUT_SRAM_287) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_287_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_287_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_287_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_287_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_287_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_287_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_287_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_287_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_287_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_287_RESET 0x0 #define BB_TPC_PLUT_SRAM_287_ADDRESS (0x9fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_287_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_287_RESET 0x0 // 0xa00 (BB_TPC_PLUT_SRAM_288) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_288_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_288_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_288_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_288_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_288_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_288_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_288_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_288_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_288_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_288_RESET 0x0 #define BB_TPC_PLUT_SRAM_288_ADDRESS (0xa00 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_288_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_288_RESET 0x0 // 0xa04 (BB_TPC_PLUT_SRAM_289) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_289_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_289_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_289_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_289_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_289_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_289_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_289_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_289_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_289_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_289_RESET 0x0 #define BB_TPC_PLUT_SRAM_289_ADDRESS (0xa04 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_289_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_289_RESET 0x0 // 0xa08 (BB_TPC_PLUT_SRAM_290) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_290_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_290_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_290_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_290_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_290_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_290_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_290_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_290_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_290_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_290_RESET 0x0 #define BB_TPC_PLUT_SRAM_290_ADDRESS (0xa08 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_290_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_290_RESET 0x0 // 0xa0c (BB_TPC_PLUT_SRAM_291) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_291_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_291_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_291_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_291_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_291_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_291_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_291_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_291_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_291_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_291_RESET 0x0 #define BB_TPC_PLUT_SRAM_291_ADDRESS (0xa0c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_291_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_291_RESET 0x0 // 0xa10 (BB_TPC_PLUT_SRAM_292) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_292_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_292_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_292_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_292_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_292_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_292_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_292_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_292_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_292_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_292_RESET 0x0 #define BB_TPC_PLUT_SRAM_292_ADDRESS (0xa10 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_292_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_292_RESET 0x0 // 0xa14 (BB_TPC_PLUT_SRAM_293) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_293_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_293_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_293_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_293_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_293_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_293_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_293_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_293_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_293_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_293_RESET 0x0 #define BB_TPC_PLUT_SRAM_293_ADDRESS (0xa14 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_293_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_293_RESET 0x0 // 0xa18 (BB_TPC_PLUT_SRAM_294) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_294_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_294_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_294_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_294_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_294_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_294_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_294_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_294_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_294_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_294_RESET 0x0 #define BB_TPC_PLUT_SRAM_294_ADDRESS (0xa18 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_294_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_294_RESET 0x0 // 0xa1c (BB_TPC_PLUT_SRAM_295) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_295_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_295_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_295_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_295_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_295_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_295_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_295_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_295_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_295_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_295_RESET 0x0 #define BB_TPC_PLUT_SRAM_295_ADDRESS (0xa1c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_295_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_295_RESET 0x0 // 0xa20 (BB_TPC_PLUT_SRAM_296) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_296_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_296_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_296_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_296_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_296_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_296_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_296_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_296_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_296_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_296_RESET 0x0 #define BB_TPC_PLUT_SRAM_296_ADDRESS (0xa20 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_296_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_296_RESET 0x0 // 0xa24 (BB_TPC_PLUT_SRAM_297) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_297_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_297_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_297_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_297_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_297_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_297_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_297_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_297_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_297_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_297_RESET 0x0 #define BB_TPC_PLUT_SRAM_297_ADDRESS (0xa24 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_297_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_297_RESET 0x0 // 0xa28 (BB_TPC_PLUT_SRAM_298) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_298_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_298_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_298_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_298_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_298_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_298_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_298_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_298_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_298_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_298_RESET 0x0 #define BB_TPC_PLUT_SRAM_298_ADDRESS (0xa28 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_298_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_298_RESET 0x0 // 0xa2c (BB_TPC_PLUT_SRAM_299) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_299_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_299_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_299_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_299_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_299_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_299_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_299_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_299_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_299_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_299_RESET 0x0 #define BB_TPC_PLUT_SRAM_299_ADDRESS (0xa2c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_299_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_299_RESET 0x0 // 0xa30 (BB_TPC_PLUT_SRAM_300) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_300_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_300_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_300_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_300_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_300_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_300_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_300_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_300_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_300_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_300_RESET 0x0 #define BB_TPC_PLUT_SRAM_300_ADDRESS (0xa30 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_300_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_300_RESET 0x0 // 0xa34 (BB_TPC_PLUT_SRAM_301) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_301_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_301_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_301_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_301_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_301_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_301_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_301_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_301_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_301_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_301_RESET 0x0 #define BB_TPC_PLUT_SRAM_301_ADDRESS (0xa34 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_301_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_301_RESET 0x0 // 0xa38 (BB_TPC_PLUT_SRAM_302) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_302_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_302_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_302_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_302_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_302_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_302_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_302_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_302_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_302_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_302_RESET 0x0 #define BB_TPC_PLUT_SRAM_302_ADDRESS (0xa38 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_302_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_302_RESET 0x0 // 0xa3c (BB_TPC_PLUT_SRAM_303) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_303_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_303_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_303_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_303_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_303_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_303_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_303_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_303_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_303_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_303_RESET 0x0 #define BB_TPC_PLUT_SRAM_303_ADDRESS (0xa3c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_303_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_303_RESET 0x0 // 0xa40 (BB_TPC_PLUT_SRAM_304) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_304_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_304_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_304_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_304_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_304_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_304_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_304_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_304_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_304_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_304_RESET 0x0 #define BB_TPC_PLUT_SRAM_304_ADDRESS (0xa40 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_304_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_304_RESET 0x0 // 0xa44 (BB_TPC_PLUT_SRAM_305) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_305_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_305_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_305_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_305_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_305_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_305_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_305_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_305_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_305_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_305_RESET 0x0 #define BB_TPC_PLUT_SRAM_305_ADDRESS (0xa44 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_305_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_305_RESET 0x0 // 0xa48 (BB_TPC_PLUT_SRAM_306) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_306_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_306_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_306_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_306_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_306_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_306_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_306_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_306_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_306_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_306_RESET 0x0 #define BB_TPC_PLUT_SRAM_306_ADDRESS (0xa48 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_306_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_306_RESET 0x0 // 0xa4c (BB_TPC_PLUT_SRAM_307) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_307_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_307_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_307_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_307_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_307_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_307_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_307_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_307_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_307_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_307_RESET 0x0 #define BB_TPC_PLUT_SRAM_307_ADDRESS (0xa4c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_307_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_307_RESET 0x0 // 0xa50 (BB_TPC_PLUT_SRAM_308) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_308_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_308_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_308_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_308_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_308_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_308_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_308_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_308_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_308_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_308_RESET 0x0 #define BB_TPC_PLUT_SRAM_308_ADDRESS (0xa50 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_308_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_308_RESET 0x0 // 0xa54 (BB_TPC_PLUT_SRAM_309) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_309_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_309_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_309_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_309_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_309_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_309_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_309_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_309_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_309_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_309_RESET 0x0 #define BB_TPC_PLUT_SRAM_309_ADDRESS (0xa54 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_309_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_309_RESET 0x0 // 0xa58 (BB_TPC_PLUT_SRAM_310) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_310_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_310_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_310_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_310_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_310_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_310_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_310_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_310_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_310_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_310_RESET 0x0 #define BB_TPC_PLUT_SRAM_310_ADDRESS (0xa58 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_310_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_310_RESET 0x0 // 0xa5c (BB_TPC_PLUT_SRAM_311) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_311_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_311_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_311_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_311_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_311_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_311_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_311_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_311_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_311_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_311_RESET 0x0 #define BB_TPC_PLUT_SRAM_311_ADDRESS (0xa5c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_311_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_311_RESET 0x0 // 0xa60 (BB_TPC_PLUT_SRAM_312) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_312_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_312_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_312_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_312_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_312_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_312_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_312_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_312_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_312_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_312_RESET 0x0 #define BB_TPC_PLUT_SRAM_312_ADDRESS (0xa60 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_312_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_312_RESET 0x0 // 0xa64 (BB_TPC_PLUT_SRAM_313) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_313_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_313_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_313_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_313_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_313_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_313_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_313_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_313_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_313_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_313_RESET 0x0 #define BB_TPC_PLUT_SRAM_313_ADDRESS (0xa64 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_313_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_313_RESET 0x0 // 0xa68 (BB_TPC_PLUT_SRAM_314) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_314_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_314_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_314_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_314_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_314_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_314_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_314_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_314_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_314_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_314_RESET 0x0 #define BB_TPC_PLUT_SRAM_314_ADDRESS (0xa68 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_314_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_314_RESET 0x0 // 0xa6c (BB_TPC_PLUT_SRAM_315) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_315_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_315_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_315_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_315_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_315_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_315_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_315_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_315_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_315_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_315_RESET 0x0 #define BB_TPC_PLUT_SRAM_315_ADDRESS (0xa6c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_315_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_315_RESET 0x0 // 0xa70 (BB_TPC_PLUT_SRAM_316) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_316_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_316_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_316_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_316_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_316_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_316_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_316_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_316_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_316_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_316_RESET 0x0 #define BB_TPC_PLUT_SRAM_316_ADDRESS (0xa70 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_316_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_316_RESET 0x0 // 0xa74 (BB_TPC_PLUT_SRAM_317) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_317_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_317_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_317_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_317_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_317_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_317_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_317_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_317_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_317_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_317_RESET 0x0 #define BB_TPC_PLUT_SRAM_317_ADDRESS (0xa74 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_317_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_317_RESET 0x0 // 0xa78 (BB_TPC_PLUT_SRAM_318) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_318_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_318_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_318_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_318_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_318_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_318_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_318_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_318_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_318_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_318_RESET 0x0 #define BB_TPC_PLUT_SRAM_318_ADDRESS (0xa78 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_318_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_318_RESET 0x0 // 0xa7c (BB_TPC_PLUT_SRAM_319) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_319_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_319_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_319_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_319_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_319_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_319_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_319_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_319_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_319_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_319_RESET 0x0 #define BB_TPC_PLUT_SRAM_319_ADDRESS (0xa7c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_319_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_319_RESET 0x0 // 0xa80 (BB_TPC_PLUT_SRAM_320) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_320_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_320_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_320_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_320_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_320_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_320_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_320_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_320_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_320_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_320_RESET 0x0 #define BB_TPC_PLUT_SRAM_320_ADDRESS (0xa80 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_320_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_320_RESET 0x0 // 0xa84 (BB_TPC_PLUT_SRAM_321) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_321_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_321_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_321_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_321_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_321_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_321_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_321_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_321_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_321_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_321_RESET 0x0 #define BB_TPC_PLUT_SRAM_321_ADDRESS (0xa84 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_321_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_321_RESET 0x0 // 0xa88 (BB_TPC_PLUT_SRAM_322) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_322_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_322_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_322_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_322_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_322_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_322_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_322_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_322_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_322_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_322_RESET 0x0 #define BB_TPC_PLUT_SRAM_322_ADDRESS (0xa88 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_322_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_322_RESET 0x0 // 0xa8c (BB_TPC_PLUT_SRAM_323) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_323_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_323_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_323_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_323_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_323_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_323_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_323_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_323_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_323_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_323_RESET 0x0 #define BB_TPC_PLUT_SRAM_323_ADDRESS (0xa8c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_323_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_323_RESET 0x0 // 0xa90 (BB_TPC_PLUT_SRAM_324) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_324_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_324_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_324_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_324_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_324_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_324_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_324_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_324_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_324_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_324_RESET 0x0 #define BB_TPC_PLUT_SRAM_324_ADDRESS (0xa90 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_324_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_324_RESET 0x0 // 0xa94 (BB_TPC_PLUT_SRAM_325) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_325_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_325_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_325_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_325_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_325_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_325_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_325_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_325_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_325_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_325_RESET 0x0 #define BB_TPC_PLUT_SRAM_325_ADDRESS (0xa94 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_325_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_325_RESET 0x0 // 0xa98 (BB_TPC_PLUT_SRAM_326) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_326_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_326_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_326_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_326_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_326_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_326_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_326_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_326_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_326_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_326_RESET 0x0 #define BB_TPC_PLUT_SRAM_326_ADDRESS (0xa98 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_326_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_326_RESET 0x0 // 0xa9c (BB_TPC_PLUT_SRAM_327) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_327_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_327_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_327_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_327_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_327_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_327_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_327_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_327_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_327_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_327_RESET 0x0 #define BB_TPC_PLUT_SRAM_327_ADDRESS (0xa9c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_327_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_327_RESET 0x0 // 0xaa0 (BB_TPC_PLUT_SRAM_328) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_328_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_328_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_328_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_328_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_328_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_328_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_328_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_328_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_328_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_328_RESET 0x0 #define BB_TPC_PLUT_SRAM_328_ADDRESS (0xaa0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_328_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_328_RESET 0x0 // 0xaa4 (BB_TPC_PLUT_SRAM_329) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_329_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_329_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_329_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_329_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_329_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_329_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_329_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_329_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_329_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_329_RESET 0x0 #define BB_TPC_PLUT_SRAM_329_ADDRESS (0xaa4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_329_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_329_RESET 0x0 // 0xaa8 (BB_TPC_PLUT_SRAM_330) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_330_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_330_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_330_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_330_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_330_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_330_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_330_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_330_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_330_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_330_RESET 0x0 #define BB_TPC_PLUT_SRAM_330_ADDRESS (0xaa8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_330_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_330_RESET 0x0 // 0xaac (BB_TPC_PLUT_SRAM_331) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_331_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_331_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_331_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_331_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_331_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_331_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_331_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_331_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_331_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_331_RESET 0x0 #define BB_TPC_PLUT_SRAM_331_ADDRESS (0xaac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_331_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_331_RESET 0x0 // 0xab0 (BB_TPC_PLUT_SRAM_332) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_332_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_332_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_332_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_332_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_332_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_332_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_332_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_332_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_332_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_332_RESET 0x0 #define BB_TPC_PLUT_SRAM_332_ADDRESS (0xab0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_332_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_332_RESET 0x0 // 0xab4 (BB_TPC_PLUT_SRAM_333) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_333_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_333_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_333_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_333_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_333_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_333_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_333_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_333_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_333_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_333_RESET 0x0 #define BB_TPC_PLUT_SRAM_333_ADDRESS (0xab4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_333_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_333_RESET 0x0 // 0xab8 (BB_TPC_PLUT_SRAM_334) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_334_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_334_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_334_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_334_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_334_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_334_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_334_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_334_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_334_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_334_RESET 0x0 #define BB_TPC_PLUT_SRAM_334_ADDRESS (0xab8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_334_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_334_RESET 0x0 // 0xabc (BB_TPC_PLUT_SRAM_335) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_335_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_335_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_335_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_335_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_335_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_335_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_335_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_335_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_335_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_335_RESET 0x0 #define BB_TPC_PLUT_SRAM_335_ADDRESS (0xabc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_335_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_335_RESET 0x0 // 0xac0 (BB_TPC_PLUT_SRAM_336) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_336_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_336_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_336_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_336_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_336_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_336_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_336_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_336_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_336_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_336_RESET 0x0 #define BB_TPC_PLUT_SRAM_336_ADDRESS (0xac0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_336_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_336_RESET 0x0 // 0xac4 (BB_TPC_PLUT_SRAM_337) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_337_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_337_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_337_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_337_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_337_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_337_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_337_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_337_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_337_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_337_RESET 0x0 #define BB_TPC_PLUT_SRAM_337_ADDRESS (0xac4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_337_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_337_RESET 0x0 // 0xac8 (BB_TPC_PLUT_SRAM_338) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_338_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_338_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_338_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_338_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_338_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_338_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_338_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_338_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_338_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_338_RESET 0x0 #define BB_TPC_PLUT_SRAM_338_ADDRESS (0xac8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_338_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_338_RESET 0x0 // 0xacc (BB_TPC_PLUT_SRAM_339) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_339_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_339_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_339_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_339_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_339_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_339_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_339_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_339_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_339_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_339_RESET 0x0 #define BB_TPC_PLUT_SRAM_339_ADDRESS (0xacc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_339_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_339_RESET 0x0 // 0xad0 (BB_TPC_PLUT_SRAM_340) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_340_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_340_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_340_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_340_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_340_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_340_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_340_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_340_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_340_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_340_RESET 0x0 #define BB_TPC_PLUT_SRAM_340_ADDRESS (0xad0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_340_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_340_RESET 0x0 // 0xad4 (BB_TPC_PLUT_SRAM_341) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_341_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_341_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_341_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_341_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_341_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_341_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_341_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_341_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_341_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_341_RESET 0x0 #define BB_TPC_PLUT_SRAM_341_ADDRESS (0xad4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_341_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_341_RESET 0x0 // 0xad8 (BB_TPC_PLUT_SRAM_342) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_342_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_342_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_342_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_342_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_342_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_342_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_342_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_342_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_342_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_342_RESET 0x0 #define BB_TPC_PLUT_SRAM_342_ADDRESS (0xad8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_342_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_342_RESET 0x0 // 0xadc (BB_TPC_PLUT_SRAM_343) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_343_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_343_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_343_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_343_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_343_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_343_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_343_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_343_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_343_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_343_RESET 0x0 #define BB_TPC_PLUT_SRAM_343_ADDRESS (0xadc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_343_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_343_RESET 0x0 // 0xae0 (BB_TPC_PLUT_SRAM_344) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_344_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_344_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_344_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_344_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_344_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_344_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_344_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_344_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_344_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_344_RESET 0x0 #define BB_TPC_PLUT_SRAM_344_ADDRESS (0xae0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_344_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_344_RESET 0x0 // 0xae4 (BB_TPC_PLUT_SRAM_345) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_345_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_345_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_345_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_345_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_345_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_345_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_345_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_345_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_345_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_345_RESET 0x0 #define BB_TPC_PLUT_SRAM_345_ADDRESS (0xae4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_345_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_345_RESET 0x0 // 0xae8 (BB_TPC_PLUT_SRAM_346) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_346_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_346_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_346_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_346_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_346_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_346_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_346_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_346_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_346_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_346_RESET 0x0 #define BB_TPC_PLUT_SRAM_346_ADDRESS (0xae8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_346_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_346_RESET 0x0 // 0xaec (BB_TPC_PLUT_SRAM_347) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_347_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_347_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_347_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_347_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_347_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_347_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_347_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_347_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_347_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_347_RESET 0x0 #define BB_TPC_PLUT_SRAM_347_ADDRESS (0xaec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_347_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_347_RESET 0x0 // 0xaf0 (BB_TPC_PLUT_SRAM_348) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_348_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_348_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_348_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_348_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_348_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_348_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_348_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_348_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_348_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_348_RESET 0x0 #define BB_TPC_PLUT_SRAM_348_ADDRESS (0xaf0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_348_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_348_RESET 0x0 // 0xaf4 (BB_TPC_PLUT_SRAM_349) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_349_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_349_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_349_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_349_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_349_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_349_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_349_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_349_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_349_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_349_RESET 0x0 #define BB_TPC_PLUT_SRAM_349_ADDRESS (0xaf4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_349_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_349_RESET 0x0 // 0xaf8 (BB_TPC_PLUT_SRAM_350) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_350_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_350_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_350_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_350_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_350_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_350_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_350_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_350_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_350_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_350_RESET 0x0 #define BB_TPC_PLUT_SRAM_350_ADDRESS (0xaf8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_350_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_350_RESET 0x0 // 0xafc (BB_TPC_PLUT_SRAM_351) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_351_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_351_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_351_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_351_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_351_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_351_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_351_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_351_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_351_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_351_RESET 0x0 #define BB_TPC_PLUT_SRAM_351_ADDRESS (0xafc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_351_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_351_RESET 0x0 // 0xb00 (BB_TPC_PLUT_SRAM_352) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_352_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_352_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_352_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_352_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_352_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_352_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_352_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_352_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_352_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_352_RESET 0x0 #define BB_TPC_PLUT_SRAM_352_ADDRESS (0xb00 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_352_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_352_RESET 0x0 // 0xb04 (BB_TPC_PLUT_SRAM_353) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_353_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_353_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_353_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_353_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_353_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_353_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_353_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_353_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_353_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_353_RESET 0x0 #define BB_TPC_PLUT_SRAM_353_ADDRESS (0xb04 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_353_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_353_RESET 0x0 // 0xb08 (BB_TPC_PLUT_SRAM_354) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_354_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_354_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_354_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_354_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_354_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_354_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_354_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_354_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_354_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_354_RESET 0x0 #define BB_TPC_PLUT_SRAM_354_ADDRESS (0xb08 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_354_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_354_RESET 0x0 // 0xb0c (BB_TPC_PLUT_SRAM_355) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_355_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_355_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_355_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_355_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_355_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_355_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_355_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_355_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_355_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_355_RESET 0x0 #define BB_TPC_PLUT_SRAM_355_ADDRESS (0xb0c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_355_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_355_RESET 0x0 // 0xb10 (BB_TPC_PLUT_SRAM_356) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_356_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_356_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_356_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_356_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_356_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_356_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_356_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_356_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_356_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_356_RESET 0x0 #define BB_TPC_PLUT_SRAM_356_ADDRESS (0xb10 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_356_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_356_RESET 0x0 // 0xb14 (BB_TPC_PLUT_SRAM_357) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_357_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_357_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_357_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_357_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_357_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_357_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_357_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_357_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_357_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_357_RESET 0x0 #define BB_TPC_PLUT_SRAM_357_ADDRESS (0xb14 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_357_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_357_RESET 0x0 // 0xb18 (BB_TPC_PLUT_SRAM_358) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_358_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_358_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_358_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_358_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_358_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_358_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_358_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_358_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_358_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_358_RESET 0x0 #define BB_TPC_PLUT_SRAM_358_ADDRESS (0xb18 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_358_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_358_RESET 0x0 // 0xb1c (BB_TPC_PLUT_SRAM_359) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_359_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_359_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_359_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_359_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_359_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_359_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_359_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_359_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_359_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_359_RESET 0x0 #define BB_TPC_PLUT_SRAM_359_ADDRESS (0xb1c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_359_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_359_RESET 0x0 // 0xb20 (BB_TPC_PLUT_SRAM_360) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_360_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_360_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_360_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_360_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_360_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_360_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_360_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_360_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_360_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_360_RESET 0x0 #define BB_TPC_PLUT_SRAM_360_ADDRESS (0xb20 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_360_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_360_RESET 0x0 // 0xb24 (BB_TPC_PLUT_SRAM_361) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_361_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_361_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_361_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_361_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_361_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_361_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_361_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_361_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_361_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_361_RESET 0x0 #define BB_TPC_PLUT_SRAM_361_ADDRESS (0xb24 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_361_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_361_RESET 0x0 // 0xb28 (BB_TPC_PLUT_SRAM_362) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_362_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_362_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_362_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_362_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_362_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_362_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_362_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_362_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_362_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_362_RESET 0x0 #define BB_TPC_PLUT_SRAM_362_ADDRESS (0xb28 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_362_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_362_RESET 0x0 // 0xb2c (BB_TPC_PLUT_SRAM_363) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_363_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_363_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_363_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_363_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_363_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_363_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_363_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_363_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_363_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_363_RESET 0x0 #define BB_TPC_PLUT_SRAM_363_ADDRESS (0xb2c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_363_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_363_RESET 0x0 // 0xb30 (BB_TPC_PLUT_SRAM_364) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_364_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_364_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_364_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_364_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_364_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_364_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_364_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_364_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_364_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_364_RESET 0x0 #define BB_TPC_PLUT_SRAM_364_ADDRESS (0xb30 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_364_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_364_RESET 0x0 // 0xb34 (BB_TPC_PLUT_SRAM_365) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_365_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_365_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_365_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_365_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_365_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_365_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_365_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_365_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_365_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_365_RESET 0x0 #define BB_TPC_PLUT_SRAM_365_ADDRESS (0xb34 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_365_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_365_RESET 0x0 // 0xb38 (BB_TPC_PLUT_SRAM_366) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_366_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_366_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_366_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_366_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_366_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_366_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_366_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_366_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_366_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_366_RESET 0x0 #define BB_TPC_PLUT_SRAM_366_ADDRESS (0xb38 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_366_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_366_RESET 0x0 // 0xb3c (BB_TPC_PLUT_SRAM_367) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_367_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_367_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_367_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_367_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_367_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_367_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_367_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_367_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_367_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_367_RESET 0x0 #define BB_TPC_PLUT_SRAM_367_ADDRESS (0xb3c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_367_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_367_RESET 0x0 // 0xb40 (BB_TPC_PLUT_SRAM_368) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_368_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_368_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_368_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_368_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_368_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_368_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_368_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_368_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_368_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_368_RESET 0x0 #define BB_TPC_PLUT_SRAM_368_ADDRESS (0xb40 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_368_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_368_RESET 0x0 // 0xb44 (BB_TPC_PLUT_SRAM_369) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_369_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_369_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_369_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_369_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_369_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_369_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_369_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_369_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_369_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_369_RESET 0x0 #define BB_TPC_PLUT_SRAM_369_ADDRESS (0xb44 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_369_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_369_RESET 0x0 // 0xb48 (BB_TPC_PLUT_SRAM_370) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_370_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_370_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_370_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_370_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_370_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_370_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_370_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_370_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_370_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_370_RESET 0x0 #define BB_TPC_PLUT_SRAM_370_ADDRESS (0xb48 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_370_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_370_RESET 0x0 // 0xb4c (BB_TPC_PLUT_SRAM_371) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_371_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_371_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_371_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_371_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_371_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_371_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_371_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_371_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_371_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_371_RESET 0x0 #define BB_TPC_PLUT_SRAM_371_ADDRESS (0xb4c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_371_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_371_RESET 0x0 // 0xb50 (BB_TPC_PLUT_SRAM_372) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_372_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_372_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_372_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_372_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_372_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_372_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_372_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_372_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_372_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_372_RESET 0x0 #define BB_TPC_PLUT_SRAM_372_ADDRESS (0xb50 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_372_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_372_RESET 0x0 // 0xb54 (BB_TPC_PLUT_SRAM_373) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_373_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_373_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_373_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_373_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_373_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_373_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_373_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_373_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_373_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_373_RESET 0x0 #define BB_TPC_PLUT_SRAM_373_ADDRESS (0xb54 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_373_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_373_RESET 0x0 // 0xb58 (BB_TPC_PLUT_SRAM_374) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_374_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_374_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_374_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_374_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_374_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_374_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_374_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_374_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_374_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_374_RESET 0x0 #define BB_TPC_PLUT_SRAM_374_ADDRESS (0xb58 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_374_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_374_RESET 0x0 // 0xb5c (BB_TPC_PLUT_SRAM_375) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_375_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_375_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_375_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_375_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_375_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_375_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_375_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_375_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_375_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_375_RESET 0x0 #define BB_TPC_PLUT_SRAM_375_ADDRESS (0xb5c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_375_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_375_RESET 0x0 // 0xb60 (BB_TPC_PLUT_SRAM_376) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_376_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_376_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_376_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_376_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_376_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_376_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_376_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_376_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_376_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_376_RESET 0x0 #define BB_TPC_PLUT_SRAM_376_ADDRESS (0xb60 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_376_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_376_RESET 0x0 // 0xb64 (BB_TPC_PLUT_SRAM_377) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_377_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_377_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_377_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_377_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_377_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_377_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_377_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_377_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_377_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_377_RESET 0x0 #define BB_TPC_PLUT_SRAM_377_ADDRESS (0xb64 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_377_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_377_RESET 0x0 // 0xb68 (BB_TPC_PLUT_SRAM_378) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_378_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_378_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_378_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_378_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_378_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_378_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_378_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_378_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_378_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_378_RESET 0x0 #define BB_TPC_PLUT_SRAM_378_ADDRESS (0xb68 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_378_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_378_RESET 0x0 // 0xb6c (BB_TPC_PLUT_SRAM_379) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_379_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_379_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_379_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_379_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_379_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_379_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_379_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_379_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_379_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_379_RESET 0x0 #define BB_TPC_PLUT_SRAM_379_ADDRESS (0xb6c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_379_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_379_RESET 0x0 // 0xb70 (BB_TPC_PLUT_SRAM_380) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_380_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_380_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_380_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_380_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_380_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_380_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_380_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_380_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_380_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_380_RESET 0x0 #define BB_TPC_PLUT_SRAM_380_ADDRESS (0xb70 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_380_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_380_RESET 0x0 // 0xb74 (BB_TPC_PLUT_SRAM_381) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_381_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_381_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_381_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_381_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_381_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_381_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_381_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_381_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_381_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_381_RESET 0x0 #define BB_TPC_PLUT_SRAM_381_ADDRESS (0xb74 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_381_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_381_RESET 0x0 // 0xb78 (BB_TPC_PLUT_SRAM_382) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_382_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_382_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_382_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_382_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_382_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_382_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_382_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_382_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_382_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_382_RESET 0x0 #define BB_TPC_PLUT_SRAM_382_ADDRESS (0xb78 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_382_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_382_RESET 0x0 // 0xb7c (BB_TPC_PLUT_SRAM_383) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_383_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_383_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_383_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_383_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_383_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_383_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_383_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_383_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_383_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_383_RESET 0x0 #define BB_TPC_PLUT_SRAM_383_ADDRESS (0xb7c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_383_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_383_RESET 0x0 // 0xb80 (BB_TPC_PLUT_SRAM_384) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_384_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_384_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_384_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_384_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_384_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_384_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_384_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_384_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_384_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_384_RESET 0x0 #define BB_TPC_PLUT_SRAM_384_ADDRESS (0xb80 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_384_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_384_RESET 0x0 // 0xb84 (BB_TPC_PLUT_SRAM_385) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_385_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_385_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_385_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_385_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_385_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_385_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_385_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_385_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_385_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_385_RESET 0x0 #define BB_TPC_PLUT_SRAM_385_ADDRESS (0xb84 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_385_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_385_RESET 0x0 // 0xb88 (BB_TPC_PLUT_SRAM_386) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_386_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_386_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_386_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_386_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_386_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_386_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_386_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_386_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_386_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_386_RESET 0x0 #define BB_TPC_PLUT_SRAM_386_ADDRESS (0xb88 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_386_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_386_RESET 0x0 // 0xb8c (BB_TPC_PLUT_SRAM_387) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_387_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_387_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_387_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_387_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_387_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_387_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_387_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_387_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_387_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_387_RESET 0x0 #define BB_TPC_PLUT_SRAM_387_ADDRESS (0xb8c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_387_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_387_RESET 0x0 // 0xb90 (BB_TPC_PLUT_SRAM_388) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_388_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_388_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_388_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_388_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_388_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_388_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_388_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_388_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_388_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_388_RESET 0x0 #define BB_TPC_PLUT_SRAM_388_ADDRESS (0xb90 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_388_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_388_RESET 0x0 // 0xb94 (BB_TPC_PLUT_SRAM_389) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_389_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_389_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_389_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_389_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_389_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_389_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_389_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_389_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_389_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_389_RESET 0x0 #define BB_TPC_PLUT_SRAM_389_ADDRESS (0xb94 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_389_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_389_RESET 0x0 // 0xb98 (BB_TPC_PLUT_SRAM_390) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_390_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_390_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_390_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_390_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_390_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_390_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_390_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_390_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_390_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_390_RESET 0x0 #define BB_TPC_PLUT_SRAM_390_ADDRESS (0xb98 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_390_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_390_RESET 0x0 // 0xb9c (BB_TPC_PLUT_SRAM_391) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_391_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_391_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_391_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_391_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_391_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_391_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_391_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_391_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_391_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_391_RESET 0x0 #define BB_TPC_PLUT_SRAM_391_ADDRESS (0xb9c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_391_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_391_RESET 0x0 // 0xba0 (BB_TPC_PLUT_SRAM_392) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_392_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_392_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_392_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_392_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_392_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_392_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_392_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_392_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_392_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_392_RESET 0x0 #define BB_TPC_PLUT_SRAM_392_ADDRESS (0xba0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_392_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_392_RESET 0x0 // 0xba4 (BB_TPC_PLUT_SRAM_393) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_393_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_393_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_393_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_393_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_393_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_393_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_393_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_393_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_393_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_393_RESET 0x0 #define BB_TPC_PLUT_SRAM_393_ADDRESS (0xba4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_393_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_393_RESET 0x0 // 0xba8 (BB_TPC_PLUT_SRAM_394) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_394_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_394_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_394_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_394_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_394_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_394_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_394_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_394_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_394_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_394_RESET 0x0 #define BB_TPC_PLUT_SRAM_394_ADDRESS (0xba8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_394_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_394_RESET 0x0 // 0xbac (BB_TPC_PLUT_SRAM_395) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_395_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_395_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_395_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_395_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_395_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_395_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_395_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_395_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_395_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_395_RESET 0x0 #define BB_TPC_PLUT_SRAM_395_ADDRESS (0xbac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_395_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_395_RESET 0x0 // 0xbb0 (BB_TPC_PLUT_SRAM_396) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_396_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_396_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_396_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_396_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_396_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_396_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_396_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_396_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_396_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_396_RESET 0x0 #define BB_TPC_PLUT_SRAM_396_ADDRESS (0xbb0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_396_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_396_RESET 0x0 // 0xbb4 (BB_TPC_PLUT_SRAM_397) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_397_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_397_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_397_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_397_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_397_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_397_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_397_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_397_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_397_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_397_RESET 0x0 #define BB_TPC_PLUT_SRAM_397_ADDRESS (0xbb4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_397_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_397_RESET 0x0 // 0xbb8 (BB_TPC_PLUT_SRAM_398) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_398_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_398_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_398_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_398_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_398_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_398_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_398_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_398_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_398_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_398_RESET 0x0 #define BB_TPC_PLUT_SRAM_398_ADDRESS (0xbb8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_398_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_398_RESET 0x0 // 0xbbc (BB_TPC_PLUT_SRAM_399) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_399_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_399_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_399_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_399_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_399_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_399_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_399_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_399_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_399_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_399_RESET 0x0 #define BB_TPC_PLUT_SRAM_399_ADDRESS (0xbbc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_399_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_399_RESET 0x0 // 0xbc0 (BB_TPC_PLUT_SRAM_400) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_400_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_400_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_400_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_400_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_400_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_400_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_400_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_400_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_400_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_400_RESET 0x0 #define BB_TPC_PLUT_SRAM_400_ADDRESS (0xbc0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_400_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_400_RESET 0x0 // 0xbc4 (BB_TPC_PLUT_SRAM_401) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_401_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_401_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_401_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_401_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_401_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_401_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_401_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_401_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_401_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_401_RESET 0x0 #define BB_TPC_PLUT_SRAM_401_ADDRESS (0xbc4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_401_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_401_RESET 0x0 // 0xbc8 (BB_TPC_PLUT_SRAM_402) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_402_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_402_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_402_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_402_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_402_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_402_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_402_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_402_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_402_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_402_RESET 0x0 #define BB_TPC_PLUT_SRAM_402_ADDRESS (0xbc8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_402_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_402_RESET 0x0 // 0xbcc (BB_TPC_PLUT_SRAM_403) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_403_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_403_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_403_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_403_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_403_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_403_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_403_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_403_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_403_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_403_RESET 0x0 #define BB_TPC_PLUT_SRAM_403_ADDRESS (0xbcc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_403_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_403_RESET 0x0 // 0xbd0 (BB_TPC_PLUT_SRAM_404) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_404_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_404_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_404_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_404_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_404_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_404_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_404_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_404_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_404_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_404_RESET 0x0 #define BB_TPC_PLUT_SRAM_404_ADDRESS (0xbd0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_404_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_404_RESET 0x0 // 0xbd4 (BB_TPC_PLUT_SRAM_405) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_405_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_405_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_405_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_405_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_405_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_405_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_405_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_405_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_405_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_405_RESET 0x0 #define BB_TPC_PLUT_SRAM_405_ADDRESS (0xbd4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_405_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_405_RESET 0x0 // 0xbd8 (BB_TPC_PLUT_SRAM_406) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_406_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_406_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_406_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_406_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_406_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_406_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_406_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_406_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_406_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_406_RESET 0x0 #define BB_TPC_PLUT_SRAM_406_ADDRESS (0xbd8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_406_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_406_RESET 0x0 // 0xbdc (BB_TPC_PLUT_SRAM_407) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_407_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_407_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_407_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_407_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_407_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_407_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_407_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_407_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_407_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_407_RESET 0x0 #define BB_TPC_PLUT_SRAM_407_ADDRESS (0xbdc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_407_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_407_RESET 0x0 // 0xbe0 (BB_TPC_PLUT_SRAM_408) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_408_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_408_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_408_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_408_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_408_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_408_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_408_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_408_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_408_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_408_RESET 0x0 #define BB_TPC_PLUT_SRAM_408_ADDRESS (0xbe0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_408_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_408_RESET 0x0 // 0xbe4 (BB_TPC_PLUT_SRAM_409) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_409_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_409_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_409_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_409_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_409_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_409_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_409_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_409_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_409_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_409_RESET 0x0 #define BB_TPC_PLUT_SRAM_409_ADDRESS (0xbe4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_409_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_409_RESET 0x0 // 0xbe8 (BB_TPC_PLUT_SRAM_410) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_410_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_410_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_410_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_410_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_410_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_410_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_410_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_410_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_410_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_410_RESET 0x0 #define BB_TPC_PLUT_SRAM_410_ADDRESS (0xbe8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_410_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_410_RESET 0x0 // 0xbec (BB_TPC_PLUT_SRAM_411) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_411_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_411_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_411_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_411_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_411_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_411_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_411_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_411_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_411_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_411_RESET 0x0 #define BB_TPC_PLUT_SRAM_411_ADDRESS (0xbec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_411_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_411_RESET 0x0 // 0xbf0 (BB_TPC_PLUT_SRAM_412) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_412_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_412_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_412_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_412_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_412_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_412_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_412_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_412_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_412_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_412_RESET 0x0 #define BB_TPC_PLUT_SRAM_412_ADDRESS (0xbf0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_412_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_412_RESET 0x0 // 0xbf4 (BB_TPC_PLUT_SRAM_413) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_413_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_413_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_413_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_413_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_413_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_413_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_413_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_413_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_413_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_413_RESET 0x0 #define BB_TPC_PLUT_SRAM_413_ADDRESS (0xbf4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_413_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_413_RESET 0x0 // 0xbf8 (BB_TPC_PLUT_SRAM_414) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_414_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_414_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_414_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_414_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_414_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_414_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_414_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_414_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_414_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_414_RESET 0x0 #define BB_TPC_PLUT_SRAM_414_ADDRESS (0xbf8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_414_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_414_RESET 0x0 // 0xbfc (BB_TPC_PLUT_SRAM_415) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_415_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_415_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_415_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_415_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_415_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_415_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_415_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_415_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_415_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_415_RESET 0x0 #define BB_TPC_PLUT_SRAM_415_ADDRESS (0xbfc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_415_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_415_RESET 0x0 // 0xc00 (BB_TPC_PLUT_SRAM_416) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_416_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_416_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_416_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_416_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_416_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_416_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_416_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_416_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_416_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_416_RESET 0x0 #define BB_TPC_PLUT_SRAM_416_ADDRESS (0xc00 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_416_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_416_RESET 0x0 // 0xc04 (BB_TPC_PLUT_SRAM_417) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_417_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_417_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_417_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_417_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_417_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_417_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_417_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_417_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_417_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_417_RESET 0x0 #define BB_TPC_PLUT_SRAM_417_ADDRESS (0xc04 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_417_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_417_RESET 0x0 // 0xc08 (BB_TPC_PLUT_SRAM_418) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_418_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_418_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_418_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_418_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_418_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_418_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_418_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_418_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_418_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_418_RESET 0x0 #define BB_TPC_PLUT_SRAM_418_ADDRESS (0xc08 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_418_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_418_RESET 0x0 // 0xc0c (BB_TPC_PLUT_SRAM_419) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_419_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_419_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_419_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_419_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_419_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_419_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_419_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_419_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_419_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_419_RESET 0x0 #define BB_TPC_PLUT_SRAM_419_ADDRESS (0xc0c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_419_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_419_RESET 0x0 // 0xc10 (BB_TPC_PLUT_SRAM_420) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_420_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_420_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_420_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_420_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_420_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_420_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_420_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_420_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_420_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_420_RESET 0x0 #define BB_TPC_PLUT_SRAM_420_ADDRESS (0xc10 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_420_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_420_RESET 0x0 // 0xc14 (BB_TPC_PLUT_SRAM_421) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_421_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_421_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_421_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_421_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_421_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_421_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_421_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_421_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_421_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_421_RESET 0x0 #define BB_TPC_PLUT_SRAM_421_ADDRESS (0xc14 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_421_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_421_RESET 0x0 // 0xc18 (BB_TPC_PLUT_SRAM_422) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_422_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_422_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_422_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_422_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_422_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_422_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_422_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_422_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_422_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_422_RESET 0x0 #define BB_TPC_PLUT_SRAM_422_ADDRESS (0xc18 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_422_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_422_RESET 0x0 // 0xc1c (BB_TPC_PLUT_SRAM_423) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_423_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_423_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_423_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_423_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_423_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_423_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_423_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_423_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_423_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_423_RESET 0x0 #define BB_TPC_PLUT_SRAM_423_ADDRESS (0xc1c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_423_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_423_RESET 0x0 // 0xc20 (BB_TPC_PLUT_SRAM_424) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_424_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_424_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_424_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_424_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_424_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_424_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_424_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_424_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_424_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_424_RESET 0x0 #define BB_TPC_PLUT_SRAM_424_ADDRESS (0xc20 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_424_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_424_RESET 0x0 // 0xc24 (BB_TPC_PLUT_SRAM_425) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_425_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_425_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_425_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_425_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_425_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_425_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_425_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_425_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_425_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_425_RESET 0x0 #define BB_TPC_PLUT_SRAM_425_ADDRESS (0xc24 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_425_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_425_RESET 0x0 // 0xc28 (BB_TPC_PLUT_SRAM_426) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_426_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_426_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_426_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_426_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_426_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_426_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_426_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_426_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_426_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_426_RESET 0x0 #define BB_TPC_PLUT_SRAM_426_ADDRESS (0xc28 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_426_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_426_RESET 0x0 // 0xc2c (BB_TPC_PLUT_SRAM_427) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_427_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_427_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_427_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_427_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_427_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_427_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_427_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_427_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_427_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_427_RESET 0x0 #define BB_TPC_PLUT_SRAM_427_ADDRESS (0xc2c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_427_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_427_RESET 0x0 // 0xc30 (BB_TPC_PLUT_SRAM_428) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_428_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_428_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_428_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_428_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_428_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_428_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_428_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_428_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_428_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_428_RESET 0x0 #define BB_TPC_PLUT_SRAM_428_ADDRESS (0xc30 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_428_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_428_RESET 0x0 // 0xc34 (BB_TPC_PLUT_SRAM_429) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_429_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_429_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_429_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_429_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_429_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_429_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_429_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_429_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_429_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_429_RESET 0x0 #define BB_TPC_PLUT_SRAM_429_ADDRESS (0xc34 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_429_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_429_RESET 0x0 // 0xc38 (BB_TPC_PLUT_SRAM_430) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_430_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_430_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_430_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_430_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_430_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_430_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_430_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_430_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_430_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_430_RESET 0x0 #define BB_TPC_PLUT_SRAM_430_ADDRESS (0xc38 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_430_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_430_RESET 0x0 // 0xc3c (BB_TPC_PLUT_SRAM_431) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_431_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_431_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_431_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_431_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_431_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_431_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_431_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_431_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_431_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_431_RESET 0x0 #define BB_TPC_PLUT_SRAM_431_ADDRESS (0xc3c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_431_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_431_RESET 0x0 // 0xc40 (BB_TPC_PLUT_SRAM_432) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_432_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_432_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_432_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_432_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_432_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_432_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_432_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_432_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_432_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_432_RESET 0x0 #define BB_TPC_PLUT_SRAM_432_ADDRESS (0xc40 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_432_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_432_RESET 0x0 // 0xc44 (BB_TPC_PLUT_SRAM_433) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_433_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_433_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_433_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_433_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_433_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_433_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_433_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_433_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_433_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_433_RESET 0x0 #define BB_TPC_PLUT_SRAM_433_ADDRESS (0xc44 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_433_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_433_RESET 0x0 // 0xc48 (BB_TPC_PLUT_SRAM_434) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_434_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_434_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_434_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_434_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_434_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_434_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_434_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_434_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_434_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_434_RESET 0x0 #define BB_TPC_PLUT_SRAM_434_ADDRESS (0xc48 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_434_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_434_RESET 0x0 // 0xc4c (BB_TPC_PLUT_SRAM_435) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_435_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_435_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_435_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_435_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_435_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_435_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_435_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_435_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_435_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_435_RESET 0x0 #define BB_TPC_PLUT_SRAM_435_ADDRESS (0xc4c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_435_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_435_RESET 0x0 // 0xc50 (BB_TPC_PLUT_SRAM_436) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_436_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_436_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_436_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_436_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_436_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_436_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_436_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_436_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_436_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_436_RESET 0x0 #define BB_TPC_PLUT_SRAM_436_ADDRESS (0xc50 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_436_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_436_RESET 0x0 // 0xc54 (BB_TPC_PLUT_SRAM_437) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_437_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_437_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_437_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_437_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_437_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_437_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_437_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_437_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_437_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_437_RESET 0x0 #define BB_TPC_PLUT_SRAM_437_ADDRESS (0xc54 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_437_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_437_RESET 0x0 // 0xc58 (BB_TPC_PLUT_SRAM_438) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_438_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_438_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_438_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_438_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_438_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_438_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_438_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_438_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_438_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_438_RESET 0x0 #define BB_TPC_PLUT_SRAM_438_ADDRESS (0xc58 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_438_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_438_RESET 0x0 // 0xc5c (BB_TPC_PLUT_SRAM_439) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_439_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_439_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_439_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_439_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_439_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_439_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_439_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_439_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_439_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_439_RESET 0x0 #define BB_TPC_PLUT_SRAM_439_ADDRESS (0xc5c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_439_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_439_RESET 0x0 // 0xc60 (BB_TPC_PLUT_SRAM_440) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_440_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_440_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_440_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_440_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_440_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_440_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_440_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_440_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_440_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_440_RESET 0x0 #define BB_TPC_PLUT_SRAM_440_ADDRESS (0xc60 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_440_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_440_RESET 0x0 // 0xc64 (BB_TPC_PLUT_SRAM_441) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_441_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_441_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_441_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_441_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_441_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_441_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_441_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_441_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_441_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_441_RESET 0x0 #define BB_TPC_PLUT_SRAM_441_ADDRESS (0xc64 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_441_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_441_RESET 0x0 // 0xc68 (BB_TPC_PLUT_SRAM_442) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_442_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_442_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_442_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_442_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_442_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_442_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_442_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_442_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_442_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_442_RESET 0x0 #define BB_TPC_PLUT_SRAM_442_ADDRESS (0xc68 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_442_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_442_RESET 0x0 // 0xc6c (BB_TPC_PLUT_SRAM_443) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_443_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_443_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_443_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_443_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_443_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_443_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_443_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_443_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_443_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_443_RESET 0x0 #define BB_TPC_PLUT_SRAM_443_ADDRESS (0xc6c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_443_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_443_RESET 0x0 // 0xc70 (BB_TPC_PLUT_SRAM_444) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_444_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_444_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_444_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_444_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_444_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_444_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_444_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_444_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_444_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_444_RESET 0x0 #define BB_TPC_PLUT_SRAM_444_ADDRESS (0xc70 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_444_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_444_RESET 0x0 // 0xc74 (BB_TPC_PLUT_SRAM_445) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_445_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_445_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_445_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_445_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_445_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_445_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_445_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_445_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_445_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_445_RESET 0x0 #define BB_TPC_PLUT_SRAM_445_ADDRESS (0xc74 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_445_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_445_RESET 0x0 // 0xc78 (BB_TPC_PLUT_SRAM_446) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_446_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_446_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_446_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_446_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_446_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_446_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_446_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_446_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_446_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_446_RESET 0x0 #define BB_TPC_PLUT_SRAM_446_ADDRESS (0xc78 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_446_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_446_RESET 0x0 // 0xc7c (BB_TPC_PLUT_SRAM_447) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_447_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_447_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_447_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_447_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_447_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_447_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_447_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_447_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_447_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_447_RESET 0x0 #define BB_TPC_PLUT_SRAM_447_ADDRESS (0xc7c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_447_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_447_RESET 0x0 // 0xc80 (BB_TPC_PLUT_SRAM_448) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_448_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_448_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_448_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_448_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_448_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_448_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_448_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_448_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_448_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_448_RESET 0x0 #define BB_TPC_PLUT_SRAM_448_ADDRESS (0xc80 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_448_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_448_RESET 0x0 // 0xc84 (BB_TPC_PLUT_SRAM_449) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_449_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_449_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_449_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_449_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_449_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_449_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_449_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_449_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_449_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_449_RESET 0x0 #define BB_TPC_PLUT_SRAM_449_ADDRESS (0xc84 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_449_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_449_RESET 0x0 // 0xc88 (BB_TPC_PLUT_SRAM_450) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_450_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_450_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_450_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_450_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_450_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_450_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_450_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_450_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_450_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_450_RESET 0x0 #define BB_TPC_PLUT_SRAM_450_ADDRESS (0xc88 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_450_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_450_RESET 0x0 // 0xc8c (BB_TPC_PLUT_SRAM_451) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_451_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_451_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_451_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_451_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_451_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_451_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_451_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_451_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_451_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_451_RESET 0x0 #define BB_TPC_PLUT_SRAM_451_ADDRESS (0xc8c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_451_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_451_RESET 0x0 // 0xc90 (BB_TPC_PLUT_SRAM_452) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_452_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_452_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_452_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_452_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_452_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_452_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_452_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_452_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_452_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_452_RESET 0x0 #define BB_TPC_PLUT_SRAM_452_ADDRESS (0xc90 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_452_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_452_RESET 0x0 // 0xc94 (BB_TPC_PLUT_SRAM_453) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_453_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_453_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_453_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_453_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_453_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_453_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_453_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_453_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_453_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_453_RESET 0x0 #define BB_TPC_PLUT_SRAM_453_ADDRESS (0xc94 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_453_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_453_RESET 0x0 // 0xc98 (BB_TPC_PLUT_SRAM_454) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_454_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_454_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_454_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_454_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_454_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_454_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_454_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_454_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_454_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_454_RESET 0x0 #define BB_TPC_PLUT_SRAM_454_ADDRESS (0xc98 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_454_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_454_RESET 0x0 // 0xc9c (BB_TPC_PLUT_SRAM_455) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_455_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_455_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_455_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_455_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_455_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_455_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_455_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_455_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_455_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_455_RESET 0x0 #define BB_TPC_PLUT_SRAM_455_ADDRESS (0xc9c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_455_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_455_RESET 0x0 // 0xca0 (BB_TPC_PLUT_SRAM_456) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_456_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_456_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_456_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_456_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_456_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_456_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_456_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_456_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_456_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_456_RESET 0x0 #define BB_TPC_PLUT_SRAM_456_ADDRESS (0xca0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_456_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_456_RESET 0x0 // 0xca4 (BB_TPC_PLUT_SRAM_457) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_457_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_457_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_457_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_457_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_457_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_457_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_457_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_457_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_457_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_457_RESET 0x0 #define BB_TPC_PLUT_SRAM_457_ADDRESS (0xca4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_457_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_457_RESET 0x0 // 0xca8 (BB_TPC_PLUT_SRAM_458) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_458_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_458_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_458_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_458_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_458_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_458_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_458_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_458_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_458_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_458_RESET 0x0 #define BB_TPC_PLUT_SRAM_458_ADDRESS (0xca8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_458_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_458_RESET 0x0 // 0xcac (BB_TPC_PLUT_SRAM_459) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_459_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_459_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_459_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_459_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_459_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_459_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_459_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_459_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_459_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_459_RESET 0x0 #define BB_TPC_PLUT_SRAM_459_ADDRESS (0xcac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_459_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_459_RESET 0x0 // 0xcb0 (BB_TPC_PLUT_SRAM_460) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_460_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_460_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_460_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_460_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_460_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_460_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_460_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_460_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_460_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_460_RESET 0x0 #define BB_TPC_PLUT_SRAM_460_ADDRESS (0xcb0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_460_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_460_RESET 0x0 // 0xcb4 (BB_TPC_PLUT_SRAM_461) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_461_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_461_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_461_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_461_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_461_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_461_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_461_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_461_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_461_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_461_RESET 0x0 #define BB_TPC_PLUT_SRAM_461_ADDRESS (0xcb4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_461_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_461_RESET 0x0 // 0xcb8 (BB_TPC_PLUT_SRAM_462) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_462_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_462_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_462_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_462_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_462_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_462_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_462_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_462_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_462_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_462_RESET 0x0 #define BB_TPC_PLUT_SRAM_462_ADDRESS (0xcb8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_462_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_462_RESET 0x0 // 0xcbc (BB_TPC_PLUT_SRAM_463) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_463_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_463_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_463_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_463_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_463_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_463_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_463_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_463_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_463_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_463_RESET 0x0 #define BB_TPC_PLUT_SRAM_463_ADDRESS (0xcbc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_463_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_463_RESET 0x0 // 0xcc0 (BB_TPC_PLUT_SRAM_464) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_464_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_464_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_464_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_464_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_464_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_464_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_464_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_464_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_464_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_464_RESET 0x0 #define BB_TPC_PLUT_SRAM_464_ADDRESS (0xcc0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_464_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_464_RESET 0x0 // 0xcc4 (BB_TPC_PLUT_SRAM_465) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_465_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_465_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_465_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_465_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_465_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_465_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_465_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_465_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_465_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_465_RESET 0x0 #define BB_TPC_PLUT_SRAM_465_ADDRESS (0xcc4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_465_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_465_RESET 0x0 // 0xcc8 (BB_TPC_PLUT_SRAM_466) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_466_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_466_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_466_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_466_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_466_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_466_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_466_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_466_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_466_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_466_RESET 0x0 #define BB_TPC_PLUT_SRAM_466_ADDRESS (0xcc8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_466_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_466_RESET 0x0 // 0xccc (BB_TPC_PLUT_SRAM_467) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_467_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_467_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_467_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_467_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_467_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_467_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_467_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_467_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_467_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_467_RESET 0x0 #define BB_TPC_PLUT_SRAM_467_ADDRESS (0xccc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_467_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_467_RESET 0x0 // 0xcd0 (BB_TPC_PLUT_SRAM_468) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_468_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_468_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_468_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_468_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_468_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_468_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_468_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_468_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_468_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_468_RESET 0x0 #define BB_TPC_PLUT_SRAM_468_ADDRESS (0xcd0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_468_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_468_RESET 0x0 // 0xcd4 (BB_TPC_PLUT_SRAM_469) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_469_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_469_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_469_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_469_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_469_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_469_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_469_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_469_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_469_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_469_RESET 0x0 #define BB_TPC_PLUT_SRAM_469_ADDRESS (0xcd4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_469_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_469_RESET 0x0 // 0xcd8 (BB_TPC_PLUT_SRAM_470) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_470_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_470_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_470_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_470_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_470_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_470_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_470_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_470_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_470_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_470_RESET 0x0 #define BB_TPC_PLUT_SRAM_470_ADDRESS (0xcd8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_470_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_470_RESET 0x0 // 0xcdc (BB_TPC_PLUT_SRAM_471) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_471_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_471_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_471_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_471_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_471_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_471_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_471_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_471_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_471_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_471_RESET 0x0 #define BB_TPC_PLUT_SRAM_471_ADDRESS (0xcdc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_471_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_471_RESET 0x0 // 0xce0 (BB_TPC_PLUT_SRAM_472) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_472_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_472_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_472_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_472_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_472_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_472_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_472_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_472_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_472_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_472_RESET 0x0 #define BB_TPC_PLUT_SRAM_472_ADDRESS (0xce0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_472_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_472_RESET 0x0 // 0xce4 (BB_TPC_PLUT_SRAM_473) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_473_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_473_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_473_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_473_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_473_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_473_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_473_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_473_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_473_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_473_RESET 0x0 #define BB_TPC_PLUT_SRAM_473_ADDRESS (0xce4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_473_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_473_RESET 0x0 // 0xce8 (BB_TPC_PLUT_SRAM_474) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_474_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_474_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_474_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_474_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_474_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_474_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_474_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_474_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_474_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_474_RESET 0x0 #define BB_TPC_PLUT_SRAM_474_ADDRESS (0xce8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_474_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_474_RESET 0x0 // 0xcec (BB_TPC_PLUT_SRAM_475) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_475_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_475_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_475_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_475_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_475_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_475_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_475_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_475_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_475_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_475_RESET 0x0 #define BB_TPC_PLUT_SRAM_475_ADDRESS (0xcec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_475_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_475_RESET 0x0 // 0xcf0 (BB_TPC_PLUT_SRAM_476) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_476_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_476_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_476_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_476_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_476_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_476_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_476_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_476_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_476_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_476_RESET 0x0 #define BB_TPC_PLUT_SRAM_476_ADDRESS (0xcf0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_476_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_476_RESET 0x0 // 0xcf4 (BB_TPC_PLUT_SRAM_477) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_477_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_477_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_477_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_477_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_477_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_477_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_477_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_477_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_477_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_477_RESET 0x0 #define BB_TPC_PLUT_SRAM_477_ADDRESS (0xcf4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_477_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_477_RESET 0x0 // 0xcf8 (BB_TPC_PLUT_SRAM_478) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_478_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_478_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_478_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_478_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_478_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_478_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_478_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_478_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_478_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_478_RESET 0x0 #define BB_TPC_PLUT_SRAM_478_ADDRESS (0xcf8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_478_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_478_RESET 0x0 // 0xcfc (BB_TPC_PLUT_SRAM_479) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_479_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_479_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_479_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_479_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_479_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_479_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_479_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_479_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_479_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_479_RESET 0x0 #define BB_TPC_PLUT_SRAM_479_ADDRESS (0xcfc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_479_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_479_RESET 0x0 // 0xd00 (BB_TPC_PLUT_SRAM_480) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_480_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_480_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_480_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_480_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_480_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_480_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_480_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_480_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_480_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_480_RESET 0x0 #define BB_TPC_PLUT_SRAM_480_ADDRESS (0xd00 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_480_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_480_RESET 0x0 // 0xd04 (BB_TPC_PLUT_SRAM_481) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_481_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_481_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_481_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_481_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_481_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_481_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_481_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_481_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_481_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_481_RESET 0x0 #define BB_TPC_PLUT_SRAM_481_ADDRESS (0xd04 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_481_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_481_RESET 0x0 // 0xd08 (BB_TPC_PLUT_SRAM_482) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_482_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_482_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_482_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_482_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_482_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_482_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_482_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_482_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_482_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_482_RESET 0x0 #define BB_TPC_PLUT_SRAM_482_ADDRESS (0xd08 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_482_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_482_RESET 0x0 // 0xd0c (BB_TPC_PLUT_SRAM_483) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_483_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_483_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_483_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_483_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_483_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_483_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_483_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_483_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_483_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_483_RESET 0x0 #define BB_TPC_PLUT_SRAM_483_ADDRESS (0xd0c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_483_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_483_RESET 0x0 // 0xd10 (BB_TPC_PLUT_SRAM_484) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_484_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_484_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_484_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_484_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_484_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_484_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_484_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_484_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_484_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_484_RESET 0x0 #define BB_TPC_PLUT_SRAM_484_ADDRESS (0xd10 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_484_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_484_RESET 0x0 // 0xd14 (BB_TPC_PLUT_SRAM_485) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_485_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_485_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_485_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_485_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_485_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_485_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_485_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_485_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_485_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_485_RESET 0x0 #define BB_TPC_PLUT_SRAM_485_ADDRESS (0xd14 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_485_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_485_RESET 0x0 // 0xd18 (BB_TPC_PLUT_SRAM_486) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_486_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_486_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_486_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_486_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_486_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_486_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_486_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_486_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_486_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_486_RESET 0x0 #define BB_TPC_PLUT_SRAM_486_ADDRESS (0xd18 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_486_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_486_RESET 0x0 // 0xd1c (BB_TPC_PLUT_SRAM_487) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_487_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_487_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_487_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_487_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_487_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_487_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_487_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_487_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_487_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_487_RESET 0x0 #define BB_TPC_PLUT_SRAM_487_ADDRESS (0xd1c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_487_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_487_RESET 0x0 // 0xd20 (BB_TPC_PLUT_SRAM_488) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_488_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_488_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_488_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_488_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_488_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_488_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_488_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_488_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_488_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_488_RESET 0x0 #define BB_TPC_PLUT_SRAM_488_ADDRESS (0xd20 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_488_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_488_RESET 0x0 // 0xd24 (BB_TPC_PLUT_SRAM_489) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_489_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_489_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_489_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_489_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_489_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_489_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_489_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_489_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_489_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_489_RESET 0x0 #define BB_TPC_PLUT_SRAM_489_ADDRESS (0xd24 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_489_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_489_RESET 0x0 // 0xd28 (BB_TPC_PLUT_SRAM_490) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_490_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_490_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_490_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_490_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_490_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_490_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_490_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_490_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_490_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_490_RESET 0x0 #define BB_TPC_PLUT_SRAM_490_ADDRESS (0xd28 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_490_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_490_RESET 0x0 // 0xd2c (BB_TPC_PLUT_SRAM_491) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_491_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_491_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_491_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_491_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_491_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_491_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_491_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_491_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_491_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_491_RESET 0x0 #define BB_TPC_PLUT_SRAM_491_ADDRESS (0xd2c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_491_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_491_RESET 0x0 // 0xd30 (BB_TPC_PLUT_SRAM_492) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_492_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_492_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_492_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_492_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_492_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_492_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_492_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_492_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_492_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_492_RESET 0x0 #define BB_TPC_PLUT_SRAM_492_ADDRESS (0xd30 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_492_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_492_RESET 0x0 // 0xd34 (BB_TPC_PLUT_SRAM_493) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_493_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_493_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_493_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_493_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_493_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_493_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_493_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_493_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_493_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_493_RESET 0x0 #define BB_TPC_PLUT_SRAM_493_ADDRESS (0xd34 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_493_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_493_RESET 0x0 // 0xd38 (BB_TPC_PLUT_SRAM_494) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_494_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_494_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_494_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_494_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_494_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_494_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_494_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_494_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_494_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_494_RESET 0x0 #define BB_TPC_PLUT_SRAM_494_ADDRESS (0xd38 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_494_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_494_RESET 0x0 // 0xd3c (BB_TPC_PLUT_SRAM_495) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_495_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_495_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_495_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_495_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_495_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_495_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_495_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_495_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_495_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_495_RESET 0x0 #define BB_TPC_PLUT_SRAM_495_ADDRESS (0xd3c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_495_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_495_RESET 0x0 // 0xd40 (BB_TPC_PLUT_SRAM_496) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_496_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_496_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_496_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_496_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_496_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_496_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_496_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_496_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_496_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_496_RESET 0x0 #define BB_TPC_PLUT_SRAM_496_ADDRESS (0xd40 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_496_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_496_RESET 0x0 // 0xd44 (BB_TPC_PLUT_SRAM_497) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_497_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_497_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_497_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_497_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_497_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_497_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_497_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_497_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_497_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_497_RESET 0x0 #define BB_TPC_PLUT_SRAM_497_ADDRESS (0xd44 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_497_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_497_RESET 0x0 // 0xd48 (BB_TPC_PLUT_SRAM_498) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_498_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_498_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_498_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_498_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_498_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_498_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_498_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_498_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_498_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_498_RESET 0x0 #define BB_TPC_PLUT_SRAM_498_ADDRESS (0xd48 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_498_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_498_RESET 0x0 // 0xd4c (BB_TPC_PLUT_SRAM_499) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_499_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_499_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_499_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_499_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_499_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_499_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_499_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_499_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_499_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_499_RESET 0x0 #define BB_TPC_PLUT_SRAM_499_ADDRESS (0xd4c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_499_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_499_RESET 0x0 // 0xd50 (BB_TPC_PLUT_SRAM_500) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_500_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_500_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_500_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_500_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_500_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_500_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_500_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_500_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_500_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_500_RESET 0x0 #define BB_TPC_PLUT_SRAM_500_ADDRESS (0xd50 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_500_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_500_RESET 0x0 // 0xd54 (BB_TPC_PLUT_SRAM_501) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_501_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_501_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_501_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_501_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_501_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_501_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_501_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_501_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_501_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_501_RESET 0x0 #define BB_TPC_PLUT_SRAM_501_ADDRESS (0xd54 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_501_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_501_RESET 0x0 // 0xd58 (BB_TPC_PLUT_SRAM_502) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_502_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_502_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_502_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_502_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_502_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_502_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_502_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_502_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_502_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_502_RESET 0x0 #define BB_TPC_PLUT_SRAM_502_ADDRESS (0xd58 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_502_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_502_RESET 0x0 // 0xd5c (BB_TPC_PLUT_SRAM_503) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_503_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_503_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_503_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_503_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_503_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_503_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_503_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_503_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_503_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_503_RESET 0x0 #define BB_TPC_PLUT_SRAM_503_ADDRESS (0xd5c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_503_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_503_RESET 0x0 // 0xd60 (BB_TPC_PLUT_SRAM_504) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_504_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_504_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_504_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_504_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_504_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_504_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_504_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_504_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_504_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_504_RESET 0x0 #define BB_TPC_PLUT_SRAM_504_ADDRESS (0xd60 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_504_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_504_RESET 0x0 // 0xd64 (BB_TPC_PLUT_SRAM_505) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_505_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_505_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_505_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_505_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_505_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_505_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_505_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_505_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_505_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_505_RESET 0x0 #define BB_TPC_PLUT_SRAM_505_ADDRESS (0xd64 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_505_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_505_RESET 0x0 // 0xd68 (BB_TPC_PLUT_SRAM_506) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_506_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_506_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_506_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_506_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_506_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_506_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_506_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_506_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_506_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_506_RESET 0x0 #define BB_TPC_PLUT_SRAM_506_ADDRESS (0xd68 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_506_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_506_RESET 0x0 // 0xd6c (BB_TPC_PLUT_SRAM_507) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_507_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_507_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_507_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_507_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_507_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_507_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_507_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_507_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_507_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_507_RESET 0x0 #define BB_TPC_PLUT_SRAM_507_ADDRESS (0xd6c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_507_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_507_RESET 0x0 // 0xd70 (BB_TPC_PLUT_SRAM_508) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_508_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_508_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_508_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_508_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_508_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_508_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_508_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_508_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_508_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_508_RESET 0x0 #define BB_TPC_PLUT_SRAM_508_ADDRESS (0xd70 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_508_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_508_RESET 0x0 // 0xd74 (BB_TPC_PLUT_SRAM_509) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_509_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_509_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_509_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_509_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_509_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_509_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_509_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_509_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_509_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_509_RESET 0x0 #define BB_TPC_PLUT_SRAM_509_ADDRESS (0xd74 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_509_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_509_RESET 0x0 // 0xd78 (BB_TPC_PLUT_SRAM_510) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_510_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_510_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_510_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_510_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_510_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_510_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_510_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_510_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_510_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_510_RESET 0x0 #define BB_TPC_PLUT_SRAM_510_ADDRESS (0xd78 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_510_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_510_RESET 0x0 // 0xd7c (BB_TPC_PLUT_SRAM_511) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_511_LSB 0 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_511_MSB 31 #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_511_MASK 0xffffffff #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_511_GET(x) (((x) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_511_MASK) >> BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_511_LSB) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_511_SET(x) (((0 | (x)) << BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_511_LSB) & BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_511_MASK) #define BB_TPC_PLUT_SRAM_TPC_PLUT_WORD_511_RESET 0x0 #define BB_TPC_PLUT_SRAM_511_ADDRESS (0xd7c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_PLUT_SRAM_511_RSTMASK 0xffffffff #define BB_TPC_PLUT_SRAM_511_RESET 0x0 // 0xd80 (BB_TPC_GLUT_SRAM) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_RESET 0x0 #define BB_TPC_GLUT_SRAM_ADDRESS (0xd80 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_RESET 0x0 // 0xd80 (BB_TPC_GLUT_SRAM_0) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_0_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_0_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_0_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_0_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_0_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_0_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_0_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_0_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_0_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_0_RESET 0x0 #define BB_TPC_GLUT_SRAM_0_ADDRESS (0xd80 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_0_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_0_RESET 0x0 // 0xd84 (BB_TPC_GLUT_SRAM_1) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_1_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_1_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_1_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_1_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_1_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_1_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_1_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_1_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_1_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_1_RESET 0x0 #define BB_TPC_GLUT_SRAM_1_ADDRESS (0xd84 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_1_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_1_RESET 0x0 // 0xd88 (BB_TPC_GLUT_SRAM_2) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_2_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_2_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_2_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_2_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_2_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_2_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_2_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_2_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_2_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_2_RESET 0x0 #define BB_TPC_GLUT_SRAM_2_ADDRESS (0xd88 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_2_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_2_RESET 0x0 // 0xd8c (BB_TPC_GLUT_SRAM_3) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_3_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_3_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_3_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_3_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_3_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_3_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_3_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_3_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_3_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_3_RESET 0x0 #define BB_TPC_GLUT_SRAM_3_ADDRESS (0xd8c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_3_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_3_RESET 0x0 // 0xd90 (BB_TPC_GLUT_SRAM_4) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_4_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_4_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_4_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_4_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_4_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_4_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_4_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_4_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_4_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_4_RESET 0x0 #define BB_TPC_GLUT_SRAM_4_ADDRESS (0xd90 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_4_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_4_RESET 0x0 // 0xd94 (BB_TPC_GLUT_SRAM_5) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_5_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_5_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_5_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_5_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_5_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_5_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_5_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_5_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_5_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_5_RESET 0x0 #define BB_TPC_GLUT_SRAM_5_ADDRESS (0xd94 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_5_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_5_RESET 0x0 // 0xd98 (BB_TPC_GLUT_SRAM_6) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_6_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_6_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_6_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_6_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_6_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_6_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_6_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_6_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_6_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_6_RESET 0x0 #define BB_TPC_GLUT_SRAM_6_ADDRESS (0xd98 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_6_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_6_RESET 0x0 // 0xd9c (BB_TPC_GLUT_SRAM_7) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_7_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_7_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_7_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_7_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_7_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_7_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_7_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_7_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_7_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_7_RESET 0x0 #define BB_TPC_GLUT_SRAM_7_ADDRESS (0xd9c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_7_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_7_RESET 0x0 // 0xda0 (BB_TPC_GLUT_SRAM_8) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_8_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_8_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_8_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_8_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_8_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_8_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_8_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_8_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_8_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_8_RESET 0x0 #define BB_TPC_GLUT_SRAM_8_ADDRESS (0xda0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_8_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_8_RESET 0x0 // 0xda4 (BB_TPC_GLUT_SRAM_9) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_9_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_9_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_9_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_9_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_9_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_9_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_9_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_9_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_9_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_9_RESET 0x0 #define BB_TPC_GLUT_SRAM_9_ADDRESS (0xda4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_9_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_9_RESET 0x0 // 0xda8 (BB_TPC_GLUT_SRAM_10) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_10_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_10_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_10_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_10_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_10_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_10_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_10_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_10_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_10_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_10_RESET 0x0 #define BB_TPC_GLUT_SRAM_10_ADDRESS (0xda8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_10_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_10_RESET 0x0 // 0xdac (BB_TPC_GLUT_SRAM_11) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_11_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_11_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_11_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_11_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_11_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_11_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_11_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_11_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_11_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_11_RESET 0x0 #define BB_TPC_GLUT_SRAM_11_ADDRESS (0xdac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_11_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_11_RESET 0x0 // 0xdb0 (BB_TPC_GLUT_SRAM_12) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_12_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_12_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_12_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_12_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_12_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_12_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_12_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_12_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_12_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_12_RESET 0x0 #define BB_TPC_GLUT_SRAM_12_ADDRESS (0xdb0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_12_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_12_RESET 0x0 // 0xdb4 (BB_TPC_GLUT_SRAM_13) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_13_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_13_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_13_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_13_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_13_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_13_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_13_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_13_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_13_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_13_RESET 0x0 #define BB_TPC_GLUT_SRAM_13_ADDRESS (0xdb4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_13_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_13_RESET 0x0 // 0xdb8 (BB_TPC_GLUT_SRAM_14) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_14_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_14_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_14_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_14_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_14_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_14_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_14_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_14_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_14_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_14_RESET 0x0 #define BB_TPC_GLUT_SRAM_14_ADDRESS (0xdb8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_14_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_14_RESET 0x0 // 0xdbc (BB_TPC_GLUT_SRAM_15) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_15_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_15_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_15_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_15_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_15_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_15_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_15_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_15_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_15_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_15_RESET 0x0 #define BB_TPC_GLUT_SRAM_15_ADDRESS (0xdbc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_15_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_15_RESET 0x0 // 0xdc0 (BB_TPC_GLUT_SRAM_16) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_16_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_16_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_16_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_16_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_16_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_16_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_16_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_16_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_16_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_16_RESET 0x0 #define BB_TPC_GLUT_SRAM_16_ADDRESS (0xdc0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_16_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_16_RESET 0x0 // 0xdc4 (BB_TPC_GLUT_SRAM_17) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_17_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_17_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_17_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_17_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_17_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_17_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_17_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_17_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_17_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_17_RESET 0x0 #define BB_TPC_GLUT_SRAM_17_ADDRESS (0xdc4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_17_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_17_RESET 0x0 // 0xdc8 (BB_TPC_GLUT_SRAM_18) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_18_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_18_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_18_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_18_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_18_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_18_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_18_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_18_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_18_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_18_RESET 0x0 #define BB_TPC_GLUT_SRAM_18_ADDRESS (0xdc8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_18_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_18_RESET 0x0 // 0xdcc (BB_TPC_GLUT_SRAM_19) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_19_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_19_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_19_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_19_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_19_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_19_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_19_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_19_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_19_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_19_RESET 0x0 #define BB_TPC_GLUT_SRAM_19_ADDRESS (0xdcc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_19_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_19_RESET 0x0 // 0xdd0 (BB_TPC_GLUT_SRAM_20) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_20_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_20_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_20_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_20_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_20_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_20_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_20_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_20_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_20_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_20_RESET 0x0 #define BB_TPC_GLUT_SRAM_20_ADDRESS (0xdd0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_20_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_20_RESET 0x0 // 0xdd4 (BB_TPC_GLUT_SRAM_21) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_21_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_21_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_21_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_21_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_21_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_21_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_21_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_21_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_21_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_21_RESET 0x0 #define BB_TPC_GLUT_SRAM_21_ADDRESS (0xdd4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_21_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_21_RESET 0x0 // 0xdd8 (BB_TPC_GLUT_SRAM_22) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_22_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_22_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_22_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_22_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_22_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_22_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_22_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_22_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_22_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_22_RESET 0x0 #define BB_TPC_GLUT_SRAM_22_ADDRESS (0xdd8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_22_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_22_RESET 0x0 // 0xddc (BB_TPC_GLUT_SRAM_23) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_23_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_23_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_23_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_23_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_23_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_23_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_23_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_23_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_23_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_23_RESET 0x0 #define BB_TPC_GLUT_SRAM_23_ADDRESS (0xddc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_23_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_23_RESET 0x0 // 0xde0 (BB_TPC_GLUT_SRAM_24) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_24_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_24_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_24_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_24_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_24_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_24_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_24_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_24_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_24_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_24_RESET 0x0 #define BB_TPC_GLUT_SRAM_24_ADDRESS (0xde0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_24_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_24_RESET 0x0 // 0xde4 (BB_TPC_GLUT_SRAM_25) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_25_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_25_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_25_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_25_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_25_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_25_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_25_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_25_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_25_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_25_RESET 0x0 #define BB_TPC_GLUT_SRAM_25_ADDRESS (0xde4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_25_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_25_RESET 0x0 // 0xde8 (BB_TPC_GLUT_SRAM_26) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_26_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_26_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_26_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_26_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_26_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_26_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_26_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_26_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_26_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_26_RESET 0x0 #define BB_TPC_GLUT_SRAM_26_ADDRESS (0xde8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_26_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_26_RESET 0x0 // 0xdec (BB_TPC_GLUT_SRAM_27) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_27_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_27_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_27_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_27_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_27_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_27_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_27_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_27_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_27_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_27_RESET 0x0 #define BB_TPC_GLUT_SRAM_27_ADDRESS (0xdec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_27_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_27_RESET 0x0 // 0xdf0 (BB_TPC_GLUT_SRAM_28) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_28_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_28_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_28_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_28_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_28_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_28_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_28_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_28_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_28_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_28_RESET 0x0 #define BB_TPC_GLUT_SRAM_28_ADDRESS (0xdf0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_28_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_28_RESET 0x0 // 0xdf4 (BB_TPC_GLUT_SRAM_29) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_29_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_29_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_29_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_29_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_29_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_29_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_29_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_29_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_29_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_29_RESET 0x0 #define BB_TPC_GLUT_SRAM_29_ADDRESS (0xdf4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_29_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_29_RESET 0x0 // 0xdf8 (BB_TPC_GLUT_SRAM_30) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_30_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_30_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_30_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_30_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_30_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_30_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_30_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_30_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_30_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_30_RESET 0x0 #define BB_TPC_GLUT_SRAM_30_ADDRESS (0xdf8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_30_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_30_RESET 0x0 // 0xdfc (BB_TPC_GLUT_SRAM_31) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_31_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_31_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_31_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_31_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_31_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_31_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_31_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_31_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_31_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_31_RESET 0x0 #define BB_TPC_GLUT_SRAM_31_ADDRESS (0xdfc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_31_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_31_RESET 0x0 // 0xe00 (BB_TPC_GLUT_SRAM_32) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_32_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_32_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_32_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_32_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_32_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_32_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_32_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_32_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_32_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_32_RESET 0x0 #define BB_TPC_GLUT_SRAM_32_ADDRESS (0xe00 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_32_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_32_RESET 0x0 // 0xe04 (BB_TPC_GLUT_SRAM_33) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_33_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_33_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_33_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_33_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_33_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_33_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_33_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_33_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_33_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_33_RESET 0x0 #define BB_TPC_GLUT_SRAM_33_ADDRESS (0xe04 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_33_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_33_RESET 0x0 // 0xe08 (BB_TPC_GLUT_SRAM_34) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_34_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_34_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_34_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_34_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_34_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_34_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_34_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_34_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_34_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_34_RESET 0x0 #define BB_TPC_GLUT_SRAM_34_ADDRESS (0xe08 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_34_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_34_RESET 0x0 // 0xe0c (BB_TPC_GLUT_SRAM_35) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_35_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_35_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_35_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_35_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_35_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_35_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_35_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_35_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_35_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_35_RESET 0x0 #define BB_TPC_GLUT_SRAM_35_ADDRESS (0xe0c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_35_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_35_RESET 0x0 // 0xe10 (BB_TPC_GLUT_SRAM_36) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_36_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_36_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_36_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_36_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_36_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_36_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_36_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_36_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_36_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_36_RESET 0x0 #define BB_TPC_GLUT_SRAM_36_ADDRESS (0xe10 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_36_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_36_RESET 0x0 // 0xe14 (BB_TPC_GLUT_SRAM_37) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_37_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_37_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_37_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_37_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_37_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_37_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_37_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_37_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_37_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_37_RESET 0x0 #define BB_TPC_GLUT_SRAM_37_ADDRESS (0xe14 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_37_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_37_RESET 0x0 // 0xe18 (BB_TPC_GLUT_SRAM_38) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_38_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_38_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_38_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_38_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_38_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_38_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_38_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_38_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_38_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_38_RESET 0x0 #define BB_TPC_GLUT_SRAM_38_ADDRESS (0xe18 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_38_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_38_RESET 0x0 // 0xe1c (BB_TPC_GLUT_SRAM_39) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_39_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_39_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_39_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_39_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_39_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_39_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_39_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_39_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_39_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_39_RESET 0x0 #define BB_TPC_GLUT_SRAM_39_ADDRESS (0xe1c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_39_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_39_RESET 0x0 // 0xe20 (BB_TPC_GLUT_SRAM_40) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_40_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_40_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_40_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_40_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_40_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_40_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_40_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_40_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_40_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_40_RESET 0x0 #define BB_TPC_GLUT_SRAM_40_ADDRESS (0xe20 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_40_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_40_RESET 0x0 // 0xe24 (BB_TPC_GLUT_SRAM_41) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_41_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_41_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_41_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_41_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_41_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_41_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_41_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_41_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_41_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_41_RESET 0x0 #define BB_TPC_GLUT_SRAM_41_ADDRESS (0xe24 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_41_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_41_RESET 0x0 // 0xe28 (BB_TPC_GLUT_SRAM_42) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_42_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_42_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_42_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_42_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_42_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_42_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_42_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_42_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_42_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_42_RESET 0x0 #define BB_TPC_GLUT_SRAM_42_ADDRESS (0xe28 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_42_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_42_RESET 0x0 // 0xe2c (BB_TPC_GLUT_SRAM_43) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_43_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_43_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_43_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_43_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_43_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_43_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_43_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_43_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_43_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_43_RESET 0x0 #define BB_TPC_GLUT_SRAM_43_ADDRESS (0xe2c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_43_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_43_RESET 0x0 // 0xe30 (BB_TPC_GLUT_SRAM_44) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_44_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_44_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_44_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_44_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_44_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_44_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_44_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_44_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_44_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_44_RESET 0x0 #define BB_TPC_GLUT_SRAM_44_ADDRESS (0xe30 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_44_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_44_RESET 0x0 // 0xe34 (BB_TPC_GLUT_SRAM_45) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_45_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_45_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_45_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_45_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_45_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_45_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_45_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_45_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_45_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_45_RESET 0x0 #define BB_TPC_GLUT_SRAM_45_ADDRESS (0xe34 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_45_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_45_RESET 0x0 // 0xe38 (BB_TPC_GLUT_SRAM_46) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_46_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_46_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_46_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_46_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_46_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_46_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_46_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_46_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_46_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_46_RESET 0x0 #define BB_TPC_GLUT_SRAM_46_ADDRESS (0xe38 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_46_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_46_RESET 0x0 // 0xe3c (BB_TPC_GLUT_SRAM_47) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_47_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_47_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_47_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_47_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_47_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_47_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_47_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_47_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_47_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_47_RESET 0x0 #define BB_TPC_GLUT_SRAM_47_ADDRESS (0xe3c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_47_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_47_RESET 0x0 // 0xe40 (BB_TPC_GLUT_SRAM_48) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_48_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_48_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_48_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_48_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_48_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_48_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_48_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_48_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_48_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_48_RESET 0x0 #define BB_TPC_GLUT_SRAM_48_ADDRESS (0xe40 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_48_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_48_RESET 0x0 // 0xe44 (BB_TPC_GLUT_SRAM_49) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_49_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_49_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_49_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_49_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_49_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_49_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_49_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_49_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_49_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_49_RESET 0x0 #define BB_TPC_GLUT_SRAM_49_ADDRESS (0xe44 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_49_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_49_RESET 0x0 // 0xe48 (BB_TPC_GLUT_SRAM_50) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_50_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_50_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_50_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_50_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_50_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_50_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_50_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_50_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_50_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_50_RESET 0x0 #define BB_TPC_GLUT_SRAM_50_ADDRESS (0xe48 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_50_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_50_RESET 0x0 // 0xe4c (BB_TPC_GLUT_SRAM_51) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_51_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_51_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_51_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_51_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_51_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_51_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_51_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_51_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_51_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_51_RESET 0x0 #define BB_TPC_GLUT_SRAM_51_ADDRESS (0xe4c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_51_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_51_RESET 0x0 // 0xe50 (BB_TPC_GLUT_SRAM_52) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_52_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_52_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_52_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_52_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_52_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_52_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_52_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_52_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_52_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_52_RESET 0x0 #define BB_TPC_GLUT_SRAM_52_ADDRESS (0xe50 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_52_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_52_RESET 0x0 // 0xe54 (BB_TPC_GLUT_SRAM_53) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_53_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_53_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_53_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_53_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_53_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_53_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_53_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_53_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_53_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_53_RESET 0x0 #define BB_TPC_GLUT_SRAM_53_ADDRESS (0xe54 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_53_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_53_RESET 0x0 // 0xe58 (BB_TPC_GLUT_SRAM_54) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_54_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_54_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_54_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_54_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_54_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_54_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_54_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_54_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_54_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_54_RESET 0x0 #define BB_TPC_GLUT_SRAM_54_ADDRESS (0xe58 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_54_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_54_RESET 0x0 // 0xe5c (BB_TPC_GLUT_SRAM_55) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_55_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_55_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_55_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_55_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_55_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_55_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_55_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_55_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_55_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_55_RESET 0x0 #define BB_TPC_GLUT_SRAM_55_ADDRESS (0xe5c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_55_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_55_RESET 0x0 // 0xe60 (BB_TPC_GLUT_SRAM_56) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_56_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_56_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_56_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_56_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_56_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_56_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_56_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_56_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_56_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_56_RESET 0x0 #define BB_TPC_GLUT_SRAM_56_ADDRESS (0xe60 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_56_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_56_RESET 0x0 // 0xe64 (BB_TPC_GLUT_SRAM_57) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_57_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_57_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_57_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_57_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_57_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_57_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_57_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_57_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_57_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_57_RESET 0x0 #define BB_TPC_GLUT_SRAM_57_ADDRESS (0xe64 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_57_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_57_RESET 0x0 // 0xe68 (BB_TPC_GLUT_SRAM_58) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_58_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_58_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_58_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_58_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_58_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_58_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_58_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_58_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_58_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_58_RESET 0x0 #define BB_TPC_GLUT_SRAM_58_ADDRESS (0xe68 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_58_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_58_RESET 0x0 // 0xe6c (BB_TPC_GLUT_SRAM_59) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_59_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_59_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_59_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_59_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_59_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_59_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_59_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_59_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_59_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_59_RESET 0x0 #define BB_TPC_GLUT_SRAM_59_ADDRESS (0xe6c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_59_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_59_RESET 0x0 // 0xe70 (BB_TPC_GLUT_SRAM_60) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_60_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_60_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_60_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_60_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_60_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_60_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_60_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_60_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_60_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_60_RESET 0x0 #define BB_TPC_GLUT_SRAM_60_ADDRESS (0xe70 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_60_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_60_RESET 0x0 // 0xe74 (BB_TPC_GLUT_SRAM_61) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_61_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_61_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_61_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_61_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_61_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_61_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_61_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_61_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_61_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_61_RESET 0x0 #define BB_TPC_GLUT_SRAM_61_ADDRESS (0xe74 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_61_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_61_RESET 0x0 // 0xe78 (BB_TPC_GLUT_SRAM_62) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_62_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_62_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_62_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_62_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_62_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_62_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_62_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_62_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_62_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_62_RESET 0x0 #define BB_TPC_GLUT_SRAM_62_ADDRESS (0xe78 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_62_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_62_RESET 0x0 // 0xe7c (BB_TPC_GLUT_SRAM_63) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_63_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_63_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_63_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_63_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_63_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_63_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_63_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_63_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_63_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_63_RESET 0x0 #define BB_TPC_GLUT_SRAM_63_ADDRESS (0xe7c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_63_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_63_RESET 0x0 // 0xe80 (BB_TPC_GLUT_SRAM_64) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_64_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_64_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_64_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_64_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_64_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_64_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_64_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_64_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_64_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_64_RESET 0x0 #define BB_TPC_GLUT_SRAM_64_ADDRESS (0xe80 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_64_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_64_RESET 0x0 // 0xe84 (BB_TPC_GLUT_SRAM_65) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_65_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_65_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_65_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_65_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_65_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_65_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_65_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_65_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_65_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_65_RESET 0x0 #define BB_TPC_GLUT_SRAM_65_ADDRESS (0xe84 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_65_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_65_RESET 0x0 // 0xe88 (BB_TPC_GLUT_SRAM_66) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_66_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_66_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_66_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_66_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_66_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_66_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_66_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_66_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_66_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_66_RESET 0x0 #define BB_TPC_GLUT_SRAM_66_ADDRESS (0xe88 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_66_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_66_RESET 0x0 // 0xe8c (BB_TPC_GLUT_SRAM_67) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_67_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_67_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_67_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_67_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_67_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_67_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_67_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_67_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_67_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_67_RESET 0x0 #define BB_TPC_GLUT_SRAM_67_ADDRESS (0xe8c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_67_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_67_RESET 0x0 // 0xe90 (BB_TPC_GLUT_SRAM_68) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_68_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_68_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_68_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_68_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_68_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_68_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_68_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_68_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_68_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_68_RESET 0x0 #define BB_TPC_GLUT_SRAM_68_ADDRESS (0xe90 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_68_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_68_RESET 0x0 // 0xe94 (BB_TPC_GLUT_SRAM_69) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_69_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_69_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_69_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_69_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_69_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_69_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_69_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_69_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_69_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_69_RESET 0x0 #define BB_TPC_GLUT_SRAM_69_ADDRESS (0xe94 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_69_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_69_RESET 0x0 // 0xe98 (BB_TPC_GLUT_SRAM_70) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_70_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_70_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_70_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_70_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_70_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_70_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_70_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_70_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_70_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_70_RESET 0x0 #define BB_TPC_GLUT_SRAM_70_ADDRESS (0xe98 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_70_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_70_RESET 0x0 // 0xe9c (BB_TPC_GLUT_SRAM_71) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_71_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_71_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_71_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_71_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_71_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_71_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_71_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_71_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_71_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_71_RESET 0x0 #define BB_TPC_GLUT_SRAM_71_ADDRESS (0xe9c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_71_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_71_RESET 0x0 // 0xea0 (BB_TPC_GLUT_SRAM_72) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_72_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_72_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_72_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_72_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_72_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_72_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_72_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_72_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_72_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_72_RESET 0x0 #define BB_TPC_GLUT_SRAM_72_ADDRESS (0xea0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_72_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_72_RESET 0x0 // 0xea4 (BB_TPC_GLUT_SRAM_73) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_73_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_73_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_73_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_73_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_73_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_73_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_73_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_73_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_73_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_73_RESET 0x0 #define BB_TPC_GLUT_SRAM_73_ADDRESS (0xea4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_73_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_73_RESET 0x0 // 0xea8 (BB_TPC_GLUT_SRAM_74) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_74_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_74_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_74_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_74_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_74_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_74_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_74_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_74_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_74_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_74_RESET 0x0 #define BB_TPC_GLUT_SRAM_74_ADDRESS (0xea8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_74_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_74_RESET 0x0 // 0xeac (BB_TPC_GLUT_SRAM_75) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_75_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_75_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_75_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_75_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_75_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_75_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_75_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_75_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_75_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_75_RESET 0x0 #define BB_TPC_GLUT_SRAM_75_ADDRESS (0xeac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_75_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_75_RESET 0x0 // 0xeb0 (BB_TPC_GLUT_SRAM_76) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_76_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_76_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_76_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_76_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_76_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_76_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_76_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_76_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_76_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_76_RESET 0x0 #define BB_TPC_GLUT_SRAM_76_ADDRESS (0xeb0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_76_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_76_RESET 0x0 // 0xeb4 (BB_TPC_GLUT_SRAM_77) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_77_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_77_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_77_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_77_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_77_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_77_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_77_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_77_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_77_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_77_RESET 0x0 #define BB_TPC_GLUT_SRAM_77_ADDRESS (0xeb4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_77_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_77_RESET 0x0 // 0xeb8 (BB_TPC_GLUT_SRAM_78) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_78_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_78_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_78_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_78_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_78_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_78_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_78_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_78_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_78_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_78_RESET 0x0 #define BB_TPC_GLUT_SRAM_78_ADDRESS (0xeb8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_78_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_78_RESET 0x0 // 0xebc (BB_TPC_GLUT_SRAM_79) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_79_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_79_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_79_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_79_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_79_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_79_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_79_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_79_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_79_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_79_RESET 0x0 #define BB_TPC_GLUT_SRAM_79_ADDRESS (0xebc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_79_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_79_RESET 0x0 // 0xec0 (BB_TPC_GLUT_SRAM_80) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_80_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_80_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_80_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_80_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_80_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_80_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_80_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_80_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_80_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_80_RESET 0x0 #define BB_TPC_GLUT_SRAM_80_ADDRESS (0xec0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_80_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_80_RESET 0x0 // 0xec4 (BB_TPC_GLUT_SRAM_81) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_81_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_81_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_81_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_81_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_81_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_81_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_81_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_81_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_81_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_81_RESET 0x0 #define BB_TPC_GLUT_SRAM_81_ADDRESS (0xec4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_81_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_81_RESET 0x0 // 0xec8 (BB_TPC_GLUT_SRAM_82) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_82_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_82_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_82_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_82_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_82_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_82_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_82_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_82_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_82_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_82_RESET 0x0 #define BB_TPC_GLUT_SRAM_82_ADDRESS (0xec8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_82_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_82_RESET 0x0 // 0xecc (BB_TPC_GLUT_SRAM_83) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_83_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_83_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_83_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_83_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_83_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_83_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_83_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_83_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_83_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_83_RESET 0x0 #define BB_TPC_GLUT_SRAM_83_ADDRESS (0xecc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_83_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_83_RESET 0x0 // 0xed0 (BB_TPC_GLUT_SRAM_84) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_84_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_84_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_84_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_84_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_84_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_84_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_84_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_84_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_84_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_84_RESET 0x0 #define BB_TPC_GLUT_SRAM_84_ADDRESS (0xed0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_84_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_84_RESET 0x0 // 0xed4 (BB_TPC_GLUT_SRAM_85) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_85_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_85_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_85_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_85_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_85_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_85_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_85_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_85_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_85_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_85_RESET 0x0 #define BB_TPC_GLUT_SRAM_85_ADDRESS (0xed4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_85_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_85_RESET 0x0 // 0xed8 (BB_TPC_GLUT_SRAM_86) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_86_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_86_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_86_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_86_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_86_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_86_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_86_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_86_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_86_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_86_RESET 0x0 #define BB_TPC_GLUT_SRAM_86_ADDRESS (0xed8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_86_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_86_RESET 0x0 // 0xedc (BB_TPC_GLUT_SRAM_87) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_87_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_87_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_87_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_87_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_87_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_87_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_87_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_87_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_87_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_87_RESET 0x0 #define BB_TPC_GLUT_SRAM_87_ADDRESS (0xedc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_87_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_87_RESET 0x0 // 0xee0 (BB_TPC_GLUT_SRAM_88) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_88_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_88_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_88_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_88_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_88_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_88_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_88_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_88_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_88_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_88_RESET 0x0 #define BB_TPC_GLUT_SRAM_88_ADDRESS (0xee0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_88_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_88_RESET 0x0 // 0xee4 (BB_TPC_GLUT_SRAM_89) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_89_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_89_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_89_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_89_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_89_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_89_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_89_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_89_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_89_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_89_RESET 0x0 #define BB_TPC_GLUT_SRAM_89_ADDRESS (0xee4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_89_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_89_RESET 0x0 // 0xee8 (BB_TPC_GLUT_SRAM_90) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_90_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_90_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_90_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_90_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_90_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_90_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_90_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_90_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_90_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_90_RESET 0x0 #define BB_TPC_GLUT_SRAM_90_ADDRESS (0xee8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_90_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_90_RESET 0x0 // 0xeec (BB_TPC_GLUT_SRAM_91) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_91_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_91_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_91_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_91_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_91_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_91_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_91_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_91_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_91_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_91_RESET 0x0 #define BB_TPC_GLUT_SRAM_91_ADDRESS (0xeec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_91_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_91_RESET 0x0 // 0xef0 (BB_TPC_GLUT_SRAM_92) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_92_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_92_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_92_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_92_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_92_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_92_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_92_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_92_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_92_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_92_RESET 0x0 #define BB_TPC_GLUT_SRAM_92_ADDRESS (0xef0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_92_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_92_RESET 0x0 // 0xef4 (BB_TPC_GLUT_SRAM_93) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_93_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_93_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_93_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_93_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_93_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_93_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_93_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_93_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_93_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_93_RESET 0x0 #define BB_TPC_GLUT_SRAM_93_ADDRESS (0xef4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_93_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_93_RESET 0x0 // 0xef8 (BB_TPC_GLUT_SRAM_94) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_94_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_94_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_94_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_94_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_94_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_94_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_94_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_94_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_94_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_94_RESET 0x0 #define BB_TPC_GLUT_SRAM_94_ADDRESS (0xef8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_94_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_94_RESET 0x0 // 0xefc (BB_TPC_GLUT_SRAM_95) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_95_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_95_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_95_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_95_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_95_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_95_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_95_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_95_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_95_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_95_RESET 0x0 #define BB_TPC_GLUT_SRAM_95_ADDRESS (0xefc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_95_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_95_RESET 0x0 // 0xf00 (BB_TPC_GLUT_SRAM_96) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_96_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_96_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_96_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_96_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_96_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_96_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_96_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_96_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_96_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_96_RESET 0x0 #define BB_TPC_GLUT_SRAM_96_ADDRESS (0xf00 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_96_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_96_RESET 0x0 // 0xf04 (BB_TPC_GLUT_SRAM_97) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_97_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_97_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_97_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_97_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_97_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_97_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_97_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_97_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_97_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_97_RESET 0x0 #define BB_TPC_GLUT_SRAM_97_ADDRESS (0xf04 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_97_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_97_RESET 0x0 // 0xf08 (BB_TPC_GLUT_SRAM_98) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_98_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_98_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_98_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_98_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_98_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_98_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_98_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_98_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_98_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_98_RESET 0x0 #define BB_TPC_GLUT_SRAM_98_ADDRESS (0xf08 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_98_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_98_RESET 0x0 // 0xf0c (BB_TPC_GLUT_SRAM_99) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_99_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_99_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_99_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_99_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_99_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_99_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_99_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_99_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_99_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_99_RESET 0x0 #define BB_TPC_GLUT_SRAM_99_ADDRESS (0xf0c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_99_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_99_RESET 0x0 // 0xf10 (BB_TPC_GLUT_SRAM_100) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_100_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_100_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_100_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_100_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_100_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_100_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_100_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_100_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_100_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_100_RESET 0x0 #define BB_TPC_GLUT_SRAM_100_ADDRESS (0xf10 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_100_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_100_RESET 0x0 // 0xf14 (BB_TPC_GLUT_SRAM_101) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_101_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_101_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_101_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_101_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_101_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_101_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_101_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_101_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_101_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_101_RESET 0x0 #define BB_TPC_GLUT_SRAM_101_ADDRESS (0xf14 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_101_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_101_RESET 0x0 // 0xf18 (BB_TPC_GLUT_SRAM_102) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_102_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_102_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_102_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_102_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_102_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_102_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_102_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_102_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_102_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_102_RESET 0x0 #define BB_TPC_GLUT_SRAM_102_ADDRESS (0xf18 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_102_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_102_RESET 0x0 // 0xf1c (BB_TPC_GLUT_SRAM_103) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_103_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_103_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_103_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_103_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_103_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_103_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_103_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_103_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_103_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_103_RESET 0x0 #define BB_TPC_GLUT_SRAM_103_ADDRESS (0xf1c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_103_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_103_RESET 0x0 // 0xf20 (BB_TPC_GLUT_SRAM_104) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_104_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_104_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_104_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_104_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_104_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_104_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_104_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_104_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_104_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_104_RESET 0x0 #define BB_TPC_GLUT_SRAM_104_ADDRESS (0xf20 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_104_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_104_RESET 0x0 // 0xf24 (BB_TPC_GLUT_SRAM_105) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_105_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_105_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_105_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_105_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_105_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_105_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_105_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_105_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_105_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_105_RESET 0x0 #define BB_TPC_GLUT_SRAM_105_ADDRESS (0xf24 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_105_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_105_RESET 0x0 // 0xf28 (BB_TPC_GLUT_SRAM_106) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_106_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_106_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_106_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_106_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_106_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_106_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_106_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_106_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_106_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_106_RESET 0x0 #define BB_TPC_GLUT_SRAM_106_ADDRESS (0xf28 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_106_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_106_RESET 0x0 // 0xf2c (BB_TPC_GLUT_SRAM_107) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_107_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_107_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_107_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_107_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_107_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_107_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_107_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_107_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_107_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_107_RESET 0x0 #define BB_TPC_GLUT_SRAM_107_ADDRESS (0xf2c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_107_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_107_RESET 0x0 // 0xf30 (BB_TPC_GLUT_SRAM_108) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_108_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_108_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_108_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_108_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_108_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_108_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_108_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_108_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_108_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_108_RESET 0x0 #define BB_TPC_GLUT_SRAM_108_ADDRESS (0xf30 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_108_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_108_RESET 0x0 // 0xf34 (BB_TPC_GLUT_SRAM_109) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_109_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_109_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_109_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_109_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_109_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_109_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_109_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_109_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_109_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_109_RESET 0x0 #define BB_TPC_GLUT_SRAM_109_ADDRESS (0xf34 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_109_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_109_RESET 0x0 // 0xf38 (BB_TPC_GLUT_SRAM_110) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_110_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_110_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_110_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_110_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_110_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_110_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_110_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_110_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_110_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_110_RESET 0x0 #define BB_TPC_GLUT_SRAM_110_ADDRESS (0xf38 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_110_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_110_RESET 0x0 // 0xf3c (BB_TPC_GLUT_SRAM_111) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_111_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_111_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_111_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_111_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_111_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_111_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_111_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_111_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_111_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_111_RESET 0x0 #define BB_TPC_GLUT_SRAM_111_ADDRESS (0xf3c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_111_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_111_RESET 0x0 // 0xf40 (BB_TPC_GLUT_SRAM_112) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_112_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_112_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_112_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_112_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_112_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_112_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_112_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_112_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_112_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_112_RESET 0x0 #define BB_TPC_GLUT_SRAM_112_ADDRESS (0xf40 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_112_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_112_RESET 0x0 // 0xf44 (BB_TPC_GLUT_SRAM_113) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_113_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_113_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_113_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_113_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_113_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_113_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_113_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_113_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_113_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_113_RESET 0x0 #define BB_TPC_GLUT_SRAM_113_ADDRESS (0xf44 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_113_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_113_RESET 0x0 // 0xf48 (BB_TPC_GLUT_SRAM_114) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_114_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_114_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_114_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_114_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_114_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_114_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_114_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_114_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_114_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_114_RESET 0x0 #define BB_TPC_GLUT_SRAM_114_ADDRESS (0xf48 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_114_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_114_RESET 0x0 // 0xf4c (BB_TPC_GLUT_SRAM_115) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_115_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_115_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_115_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_115_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_115_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_115_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_115_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_115_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_115_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_115_RESET 0x0 #define BB_TPC_GLUT_SRAM_115_ADDRESS (0xf4c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_115_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_115_RESET 0x0 // 0xf50 (BB_TPC_GLUT_SRAM_116) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_116_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_116_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_116_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_116_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_116_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_116_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_116_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_116_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_116_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_116_RESET 0x0 #define BB_TPC_GLUT_SRAM_116_ADDRESS (0xf50 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_116_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_116_RESET 0x0 // 0xf54 (BB_TPC_GLUT_SRAM_117) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_117_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_117_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_117_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_117_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_117_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_117_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_117_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_117_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_117_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_117_RESET 0x0 #define BB_TPC_GLUT_SRAM_117_ADDRESS (0xf54 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_117_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_117_RESET 0x0 // 0xf58 (BB_TPC_GLUT_SRAM_118) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_118_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_118_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_118_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_118_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_118_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_118_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_118_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_118_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_118_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_118_RESET 0x0 #define BB_TPC_GLUT_SRAM_118_ADDRESS (0xf58 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_118_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_118_RESET 0x0 // 0xf5c (BB_TPC_GLUT_SRAM_119) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_119_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_119_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_119_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_119_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_119_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_119_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_119_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_119_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_119_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_119_RESET 0x0 #define BB_TPC_GLUT_SRAM_119_ADDRESS (0xf5c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_119_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_119_RESET 0x0 // 0xf60 (BB_TPC_GLUT_SRAM_120) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_120_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_120_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_120_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_120_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_120_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_120_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_120_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_120_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_120_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_120_RESET 0x0 #define BB_TPC_GLUT_SRAM_120_ADDRESS (0xf60 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_120_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_120_RESET 0x0 // 0xf64 (BB_TPC_GLUT_SRAM_121) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_121_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_121_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_121_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_121_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_121_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_121_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_121_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_121_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_121_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_121_RESET 0x0 #define BB_TPC_GLUT_SRAM_121_ADDRESS (0xf64 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_121_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_121_RESET 0x0 // 0xf68 (BB_TPC_GLUT_SRAM_122) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_122_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_122_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_122_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_122_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_122_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_122_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_122_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_122_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_122_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_122_RESET 0x0 #define BB_TPC_GLUT_SRAM_122_ADDRESS (0xf68 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_122_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_122_RESET 0x0 // 0xf6c (BB_TPC_GLUT_SRAM_123) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_123_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_123_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_123_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_123_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_123_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_123_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_123_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_123_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_123_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_123_RESET 0x0 #define BB_TPC_GLUT_SRAM_123_ADDRESS (0xf6c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_123_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_123_RESET 0x0 // 0xf70 (BB_TPC_GLUT_SRAM_124) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_124_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_124_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_124_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_124_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_124_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_124_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_124_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_124_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_124_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_124_RESET 0x0 #define BB_TPC_GLUT_SRAM_124_ADDRESS (0xf70 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_124_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_124_RESET 0x0 // 0xf74 (BB_TPC_GLUT_SRAM_125) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_125_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_125_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_125_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_125_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_125_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_125_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_125_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_125_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_125_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_125_RESET 0x0 #define BB_TPC_GLUT_SRAM_125_ADDRESS (0xf74 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_125_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_125_RESET 0x0 // 0xf78 (BB_TPC_GLUT_SRAM_126) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_126_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_126_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_126_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_126_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_126_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_126_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_126_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_126_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_126_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_126_RESET 0x0 #define BB_TPC_GLUT_SRAM_126_ADDRESS (0xf78 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_126_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_126_RESET 0x0 // 0xf7c (BB_TPC_GLUT_SRAM_127) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_127_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_127_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_127_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_127_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_127_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_127_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_127_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_127_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_127_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_127_RESET 0x0 #define BB_TPC_GLUT_SRAM_127_ADDRESS (0xf7c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_127_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_127_RESET 0x0 // 0xf80 (BB_TPC_GLUT_SRAM_128) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_128_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_128_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_128_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_128_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_128_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_128_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_128_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_128_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_128_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_128_RESET 0x0 #define BB_TPC_GLUT_SRAM_128_ADDRESS (0xf80 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_128_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_128_RESET 0x0 // 0xf84 (BB_TPC_GLUT_SRAM_129) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_129_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_129_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_129_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_129_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_129_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_129_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_129_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_129_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_129_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_129_RESET 0x0 #define BB_TPC_GLUT_SRAM_129_ADDRESS (0xf84 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_129_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_129_RESET 0x0 // 0xf88 (BB_TPC_GLUT_SRAM_130) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_130_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_130_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_130_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_130_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_130_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_130_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_130_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_130_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_130_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_130_RESET 0x0 #define BB_TPC_GLUT_SRAM_130_ADDRESS (0xf88 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_130_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_130_RESET 0x0 // 0xf8c (BB_TPC_GLUT_SRAM_131) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_131_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_131_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_131_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_131_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_131_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_131_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_131_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_131_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_131_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_131_RESET 0x0 #define BB_TPC_GLUT_SRAM_131_ADDRESS (0xf8c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_131_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_131_RESET 0x0 // 0xf90 (BB_TPC_GLUT_SRAM_132) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_132_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_132_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_132_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_132_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_132_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_132_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_132_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_132_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_132_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_132_RESET 0x0 #define BB_TPC_GLUT_SRAM_132_ADDRESS (0xf90 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_132_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_132_RESET 0x0 // 0xf94 (BB_TPC_GLUT_SRAM_133) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_133_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_133_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_133_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_133_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_133_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_133_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_133_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_133_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_133_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_133_RESET 0x0 #define BB_TPC_GLUT_SRAM_133_ADDRESS (0xf94 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_133_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_133_RESET 0x0 // 0xf98 (BB_TPC_GLUT_SRAM_134) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_134_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_134_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_134_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_134_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_134_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_134_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_134_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_134_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_134_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_134_RESET 0x0 #define BB_TPC_GLUT_SRAM_134_ADDRESS (0xf98 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_134_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_134_RESET 0x0 // 0xf9c (BB_TPC_GLUT_SRAM_135) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_135_LSB 0 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_135_MSB 25 #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_135_MASK 0x3ffffff #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_135_GET(x) (((x) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_135_MASK) >> BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_135_LSB) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_135_SET(x) (((0 | (x)) << BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_135_LSB) & BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_135_MASK) #define BB_TPC_GLUT_SRAM_TPC_GLUT_WORD_135_RESET 0x0 #define BB_TPC_GLUT_SRAM_135_ADDRESS (0xf9c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_GLUT_SRAM_135_RSTMASK 0x3ffffff #define BB_TPC_GLUT_SRAM_135_RESET 0x0 // 0xfa0 (BB_TPC_ALUT_SRAM) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_RESET 0x0 #define BB_TPC_ALUT_SRAM_ADDRESS (0xfa0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_RESET 0x0 // 0xfa0 (BB_TPC_ALUT_SRAM_0) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_0_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_0_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_0_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_0_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_0_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_0_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_0_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_0_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_0_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_0_RESET 0x0 #define BB_TPC_ALUT_SRAM_0_ADDRESS (0xfa0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_0_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_0_RESET 0x0 // 0xfa4 (BB_TPC_ALUT_SRAM_1) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_1_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_1_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_1_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_1_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_1_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_1_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_1_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_1_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_1_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_1_RESET 0x0 #define BB_TPC_ALUT_SRAM_1_ADDRESS (0xfa4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_1_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_1_RESET 0x0 // 0xfa8 (BB_TPC_ALUT_SRAM_2) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_2_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_2_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_2_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_2_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_2_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_2_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_2_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_2_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_2_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_2_RESET 0x0 #define BB_TPC_ALUT_SRAM_2_ADDRESS (0xfa8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_2_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_2_RESET 0x0 // 0xfac (BB_TPC_ALUT_SRAM_3) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_3_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_3_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_3_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_3_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_3_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_3_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_3_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_3_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_3_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_3_RESET 0x0 #define BB_TPC_ALUT_SRAM_3_ADDRESS (0xfac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_3_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_3_RESET 0x0 // 0xfb0 (BB_TPC_ALUT_SRAM_4) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_4_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_4_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_4_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_4_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_4_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_4_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_4_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_4_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_4_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_4_RESET 0x0 #define BB_TPC_ALUT_SRAM_4_ADDRESS (0xfb0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_4_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_4_RESET 0x0 // 0xfb4 (BB_TPC_ALUT_SRAM_5) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_5_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_5_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_5_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_5_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_5_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_5_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_5_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_5_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_5_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_5_RESET 0x0 #define BB_TPC_ALUT_SRAM_5_ADDRESS (0xfb4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_5_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_5_RESET 0x0 // 0xfb8 (BB_TPC_ALUT_SRAM_6) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_6_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_6_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_6_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_6_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_6_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_6_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_6_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_6_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_6_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_6_RESET 0x0 #define BB_TPC_ALUT_SRAM_6_ADDRESS (0xfb8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_6_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_6_RESET 0x0 // 0xfbc (BB_TPC_ALUT_SRAM_7) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_7_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_7_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_7_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_7_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_7_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_7_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_7_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_7_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_7_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_7_RESET 0x0 #define BB_TPC_ALUT_SRAM_7_ADDRESS (0xfbc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_7_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_7_RESET 0x0 // 0xfc0 (BB_TPC_ALUT_SRAM_8) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_8_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_8_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_8_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_8_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_8_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_8_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_8_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_8_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_8_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_8_RESET 0x0 #define BB_TPC_ALUT_SRAM_8_ADDRESS (0xfc0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_8_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_8_RESET 0x0 // 0xfc4 (BB_TPC_ALUT_SRAM_9) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_9_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_9_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_9_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_9_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_9_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_9_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_9_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_9_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_9_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_9_RESET 0x0 #define BB_TPC_ALUT_SRAM_9_ADDRESS (0xfc4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_9_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_9_RESET 0x0 // 0xfc8 (BB_TPC_ALUT_SRAM_10) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_10_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_10_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_10_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_10_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_10_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_10_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_10_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_10_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_10_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_10_RESET 0x0 #define BB_TPC_ALUT_SRAM_10_ADDRESS (0xfc8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_10_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_10_RESET 0x0 // 0xfcc (BB_TPC_ALUT_SRAM_11) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_11_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_11_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_11_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_11_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_11_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_11_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_11_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_11_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_11_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_11_RESET 0x0 #define BB_TPC_ALUT_SRAM_11_ADDRESS (0xfcc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_11_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_11_RESET 0x0 // 0xfd0 (BB_TPC_ALUT_SRAM_12) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_12_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_12_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_12_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_12_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_12_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_12_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_12_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_12_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_12_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_12_RESET 0x0 #define BB_TPC_ALUT_SRAM_12_ADDRESS (0xfd0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_12_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_12_RESET 0x0 // 0xfd4 (BB_TPC_ALUT_SRAM_13) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_13_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_13_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_13_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_13_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_13_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_13_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_13_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_13_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_13_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_13_RESET 0x0 #define BB_TPC_ALUT_SRAM_13_ADDRESS (0xfd4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_13_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_13_RESET 0x0 // 0xfd8 (BB_TPC_ALUT_SRAM_14) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_14_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_14_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_14_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_14_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_14_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_14_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_14_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_14_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_14_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_14_RESET 0x0 #define BB_TPC_ALUT_SRAM_14_ADDRESS (0xfd8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_14_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_14_RESET 0x0 // 0xfdc (BB_TPC_ALUT_SRAM_15) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_15_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_15_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_15_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_15_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_15_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_15_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_15_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_15_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_15_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_15_RESET 0x0 #define BB_TPC_ALUT_SRAM_15_ADDRESS (0xfdc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_15_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_15_RESET 0x0 // 0xfe0 (BB_TPC_ALUT_SRAM_16) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_16_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_16_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_16_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_16_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_16_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_16_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_16_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_16_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_16_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_16_RESET 0x0 #define BB_TPC_ALUT_SRAM_16_ADDRESS (0xfe0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_16_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_16_RESET 0x0 // 0xfe4 (BB_TPC_ALUT_SRAM_17) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_17_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_17_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_17_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_17_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_17_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_17_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_17_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_17_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_17_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_17_RESET 0x0 #define BB_TPC_ALUT_SRAM_17_ADDRESS (0xfe4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_17_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_17_RESET 0x0 // 0xfe8 (BB_TPC_ALUT_SRAM_18) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_18_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_18_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_18_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_18_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_18_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_18_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_18_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_18_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_18_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_18_RESET 0x0 #define BB_TPC_ALUT_SRAM_18_ADDRESS (0xfe8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_18_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_18_RESET 0x0 // 0xfec (BB_TPC_ALUT_SRAM_19) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_19_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_19_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_19_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_19_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_19_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_19_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_19_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_19_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_19_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_19_RESET 0x0 #define BB_TPC_ALUT_SRAM_19_ADDRESS (0xfec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_19_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_19_RESET 0x0 // 0xff0 (BB_TPC_ALUT_SRAM_20) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_20_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_20_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_20_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_20_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_20_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_20_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_20_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_20_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_20_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_20_RESET 0x0 #define BB_TPC_ALUT_SRAM_20_ADDRESS (0xff0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_20_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_20_RESET 0x0 // 0xff4 (BB_TPC_ALUT_SRAM_21) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_21_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_21_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_21_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_21_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_21_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_21_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_21_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_21_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_21_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_21_RESET 0x0 #define BB_TPC_ALUT_SRAM_21_ADDRESS (0xff4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_21_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_21_RESET 0x0 // 0xff8 (BB_TPC_ALUT_SRAM_22) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_22_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_22_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_22_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_22_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_22_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_22_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_22_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_22_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_22_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_22_RESET 0x0 #define BB_TPC_ALUT_SRAM_22_ADDRESS (0xff8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_22_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_22_RESET 0x0 // 0xffc (BB_TPC_ALUT_SRAM_23) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_23_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_23_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_23_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_23_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_23_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_23_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_23_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_23_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_23_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_23_RESET 0x0 #define BB_TPC_ALUT_SRAM_23_ADDRESS (0xffc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_23_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_23_RESET 0x0 // 0x1000 (BB_TPC_ALUT_SRAM_24) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_24_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_24_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_24_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_24_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_24_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_24_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_24_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_24_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_24_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_24_RESET 0x0 #define BB_TPC_ALUT_SRAM_24_ADDRESS (0x1000 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_24_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_24_RESET 0x0 // 0x1004 (BB_TPC_ALUT_SRAM_25) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_25_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_25_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_25_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_25_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_25_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_25_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_25_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_25_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_25_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_25_RESET 0x0 #define BB_TPC_ALUT_SRAM_25_ADDRESS (0x1004 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_25_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_25_RESET 0x0 // 0x1008 (BB_TPC_ALUT_SRAM_26) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_26_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_26_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_26_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_26_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_26_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_26_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_26_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_26_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_26_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_26_RESET 0x0 #define BB_TPC_ALUT_SRAM_26_ADDRESS (0x1008 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_26_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_26_RESET 0x0 // 0x100c (BB_TPC_ALUT_SRAM_27) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_27_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_27_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_27_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_27_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_27_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_27_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_27_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_27_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_27_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_27_RESET 0x0 #define BB_TPC_ALUT_SRAM_27_ADDRESS (0x100c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_27_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_27_RESET 0x0 // 0x1010 (BB_TPC_ALUT_SRAM_28) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_28_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_28_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_28_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_28_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_28_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_28_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_28_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_28_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_28_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_28_RESET 0x0 #define BB_TPC_ALUT_SRAM_28_ADDRESS (0x1010 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_28_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_28_RESET 0x0 // 0x1014 (BB_TPC_ALUT_SRAM_29) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_29_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_29_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_29_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_29_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_29_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_29_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_29_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_29_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_29_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_29_RESET 0x0 #define BB_TPC_ALUT_SRAM_29_ADDRESS (0x1014 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_29_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_29_RESET 0x0 // 0x1018 (BB_TPC_ALUT_SRAM_30) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_30_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_30_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_30_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_30_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_30_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_30_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_30_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_30_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_30_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_30_RESET 0x0 #define BB_TPC_ALUT_SRAM_30_ADDRESS (0x1018 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_30_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_30_RESET 0x0 // 0x101c (BB_TPC_ALUT_SRAM_31) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_31_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_31_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_31_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_31_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_31_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_31_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_31_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_31_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_31_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_31_RESET 0x0 #define BB_TPC_ALUT_SRAM_31_ADDRESS (0x101c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_31_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_31_RESET 0x0 // 0x1020 (BB_TPC_ALUT_SRAM_32) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_32_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_32_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_32_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_32_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_32_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_32_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_32_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_32_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_32_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_32_RESET 0x0 #define BB_TPC_ALUT_SRAM_32_ADDRESS (0x1020 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_32_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_32_RESET 0x0 // 0x1024 (BB_TPC_ALUT_SRAM_33) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_33_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_33_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_33_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_33_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_33_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_33_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_33_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_33_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_33_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_33_RESET 0x0 #define BB_TPC_ALUT_SRAM_33_ADDRESS (0x1024 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_33_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_33_RESET 0x0 // 0x1028 (BB_TPC_ALUT_SRAM_34) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_34_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_34_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_34_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_34_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_34_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_34_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_34_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_34_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_34_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_34_RESET 0x0 #define BB_TPC_ALUT_SRAM_34_ADDRESS (0x1028 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_34_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_34_RESET 0x0 // 0x102c (BB_TPC_ALUT_SRAM_35) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_35_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_35_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_35_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_35_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_35_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_35_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_35_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_35_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_35_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_35_RESET 0x0 #define BB_TPC_ALUT_SRAM_35_ADDRESS (0x102c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_35_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_35_RESET 0x0 // 0x1030 (BB_TPC_ALUT_SRAM_36) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_36_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_36_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_36_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_36_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_36_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_36_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_36_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_36_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_36_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_36_RESET 0x0 #define BB_TPC_ALUT_SRAM_36_ADDRESS (0x1030 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_36_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_36_RESET 0x0 // 0x1034 (BB_TPC_ALUT_SRAM_37) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_37_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_37_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_37_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_37_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_37_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_37_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_37_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_37_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_37_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_37_RESET 0x0 #define BB_TPC_ALUT_SRAM_37_ADDRESS (0x1034 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_37_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_37_RESET 0x0 // 0x1038 (BB_TPC_ALUT_SRAM_38) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_38_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_38_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_38_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_38_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_38_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_38_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_38_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_38_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_38_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_38_RESET 0x0 #define BB_TPC_ALUT_SRAM_38_ADDRESS (0x1038 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_38_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_38_RESET 0x0 // 0x103c (BB_TPC_ALUT_SRAM_39) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_39_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_39_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_39_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_39_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_39_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_39_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_39_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_39_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_39_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_39_RESET 0x0 #define BB_TPC_ALUT_SRAM_39_ADDRESS (0x103c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_39_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_39_RESET 0x0 // 0x1040 (BB_TPC_ALUT_SRAM_40) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_40_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_40_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_40_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_40_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_40_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_40_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_40_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_40_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_40_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_40_RESET 0x0 #define BB_TPC_ALUT_SRAM_40_ADDRESS (0x1040 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_40_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_40_RESET 0x0 // 0x1044 (BB_TPC_ALUT_SRAM_41) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_41_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_41_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_41_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_41_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_41_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_41_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_41_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_41_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_41_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_41_RESET 0x0 #define BB_TPC_ALUT_SRAM_41_ADDRESS (0x1044 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_41_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_41_RESET 0x0 // 0x1048 (BB_TPC_ALUT_SRAM_42) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_42_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_42_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_42_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_42_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_42_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_42_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_42_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_42_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_42_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_42_RESET 0x0 #define BB_TPC_ALUT_SRAM_42_ADDRESS (0x1048 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_42_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_42_RESET 0x0 // 0x104c (BB_TPC_ALUT_SRAM_43) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_43_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_43_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_43_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_43_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_43_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_43_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_43_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_43_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_43_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_43_RESET 0x0 #define BB_TPC_ALUT_SRAM_43_ADDRESS (0x104c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_43_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_43_RESET 0x0 // 0x1050 (BB_TPC_ALUT_SRAM_44) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_44_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_44_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_44_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_44_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_44_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_44_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_44_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_44_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_44_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_44_RESET 0x0 #define BB_TPC_ALUT_SRAM_44_ADDRESS (0x1050 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_44_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_44_RESET 0x0 // 0x1054 (BB_TPC_ALUT_SRAM_45) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_45_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_45_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_45_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_45_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_45_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_45_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_45_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_45_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_45_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_45_RESET 0x0 #define BB_TPC_ALUT_SRAM_45_ADDRESS (0x1054 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_45_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_45_RESET 0x0 // 0x1058 (BB_TPC_ALUT_SRAM_46) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_46_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_46_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_46_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_46_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_46_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_46_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_46_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_46_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_46_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_46_RESET 0x0 #define BB_TPC_ALUT_SRAM_46_ADDRESS (0x1058 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_46_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_46_RESET 0x0 // 0x105c (BB_TPC_ALUT_SRAM_47) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_47_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_47_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_47_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_47_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_47_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_47_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_47_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_47_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_47_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_47_RESET 0x0 #define BB_TPC_ALUT_SRAM_47_ADDRESS (0x105c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_47_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_47_RESET 0x0 // 0x1060 (BB_TPC_ALUT_SRAM_48) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_48_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_48_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_48_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_48_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_48_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_48_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_48_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_48_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_48_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_48_RESET 0x0 #define BB_TPC_ALUT_SRAM_48_ADDRESS (0x1060 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_48_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_48_RESET 0x0 // 0x1064 (BB_TPC_ALUT_SRAM_49) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_49_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_49_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_49_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_49_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_49_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_49_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_49_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_49_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_49_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_49_RESET 0x0 #define BB_TPC_ALUT_SRAM_49_ADDRESS (0x1064 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_49_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_49_RESET 0x0 // 0x1068 (BB_TPC_ALUT_SRAM_50) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_50_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_50_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_50_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_50_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_50_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_50_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_50_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_50_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_50_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_50_RESET 0x0 #define BB_TPC_ALUT_SRAM_50_ADDRESS (0x1068 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_50_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_50_RESET 0x0 // 0x106c (BB_TPC_ALUT_SRAM_51) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_51_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_51_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_51_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_51_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_51_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_51_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_51_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_51_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_51_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_51_RESET 0x0 #define BB_TPC_ALUT_SRAM_51_ADDRESS (0x106c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_51_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_51_RESET 0x0 // 0x1070 (BB_TPC_ALUT_SRAM_52) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_52_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_52_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_52_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_52_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_52_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_52_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_52_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_52_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_52_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_52_RESET 0x0 #define BB_TPC_ALUT_SRAM_52_ADDRESS (0x1070 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_52_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_52_RESET 0x0 // 0x1074 (BB_TPC_ALUT_SRAM_53) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_53_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_53_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_53_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_53_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_53_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_53_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_53_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_53_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_53_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_53_RESET 0x0 #define BB_TPC_ALUT_SRAM_53_ADDRESS (0x1074 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_53_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_53_RESET 0x0 // 0x1078 (BB_TPC_ALUT_SRAM_54) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_54_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_54_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_54_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_54_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_54_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_54_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_54_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_54_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_54_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_54_RESET 0x0 #define BB_TPC_ALUT_SRAM_54_ADDRESS (0x1078 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_54_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_54_RESET 0x0 // 0x107c (BB_TPC_ALUT_SRAM_55) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_55_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_55_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_55_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_55_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_55_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_55_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_55_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_55_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_55_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_55_RESET 0x0 #define BB_TPC_ALUT_SRAM_55_ADDRESS (0x107c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_55_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_55_RESET 0x0 // 0x1080 (BB_TPC_ALUT_SRAM_56) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_56_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_56_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_56_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_56_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_56_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_56_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_56_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_56_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_56_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_56_RESET 0x0 #define BB_TPC_ALUT_SRAM_56_ADDRESS (0x1080 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_56_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_56_RESET 0x0 // 0x1084 (BB_TPC_ALUT_SRAM_57) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_57_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_57_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_57_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_57_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_57_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_57_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_57_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_57_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_57_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_57_RESET 0x0 #define BB_TPC_ALUT_SRAM_57_ADDRESS (0x1084 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_57_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_57_RESET 0x0 // 0x1088 (BB_TPC_ALUT_SRAM_58) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_58_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_58_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_58_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_58_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_58_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_58_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_58_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_58_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_58_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_58_RESET 0x0 #define BB_TPC_ALUT_SRAM_58_ADDRESS (0x1088 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_58_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_58_RESET 0x0 // 0x108c (BB_TPC_ALUT_SRAM_59) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_59_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_59_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_59_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_59_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_59_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_59_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_59_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_59_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_59_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_59_RESET 0x0 #define BB_TPC_ALUT_SRAM_59_ADDRESS (0x108c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_59_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_59_RESET 0x0 // 0x1090 (BB_TPC_ALUT_SRAM_60) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_60_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_60_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_60_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_60_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_60_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_60_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_60_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_60_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_60_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_60_RESET 0x0 #define BB_TPC_ALUT_SRAM_60_ADDRESS (0x1090 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_60_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_60_RESET 0x0 // 0x1094 (BB_TPC_ALUT_SRAM_61) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_61_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_61_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_61_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_61_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_61_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_61_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_61_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_61_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_61_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_61_RESET 0x0 #define BB_TPC_ALUT_SRAM_61_ADDRESS (0x1094 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_61_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_61_RESET 0x0 // 0x1098 (BB_TPC_ALUT_SRAM_62) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_62_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_62_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_62_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_62_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_62_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_62_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_62_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_62_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_62_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_62_RESET 0x0 #define BB_TPC_ALUT_SRAM_62_ADDRESS (0x1098 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_62_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_62_RESET 0x0 // 0x109c (BB_TPC_ALUT_SRAM_63) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_63_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_63_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_63_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_63_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_63_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_63_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_63_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_63_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_63_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_63_RESET 0x0 #define BB_TPC_ALUT_SRAM_63_ADDRESS (0x109c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_63_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_63_RESET 0x0 // 0x10a0 (BB_TPC_ALUT_SRAM_64) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_64_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_64_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_64_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_64_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_64_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_64_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_64_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_64_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_64_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_64_RESET 0x0 #define BB_TPC_ALUT_SRAM_64_ADDRESS (0x10a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_64_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_64_RESET 0x0 // 0x10a4 (BB_TPC_ALUT_SRAM_65) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_65_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_65_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_65_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_65_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_65_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_65_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_65_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_65_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_65_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_65_RESET 0x0 #define BB_TPC_ALUT_SRAM_65_ADDRESS (0x10a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_65_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_65_RESET 0x0 // 0x10a8 (BB_TPC_ALUT_SRAM_66) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_66_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_66_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_66_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_66_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_66_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_66_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_66_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_66_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_66_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_66_RESET 0x0 #define BB_TPC_ALUT_SRAM_66_ADDRESS (0x10a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_66_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_66_RESET 0x0 // 0x10ac (BB_TPC_ALUT_SRAM_67) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_67_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_67_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_67_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_67_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_67_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_67_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_67_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_67_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_67_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_67_RESET 0x0 #define BB_TPC_ALUT_SRAM_67_ADDRESS (0x10ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_67_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_67_RESET 0x0 // 0x10b0 (BB_TPC_ALUT_SRAM_68) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_68_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_68_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_68_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_68_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_68_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_68_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_68_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_68_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_68_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_68_RESET 0x0 #define BB_TPC_ALUT_SRAM_68_ADDRESS (0x10b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_68_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_68_RESET 0x0 // 0x10b4 (BB_TPC_ALUT_SRAM_69) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_69_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_69_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_69_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_69_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_69_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_69_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_69_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_69_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_69_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_69_RESET 0x0 #define BB_TPC_ALUT_SRAM_69_ADDRESS (0x10b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_69_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_69_RESET 0x0 // 0x10b8 (BB_TPC_ALUT_SRAM_70) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_70_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_70_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_70_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_70_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_70_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_70_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_70_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_70_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_70_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_70_RESET 0x0 #define BB_TPC_ALUT_SRAM_70_ADDRESS (0x10b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_70_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_70_RESET 0x0 // 0x10bc (BB_TPC_ALUT_SRAM_71) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_71_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_71_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_71_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_71_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_71_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_71_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_71_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_71_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_71_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_71_RESET 0x0 #define BB_TPC_ALUT_SRAM_71_ADDRESS (0x10bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_71_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_71_RESET 0x0 // 0x10c0 (BB_TPC_ALUT_SRAM_72) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_72_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_72_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_72_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_72_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_72_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_72_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_72_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_72_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_72_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_72_RESET 0x0 #define BB_TPC_ALUT_SRAM_72_ADDRESS (0x10c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_72_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_72_RESET 0x0 // 0x10c4 (BB_TPC_ALUT_SRAM_73) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_73_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_73_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_73_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_73_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_73_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_73_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_73_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_73_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_73_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_73_RESET 0x0 #define BB_TPC_ALUT_SRAM_73_ADDRESS (0x10c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_73_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_73_RESET 0x0 // 0x10c8 (BB_TPC_ALUT_SRAM_74) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_74_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_74_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_74_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_74_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_74_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_74_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_74_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_74_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_74_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_74_RESET 0x0 #define BB_TPC_ALUT_SRAM_74_ADDRESS (0x10c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_74_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_74_RESET 0x0 // 0x10cc (BB_TPC_ALUT_SRAM_75) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_75_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_75_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_75_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_75_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_75_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_75_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_75_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_75_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_75_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_75_RESET 0x0 #define BB_TPC_ALUT_SRAM_75_ADDRESS (0x10cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_75_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_75_RESET 0x0 // 0x10d0 (BB_TPC_ALUT_SRAM_76) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_76_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_76_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_76_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_76_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_76_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_76_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_76_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_76_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_76_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_76_RESET 0x0 #define BB_TPC_ALUT_SRAM_76_ADDRESS (0x10d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_76_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_76_RESET 0x0 // 0x10d4 (BB_TPC_ALUT_SRAM_77) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_77_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_77_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_77_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_77_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_77_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_77_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_77_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_77_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_77_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_77_RESET 0x0 #define BB_TPC_ALUT_SRAM_77_ADDRESS (0x10d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_77_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_77_RESET 0x0 // 0x10d8 (BB_TPC_ALUT_SRAM_78) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_78_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_78_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_78_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_78_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_78_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_78_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_78_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_78_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_78_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_78_RESET 0x0 #define BB_TPC_ALUT_SRAM_78_ADDRESS (0x10d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_78_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_78_RESET 0x0 // 0x10dc (BB_TPC_ALUT_SRAM_79) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_79_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_79_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_79_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_79_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_79_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_79_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_79_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_79_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_79_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_79_RESET 0x0 #define BB_TPC_ALUT_SRAM_79_ADDRESS (0x10dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_79_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_79_RESET 0x0 // 0x10e0 (BB_TPC_ALUT_SRAM_80) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_80_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_80_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_80_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_80_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_80_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_80_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_80_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_80_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_80_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_80_RESET 0x0 #define BB_TPC_ALUT_SRAM_80_ADDRESS (0x10e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_80_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_80_RESET 0x0 // 0x10e4 (BB_TPC_ALUT_SRAM_81) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_81_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_81_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_81_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_81_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_81_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_81_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_81_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_81_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_81_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_81_RESET 0x0 #define BB_TPC_ALUT_SRAM_81_ADDRESS (0x10e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_81_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_81_RESET 0x0 // 0x10e8 (BB_TPC_ALUT_SRAM_82) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_82_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_82_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_82_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_82_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_82_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_82_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_82_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_82_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_82_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_82_RESET 0x0 #define BB_TPC_ALUT_SRAM_82_ADDRESS (0x10e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_82_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_82_RESET 0x0 // 0x10ec (BB_TPC_ALUT_SRAM_83) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_83_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_83_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_83_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_83_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_83_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_83_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_83_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_83_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_83_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_83_RESET 0x0 #define BB_TPC_ALUT_SRAM_83_ADDRESS (0x10ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_83_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_83_RESET 0x0 // 0x10f0 (BB_TPC_ALUT_SRAM_84) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_84_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_84_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_84_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_84_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_84_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_84_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_84_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_84_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_84_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_84_RESET 0x0 #define BB_TPC_ALUT_SRAM_84_ADDRESS (0x10f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_84_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_84_RESET 0x0 // 0x10f4 (BB_TPC_ALUT_SRAM_85) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_85_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_85_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_85_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_85_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_85_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_85_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_85_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_85_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_85_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_85_RESET 0x0 #define BB_TPC_ALUT_SRAM_85_ADDRESS (0x10f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_85_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_85_RESET 0x0 // 0x10f8 (BB_TPC_ALUT_SRAM_86) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_86_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_86_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_86_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_86_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_86_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_86_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_86_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_86_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_86_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_86_RESET 0x0 #define BB_TPC_ALUT_SRAM_86_ADDRESS (0x10f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_86_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_86_RESET 0x0 // 0x10fc (BB_TPC_ALUT_SRAM_87) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_87_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_87_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_87_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_87_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_87_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_87_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_87_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_87_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_87_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_87_RESET 0x0 #define BB_TPC_ALUT_SRAM_87_ADDRESS (0x10fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_87_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_87_RESET 0x0 // 0x1100 (BB_TPC_ALUT_SRAM_88) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_88_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_88_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_88_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_88_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_88_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_88_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_88_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_88_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_88_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_88_RESET 0x0 #define BB_TPC_ALUT_SRAM_88_ADDRESS (0x1100 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_88_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_88_RESET 0x0 // 0x1104 (BB_TPC_ALUT_SRAM_89) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_89_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_89_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_89_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_89_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_89_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_89_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_89_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_89_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_89_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_89_RESET 0x0 #define BB_TPC_ALUT_SRAM_89_ADDRESS (0x1104 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_89_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_89_RESET 0x0 // 0x1108 (BB_TPC_ALUT_SRAM_90) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_90_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_90_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_90_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_90_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_90_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_90_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_90_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_90_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_90_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_90_RESET 0x0 #define BB_TPC_ALUT_SRAM_90_ADDRESS (0x1108 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_90_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_90_RESET 0x0 // 0x110c (BB_TPC_ALUT_SRAM_91) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_91_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_91_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_91_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_91_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_91_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_91_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_91_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_91_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_91_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_91_RESET 0x0 #define BB_TPC_ALUT_SRAM_91_ADDRESS (0x110c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_91_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_91_RESET 0x0 // 0x1110 (BB_TPC_ALUT_SRAM_92) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_92_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_92_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_92_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_92_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_92_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_92_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_92_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_92_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_92_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_92_RESET 0x0 #define BB_TPC_ALUT_SRAM_92_ADDRESS (0x1110 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_92_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_92_RESET 0x0 // 0x1114 (BB_TPC_ALUT_SRAM_93) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_93_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_93_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_93_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_93_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_93_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_93_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_93_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_93_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_93_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_93_RESET 0x0 #define BB_TPC_ALUT_SRAM_93_ADDRESS (0x1114 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_93_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_93_RESET 0x0 // 0x1118 (BB_TPC_ALUT_SRAM_94) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_94_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_94_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_94_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_94_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_94_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_94_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_94_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_94_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_94_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_94_RESET 0x0 #define BB_TPC_ALUT_SRAM_94_ADDRESS (0x1118 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_94_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_94_RESET 0x0 // 0x111c (BB_TPC_ALUT_SRAM_95) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_95_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_95_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_95_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_95_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_95_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_95_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_95_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_95_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_95_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_95_RESET 0x0 #define BB_TPC_ALUT_SRAM_95_ADDRESS (0x111c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_95_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_95_RESET 0x0 // 0x1120 (BB_TPC_ALUT_SRAM_96) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_96_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_96_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_96_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_96_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_96_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_96_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_96_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_96_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_96_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_96_RESET 0x0 #define BB_TPC_ALUT_SRAM_96_ADDRESS (0x1120 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_96_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_96_RESET 0x0 // 0x1124 (BB_TPC_ALUT_SRAM_97) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_97_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_97_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_97_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_97_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_97_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_97_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_97_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_97_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_97_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_97_RESET 0x0 #define BB_TPC_ALUT_SRAM_97_ADDRESS (0x1124 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_97_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_97_RESET 0x0 // 0x1128 (BB_TPC_ALUT_SRAM_98) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_98_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_98_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_98_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_98_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_98_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_98_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_98_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_98_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_98_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_98_RESET 0x0 #define BB_TPC_ALUT_SRAM_98_ADDRESS (0x1128 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_98_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_98_RESET 0x0 // 0x112c (BB_TPC_ALUT_SRAM_99) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_99_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_99_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_99_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_99_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_99_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_99_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_99_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_99_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_99_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_99_RESET 0x0 #define BB_TPC_ALUT_SRAM_99_ADDRESS (0x112c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_99_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_99_RESET 0x0 // 0x1130 (BB_TPC_ALUT_SRAM_100) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_100_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_100_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_100_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_100_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_100_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_100_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_100_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_100_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_100_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_100_RESET 0x0 #define BB_TPC_ALUT_SRAM_100_ADDRESS (0x1130 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_100_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_100_RESET 0x0 // 0x1134 (BB_TPC_ALUT_SRAM_101) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_101_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_101_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_101_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_101_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_101_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_101_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_101_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_101_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_101_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_101_RESET 0x0 #define BB_TPC_ALUT_SRAM_101_ADDRESS (0x1134 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_101_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_101_RESET 0x0 // 0x1138 (BB_TPC_ALUT_SRAM_102) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_102_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_102_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_102_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_102_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_102_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_102_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_102_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_102_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_102_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_102_RESET 0x0 #define BB_TPC_ALUT_SRAM_102_ADDRESS (0x1138 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_102_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_102_RESET 0x0 // 0x113c (BB_TPC_ALUT_SRAM_103) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_103_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_103_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_103_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_103_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_103_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_103_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_103_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_103_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_103_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_103_RESET 0x0 #define BB_TPC_ALUT_SRAM_103_ADDRESS (0x113c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_103_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_103_RESET 0x0 // 0x1140 (BB_TPC_ALUT_SRAM_104) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_104_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_104_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_104_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_104_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_104_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_104_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_104_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_104_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_104_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_104_RESET 0x0 #define BB_TPC_ALUT_SRAM_104_ADDRESS (0x1140 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_104_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_104_RESET 0x0 // 0x1144 (BB_TPC_ALUT_SRAM_105) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_105_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_105_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_105_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_105_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_105_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_105_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_105_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_105_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_105_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_105_RESET 0x0 #define BB_TPC_ALUT_SRAM_105_ADDRESS (0x1144 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_105_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_105_RESET 0x0 // 0x1148 (BB_TPC_ALUT_SRAM_106) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_106_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_106_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_106_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_106_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_106_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_106_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_106_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_106_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_106_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_106_RESET 0x0 #define BB_TPC_ALUT_SRAM_106_ADDRESS (0x1148 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_106_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_106_RESET 0x0 // 0x114c (BB_TPC_ALUT_SRAM_107) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_107_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_107_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_107_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_107_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_107_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_107_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_107_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_107_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_107_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_107_RESET 0x0 #define BB_TPC_ALUT_SRAM_107_ADDRESS (0x114c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_107_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_107_RESET 0x0 // 0x1150 (BB_TPC_ALUT_SRAM_108) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_108_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_108_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_108_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_108_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_108_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_108_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_108_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_108_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_108_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_108_RESET 0x0 #define BB_TPC_ALUT_SRAM_108_ADDRESS (0x1150 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_108_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_108_RESET 0x0 // 0x1154 (BB_TPC_ALUT_SRAM_109) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_109_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_109_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_109_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_109_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_109_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_109_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_109_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_109_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_109_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_109_RESET 0x0 #define BB_TPC_ALUT_SRAM_109_ADDRESS (0x1154 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_109_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_109_RESET 0x0 // 0x1158 (BB_TPC_ALUT_SRAM_110) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_110_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_110_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_110_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_110_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_110_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_110_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_110_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_110_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_110_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_110_RESET 0x0 #define BB_TPC_ALUT_SRAM_110_ADDRESS (0x1158 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_110_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_110_RESET 0x0 // 0x115c (BB_TPC_ALUT_SRAM_111) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_111_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_111_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_111_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_111_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_111_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_111_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_111_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_111_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_111_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_111_RESET 0x0 #define BB_TPC_ALUT_SRAM_111_ADDRESS (0x115c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_111_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_111_RESET 0x0 // 0x1160 (BB_TPC_ALUT_SRAM_112) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_112_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_112_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_112_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_112_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_112_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_112_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_112_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_112_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_112_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_112_RESET 0x0 #define BB_TPC_ALUT_SRAM_112_ADDRESS (0x1160 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_112_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_112_RESET 0x0 // 0x1164 (BB_TPC_ALUT_SRAM_113) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_113_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_113_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_113_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_113_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_113_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_113_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_113_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_113_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_113_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_113_RESET 0x0 #define BB_TPC_ALUT_SRAM_113_ADDRESS (0x1164 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_113_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_113_RESET 0x0 // 0x1168 (BB_TPC_ALUT_SRAM_114) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_114_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_114_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_114_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_114_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_114_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_114_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_114_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_114_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_114_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_114_RESET 0x0 #define BB_TPC_ALUT_SRAM_114_ADDRESS (0x1168 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_114_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_114_RESET 0x0 // 0x116c (BB_TPC_ALUT_SRAM_115) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_115_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_115_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_115_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_115_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_115_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_115_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_115_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_115_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_115_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_115_RESET 0x0 #define BB_TPC_ALUT_SRAM_115_ADDRESS (0x116c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_115_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_115_RESET 0x0 // 0x1170 (BB_TPC_ALUT_SRAM_116) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_116_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_116_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_116_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_116_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_116_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_116_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_116_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_116_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_116_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_116_RESET 0x0 #define BB_TPC_ALUT_SRAM_116_ADDRESS (0x1170 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_116_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_116_RESET 0x0 // 0x1174 (BB_TPC_ALUT_SRAM_117) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_117_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_117_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_117_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_117_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_117_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_117_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_117_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_117_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_117_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_117_RESET 0x0 #define BB_TPC_ALUT_SRAM_117_ADDRESS (0x1174 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_117_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_117_RESET 0x0 // 0x1178 (BB_TPC_ALUT_SRAM_118) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_118_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_118_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_118_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_118_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_118_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_118_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_118_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_118_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_118_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_118_RESET 0x0 #define BB_TPC_ALUT_SRAM_118_ADDRESS (0x1178 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_118_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_118_RESET 0x0 // 0x117c (BB_TPC_ALUT_SRAM_119) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_119_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_119_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_119_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_119_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_119_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_119_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_119_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_119_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_119_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_119_RESET 0x0 #define BB_TPC_ALUT_SRAM_119_ADDRESS (0x117c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_119_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_119_RESET 0x0 // 0x1180 (BB_TPC_ALUT_SRAM_120) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_120_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_120_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_120_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_120_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_120_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_120_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_120_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_120_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_120_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_120_RESET 0x0 #define BB_TPC_ALUT_SRAM_120_ADDRESS (0x1180 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_120_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_120_RESET 0x0 // 0x1184 (BB_TPC_ALUT_SRAM_121) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_121_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_121_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_121_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_121_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_121_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_121_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_121_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_121_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_121_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_121_RESET 0x0 #define BB_TPC_ALUT_SRAM_121_ADDRESS (0x1184 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_121_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_121_RESET 0x0 // 0x1188 (BB_TPC_ALUT_SRAM_122) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_122_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_122_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_122_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_122_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_122_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_122_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_122_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_122_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_122_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_122_RESET 0x0 #define BB_TPC_ALUT_SRAM_122_ADDRESS (0x1188 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_122_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_122_RESET 0x0 // 0x118c (BB_TPC_ALUT_SRAM_123) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_123_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_123_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_123_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_123_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_123_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_123_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_123_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_123_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_123_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_123_RESET 0x0 #define BB_TPC_ALUT_SRAM_123_ADDRESS (0x118c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_123_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_123_RESET 0x0 // 0x1190 (BB_TPC_ALUT_SRAM_124) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_124_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_124_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_124_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_124_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_124_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_124_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_124_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_124_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_124_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_124_RESET 0x0 #define BB_TPC_ALUT_SRAM_124_ADDRESS (0x1190 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_124_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_124_RESET 0x0 // 0x1194 (BB_TPC_ALUT_SRAM_125) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_125_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_125_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_125_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_125_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_125_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_125_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_125_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_125_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_125_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_125_RESET 0x0 #define BB_TPC_ALUT_SRAM_125_ADDRESS (0x1194 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_125_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_125_RESET 0x0 // 0x1198 (BB_TPC_ALUT_SRAM_126) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_126_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_126_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_126_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_126_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_126_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_126_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_126_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_126_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_126_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_126_RESET 0x0 #define BB_TPC_ALUT_SRAM_126_ADDRESS (0x1198 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_126_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_126_RESET 0x0 // 0x119c (BB_TPC_ALUT_SRAM_127) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_127_LSB 0 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_127_MSB 25 #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_127_MASK 0x3ffffff #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_127_GET(x) (((x) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_127_MASK) >> BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_127_LSB) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_127_SET(x) (((0 | (x)) << BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_127_LSB) & BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_127_MASK) #define BB_TPC_ALUT_SRAM_TPC_ALUT_WORD_127_RESET 0x0 #define BB_TPC_ALUT_SRAM_127_ADDRESS (0x119c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_TPC_ALUT_SRAM_127_RSTMASK 0x3ffffff #define BB_TPC_ALUT_SRAM_127_RESET 0x0 // 0x1200 (BB_RXCAL_TX_GAIN_TABLE_0) #define BB_RXCAL_TX_GAIN_TABLE_0_RXCAL_TX_GAIN_TABLE_0_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_0_RXCAL_TX_GAIN_TABLE_0_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_0_RXCAL_TX_GAIN_TABLE_0_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_0_RXCAL_TX_GAIN_TABLE_0_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_0_RXCAL_TX_GAIN_TABLE_0_MASK) >> BB_RXCAL_TX_GAIN_TABLE_0_RXCAL_TX_GAIN_TABLE_0_LSB) #define BB_RXCAL_TX_GAIN_TABLE_0_RXCAL_TX_GAIN_TABLE_0_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_0_RXCAL_TX_GAIN_TABLE_0_LSB) & BB_RXCAL_TX_GAIN_TABLE_0_RXCAL_TX_GAIN_TABLE_0_MASK) #define BB_RXCAL_TX_GAIN_TABLE_0_RXCAL_TX_GAIN_TABLE_0_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_0_ADDRESS (0x1200 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_0_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_0_RESET 0x0 // 0x1204 (BB_RXCAL_TX_GAIN_TABLE_1) #define BB_RXCAL_TX_GAIN_TABLE_1_RXCAL_TX_GAIN_TABLE_1_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_1_RXCAL_TX_GAIN_TABLE_1_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_1_RXCAL_TX_GAIN_TABLE_1_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_1_RXCAL_TX_GAIN_TABLE_1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_1_RXCAL_TX_GAIN_TABLE_1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_1_RXCAL_TX_GAIN_TABLE_1_LSB) #define BB_RXCAL_TX_GAIN_TABLE_1_RXCAL_TX_GAIN_TABLE_1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_1_RXCAL_TX_GAIN_TABLE_1_LSB) & BB_RXCAL_TX_GAIN_TABLE_1_RXCAL_TX_GAIN_TABLE_1_MASK) #define BB_RXCAL_TX_GAIN_TABLE_1_RXCAL_TX_GAIN_TABLE_1_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_1_ADDRESS (0x1204 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_1_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_1_RESET 0x0 // 0x1208 (BB_RXCAL_TX_GAIN_TABLE_2) #define BB_RXCAL_TX_GAIN_TABLE_2_RXCAL_TX_GAIN_TABLE_2_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_2_RXCAL_TX_GAIN_TABLE_2_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_2_RXCAL_TX_GAIN_TABLE_2_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_2_RXCAL_TX_GAIN_TABLE_2_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_2_RXCAL_TX_GAIN_TABLE_2_MASK) >> BB_RXCAL_TX_GAIN_TABLE_2_RXCAL_TX_GAIN_TABLE_2_LSB) #define BB_RXCAL_TX_GAIN_TABLE_2_RXCAL_TX_GAIN_TABLE_2_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_2_RXCAL_TX_GAIN_TABLE_2_LSB) & BB_RXCAL_TX_GAIN_TABLE_2_RXCAL_TX_GAIN_TABLE_2_MASK) #define BB_RXCAL_TX_GAIN_TABLE_2_RXCAL_TX_GAIN_TABLE_2_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_2_ADDRESS (0x1208 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_2_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_2_RESET 0x0 // 0x120c (BB_RXCAL_TX_GAIN_TABLE_3) #define BB_RXCAL_TX_GAIN_TABLE_3_RXCAL_TX_GAIN_TABLE_3_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_3_RXCAL_TX_GAIN_TABLE_3_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_3_RXCAL_TX_GAIN_TABLE_3_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_3_RXCAL_TX_GAIN_TABLE_3_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_3_RXCAL_TX_GAIN_TABLE_3_MASK) >> BB_RXCAL_TX_GAIN_TABLE_3_RXCAL_TX_GAIN_TABLE_3_LSB) #define BB_RXCAL_TX_GAIN_TABLE_3_RXCAL_TX_GAIN_TABLE_3_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_3_RXCAL_TX_GAIN_TABLE_3_LSB) & BB_RXCAL_TX_GAIN_TABLE_3_RXCAL_TX_GAIN_TABLE_3_MASK) #define BB_RXCAL_TX_GAIN_TABLE_3_RXCAL_TX_GAIN_TABLE_3_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_3_ADDRESS (0x120c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_3_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_3_RESET 0x0 // 0x1210 (BB_RXCAL_TX_GAIN_TABLE_4) #define BB_RXCAL_TX_GAIN_TABLE_4_RXCAL_TX_GAIN_TABLE_4_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_4_RXCAL_TX_GAIN_TABLE_4_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_4_RXCAL_TX_GAIN_TABLE_4_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_4_RXCAL_TX_GAIN_TABLE_4_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_4_RXCAL_TX_GAIN_TABLE_4_MASK) >> BB_RXCAL_TX_GAIN_TABLE_4_RXCAL_TX_GAIN_TABLE_4_LSB) #define BB_RXCAL_TX_GAIN_TABLE_4_RXCAL_TX_GAIN_TABLE_4_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_4_RXCAL_TX_GAIN_TABLE_4_LSB) & BB_RXCAL_TX_GAIN_TABLE_4_RXCAL_TX_GAIN_TABLE_4_MASK) #define BB_RXCAL_TX_GAIN_TABLE_4_RXCAL_TX_GAIN_TABLE_4_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_4_ADDRESS (0x1210 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_4_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_4_RESET 0x0 // 0x1214 (BB_RXCAL_TX_GAIN_TABLE_5) #define BB_RXCAL_TX_GAIN_TABLE_5_RXCAL_TX_GAIN_TABLE_5_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_5_RXCAL_TX_GAIN_TABLE_5_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_5_RXCAL_TX_GAIN_TABLE_5_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_5_RXCAL_TX_GAIN_TABLE_5_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_5_RXCAL_TX_GAIN_TABLE_5_MASK) >> BB_RXCAL_TX_GAIN_TABLE_5_RXCAL_TX_GAIN_TABLE_5_LSB) #define BB_RXCAL_TX_GAIN_TABLE_5_RXCAL_TX_GAIN_TABLE_5_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_5_RXCAL_TX_GAIN_TABLE_5_LSB) & BB_RXCAL_TX_GAIN_TABLE_5_RXCAL_TX_GAIN_TABLE_5_MASK) #define BB_RXCAL_TX_GAIN_TABLE_5_RXCAL_TX_GAIN_TABLE_5_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_5_ADDRESS (0x1214 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_5_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_5_RESET 0x0 // 0x1218 (BB_RXCAL_TX_GAIN_TABLE_6) #define BB_RXCAL_TX_GAIN_TABLE_6_RXCAL_TX_GAIN_TABLE_6_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_6_RXCAL_TX_GAIN_TABLE_6_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_6_RXCAL_TX_GAIN_TABLE_6_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_6_RXCAL_TX_GAIN_TABLE_6_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_6_RXCAL_TX_GAIN_TABLE_6_MASK) >> BB_RXCAL_TX_GAIN_TABLE_6_RXCAL_TX_GAIN_TABLE_6_LSB) #define BB_RXCAL_TX_GAIN_TABLE_6_RXCAL_TX_GAIN_TABLE_6_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_6_RXCAL_TX_GAIN_TABLE_6_LSB) & BB_RXCAL_TX_GAIN_TABLE_6_RXCAL_TX_GAIN_TABLE_6_MASK) #define BB_RXCAL_TX_GAIN_TABLE_6_RXCAL_TX_GAIN_TABLE_6_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_6_ADDRESS (0x1218 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_6_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_6_RESET 0x0 // 0x121c (BB_RXCAL_TX_GAIN_TABLE_7) #define BB_RXCAL_TX_GAIN_TABLE_7_RXCAL_TX_GAIN_TABLE_7_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_7_RXCAL_TX_GAIN_TABLE_7_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_7_RXCAL_TX_GAIN_TABLE_7_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_7_RXCAL_TX_GAIN_TABLE_7_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_7_RXCAL_TX_GAIN_TABLE_7_MASK) >> BB_RXCAL_TX_GAIN_TABLE_7_RXCAL_TX_GAIN_TABLE_7_LSB) #define BB_RXCAL_TX_GAIN_TABLE_7_RXCAL_TX_GAIN_TABLE_7_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_7_RXCAL_TX_GAIN_TABLE_7_LSB) & BB_RXCAL_TX_GAIN_TABLE_7_RXCAL_TX_GAIN_TABLE_7_MASK) #define BB_RXCAL_TX_GAIN_TABLE_7_RXCAL_TX_GAIN_TABLE_7_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_7_ADDRESS (0x121c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_7_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_7_RESET 0x0 // 0x1220 (BB_RXCAL_TX_GAIN_TABLE_8) #define BB_RXCAL_TX_GAIN_TABLE_8_RXCAL_TX_GAIN_TABLE_8_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_8_RXCAL_TX_GAIN_TABLE_8_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_8_RXCAL_TX_GAIN_TABLE_8_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_8_RXCAL_TX_GAIN_TABLE_8_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_8_RXCAL_TX_GAIN_TABLE_8_MASK) >> BB_RXCAL_TX_GAIN_TABLE_8_RXCAL_TX_GAIN_TABLE_8_LSB) #define BB_RXCAL_TX_GAIN_TABLE_8_RXCAL_TX_GAIN_TABLE_8_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_8_RXCAL_TX_GAIN_TABLE_8_LSB) & BB_RXCAL_TX_GAIN_TABLE_8_RXCAL_TX_GAIN_TABLE_8_MASK) #define BB_RXCAL_TX_GAIN_TABLE_8_RXCAL_TX_GAIN_TABLE_8_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_8_ADDRESS (0x1220 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_8_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_8_RESET 0x0 // 0x1224 (BB_RXCAL_TX_GAIN_TABLE_9) #define BB_RXCAL_TX_GAIN_TABLE_9_RXCAL_TX_GAIN_TABLE_9_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_9_RXCAL_TX_GAIN_TABLE_9_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_9_RXCAL_TX_GAIN_TABLE_9_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_9_RXCAL_TX_GAIN_TABLE_9_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_9_RXCAL_TX_GAIN_TABLE_9_MASK) >> BB_RXCAL_TX_GAIN_TABLE_9_RXCAL_TX_GAIN_TABLE_9_LSB) #define BB_RXCAL_TX_GAIN_TABLE_9_RXCAL_TX_GAIN_TABLE_9_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_9_RXCAL_TX_GAIN_TABLE_9_LSB) & BB_RXCAL_TX_GAIN_TABLE_9_RXCAL_TX_GAIN_TABLE_9_MASK) #define BB_RXCAL_TX_GAIN_TABLE_9_RXCAL_TX_GAIN_TABLE_9_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_9_ADDRESS (0x1224 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_9_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_9_RESET 0x0 // 0x1228 (BB_RXCAL_TX_GAIN_TABLE_10) #define BB_RXCAL_TX_GAIN_TABLE_10_RXCAL_TX_GAIN_TABLE_10_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_10_RXCAL_TX_GAIN_TABLE_10_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_10_RXCAL_TX_GAIN_TABLE_10_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_10_RXCAL_TX_GAIN_TABLE_10_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_10_RXCAL_TX_GAIN_TABLE_10_MASK) >> BB_RXCAL_TX_GAIN_TABLE_10_RXCAL_TX_GAIN_TABLE_10_LSB) #define BB_RXCAL_TX_GAIN_TABLE_10_RXCAL_TX_GAIN_TABLE_10_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_10_RXCAL_TX_GAIN_TABLE_10_LSB) & BB_RXCAL_TX_GAIN_TABLE_10_RXCAL_TX_GAIN_TABLE_10_MASK) #define BB_RXCAL_TX_GAIN_TABLE_10_RXCAL_TX_GAIN_TABLE_10_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_10_ADDRESS (0x1228 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_10_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_10_RESET 0x0 // 0x122c (BB_RXCAL_TX_GAIN_TABLE_11) #define BB_RXCAL_TX_GAIN_TABLE_11_RXCAL_TX_GAIN_TABLE_11_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_11_RXCAL_TX_GAIN_TABLE_11_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_11_RXCAL_TX_GAIN_TABLE_11_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_11_RXCAL_TX_GAIN_TABLE_11_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_11_RXCAL_TX_GAIN_TABLE_11_MASK) >> BB_RXCAL_TX_GAIN_TABLE_11_RXCAL_TX_GAIN_TABLE_11_LSB) #define BB_RXCAL_TX_GAIN_TABLE_11_RXCAL_TX_GAIN_TABLE_11_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_11_RXCAL_TX_GAIN_TABLE_11_LSB) & BB_RXCAL_TX_GAIN_TABLE_11_RXCAL_TX_GAIN_TABLE_11_MASK) #define BB_RXCAL_TX_GAIN_TABLE_11_RXCAL_TX_GAIN_TABLE_11_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_11_ADDRESS (0x122c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_11_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_11_RESET 0x0 // 0x1230 (BB_RXCAL_TX_GAIN_TABLE_12) #define BB_RXCAL_TX_GAIN_TABLE_12_RXCAL_TX_GAIN_TABLE_12_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_12_RXCAL_TX_GAIN_TABLE_12_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_12_RXCAL_TX_GAIN_TABLE_12_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_12_RXCAL_TX_GAIN_TABLE_12_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_12_RXCAL_TX_GAIN_TABLE_12_MASK) >> BB_RXCAL_TX_GAIN_TABLE_12_RXCAL_TX_GAIN_TABLE_12_LSB) #define BB_RXCAL_TX_GAIN_TABLE_12_RXCAL_TX_GAIN_TABLE_12_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_12_RXCAL_TX_GAIN_TABLE_12_LSB) & BB_RXCAL_TX_GAIN_TABLE_12_RXCAL_TX_GAIN_TABLE_12_MASK) #define BB_RXCAL_TX_GAIN_TABLE_12_RXCAL_TX_GAIN_TABLE_12_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_12_ADDRESS (0x1230 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_12_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_12_RESET 0x0 // 0x1234 (BB_RXCAL_TX_GAIN_TABLE_13) #define BB_RXCAL_TX_GAIN_TABLE_13_RXCAL_TX_GAIN_TABLE_13_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_13_RXCAL_TX_GAIN_TABLE_13_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_13_RXCAL_TX_GAIN_TABLE_13_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_13_RXCAL_TX_GAIN_TABLE_13_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_13_RXCAL_TX_GAIN_TABLE_13_MASK) >> BB_RXCAL_TX_GAIN_TABLE_13_RXCAL_TX_GAIN_TABLE_13_LSB) #define BB_RXCAL_TX_GAIN_TABLE_13_RXCAL_TX_GAIN_TABLE_13_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_13_RXCAL_TX_GAIN_TABLE_13_LSB) & BB_RXCAL_TX_GAIN_TABLE_13_RXCAL_TX_GAIN_TABLE_13_MASK) #define BB_RXCAL_TX_GAIN_TABLE_13_RXCAL_TX_GAIN_TABLE_13_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_13_ADDRESS (0x1234 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_13_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_13_RESET 0x0 // 0x1238 (BB_RXCAL_TX_GAIN_TABLE_14) #define BB_RXCAL_TX_GAIN_TABLE_14_RXCAL_TX_GAIN_TABLE_14_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_14_RXCAL_TX_GAIN_TABLE_14_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_14_RXCAL_TX_GAIN_TABLE_14_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_14_RXCAL_TX_GAIN_TABLE_14_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_14_RXCAL_TX_GAIN_TABLE_14_MASK) >> BB_RXCAL_TX_GAIN_TABLE_14_RXCAL_TX_GAIN_TABLE_14_LSB) #define BB_RXCAL_TX_GAIN_TABLE_14_RXCAL_TX_GAIN_TABLE_14_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_14_RXCAL_TX_GAIN_TABLE_14_LSB) & BB_RXCAL_TX_GAIN_TABLE_14_RXCAL_TX_GAIN_TABLE_14_MASK) #define BB_RXCAL_TX_GAIN_TABLE_14_RXCAL_TX_GAIN_TABLE_14_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_14_ADDRESS (0x1238 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_14_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_14_RESET 0x0 // 0x123c (BB_RXCAL_TX_GAIN_TABLE_15) #define BB_RXCAL_TX_GAIN_TABLE_15_RXCAL_TX_GAIN_TABLE_15_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_15_RXCAL_TX_GAIN_TABLE_15_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_15_RXCAL_TX_GAIN_TABLE_15_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_15_RXCAL_TX_GAIN_TABLE_15_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_15_RXCAL_TX_GAIN_TABLE_15_MASK) >> BB_RXCAL_TX_GAIN_TABLE_15_RXCAL_TX_GAIN_TABLE_15_LSB) #define BB_RXCAL_TX_GAIN_TABLE_15_RXCAL_TX_GAIN_TABLE_15_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_15_RXCAL_TX_GAIN_TABLE_15_LSB) & BB_RXCAL_TX_GAIN_TABLE_15_RXCAL_TX_GAIN_TABLE_15_MASK) #define BB_RXCAL_TX_GAIN_TABLE_15_RXCAL_TX_GAIN_TABLE_15_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_15_ADDRESS (0x123c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_15_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_15_RESET 0x0 // 0x1240 (BB_RXCAL_TX_GAIN_TABLE_16) #define BB_RXCAL_TX_GAIN_TABLE_16_RXCAL_TX_GAIN_TABLE_16_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_16_RXCAL_TX_GAIN_TABLE_16_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_16_RXCAL_TX_GAIN_TABLE_16_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_16_RXCAL_TX_GAIN_TABLE_16_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_16_RXCAL_TX_GAIN_TABLE_16_MASK) >> BB_RXCAL_TX_GAIN_TABLE_16_RXCAL_TX_GAIN_TABLE_16_LSB) #define BB_RXCAL_TX_GAIN_TABLE_16_RXCAL_TX_GAIN_TABLE_16_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_16_RXCAL_TX_GAIN_TABLE_16_LSB) & BB_RXCAL_TX_GAIN_TABLE_16_RXCAL_TX_GAIN_TABLE_16_MASK) #define BB_RXCAL_TX_GAIN_TABLE_16_RXCAL_TX_GAIN_TABLE_16_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_16_ADDRESS (0x1240 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_16_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_16_RESET 0x0 // 0x1244 (BB_RXCAL_TX_GAIN_TABLE_17) #define BB_RXCAL_TX_GAIN_TABLE_17_RXCAL_TX_GAIN_TABLE_17_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_17_RXCAL_TX_GAIN_TABLE_17_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_17_RXCAL_TX_GAIN_TABLE_17_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_17_RXCAL_TX_GAIN_TABLE_17_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_17_RXCAL_TX_GAIN_TABLE_17_MASK) >> BB_RXCAL_TX_GAIN_TABLE_17_RXCAL_TX_GAIN_TABLE_17_LSB) #define BB_RXCAL_TX_GAIN_TABLE_17_RXCAL_TX_GAIN_TABLE_17_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_17_RXCAL_TX_GAIN_TABLE_17_LSB) & BB_RXCAL_TX_GAIN_TABLE_17_RXCAL_TX_GAIN_TABLE_17_MASK) #define BB_RXCAL_TX_GAIN_TABLE_17_RXCAL_TX_GAIN_TABLE_17_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_17_ADDRESS (0x1244 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_17_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_17_RESET 0x0 // 0x1248 (BB_RXCAL_TX_GAIN_TABLE_18) #define BB_RXCAL_TX_GAIN_TABLE_18_RXCAL_TX_GAIN_TABLE_18_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_18_RXCAL_TX_GAIN_TABLE_18_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_18_RXCAL_TX_GAIN_TABLE_18_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_18_RXCAL_TX_GAIN_TABLE_18_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_18_RXCAL_TX_GAIN_TABLE_18_MASK) >> BB_RXCAL_TX_GAIN_TABLE_18_RXCAL_TX_GAIN_TABLE_18_LSB) #define BB_RXCAL_TX_GAIN_TABLE_18_RXCAL_TX_GAIN_TABLE_18_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_18_RXCAL_TX_GAIN_TABLE_18_LSB) & BB_RXCAL_TX_GAIN_TABLE_18_RXCAL_TX_GAIN_TABLE_18_MASK) #define BB_RXCAL_TX_GAIN_TABLE_18_RXCAL_TX_GAIN_TABLE_18_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_18_ADDRESS (0x1248 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_18_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_18_RESET 0x0 // 0x124c (BB_RXCAL_TX_GAIN_TABLE_19) #define BB_RXCAL_TX_GAIN_TABLE_19_RXCAL_TX_GAIN_TABLE_19_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_19_RXCAL_TX_GAIN_TABLE_19_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_19_RXCAL_TX_GAIN_TABLE_19_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_19_RXCAL_TX_GAIN_TABLE_19_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_19_RXCAL_TX_GAIN_TABLE_19_MASK) >> BB_RXCAL_TX_GAIN_TABLE_19_RXCAL_TX_GAIN_TABLE_19_LSB) #define BB_RXCAL_TX_GAIN_TABLE_19_RXCAL_TX_GAIN_TABLE_19_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_19_RXCAL_TX_GAIN_TABLE_19_LSB) & BB_RXCAL_TX_GAIN_TABLE_19_RXCAL_TX_GAIN_TABLE_19_MASK) #define BB_RXCAL_TX_GAIN_TABLE_19_RXCAL_TX_GAIN_TABLE_19_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_19_ADDRESS (0x124c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_19_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_19_RESET 0x0 // 0x1250 (BB_RXCAL_TX_GAIN_TABLE_20) #define BB_RXCAL_TX_GAIN_TABLE_20_RXCAL_TX_GAIN_TABLE_20_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_20_RXCAL_TX_GAIN_TABLE_20_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_20_RXCAL_TX_GAIN_TABLE_20_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_20_RXCAL_TX_GAIN_TABLE_20_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_20_RXCAL_TX_GAIN_TABLE_20_MASK) >> BB_RXCAL_TX_GAIN_TABLE_20_RXCAL_TX_GAIN_TABLE_20_LSB) #define BB_RXCAL_TX_GAIN_TABLE_20_RXCAL_TX_GAIN_TABLE_20_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_20_RXCAL_TX_GAIN_TABLE_20_LSB) & BB_RXCAL_TX_GAIN_TABLE_20_RXCAL_TX_GAIN_TABLE_20_MASK) #define BB_RXCAL_TX_GAIN_TABLE_20_RXCAL_TX_GAIN_TABLE_20_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_20_ADDRESS (0x1250 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_20_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_20_RESET 0x0 // 0x1254 (BB_RXCAL_TX_GAIN_TABLE_21) #define BB_RXCAL_TX_GAIN_TABLE_21_RXCAL_TX_GAIN_TABLE_21_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_21_RXCAL_TX_GAIN_TABLE_21_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_21_RXCAL_TX_GAIN_TABLE_21_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_21_RXCAL_TX_GAIN_TABLE_21_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_21_RXCAL_TX_GAIN_TABLE_21_MASK) >> BB_RXCAL_TX_GAIN_TABLE_21_RXCAL_TX_GAIN_TABLE_21_LSB) #define BB_RXCAL_TX_GAIN_TABLE_21_RXCAL_TX_GAIN_TABLE_21_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_21_RXCAL_TX_GAIN_TABLE_21_LSB) & BB_RXCAL_TX_GAIN_TABLE_21_RXCAL_TX_GAIN_TABLE_21_MASK) #define BB_RXCAL_TX_GAIN_TABLE_21_RXCAL_TX_GAIN_TABLE_21_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_21_ADDRESS (0x1254 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_21_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_21_RESET 0x0 // 0x1258 (BB_RXCAL_TX_GAIN_TABLE_22) #define BB_RXCAL_TX_GAIN_TABLE_22_RXCAL_TX_GAIN_TABLE_22_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_22_RXCAL_TX_GAIN_TABLE_22_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_22_RXCAL_TX_GAIN_TABLE_22_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_22_RXCAL_TX_GAIN_TABLE_22_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_22_RXCAL_TX_GAIN_TABLE_22_MASK) >> BB_RXCAL_TX_GAIN_TABLE_22_RXCAL_TX_GAIN_TABLE_22_LSB) #define BB_RXCAL_TX_GAIN_TABLE_22_RXCAL_TX_GAIN_TABLE_22_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_22_RXCAL_TX_GAIN_TABLE_22_LSB) & BB_RXCAL_TX_GAIN_TABLE_22_RXCAL_TX_GAIN_TABLE_22_MASK) #define BB_RXCAL_TX_GAIN_TABLE_22_RXCAL_TX_GAIN_TABLE_22_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_22_ADDRESS (0x1258 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_22_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_22_RESET 0x0 // 0x125c (BB_RXCAL_TX_GAIN_TABLE_23) #define BB_RXCAL_TX_GAIN_TABLE_23_RXCAL_TX_GAIN_TABLE_23_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_23_RXCAL_TX_GAIN_TABLE_23_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_23_RXCAL_TX_GAIN_TABLE_23_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_23_RXCAL_TX_GAIN_TABLE_23_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_23_RXCAL_TX_GAIN_TABLE_23_MASK) >> BB_RXCAL_TX_GAIN_TABLE_23_RXCAL_TX_GAIN_TABLE_23_LSB) #define BB_RXCAL_TX_GAIN_TABLE_23_RXCAL_TX_GAIN_TABLE_23_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_23_RXCAL_TX_GAIN_TABLE_23_LSB) & BB_RXCAL_TX_GAIN_TABLE_23_RXCAL_TX_GAIN_TABLE_23_MASK) #define BB_RXCAL_TX_GAIN_TABLE_23_RXCAL_TX_GAIN_TABLE_23_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_23_ADDRESS (0x125c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_23_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_23_RESET 0x0 // 0x1260 (BB_RXCAL_TX_GAIN_TABLE_24) #define BB_RXCAL_TX_GAIN_TABLE_24_RXCAL_TX_GAIN_TABLE_24_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_24_RXCAL_TX_GAIN_TABLE_24_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_24_RXCAL_TX_GAIN_TABLE_24_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_24_RXCAL_TX_GAIN_TABLE_24_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_24_RXCAL_TX_GAIN_TABLE_24_MASK) >> BB_RXCAL_TX_GAIN_TABLE_24_RXCAL_TX_GAIN_TABLE_24_LSB) #define BB_RXCAL_TX_GAIN_TABLE_24_RXCAL_TX_GAIN_TABLE_24_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_24_RXCAL_TX_GAIN_TABLE_24_LSB) & BB_RXCAL_TX_GAIN_TABLE_24_RXCAL_TX_GAIN_TABLE_24_MASK) #define BB_RXCAL_TX_GAIN_TABLE_24_RXCAL_TX_GAIN_TABLE_24_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_24_ADDRESS (0x1260 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_24_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_24_RESET 0x0 // 0x1264 (BB_RXCAL_TX_GAIN_TABLE_25) #define BB_RXCAL_TX_GAIN_TABLE_25_RXCAL_TX_GAIN_TABLE_25_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_25_RXCAL_TX_GAIN_TABLE_25_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_25_RXCAL_TX_GAIN_TABLE_25_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_25_RXCAL_TX_GAIN_TABLE_25_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_25_RXCAL_TX_GAIN_TABLE_25_MASK) >> BB_RXCAL_TX_GAIN_TABLE_25_RXCAL_TX_GAIN_TABLE_25_LSB) #define BB_RXCAL_TX_GAIN_TABLE_25_RXCAL_TX_GAIN_TABLE_25_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_25_RXCAL_TX_GAIN_TABLE_25_LSB) & BB_RXCAL_TX_GAIN_TABLE_25_RXCAL_TX_GAIN_TABLE_25_MASK) #define BB_RXCAL_TX_GAIN_TABLE_25_RXCAL_TX_GAIN_TABLE_25_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_25_ADDRESS (0x1264 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_25_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_25_RESET 0x0 // 0x1268 (BB_RXCAL_TX_GAIN_TABLE_26) #define BB_RXCAL_TX_GAIN_TABLE_26_RXCAL_TX_GAIN_TABLE_26_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_26_RXCAL_TX_GAIN_TABLE_26_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_26_RXCAL_TX_GAIN_TABLE_26_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_26_RXCAL_TX_GAIN_TABLE_26_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_26_RXCAL_TX_GAIN_TABLE_26_MASK) >> BB_RXCAL_TX_GAIN_TABLE_26_RXCAL_TX_GAIN_TABLE_26_LSB) #define BB_RXCAL_TX_GAIN_TABLE_26_RXCAL_TX_GAIN_TABLE_26_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_26_RXCAL_TX_GAIN_TABLE_26_LSB) & BB_RXCAL_TX_GAIN_TABLE_26_RXCAL_TX_GAIN_TABLE_26_MASK) #define BB_RXCAL_TX_GAIN_TABLE_26_RXCAL_TX_GAIN_TABLE_26_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_26_ADDRESS (0x1268 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_26_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_26_RESET 0x0 // 0x126c (BB_RXCAL_TX_GAIN_TABLE_27) #define BB_RXCAL_TX_GAIN_TABLE_27_RXCAL_TX_GAIN_TABLE_27_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_27_RXCAL_TX_GAIN_TABLE_27_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_27_RXCAL_TX_GAIN_TABLE_27_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_27_RXCAL_TX_GAIN_TABLE_27_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_27_RXCAL_TX_GAIN_TABLE_27_MASK) >> BB_RXCAL_TX_GAIN_TABLE_27_RXCAL_TX_GAIN_TABLE_27_LSB) #define BB_RXCAL_TX_GAIN_TABLE_27_RXCAL_TX_GAIN_TABLE_27_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_27_RXCAL_TX_GAIN_TABLE_27_LSB) & BB_RXCAL_TX_GAIN_TABLE_27_RXCAL_TX_GAIN_TABLE_27_MASK) #define BB_RXCAL_TX_GAIN_TABLE_27_RXCAL_TX_GAIN_TABLE_27_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_27_ADDRESS (0x126c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_27_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_27_RESET 0x0 // 0x1270 (BB_RXCAL_TX_GAIN_TABLE_28) #define BB_RXCAL_TX_GAIN_TABLE_28_RXCAL_TX_GAIN_TABLE_28_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_28_RXCAL_TX_GAIN_TABLE_28_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_28_RXCAL_TX_GAIN_TABLE_28_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_28_RXCAL_TX_GAIN_TABLE_28_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_28_RXCAL_TX_GAIN_TABLE_28_MASK) >> BB_RXCAL_TX_GAIN_TABLE_28_RXCAL_TX_GAIN_TABLE_28_LSB) #define BB_RXCAL_TX_GAIN_TABLE_28_RXCAL_TX_GAIN_TABLE_28_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_28_RXCAL_TX_GAIN_TABLE_28_LSB) & BB_RXCAL_TX_GAIN_TABLE_28_RXCAL_TX_GAIN_TABLE_28_MASK) #define BB_RXCAL_TX_GAIN_TABLE_28_RXCAL_TX_GAIN_TABLE_28_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_28_ADDRESS (0x1270 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_28_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_28_RESET 0x0 // 0x1274 (BB_RXCAL_TX_GAIN_TABLE_29) #define BB_RXCAL_TX_GAIN_TABLE_29_RXCAL_TX_GAIN_TABLE_29_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_29_RXCAL_TX_GAIN_TABLE_29_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_29_RXCAL_TX_GAIN_TABLE_29_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_29_RXCAL_TX_GAIN_TABLE_29_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_29_RXCAL_TX_GAIN_TABLE_29_MASK) >> BB_RXCAL_TX_GAIN_TABLE_29_RXCAL_TX_GAIN_TABLE_29_LSB) #define BB_RXCAL_TX_GAIN_TABLE_29_RXCAL_TX_GAIN_TABLE_29_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_29_RXCAL_TX_GAIN_TABLE_29_LSB) & BB_RXCAL_TX_GAIN_TABLE_29_RXCAL_TX_GAIN_TABLE_29_MASK) #define BB_RXCAL_TX_GAIN_TABLE_29_RXCAL_TX_GAIN_TABLE_29_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_29_ADDRESS (0x1274 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_29_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_29_RESET 0x0 // 0x1278 (BB_RXCAL_TX_GAIN_TABLE_30) #define BB_RXCAL_TX_GAIN_TABLE_30_RXCAL_TX_GAIN_TABLE_30_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_30_RXCAL_TX_GAIN_TABLE_30_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_30_RXCAL_TX_GAIN_TABLE_30_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_30_RXCAL_TX_GAIN_TABLE_30_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_30_RXCAL_TX_GAIN_TABLE_30_MASK) >> BB_RXCAL_TX_GAIN_TABLE_30_RXCAL_TX_GAIN_TABLE_30_LSB) #define BB_RXCAL_TX_GAIN_TABLE_30_RXCAL_TX_GAIN_TABLE_30_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_30_RXCAL_TX_GAIN_TABLE_30_LSB) & BB_RXCAL_TX_GAIN_TABLE_30_RXCAL_TX_GAIN_TABLE_30_MASK) #define BB_RXCAL_TX_GAIN_TABLE_30_RXCAL_TX_GAIN_TABLE_30_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_30_ADDRESS (0x1278 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_30_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_30_RESET 0x0 // 0x127c (BB_RXCAL_TX_GAIN_TABLE_31) #define BB_RXCAL_TX_GAIN_TABLE_31_RXCAL_TX_GAIN_TABLE_31_LSB 0 #define BB_RXCAL_TX_GAIN_TABLE_31_RXCAL_TX_GAIN_TABLE_31_MSB 20 #define BB_RXCAL_TX_GAIN_TABLE_31_RXCAL_TX_GAIN_TABLE_31_MASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_31_RXCAL_TX_GAIN_TABLE_31_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_31_RXCAL_TX_GAIN_TABLE_31_MASK) >> BB_RXCAL_TX_GAIN_TABLE_31_RXCAL_TX_GAIN_TABLE_31_LSB) #define BB_RXCAL_TX_GAIN_TABLE_31_RXCAL_TX_GAIN_TABLE_31_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_31_RXCAL_TX_GAIN_TABLE_31_LSB) & BB_RXCAL_TX_GAIN_TABLE_31_RXCAL_TX_GAIN_TABLE_31_MASK) #define BB_RXCAL_TX_GAIN_TABLE_31_RXCAL_TX_GAIN_TABLE_31_RESET 0x0 #define BB_RXCAL_TX_GAIN_TABLE_31_ADDRESS (0x127c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_TX_GAIN_TABLE_31_RSTMASK 0x1fffff #define BB_RXCAL_TX_GAIN_TABLE_31_RESET 0x0 // 0x1280 (BB_RXCAL_RX_GAIN_TABLE_0) #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_GAIN_DELTA_DB_TABLE_0_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_GAIN_DELTA_DB_TABLE_0_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_GAIN_DELTA_DB_TABLE_0_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_GAIN_DELTA_DB_TABLE_0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_GAIN_DELTA_DB_TABLE_0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_GAIN_DELTA_DB_TABLE_0_LSB) #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_GAIN_DELTA_DB_TABLE_0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_GAIN_DELTA_DB_TABLE_0_LSB) & BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_GAIN_DELTA_DB_TABLE_0_MASK) #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_GAIN_DELTA_DB_TABLE_0_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_RX_GAIN_TABLE_0_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_RX_GAIN_TABLE_0_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_RX_GAIN_TABLE_0_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_RX_GAIN_TABLE_0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_RX_GAIN_TABLE_0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_RX_GAIN_TABLE_0_LSB) #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_RX_GAIN_TABLE_0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_RX_GAIN_TABLE_0_LSB) & BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_RX_GAIN_TABLE_0_MASK) #define BB_RXCAL_RX_GAIN_TABLE_0_RXCAL_RX_GAIN_TABLE_0_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_0_ADDRESS (0x1280 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_0_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_0_RESET 0x0 // 0x1284 (BB_RXCAL_RX_GAIN_TABLE_1) #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_GAIN_DELTA_DB_TABLE_1_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_GAIN_DELTA_DB_TABLE_1_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_GAIN_DELTA_DB_TABLE_1_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_GAIN_DELTA_DB_TABLE_1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_GAIN_DELTA_DB_TABLE_1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_GAIN_DELTA_DB_TABLE_1_LSB) #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_GAIN_DELTA_DB_TABLE_1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_GAIN_DELTA_DB_TABLE_1_LSB) & BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_GAIN_DELTA_DB_TABLE_1_MASK) #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_GAIN_DELTA_DB_TABLE_1_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_RX_GAIN_TABLE_1_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_RX_GAIN_TABLE_1_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_RX_GAIN_TABLE_1_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_RX_GAIN_TABLE_1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_RX_GAIN_TABLE_1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_RX_GAIN_TABLE_1_LSB) #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_RX_GAIN_TABLE_1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_RX_GAIN_TABLE_1_LSB) & BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_RX_GAIN_TABLE_1_MASK) #define BB_RXCAL_RX_GAIN_TABLE_1_RXCAL_RX_GAIN_TABLE_1_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_1_ADDRESS (0x1284 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_1_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_1_RESET 0x0 // 0x1288 (BB_RXCAL_RX_GAIN_TABLE_2) #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_GAIN_DELTA_DB_TABLE_2_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_GAIN_DELTA_DB_TABLE_2_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_GAIN_DELTA_DB_TABLE_2_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_GAIN_DELTA_DB_TABLE_2_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_GAIN_DELTA_DB_TABLE_2_MASK) >> BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_GAIN_DELTA_DB_TABLE_2_LSB) #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_GAIN_DELTA_DB_TABLE_2_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_GAIN_DELTA_DB_TABLE_2_LSB) & BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_GAIN_DELTA_DB_TABLE_2_MASK) #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_GAIN_DELTA_DB_TABLE_2_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_RX_GAIN_TABLE_2_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_RX_GAIN_TABLE_2_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_RX_GAIN_TABLE_2_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_RX_GAIN_TABLE_2_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_RX_GAIN_TABLE_2_MASK) >> BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_RX_GAIN_TABLE_2_LSB) #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_RX_GAIN_TABLE_2_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_RX_GAIN_TABLE_2_LSB) & BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_RX_GAIN_TABLE_2_MASK) #define BB_RXCAL_RX_GAIN_TABLE_2_RXCAL_RX_GAIN_TABLE_2_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_2_ADDRESS (0x1288 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_2_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_2_RESET 0x0 // 0x128c (BB_RXCAL_RX_GAIN_TABLE_3) #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_GAIN_DELTA_DB_TABLE_3_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_GAIN_DELTA_DB_TABLE_3_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_GAIN_DELTA_DB_TABLE_3_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_GAIN_DELTA_DB_TABLE_3_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_GAIN_DELTA_DB_TABLE_3_MASK) >> BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_GAIN_DELTA_DB_TABLE_3_LSB) #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_GAIN_DELTA_DB_TABLE_3_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_GAIN_DELTA_DB_TABLE_3_LSB) & BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_GAIN_DELTA_DB_TABLE_3_MASK) #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_GAIN_DELTA_DB_TABLE_3_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_RX_GAIN_TABLE_3_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_RX_GAIN_TABLE_3_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_RX_GAIN_TABLE_3_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_RX_GAIN_TABLE_3_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_RX_GAIN_TABLE_3_MASK) >> BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_RX_GAIN_TABLE_3_LSB) #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_RX_GAIN_TABLE_3_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_RX_GAIN_TABLE_3_LSB) & BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_RX_GAIN_TABLE_3_MASK) #define BB_RXCAL_RX_GAIN_TABLE_3_RXCAL_RX_GAIN_TABLE_3_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_3_ADDRESS (0x128c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_3_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_3_RESET 0x0 // 0x1290 (BB_RXCAL_RX_GAIN_TABLE_4) #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_GAIN_DELTA_DB_TABLE_4_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_GAIN_DELTA_DB_TABLE_4_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_GAIN_DELTA_DB_TABLE_4_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_GAIN_DELTA_DB_TABLE_4_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_GAIN_DELTA_DB_TABLE_4_MASK) >> BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_GAIN_DELTA_DB_TABLE_4_LSB) #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_GAIN_DELTA_DB_TABLE_4_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_GAIN_DELTA_DB_TABLE_4_LSB) & BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_GAIN_DELTA_DB_TABLE_4_MASK) #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_GAIN_DELTA_DB_TABLE_4_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_RX_GAIN_TABLE_4_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_RX_GAIN_TABLE_4_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_RX_GAIN_TABLE_4_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_RX_GAIN_TABLE_4_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_RX_GAIN_TABLE_4_MASK) >> BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_RX_GAIN_TABLE_4_LSB) #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_RX_GAIN_TABLE_4_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_RX_GAIN_TABLE_4_LSB) & BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_RX_GAIN_TABLE_4_MASK) #define BB_RXCAL_RX_GAIN_TABLE_4_RXCAL_RX_GAIN_TABLE_4_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_4_ADDRESS (0x1290 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_4_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_4_RESET 0x0 // 0x1294 (BB_RXCAL_RX_GAIN_TABLE_5) #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_GAIN_DELTA_DB_TABLE_5_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_GAIN_DELTA_DB_TABLE_5_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_GAIN_DELTA_DB_TABLE_5_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_GAIN_DELTA_DB_TABLE_5_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_GAIN_DELTA_DB_TABLE_5_MASK) >> BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_GAIN_DELTA_DB_TABLE_5_LSB) #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_GAIN_DELTA_DB_TABLE_5_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_GAIN_DELTA_DB_TABLE_5_LSB) & BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_GAIN_DELTA_DB_TABLE_5_MASK) #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_GAIN_DELTA_DB_TABLE_5_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_RX_GAIN_TABLE_5_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_RX_GAIN_TABLE_5_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_RX_GAIN_TABLE_5_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_RX_GAIN_TABLE_5_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_RX_GAIN_TABLE_5_MASK) >> BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_RX_GAIN_TABLE_5_LSB) #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_RX_GAIN_TABLE_5_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_RX_GAIN_TABLE_5_LSB) & BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_RX_GAIN_TABLE_5_MASK) #define BB_RXCAL_RX_GAIN_TABLE_5_RXCAL_RX_GAIN_TABLE_5_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_5_ADDRESS (0x1294 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_5_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_5_RESET 0x0 // 0x1298 (BB_RXCAL_RX_GAIN_TABLE_6) #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_GAIN_DELTA_DB_TABLE_6_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_GAIN_DELTA_DB_TABLE_6_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_GAIN_DELTA_DB_TABLE_6_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_GAIN_DELTA_DB_TABLE_6_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_GAIN_DELTA_DB_TABLE_6_MASK) >> BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_GAIN_DELTA_DB_TABLE_6_LSB) #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_GAIN_DELTA_DB_TABLE_6_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_GAIN_DELTA_DB_TABLE_6_LSB) & BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_GAIN_DELTA_DB_TABLE_6_MASK) #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_GAIN_DELTA_DB_TABLE_6_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_RX_GAIN_TABLE_6_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_RX_GAIN_TABLE_6_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_RX_GAIN_TABLE_6_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_RX_GAIN_TABLE_6_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_RX_GAIN_TABLE_6_MASK) >> BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_RX_GAIN_TABLE_6_LSB) #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_RX_GAIN_TABLE_6_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_RX_GAIN_TABLE_6_LSB) & BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_RX_GAIN_TABLE_6_MASK) #define BB_RXCAL_RX_GAIN_TABLE_6_RXCAL_RX_GAIN_TABLE_6_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_6_ADDRESS (0x1298 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_6_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_6_RESET 0x0 // 0x129c (BB_RXCAL_RX_GAIN_TABLE_7) #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_GAIN_DELTA_DB_TABLE_7_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_GAIN_DELTA_DB_TABLE_7_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_GAIN_DELTA_DB_TABLE_7_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_GAIN_DELTA_DB_TABLE_7_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_GAIN_DELTA_DB_TABLE_7_MASK) >> BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_GAIN_DELTA_DB_TABLE_7_LSB) #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_GAIN_DELTA_DB_TABLE_7_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_GAIN_DELTA_DB_TABLE_7_LSB) & BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_GAIN_DELTA_DB_TABLE_7_MASK) #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_GAIN_DELTA_DB_TABLE_7_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_RX_GAIN_TABLE_7_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_RX_GAIN_TABLE_7_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_RX_GAIN_TABLE_7_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_RX_GAIN_TABLE_7_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_RX_GAIN_TABLE_7_MASK) >> BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_RX_GAIN_TABLE_7_LSB) #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_RX_GAIN_TABLE_7_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_RX_GAIN_TABLE_7_LSB) & BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_RX_GAIN_TABLE_7_MASK) #define BB_RXCAL_RX_GAIN_TABLE_7_RXCAL_RX_GAIN_TABLE_7_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_7_ADDRESS (0x129c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_7_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_7_RESET 0x0 // 0x12a0 (BB_RXCAL_RX_GAIN_TABLE_8) #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_GAIN_DELTA_DB_TABLE_8_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_GAIN_DELTA_DB_TABLE_8_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_GAIN_DELTA_DB_TABLE_8_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_GAIN_DELTA_DB_TABLE_8_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_GAIN_DELTA_DB_TABLE_8_MASK) >> BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_GAIN_DELTA_DB_TABLE_8_LSB) #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_GAIN_DELTA_DB_TABLE_8_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_GAIN_DELTA_DB_TABLE_8_LSB) & BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_GAIN_DELTA_DB_TABLE_8_MASK) #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_GAIN_DELTA_DB_TABLE_8_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_RX_GAIN_TABLE_8_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_RX_GAIN_TABLE_8_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_RX_GAIN_TABLE_8_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_RX_GAIN_TABLE_8_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_RX_GAIN_TABLE_8_MASK) >> BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_RX_GAIN_TABLE_8_LSB) #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_RX_GAIN_TABLE_8_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_RX_GAIN_TABLE_8_LSB) & BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_RX_GAIN_TABLE_8_MASK) #define BB_RXCAL_RX_GAIN_TABLE_8_RXCAL_RX_GAIN_TABLE_8_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_8_ADDRESS (0x12a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_8_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_8_RESET 0x0 // 0x12a4 (BB_RXCAL_RX_GAIN_TABLE_9) #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_GAIN_DELTA_DB_TABLE_9_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_GAIN_DELTA_DB_TABLE_9_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_GAIN_DELTA_DB_TABLE_9_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_GAIN_DELTA_DB_TABLE_9_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_GAIN_DELTA_DB_TABLE_9_MASK) >> BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_GAIN_DELTA_DB_TABLE_9_LSB) #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_GAIN_DELTA_DB_TABLE_9_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_GAIN_DELTA_DB_TABLE_9_LSB) & BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_GAIN_DELTA_DB_TABLE_9_MASK) #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_GAIN_DELTA_DB_TABLE_9_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_RX_GAIN_TABLE_9_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_RX_GAIN_TABLE_9_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_RX_GAIN_TABLE_9_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_RX_GAIN_TABLE_9_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_RX_GAIN_TABLE_9_MASK) >> BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_RX_GAIN_TABLE_9_LSB) #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_RX_GAIN_TABLE_9_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_RX_GAIN_TABLE_9_LSB) & BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_RX_GAIN_TABLE_9_MASK) #define BB_RXCAL_RX_GAIN_TABLE_9_RXCAL_RX_GAIN_TABLE_9_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_9_ADDRESS (0x12a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_9_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_9_RESET 0x0 // 0x12a8 (BB_RXCAL_RX_GAIN_TABLE_10) #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_GAIN_DELTA_DB_TABLE_10_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_GAIN_DELTA_DB_TABLE_10_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_GAIN_DELTA_DB_TABLE_10_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_GAIN_DELTA_DB_TABLE_10_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_GAIN_DELTA_DB_TABLE_10_MASK) >> BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_GAIN_DELTA_DB_TABLE_10_LSB) #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_GAIN_DELTA_DB_TABLE_10_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_GAIN_DELTA_DB_TABLE_10_LSB) & BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_GAIN_DELTA_DB_TABLE_10_MASK) #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_GAIN_DELTA_DB_TABLE_10_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_RX_GAIN_TABLE_10_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_RX_GAIN_TABLE_10_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_RX_GAIN_TABLE_10_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_RX_GAIN_TABLE_10_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_RX_GAIN_TABLE_10_MASK) >> BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_RX_GAIN_TABLE_10_LSB) #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_RX_GAIN_TABLE_10_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_RX_GAIN_TABLE_10_LSB) & BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_RX_GAIN_TABLE_10_MASK) #define BB_RXCAL_RX_GAIN_TABLE_10_RXCAL_RX_GAIN_TABLE_10_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_10_ADDRESS (0x12a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_10_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_10_RESET 0x0 // 0x12ac (BB_RXCAL_RX_GAIN_TABLE_11) #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_GAIN_DELTA_DB_TABLE_11_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_GAIN_DELTA_DB_TABLE_11_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_GAIN_DELTA_DB_TABLE_11_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_GAIN_DELTA_DB_TABLE_11_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_GAIN_DELTA_DB_TABLE_11_MASK) >> BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_GAIN_DELTA_DB_TABLE_11_LSB) #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_GAIN_DELTA_DB_TABLE_11_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_GAIN_DELTA_DB_TABLE_11_LSB) & BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_GAIN_DELTA_DB_TABLE_11_MASK) #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_GAIN_DELTA_DB_TABLE_11_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_RX_GAIN_TABLE_11_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_RX_GAIN_TABLE_11_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_RX_GAIN_TABLE_11_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_RX_GAIN_TABLE_11_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_RX_GAIN_TABLE_11_MASK) >> BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_RX_GAIN_TABLE_11_LSB) #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_RX_GAIN_TABLE_11_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_RX_GAIN_TABLE_11_LSB) & BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_RX_GAIN_TABLE_11_MASK) #define BB_RXCAL_RX_GAIN_TABLE_11_RXCAL_RX_GAIN_TABLE_11_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_11_ADDRESS (0x12ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_11_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_11_RESET 0x0 // 0x12b0 (BB_RXCAL_RX_GAIN_TABLE_12) #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_GAIN_DELTA_DB_TABLE_12_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_GAIN_DELTA_DB_TABLE_12_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_GAIN_DELTA_DB_TABLE_12_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_GAIN_DELTA_DB_TABLE_12_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_GAIN_DELTA_DB_TABLE_12_MASK) >> BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_GAIN_DELTA_DB_TABLE_12_LSB) #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_GAIN_DELTA_DB_TABLE_12_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_GAIN_DELTA_DB_TABLE_12_LSB) & BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_GAIN_DELTA_DB_TABLE_12_MASK) #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_GAIN_DELTA_DB_TABLE_12_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_RX_GAIN_TABLE_12_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_RX_GAIN_TABLE_12_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_RX_GAIN_TABLE_12_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_RX_GAIN_TABLE_12_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_RX_GAIN_TABLE_12_MASK) >> BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_RX_GAIN_TABLE_12_LSB) #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_RX_GAIN_TABLE_12_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_RX_GAIN_TABLE_12_LSB) & BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_RX_GAIN_TABLE_12_MASK) #define BB_RXCAL_RX_GAIN_TABLE_12_RXCAL_RX_GAIN_TABLE_12_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_12_ADDRESS (0x12b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_12_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_12_RESET 0x0 // 0x12b4 (BB_RXCAL_RX_GAIN_TABLE_13) #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_GAIN_DELTA_DB_TABLE_13_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_GAIN_DELTA_DB_TABLE_13_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_GAIN_DELTA_DB_TABLE_13_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_GAIN_DELTA_DB_TABLE_13_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_GAIN_DELTA_DB_TABLE_13_MASK) >> BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_GAIN_DELTA_DB_TABLE_13_LSB) #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_GAIN_DELTA_DB_TABLE_13_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_GAIN_DELTA_DB_TABLE_13_LSB) & BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_GAIN_DELTA_DB_TABLE_13_MASK) #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_GAIN_DELTA_DB_TABLE_13_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_RX_GAIN_TABLE_13_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_RX_GAIN_TABLE_13_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_RX_GAIN_TABLE_13_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_RX_GAIN_TABLE_13_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_RX_GAIN_TABLE_13_MASK) >> BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_RX_GAIN_TABLE_13_LSB) #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_RX_GAIN_TABLE_13_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_RX_GAIN_TABLE_13_LSB) & BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_RX_GAIN_TABLE_13_MASK) #define BB_RXCAL_RX_GAIN_TABLE_13_RXCAL_RX_GAIN_TABLE_13_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_13_ADDRESS (0x12b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_13_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_13_RESET 0x0 // 0x12b8 (BB_RXCAL_RX_GAIN_TABLE_14) #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_GAIN_DELTA_DB_TABLE_14_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_GAIN_DELTA_DB_TABLE_14_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_GAIN_DELTA_DB_TABLE_14_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_GAIN_DELTA_DB_TABLE_14_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_GAIN_DELTA_DB_TABLE_14_MASK) >> BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_GAIN_DELTA_DB_TABLE_14_LSB) #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_GAIN_DELTA_DB_TABLE_14_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_GAIN_DELTA_DB_TABLE_14_LSB) & BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_GAIN_DELTA_DB_TABLE_14_MASK) #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_GAIN_DELTA_DB_TABLE_14_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_RX_GAIN_TABLE_14_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_RX_GAIN_TABLE_14_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_RX_GAIN_TABLE_14_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_RX_GAIN_TABLE_14_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_RX_GAIN_TABLE_14_MASK) >> BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_RX_GAIN_TABLE_14_LSB) #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_RX_GAIN_TABLE_14_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_RX_GAIN_TABLE_14_LSB) & BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_RX_GAIN_TABLE_14_MASK) #define BB_RXCAL_RX_GAIN_TABLE_14_RXCAL_RX_GAIN_TABLE_14_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_14_ADDRESS (0x12b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_14_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_14_RESET 0x0 // 0x12bc (BB_RXCAL_RX_GAIN_TABLE_15) #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_GAIN_DELTA_DB_TABLE_15_LSB 12 #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_GAIN_DELTA_DB_TABLE_15_MSB 17 #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_GAIN_DELTA_DB_TABLE_15_MASK 0x3f000 #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_GAIN_DELTA_DB_TABLE_15_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_GAIN_DELTA_DB_TABLE_15_MASK) >> BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_GAIN_DELTA_DB_TABLE_15_LSB) #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_GAIN_DELTA_DB_TABLE_15_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_GAIN_DELTA_DB_TABLE_15_LSB) & BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_GAIN_DELTA_DB_TABLE_15_MASK) #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_GAIN_DELTA_DB_TABLE_15_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_RX_GAIN_TABLE_15_LSB 0 #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_RX_GAIN_TABLE_15_MSB 9 #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_RX_GAIN_TABLE_15_MASK 0x3ff #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_RX_GAIN_TABLE_15_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_RX_GAIN_TABLE_15_MASK) >> BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_RX_GAIN_TABLE_15_LSB) #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_RX_GAIN_TABLE_15_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_RX_GAIN_TABLE_15_LSB) & BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_RX_GAIN_TABLE_15_MASK) #define BB_RXCAL_RX_GAIN_TABLE_15_RXCAL_RX_GAIN_TABLE_15_RESET 0x0 #define BB_RXCAL_RX_GAIN_TABLE_15_ADDRESS (0x12bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_RXCAL_RX_GAIN_TABLE_15_RSTMASK 0x3f3ff #define BB_RXCAL_RX_GAIN_TABLE_15_RESET 0x0 // 0x1300 (BB_SM_HC_PREEMP_LUT) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_ADDRESS (0x1300 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_RESET 0x0 // 0x1300 (BB_SM_HC_PREEMP_LUT_0) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_0_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_0_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_0_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_0_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_0_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_0_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_0_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_0_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_0_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_0_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_0_ADDRESS (0x1300 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_0_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_0_RESET 0x0 // 0x1304 (BB_SM_HC_PREEMP_LUT_1) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_1_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_1_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_1_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_1_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_1_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_1_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_1_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_1_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_1_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_1_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_1_ADDRESS (0x1304 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_1_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_1_RESET 0x0 // 0x1308 (BB_SM_HC_PREEMP_LUT_2) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_2_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_2_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_2_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_2_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_2_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_2_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_2_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_2_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_2_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_2_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_2_ADDRESS (0x1308 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_2_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_2_RESET 0x0 // 0x130c (BB_SM_HC_PREEMP_LUT_3) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_3_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_3_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_3_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_3_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_3_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_3_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_3_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_3_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_3_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_3_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_3_ADDRESS (0x130c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_3_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_3_RESET 0x0 // 0x1310 (BB_SM_HC_PREEMP_LUT_4) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_4_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_4_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_4_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_4_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_4_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_4_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_4_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_4_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_4_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_4_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_4_ADDRESS (0x1310 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_4_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_4_RESET 0x0 // 0x1314 (BB_SM_HC_PREEMP_LUT_5) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_5_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_5_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_5_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_5_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_5_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_5_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_5_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_5_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_5_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_5_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_5_ADDRESS (0x1314 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_5_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_5_RESET 0x0 // 0x1318 (BB_SM_HC_PREEMP_LUT_6) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_6_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_6_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_6_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_6_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_6_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_6_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_6_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_6_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_6_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_6_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_6_ADDRESS (0x1318 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_6_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_6_RESET 0x0 // 0x131c (BB_SM_HC_PREEMP_LUT_7) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_7_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_7_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_7_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_7_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_7_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_7_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_7_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_7_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_7_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_7_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_7_ADDRESS (0x131c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_7_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_7_RESET 0x0 // 0x1320 (BB_SM_HC_PREEMP_LUT_8) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_8_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_8_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_8_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_8_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_8_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_8_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_8_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_8_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_8_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_8_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_8_ADDRESS (0x1320 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_8_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_8_RESET 0x0 // 0x1324 (BB_SM_HC_PREEMP_LUT_9) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_9_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_9_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_9_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_9_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_9_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_9_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_9_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_9_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_9_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_9_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_9_ADDRESS (0x1324 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_9_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_9_RESET 0x0 // 0x1328 (BB_SM_HC_PREEMP_LUT_10) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_10_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_10_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_10_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_10_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_10_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_10_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_10_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_10_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_10_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_10_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_10_ADDRESS (0x1328 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_10_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_10_RESET 0x0 // 0x132c (BB_SM_HC_PREEMP_LUT_11) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_11_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_11_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_11_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_11_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_11_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_11_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_11_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_11_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_11_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_11_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_11_ADDRESS (0x132c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_11_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_11_RESET 0x0 // 0x1330 (BB_SM_HC_PREEMP_LUT_12) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_12_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_12_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_12_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_12_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_12_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_12_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_12_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_12_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_12_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_12_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_12_ADDRESS (0x1330 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_12_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_12_RESET 0x0 // 0x1334 (BB_SM_HC_PREEMP_LUT_13) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_13_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_13_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_13_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_13_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_13_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_13_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_13_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_13_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_13_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_13_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_13_ADDRESS (0x1334 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_13_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_13_RESET 0x0 // 0x1338 (BB_SM_HC_PREEMP_LUT_14) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_14_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_14_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_14_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_14_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_14_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_14_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_14_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_14_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_14_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_14_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_14_ADDRESS (0x1338 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_14_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_14_RESET 0x0 // 0x133c (BB_SM_HC_PREEMP_LUT_15) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_15_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_15_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_15_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_15_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_15_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_15_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_15_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_15_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_15_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_15_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_15_ADDRESS (0x133c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_15_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_15_RESET 0x0 // 0x1340 (BB_SM_HC_PREEMP_LUT_16) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_16_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_16_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_16_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_16_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_16_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_16_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_16_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_16_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_16_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_16_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_16_ADDRESS (0x1340 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_16_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_16_RESET 0x0 // 0x1344 (BB_SM_HC_PREEMP_LUT_17) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_17_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_17_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_17_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_17_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_17_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_17_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_17_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_17_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_17_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_17_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_17_ADDRESS (0x1344 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_17_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_17_RESET 0x0 // 0x1348 (BB_SM_HC_PREEMP_LUT_18) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_18_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_18_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_18_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_18_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_18_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_18_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_18_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_18_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_18_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_18_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_18_ADDRESS (0x1348 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_18_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_18_RESET 0x0 // 0x134c (BB_SM_HC_PREEMP_LUT_19) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_19_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_19_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_19_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_19_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_19_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_19_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_19_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_19_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_19_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_19_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_19_ADDRESS (0x134c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_19_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_19_RESET 0x0 // 0x1350 (BB_SM_HC_PREEMP_LUT_20) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_20_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_20_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_20_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_20_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_20_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_20_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_20_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_20_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_20_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_20_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_20_ADDRESS (0x1350 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_20_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_20_RESET 0x0 // 0x1354 (BB_SM_HC_PREEMP_LUT_21) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_21_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_21_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_21_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_21_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_21_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_21_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_21_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_21_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_21_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_21_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_21_ADDRESS (0x1354 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_21_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_21_RESET 0x0 // 0x1358 (BB_SM_HC_PREEMP_LUT_22) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_22_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_22_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_22_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_22_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_22_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_22_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_22_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_22_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_22_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_22_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_22_ADDRESS (0x1358 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_22_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_22_RESET 0x0 // 0x135c (BB_SM_HC_PREEMP_LUT_23) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_23_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_23_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_23_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_23_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_23_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_23_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_23_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_23_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_23_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_23_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_23_ADDRESS (0x135c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_23_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_23_RESET 0x0 // 0x1360 (BB_SM_HC_PREEMP_LUT_24) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_24_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_24_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_24_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_24_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_24_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_24_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_24_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_24_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_24_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_24_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_24_ADDRESS (0x1360 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_24_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_24_RESET 0x0 // 0x1364 (BB_SM_HC_PREEMP_LUT_25) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_25_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_25_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_25_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_25_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_25_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_25_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_25_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_25_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_25_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_25_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_25_ADDRESS (0x1364 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_25_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_25_RESET 0x0 // 0x1368 (BB_SM_HC_PREEMP_LUT_26) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_26_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_26_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_26_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_26_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_26_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_26_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_26_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_26_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_26_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_26_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_26_ADDRESS (0x1368 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_26_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_26_RESET 0x0 // 0x136c (BB_SM_HC_PREEMP_LUT_27) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_27_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_27_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_27_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_27_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_27_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_27_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_27_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_27_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_27_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_27_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_27_ADDRESS (0x136c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_27_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_27_RESET 0x0 // 0x1370 (BB_SM_HC_PREEMP_LUT_28) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_28_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_28_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_28_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_28_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_28_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_28_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_28_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_28_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_28_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_28_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_28_ADDRESS (0x1370 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_28_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_28_RESET 0x0 // 0x1374 (BB_SM_HC_PREEMP_LUT_29) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_29_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_29_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_29_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_29_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_29_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_29_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_29_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_29_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_29_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_29_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_29_ADDRESS (0x1374 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_29_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_29_RESET 0x0 // 0x1378 (BB_SM_HC_PREEMP_LUT_30) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_30_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_30_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_30_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_30_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_30_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_30_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_30_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_30_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_30_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_30_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_30_ADDRESS (0x1378 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_30_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_30_RESET 0x0 // 0x137c (BB_SM_HC_PREEMP_LUT_31) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_31_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_31_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_31_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_31_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_31_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_31_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_31_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_31_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_31_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_31_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_31_ADDRESS (0x137c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_31_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_31_RESET 0x0 // 0x1380 (BB_SM_HC_PREEMP_LUT_32) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_32_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_32_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_32_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_32_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_32_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_32_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_32_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_32_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_32_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_32_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_32_ADDRESS (0x1380 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_32_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_32_RESET 0x0 // 0x1384 (BB_SM_HC_PREEMP_LUT_33) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_33_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_33_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_33_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_33_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_33_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_33_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_33_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_33_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_33_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_33_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_33_ADDRESS (0x1384 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_33_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_33_RESET 0x0 // 0x1388 (BB_SM_HC_PREEMP_LUT_34) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_34_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_34_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_34_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_34_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_34_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_34_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_34_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_34_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_34_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_34_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_34_ADDRESS (0x1388 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_34_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_34_RESET 0x0 // 0x138c (BB_SM_HC_PREEMP_LUT_35) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_35_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_35_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_35_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_35_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_35_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_35_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_35_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_35_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_35_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_35_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_35_ADDRESS (0x138c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_35_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_35_RESET 0x0 // 0x1390 (BB_SM_HC_PREEMP_LUT_36) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_36_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_36_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_36_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_36_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_36_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_36_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_36_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_36_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_36_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_36_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_36_ADDRESS (0x1390 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_36_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_36_RESET 0x0 // 0x1394 (BB_SM_HC_PREEMP_LUT_37) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_37_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_37_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_37_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_37_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_37_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_37_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_37_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_37_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_37_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_37_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_37_ADDRESS (0x1394 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_37_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_37_RESET 0x0 // 0x1398 (BB_SM_HC_PREEMP_LUT_38) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_38_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_38_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_38_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_38_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_38_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_38_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_38_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_38_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_38_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_38_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_38_ADDRESS (0x1398 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_38_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_38_RESET 0x0 // 0x139c (BB_SM_HC_PREEMP_LUT_39) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_39_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_39_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_39_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_39_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_39_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_39_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_39_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_39_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_39_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_39_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_39_ADDRESS (0x139c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_39_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_39_RESET 0x0 // 0x13a0 (BB_SM_HC_PREEMP_LUT_40) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_40_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_40_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_40_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_40_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_40_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_40_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_40_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_40_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_40_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_40_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_40_ADDRESS (0x13a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_40_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_40_RESET 0x0 // 0x13a4 (BB_SM_HC_PREEMP_LUT_41) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_41_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_41_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_41_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_41_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_41_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_41_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_41_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_41_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_41_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_41_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_41_ADDRESS (0x13a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_41_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_41_RESET 0x0 // 0x13a8 (BB_SM_HC_PREEMP_LUT_42) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_42_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_42_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_42_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_42_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_42_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_42_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_42_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_42_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_42_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_42_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_42_ADDRESS (0x13a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_42_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_42_RESET 0x0 // 0x13ac (BB_SM_HC_PREEMP_LUT_43) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_43_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_43_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_43_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_43_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_43_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_43_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_43_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_43_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_43_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_43_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_43_ADDRESS (0x13ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_43_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_43_RESET 0x0 // 0x13b0 (BB_SM_HC_PREEMP_LUT_44) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_44_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_44_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_44_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_44_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_44_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_44_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_44_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_44_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_44_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_44_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_44_ADDRESS (0x13b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_44_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_44_RESET 0x0 // 0x13b4 (BB_SM_HC_PREEMP_LUT_45) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_45_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_45_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_45_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_45_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_45_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_45_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_45_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_45_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_45_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_45_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_45_ADDRESS (0x13b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_45_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_45_RESET 0x0 // 0x13b8 (BB_SM_HC_PREEMP_LUT_46) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_46_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_46_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_46_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_46_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_46_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_46_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_46_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_46_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_46_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_46_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_46_ADDRESS (0x13b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_46_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_46_RESET 0x0 // 0x13bc (BB_SM_HC_PREEMP_LUT_47) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_47_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_47_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_47_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_47_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_47_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_47_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_47_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_47_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_47_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_47_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_47_ADDRESS (0x13bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_47_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_47_RESET 0x0 // 0x13c0 (BB_SM_HC_PREEMP_LUT_48) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_48_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_48_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_48_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_48_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_48_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_48_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_48_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_48_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_48_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_48_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_48_ADDRESS (0x13c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_48_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_48_RESET 0x0 // 0x13c4 (BB_SM_HC_PREEMP_LUT_49) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_49_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_49_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_49_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_49_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_49_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_49_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_49_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_49_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_49_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_49_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_49_ADDRESS (0x13c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_49_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_49_RESET 0x0 // 0x13c8 (BB_SM_HC_PREEMP_LUT_50) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_50_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_50_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_50_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_50_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_50_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_50_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_50_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_50_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_50_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_50_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_50_ADDRESS (0x13c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_50_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_50_RESET 0x0 // 0x13cc (BB_SM_HC_PREEMP_LUT_51) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_51_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_51_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_51_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_51_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_51_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_51_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_51_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_51_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_51_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_51_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_51_ADDRESS (0x13cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_51_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_51_RESET 0x0 // 0x13d0 (BB_SM_HC_PREEMP_LUT_52) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_52_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_52_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_52_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_52_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_52_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_52_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_52_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_52_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_52_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_52_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_52_ADDRESS (0x13d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_52_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_52_RESET 0x0 // 0x13d4 (BB_SM_HC_PREEMP_LUT_53) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_53_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_53_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_53_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_53_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_53_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_53_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_53_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_53_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_53_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_53_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_53_ADDRESS (0x13d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_53_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_53_RESET 0x0 // 0x13d8 (BB_SM_HC_PREEMP_LUT_54) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_54_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_54_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_54_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_54_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_54_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_54_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_54_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_54_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_54_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_54_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_54_ADDRESS (0x13d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_54_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_54_RESET 0x0 // 0x13dc (BB_SM_HC_PREEMP_LUT_55) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_55_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_55_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_55_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_55_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_55_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_55_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_55_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_55_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_55_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_55_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_55_ADDRESS (0x13dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_55_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_55_RESET 0x0 // 0x13e0 (BB_SM_HC_PREEMP_LUT_56) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_56_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_56_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_56_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_56_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_56_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_56_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_56_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_56_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_56_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_56_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_56_ADDRESS (0x13e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_56_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_56_RESET 0x0 // 0x13e4 (BB_SM_HC_PREEMP_LUT_57) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_57_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_57_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_57_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_57_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_57_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_57_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_57_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_57_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_57_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_57_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_57_ADDRESS (0x13e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_57_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_57_RESET 0x0 // 0x13e8 (BB_SM_HC_PREEMP_LUT_58) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_58_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_58_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_58_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_58_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_58_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_58_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_58_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_58_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_58_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_58_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_58_ADDRESS (0x13e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_58_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_58_RESET 0x0 // 0x13ec (BB_SM_HC_PREEMP_LUT_59) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_59_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_59_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_59_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_59_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_59_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_59_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_59_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_59_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_59_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_59_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_59_ADDRESS (0x13ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_59_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_59_RESET 0x0 // 0x13f0 (BB_SM_HC_PREEMP_LUT_60) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_60_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_60_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_60_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_60_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_60_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_60_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_60_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_60_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_60_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_60_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_60_ADDRESS (0x13f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_60_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_60_RESET 0x0 // 0x13f4 (BB_SM_HC_PREEMP_LUT_61) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_61_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_61_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_61_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_61_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_61_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_61_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_61_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_61_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_61_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_61_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_61_ADDRESS (0x13f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_61_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_61_RESET 0x0 // 0x13f8 (BB_SM_HC_PREEMP_LUT_62) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_62_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_62_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_62_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_62_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_62_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_62_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_62_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_62_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_62_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_62_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_62_ADDRESS (0x13f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_62_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_62_RESET 0x0 // 0x13fc (BB_SM_HC_PREEMP_LUT_63) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_63_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_63_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_63_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_63_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_63_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_63_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_63_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_63_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_63_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_63_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_63_ADDRESS (0x13fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_63_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_63_RESET 0x0 // 0x1400 (BB_SM_HC_PREEMP_LUT_64) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_64_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_64_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_64_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_64_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_64_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_64_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_64_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_64_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_64_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_64_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_64_ADDRESS (0x1400 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_64_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_64_RESET 0x0 // 0x1404 (BB_SM_HC_PREEMP_LUT_65) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_65_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_65_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_65_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_65_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_65_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_65_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_65_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_65_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_65_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_65_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_65_ADDRESS (0x1404 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_65_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_65_RESET 0x0 // 0x1408 (BB_SM_HC_PREEMP_LUT_66) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_66_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_66_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_66_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_66_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_66_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_66_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_66_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_66_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_66_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_66_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_66_ADDRESS (0x1408 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_66_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_66_RESET 0x0 // 0x140c (BB_SM_HC_PREEMP_LUT_67) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_67_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_67_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_67_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_67_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_67_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_67_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_67_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_67_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_67_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_67_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_67_ADDRESS (0x140c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_67_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_67_RESET 0x0 // 0x1410 (BB_SM_HC_PREEMP_LUT_68) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_68_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_68_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_68_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_68_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_68_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_68_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_68_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_68_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_68_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_68_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_68_ADDRESS (0x1410 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_68_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_68_RESET 0x0 // 0x1414 (BB_SM_HC_PREEMP_LUT_69) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_69_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_69_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_69_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_69_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_69_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_69_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_69_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_69_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_69_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_69_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_69_ADDRESS (0x1414 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_69_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_69_RESET 0x0 // 0x1418 (BB_SM_HC_PREEMP_LUT_70) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_70_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_70_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_70_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_70_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_70_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_70_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_70_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_70_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_70_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_70_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_70_ADDRESS (0x1418 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_70_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_70_RESET 0x0 // 0x141c (BB_SM_HC_PREEMP_LUT_71) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_71_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_71_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_71_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_71_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_71_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_71_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_71_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_71_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_71_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_71_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_71_ADDRESS (0x141c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_71_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_71_RESET 0x0 // 0x1420 (BB_SM_HC_PREEMP_LUT_72) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_72_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_72_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_72_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_72_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_72_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_72_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_72_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_72_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_72_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_72_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_72_ADDRESS (0x1420 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_72_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_72_RESET 0x0 // 0x1424 (BB_SM_HC_PREEMP_LUT_73) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_73_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_73_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_73_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_73_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_73_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_73_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_73_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_73_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_73_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_73_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_73_ADDRESS (0x1424 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_73_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_73_RESET 0x0 // 0x1428 (BB_SM_HC_PREEMP_LUT_74) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_74_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_74_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_74_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_74_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_74_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_74_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_74_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_74_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_74_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_74_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_74_ADDRESS (0x1428 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_74_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_74_RESET 0x0 // 0x142c (BB_SM_HC_PREEMP_LUT_75) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_75_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_75_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_75_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_75_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_75_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_75_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_75_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_75_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_75_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_75_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_75_ADDRESS (0x142c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_75_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_75_RESET 0x0 // 0x1430 (BB_SM_HC_PREEMP_LUT_76) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_76_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_76_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_76_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_76_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_76_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_76_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_76_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_76_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_76_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_76_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_76_ADDRESS (0x1430 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_76_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_76_RESET 0x0 // 0x1434 (BB_SM_HC_PREEMP_LUT_77) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_77_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_77_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_77_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_77_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_77_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_77_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_77_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_77_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_77_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_77_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_77_ADDRESS (0x1434 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_77_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_77_RESET 0x0 // 0x1438 (BB_SM_HC_PREEMP_LUT_78) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_78_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_78_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_78_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_78_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_78_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_78_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_78_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_78_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_78_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_78_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_78_ADDRESS (0x1438 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_78_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_78_RESET 0x0 // 0x143c (BB_SM_HC_PREEMP_LUT_79) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_79_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_79_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_79_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_79_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_79_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_79_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_79_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_79_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_79_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_79_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_79_ADDRESS (0x143c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_79_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_79_RESET 0x0 // 0x1440 (BB_SM_HC_PREEMP_LUT_80) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_80_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_80_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_80_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_80_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_80_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_80_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_80_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_80_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_80_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_80_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_80_ADDRESS (0x1440 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_80_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_80_RESET 0x0 // 0x1444 (BB_SM_HC_PREEMP_LUT_81) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_81_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_81_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_81_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_81_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_81_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_81_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_81_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_81_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_81_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_81_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_81_ADDRESS (0x1444 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_81_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_81_RESET 0x0 // 0x1448 (BB_SM_HC_PREEMP_LUT_82) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_82_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_82_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_82_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_82_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_82_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_82_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_82_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_82_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_82_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_82_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_82_ADDRESS (0x1448 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_82_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_82_RESET 0x0 // 0x144c (BB_SM_HC_PREEMP_LUT_83) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_83_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_83_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_83_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_83_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_83_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_83_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_83_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_83_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_83_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_83_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_83_ADDRESS (0x144c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_83_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_83_RESET 0x0 // 0x1450 (BB_SM_HC_PREEMP_LUT_84) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_84_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_84_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_84_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_84_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_84_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_84_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_84_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_84_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_84_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_84_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_84_ADDRESS (0x1450 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_84_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_84_RESET 0x0 // 0x1454 (BB_SM_HC_PREEMP_LUT_85) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_85_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_85_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_85_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_85_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_85_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_85_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_85_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_85_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_85_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_85_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_85_ADDRESS (0x1454 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_85_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_85_RESET 0x0 // 0x1458 (BB_SM_HC_PREEMP_LUT_86) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_86_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_86_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_86_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_86_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_86_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_86_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_86_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_86_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_86_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_86_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_86_ADDRESS (0x1458 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_86_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_86_RESET 0x0 // 0x145c (BB_SM_HC_PREEMP_LUT_87) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_87_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_87_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_87_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_87_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_87_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_87_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_87_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_87_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_87_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_87_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_87_ADDRESS (0x145c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_87_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_87_RESET 0x0 // 0x1460 (BB_SM_HC_PREEMP_LUT_88) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_88_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_88_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_88_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_88_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_88_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_88_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_88_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_88_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_88_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_88_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_88_ADDRESS (0x1460 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_88_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_88_RESET 0x0 // 0x1464 (BB_SM_HC_PREEMP_LUT_89) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_89_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_89_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_89_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_89_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_89_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_89_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_89_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_89_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_89_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_89_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_89_ADDRESS (0x1464 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_89_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_89_RESET 0x0 // 0x1468 (BB_SM_HC_PREEMP_LUT_90) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_90_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_90_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_90_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_90_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_90_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_90_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_90_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_90_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_90_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_90_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_90_ADDRESS (0x1468 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_90_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_90_RESET 0x0 // 0x146c (BB_SM_HC_PREEMP_LUT_91) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_91_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_91_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_91_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_91_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_91_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_91_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_91_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_91_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_91_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_91_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_91_ADDRESS (0x146c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_91_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_91_RESET 0x0 // 0x1470 (BB_SM_HC_PREEMP_LUT_92) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_92_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_92_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_92_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_92_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_92_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_92_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_92_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_92_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_92_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_92_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_92_ADDRESS (0x1470 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_92_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_92_RESET 0x0 // 0x1474 (BB_SM_HC_PREEMP_LUT_93) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_93_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_93_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_93_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_93_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_93_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_93_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_93_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_93_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_93_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_93_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_93_ADDRESS (0x1474 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_93_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_93_RESET 0x0 // 0x1478 (BB_SM_HC_PREEMP_LUT_94) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_94_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_94_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_94_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_94_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_94_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_94_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_94_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_94_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_94_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_94_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_94_ADDRESS (0x1478 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_94_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_94_RESET 0x0 // 0x147c (BB_SM_HC_PREEMP_LUT_95) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_95_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_95_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_95_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_95_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_95_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_95_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_95_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_95_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_95_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_95_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_95_ADDRESS (0x147c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_95_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_95_RESET 0x0 // 0x1480 (BB_SM_HC_PREEMP_LUT_96) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_96_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_96_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_96_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_96_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_96_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_96_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_96_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_96_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_96_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_96_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_96_ADDRESS (0x1480 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_96_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_96_RESET 0x0 // 0x1484 (BB_SM_HC_PREEMP_LUT_97) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_97_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_97_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_97_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_97_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_97_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_97_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_97_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_97_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_97_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_97_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_97_ADDRESS (0x1484 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_97_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_97_RESET 0x0 // 0x1488 (BB_SM_HC_PREEMP_LUT_98) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_98_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_98_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_98_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_98_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_98_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_98_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_98_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_98_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_98_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_98_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_98_ADDRESS (0x1488 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_98_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_98_RESET 0x0 // 0x148c (BB_SM_HC_PREEMP_LUT_99) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_99_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_99_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_99_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_99_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_99_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_99_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_99_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_99_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_99_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_99_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_99_ADDRESS (0x148c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_99_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_99_RESET 0x0 // 0x1490 (BB_SM_HC_PREEMP_LUT_100) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_100_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_100_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_100_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_100_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_100_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_100_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_100_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_100_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_100_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_100_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_100_ADDRESS (0x1490 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_100_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_100_RESET 0x0 // 0x1494 (BB_SM_HC_PREEMP_LUT_101) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_101_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_101_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_101_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_101_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_101_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_101_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_101_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_101_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_101_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_101_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_101_ADDRESS (0x1494 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_101_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_101_RESET 0x0 // 0x1498 (BB_SM_HC_PREEMP_LUT_102) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_102_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_102_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_102_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_102_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_102_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_102_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_102_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_102_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_102_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_102_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_102_ADDRESS (0x1498 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_102_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_102_RESET 0x0 // 0x149c (BB_SM_HC_PREEMP_LUT_103) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_103_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_103_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_103_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_103_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_103_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_103_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_103_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_103_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_103_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_103_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_103_ADDRESS (0x149c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_103_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_103_RESET 0x0 // 0x14a0 (BB_SM_HC_PREEMP_LUT_104) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_104_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_104_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_104_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_104_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_104_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_104_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_104_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_104_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_104_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_104_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_104_ADDRESS (0x14a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_104_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_104_RESET 0x0 // 0x14a4 (BB_SM_HC_PREEMP_LUT_105) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_105_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_105_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_105_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_105_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_105_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_105_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_105_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_105_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_105_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_105_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_105_ADDRESS (0x14a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_105_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_105_RESET 0x0 // 0x14a8 (BB_SM_HC_PREEMP_LUT_106) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_106_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_106_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_106_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_106_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_106_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_106_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_106_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_106_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_106_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_106_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_106_ADDRESS (0x14a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_106_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_106_RESET 0x0 // 0x14ac (BB_SM_HC_PREEMP_LUT_107) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_107_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_107_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_107_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_107_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_107_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_107_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_107_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_107_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_107_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_107_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_107_ADDRESS (0x14ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_107_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_107_RESET 0x0 // 0x14b0 (BB_SM_HC_PREEMP_LUT_108) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_108_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_108_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_108_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_108_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_108_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_108_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_108_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_108_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_108_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_108_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_108_ADDRESS (0x14b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_108_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_108_RESET 0x0 // 0x14b4 (BB_SM_HC_PREEMP_LUT_109) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_109_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_109_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_109_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_109_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_109_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_109_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_109_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_109_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_109_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_109_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_109_ADDRESS (0x14b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_109_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_109_RESET 0x0 // 0x14b8 (BB_SM_HC_PREEMP_LUT_110) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_110_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_110_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_110_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_110_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_110_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_110_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_110_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_110_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_110_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_110_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_110_ADDRESS (0x14b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_110_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_110_RESET 0x0 // 0x14bc (BB_SM_HC_PREEMP_LUT_111) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_111_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_111_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_111_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_111_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_111_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_111_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_111_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_111_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_111_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_111_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_111_ADDRESS (0x14bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_111_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_111_RESET 0x0 // 0x14c0 (BB_SM_HC_PREEMP_LUT_112) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_112_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_112_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_112_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_112_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_112_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_112_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_112_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_112_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_112_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_112_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_112_ADDRESS (0x14c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_112_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_112_RESET 0x0 // 0x14c4 (BB_SM_HC_PREEMP_LUT_113) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_113_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_113_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_113_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_113_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_113_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_113_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_113_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_113_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_113_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_113_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_113_ADDRESS (0x14c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_113_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_113_RESET 0x0 // 0x14c8 (BB_SM_HC_PREEMP_LUT_114) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_114_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_114_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_114_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_114_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_114_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_114_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_114_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_114_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_114_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_114_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_114_ADDRESS (0x14c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_114_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_114_RESET 0x0 // 0x14cc (BB_SM_HC_PREEMP_LUT_115) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_115_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_115_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_115_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_115_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_115_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_115_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_115_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_115_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_115_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_115_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_115_ADDRESS (0x14cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_115_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_115_RESET 0x0 // 0x14d0 (BB_SM_HC_PREEMP_LUT_116) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_116_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_116_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_116_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_116_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_116_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_116_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_116_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_116_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_116_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_116_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_116_ADDRESS (0x14d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_116_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_116_RESET 0x0 // 0x14d4 (BB_SM_HC_PREEMP_LUT_117) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_117_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_117_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_117_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_117_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_117_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_117_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_117_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_117_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_117_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_117_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_117_ADDRESS (0x14d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_117_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_117_RESET 0x0 // 0x14d8 (BB_SM_HC_PREEMP_LUT_118) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_118_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_118_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_118_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_118_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_118_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_118_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_118_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_118_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_118_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_118_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_118_ADDRESS (0x14d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_118_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_118_RESET 0x0 // 0x14dc (BB_SM_HC_PREEMP_LUT_119) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_119_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_119_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_119_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_119_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_119_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_119_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_119_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_119_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_119_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_119_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_119_ADDRESS (0x14dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_119_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_119_RESET 0x0 // 0x14e0 (BB_SM_HC_PREEMP_LUT_120) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_120_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_120_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_120_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_120_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_120_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_120_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_120_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_120_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_120_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_120_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_120_ADDRESS (0x14e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_120_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_120_RESET 0x0 // 0x14e4 (BB_SM_HC_PREEMP_LUT_121) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_121_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_121_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_121_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_121_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_121_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_121_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_121_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_121_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_121_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_121_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_121_ADDRESS (0x14e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_121_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_121_RESET 0x0 // 0x14e8 (BB_SM_HC_PREEMP_LUT_122) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_122_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_122_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_122_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_122_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_122_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_122_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_122_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_122_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_122_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_122_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_122_ADDRESS (0x14e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_122_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_122_RESET 0x0 // 0x14ec (BB_SM_HC_PREEMP_LUT_123) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_123_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_123_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_123_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_123_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_123_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_123_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_123_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_123_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_123_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_123_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_123_ADDRESS (0x14ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_123_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_123_RESET 0x0 // 0x14f0 (BB_SM_HC_PREEMP_LUT_124) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_124_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_124_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_124_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_124_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_124_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_124_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_124_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_124_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_124_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_124_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_124_ADDRESS (0x14f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_124_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_124_RESET 0x0 // 0x14f4 (BB_SM_HC_PREEMP_LUT_125) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_125_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_125_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_125_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_125_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_125_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_125_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_125_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_125_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_125_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_125_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_125_ADDRESS (0x14f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_125_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_125_RESET 0x0 // 0x14f8 (BB_SM_HC_PREEMP_LUT_126) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_126_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_126_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_126_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_126_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_126_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_126_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_126_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_126_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_126_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_126_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_126_ADDRESS (0x14f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_126_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_126_RESET 0x0 // 0x14fc (BB_SM_HC_PREEMP_LUT_127) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_127_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_127_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_127_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_127_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_127_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_127_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_127_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_127_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_127_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_127_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_127_ADDRESS (0x14fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_127_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_127_RESET 0x0 // 0x1500 (BB_SM_HC_PREEMP_LUT_128) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_128_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_128_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_128_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_128_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_128_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_128_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_128_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_128_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_128_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_128_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_128_ADDRESS (0x1500 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_128_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_128_RESET 0x0 // 0x1504 (BB_SM_HC_PREEMP_LUT_129) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_129_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_129_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_129_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_129_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_129_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_129_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_129_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_129_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_129_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_129_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_129_ADDRESS (0x1504 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_129_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_129_RESET 0x0 // 0x1508 (BB_SM_HC_PREEMP_LUT_130) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_130_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_130_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_130_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_130_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_130_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_130_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_130_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_130_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_130_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_130_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_130_ADDRESS (0x1508 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_130_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_130_RESET 0x0 // 0x150c (BB_SM_HC_PREEMP_LUT_131) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_131_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_131_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_131_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_131_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_131_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_131_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_131_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_131_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_131_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_131_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_131_ADDRESS (0x150c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_131_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_131_RESET 0x0 // 0x1510 (BB_SM_HC_PREEMP_LUT_132) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_132_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_132_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_132_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_132_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_132_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_132_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_132_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_132_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_132_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_132_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_132_ADDRESS (0x1510 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_132_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_132_RESET 0x0 // 0x1514 (BB_SM_HC_PREEMP_LUT_133) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_133_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_133_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_133_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_133_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_133_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_133_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_133_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_133_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_133_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_133_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_133_ADDRESS (0x1514 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_133_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_133_RESET 0x0 // 0x1518 (BB_SM_HC_PREEMP_LUT_134) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_134_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_134_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_134_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_134_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_134_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_134_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_134_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_134_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_134_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_134_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_134_ADDRESS (0x1518 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_134_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_134_RESET 0x0 // 0x151c (BB_SM_HC_PREEMP_LUT_135) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_135_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_135_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_135_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_135_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_135_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_135_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_135_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_135_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_135_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_135_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_135_ADDRESS (0x151c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_135_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_135_RESET 0x0 // 0x1520 (BB_SM_HC_PREEMP_LUT_136) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_136_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_136_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_136_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_136_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_136_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_136_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_136_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_136_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_136_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_136_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_136_ADDRESS (0x1520 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_136_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_136_RESET 0x0 // 0x1524 (BB_SM_HC_PREEMP_LUT_137) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_137_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_137_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_137_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_137_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_137_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_137_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_137_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_137_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_137_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_137_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_137_ADDRESS (0x1524 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_137_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_137_RESET 0x0 // 0x1528 (BB_SM_HC_PREEMP_LUT_138) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_138_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_138_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_138_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_138_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_138_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_138_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_138_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_138_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_138_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_138_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_138_ADDRESS (0x1528 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_138_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_138_RESET 0x0 // 0x152c (BB_SM_HC_PREEMP_LUT_139) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_139_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_139_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_139_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_139_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_139_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_139_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_139_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_139_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_139_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_139_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_139_ADDRESS (0x152c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_139_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_139_RESET 0x0 // 0x1530 (BB_SM_HC_PREEMP_LUT_140) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_140_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_140_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_140_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_140_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_140_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_140_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_140_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_140_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_140_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_140_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_140_ADDRESS (0x1530 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_140_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_140_RESET 0x0 // 0x1534 (BB_SM_HC_PREEMP_LUT_141) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_141_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_141_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_141_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_141_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_141_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_141_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_141_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_141_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_141_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_141_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_141_ADDRESS (0x1534 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_141_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_141_RESET 0x0 // 0x1538 (BB_SM_HC_PREEMP_LUT_142) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_142_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_142_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_142_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_142_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_142_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_142_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_142_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_142_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_142_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_142_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_142_ADDRESS (0x1538 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_142_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_142_RESET 0x0 // 0x153c (BB_SM_HC_PREEMP_LUT_143) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_143_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_143_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_143_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_143_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_143_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_143_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_143_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_143_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_143_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_143_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_143_ADDRESS (0x153c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_143_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_143_RESET 0x0 // 0x1540 (BB_SM_HC_PREEMP_LUT_144) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_144_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_144_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_144_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_144_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_144_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_144_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_144_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_144_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_144_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_144_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_144_ADDRESS (0x1540 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_144_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_144_RESET 0x0 // 0x1544 (BB_SM_HC_PREEMP_LUT_145) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_145_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_145_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_145_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_145_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_145_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_145_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_145_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_145_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_145_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_145_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_145_ADDRESS (0x1544 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_145_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_145_RESET 0x0 // 0x1548 (BB_SM_HC_PREEMP_LUT_146) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_146_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_146_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_146_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_146_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_146_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_146_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_146_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_146_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_146_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_146_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_146_ADDRESS (0x1548 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_146_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_146_RESET 0x0 // 0x154c (BB_SM_HC_PREEMP_LUT_147) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_147_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_147_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_147_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_147_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_147_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_147_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_147_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_147_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_147_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_147_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_147_ADDRESS (0x154c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_147_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_147_RESET 0x0 // 0x1550 (BB_SM_HC_PREEMP_LUT_148) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_148_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_148_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_148_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_148_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_148_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_148_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_148_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_148_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_148_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_148_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_148_ADDRESS (0x1550 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_148_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_148_RESET 0x0 // 0x1554 (BB_SM_HC_PREEMP_LUT_149) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_149_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_149_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_149_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_149_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_149_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_149_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_149_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_149_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_149_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_149_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_149_ADDRESS (0x1554 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_149_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_149_RESET 0x0 // 0x1558 (BB_SM_HC_PREEMP_LUT_150) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_150_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_150_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_150_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_150_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_150_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_150_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_150_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_150_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_150_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_150_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_150_ADDRESS (0x1558 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_150_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_150_RESET 0x0 // 0x155c (BB_SM_HC_PREEMP_LUT_151) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_151_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_151_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_151_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_151_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_151_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_151_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_151_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_151_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_151_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_151_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_151_ADDRESS (0x155c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_151_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_151_RESET 0x0 // 0x1560 (BB_SM_HC_PREEMP_LUT_152) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_152_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_152_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_152_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_152_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_152_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_152_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_152_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_152_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_152_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_152_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_152_ADDRESS (0x1560 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_152_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_152_RESET 0x0 // 0x1564 (BB_SM_HC_PREEMP_LUT_153) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_153_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_153_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_153_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_153_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_153_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_153_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_153_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_153_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_153_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_153_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_153_ADDRESS (0x1564 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_153_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_153_RESET 0x0 // 0x1568 (BB_SM_HC_PREEMP_LUT_154) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_154_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_154_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_154_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_154_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_154_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_154_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_154_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_154_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_154_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_154_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_154_ADDRESS (0x1568 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_154_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_154_RESET 0x0 // 0x156c (BB_SM_HC_PREEMP_LUT_155) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_155_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_155_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_155_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_155_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_155_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_155_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_155_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_155_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_155_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_155_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_155_ADDRESS (0x156c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_155_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_155_RESET 0x0 // 0x1570 (BB_SM_HC_PREEMP_LUT_156) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_156_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_156_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_156_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_156_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_156_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_156_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_156_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_156_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_156_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_156_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_156_ADDRESS (0x1570 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_156_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_156_RESET 0x0 // 0x1574 (BB_SM_HC_PREEMP_LUT_157) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_157_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_157_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_157_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_157_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_157_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_157_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_157_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_157_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_157_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_157_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_157_ADDRESS (0x1574 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_157_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_157_RESET 0x0 // 0x1578 (BB_SM_HC_PREEMP_LUT_158) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_158_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_158_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_158_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_158_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_158_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_158_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_158_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_158_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_158_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_158_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_158_ADDRESS (0x1578 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_158_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_158_RESET 0x0 // 0x157c (BB_SM_HC_PREEMP_LUT_159) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_159_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_159_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_159_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_159_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_159_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_159_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_159_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_159_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_159_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_159_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_159_ADDRESS (0x157c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_159_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_159_RESET 0x0 // 0x1580 (BB_SM_HC_PREEMP_LUT_160) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_160_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_160_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_160_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_160_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_160_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_160_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_160_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_160_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_160_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_160_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_160_ADDRESS (0x1580 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_160_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_160_RESET 0x0 // 0x1584 (BB_SM_HC_PREEMP_LUT_161) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_161_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_161_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_161_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_161_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_161_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_161_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_161_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_161_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_161_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_161_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_161_ADDRESS (0x1584 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_161_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_161_RESET 0x0 // 0x1588 (BB_SM_HC_PREEMP_LUT_162) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_162_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_162_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_162_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_162_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_162_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_162_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_162_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_162_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_162_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_162_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_162_ADDRESS (0x1588 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_162_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_162_RESET 0x0 // 0x158c (BB_SM_HC_PREEMP_LUT_163) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_163_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_163_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_163_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_163_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_163_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_163_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_163_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_163_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_163_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_163_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_163_ADDRESS (0x158c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_163_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_163_RESET 0x0 // 0x1590 (BB_SM_HC_PREEMP_LUT_164) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_164_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_164_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_164_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_164_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_164_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_164_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_164_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_164_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_164_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_164_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_164_ADDRESS (0x1590 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_164_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_164_RESET 0x0 // 0x1594 (BB_SM_HC_PREEMP_LUT_165) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_165_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_165_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_165_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_165_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_165_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_165_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_165_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_165_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_165_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_165_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_165_ADDRESS (0x1594 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_165_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_165_RESET 0x0 // 0x1598 (BB_SM_HC_PREEMP_LUT_166) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_166_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_166_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_166_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_166_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_166_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_166_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_166_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_166_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_166_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_166_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_166_ADDRESS (0x1598 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_166_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_166_RESET 0x0 // 0x159c (BB_SM_HC_PREEMP_LUT_167) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_167_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_167_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_167_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_167_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_167_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_167_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_167_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_167_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_167_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_167_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_167_ADDRESS (0x159c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_167_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_167_RESET 0x0 // 0x15a0 (BB_SM_HC_PREEMP_LUT_168) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_168_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_168_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_168_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_168_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_168_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_168_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_168_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_168_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_168_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_168_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_168_ADDRESS (0x15a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_168_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_168_RESET 0x0 // 0x15a4 (BB_SM_HC_PREEMP_LUT_169) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_169_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_169_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_169_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_169_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_169_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_169_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_169_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_169_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_169_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_169_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_169_ADDRESS (0x15a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_169_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_169_RESET 0x0 // 0x15a8 (BB_SM_HC_PREEMP_LUT_170) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_170_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_170_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_170_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_170_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_170_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_170_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_170_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_170_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_170_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_170_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_170_ADDRESS (0x15a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_170_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_170_RESET 0x0 // 0x15ac (BB_SM_HC_PREEMP_LUT_171) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_171_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_171_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_171_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_171_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_171_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_171_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_171_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_171_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_171_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_171_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_171_ADDRESS (0x15ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_171_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_171_RESET 0x0 // 0x15b0 (BB_SM_HC_PREEMP_LUT_172) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_172_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_172_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_172_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_172_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_172_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_172_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_172_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_172_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_172_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_172_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_172_ADDRESS (0x15b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_172_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_172_RESET 0x0 // 0x15b4 (BB_SM_HC_PREEMP_LUT_173) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_173_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_173_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_173_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_173_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_173_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_173_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_173_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_173_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_173_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_173_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_173_ADDRESS (0x15b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_173_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_173_RESET 0x0 // 0x15b8 (BB_SM_HC_PREEMP_LUT_174) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_174_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_174_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_174_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_174_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_174_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_174_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_174_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_174_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_174_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_174_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_174_ADDRESS (0x15b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_174_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_174_RESET 0x0 // 0x15bc (BB_SM_HC_PREEMP_LUT_175) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_175_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_175_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_175_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_175_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_175_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_175_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_175_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_175_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_175_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_175_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_175_ADDRESS (0x15bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_175_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_175_RESET 0x0 // 0x15c0 (BB_SM_HC_PREEMP_LUT_176) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_176_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_176_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_176_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_176_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_176_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_176_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_176_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_176_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_176_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_176_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_176_ADDRESS (0x15c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_176_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_176_RESET 0x0 // 0x15c4 (BB_SM_HC_PREEMP_LUT_177) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_177_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_177_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_177_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_177_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_177_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_177_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_177_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_177_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_177_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_177_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_177_ADDRESS (0x15c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_177_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_177_RESET 0x0 // 0x15c8 (BB_SM_HC_PREEMP_LUT_178) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_178_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_178_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_178_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_178_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_178_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_178_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_178_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_178_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_178_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_178_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_178_ADDRESS (0x15c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_178_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_178_RESET 0x0 // 0x15cc (BB_SM_HC_PREEMP_LUT_179) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_179_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_179_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_179_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_179_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_179_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_179_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_179_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_179_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_179_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_179_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_179_ADDRESS (0x15cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_179_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_179_RESET 0x0 // 0x15d0 (BB_SM_HC_PREEMP_LUT_180) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_180_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_180_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_180_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_180_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_180_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_180_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_180_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_180_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_180_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_180_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_180_ADDRESS (0x15d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_180_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_180_RESET 0x0 // 0x15d4 (BB_SM_HC_PREEMP_LUT_181) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_181_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_181_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_181_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_181_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_181_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_181_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_181_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_181_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_181_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_181_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_181_ADDRESS (0x15d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_181_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_181_RESET 0x0 // 0x15d8 (BB_SM_HC_PREEMP_LUT_182) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_182_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_182_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_182_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_182_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_182_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_182_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_182_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_182_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_182_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_182_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_182_ADDRESS (0x15d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_182_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_182_RESET 0x0 // 0x15dc (BB_SM_HC_PREEMP_LUT_183) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_183_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_183_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_183_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_183_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_183_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_183_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_183_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_183_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_183_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_183_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_183_ADDRESS (0x15dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_183_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_183_RESET 0x0 // 0x15e0 (BB_SM_HC_PREEMP_LUT_184) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_184_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_184_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_184_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_184_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_184_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_184_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_184_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_184_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_184_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_184_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_184_ADDRESS (0x15e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_184_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_184_RESET 0x0 // 0x15e4 (BB_SM_HC_PREEMP_LUT_185) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_185_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_185_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_185_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_185_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_185_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_185_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_185_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_185_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_185_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_185_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_185_ADDRESS (0x15e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_185_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_185_RESET 0x0 // 0x15e8 (BB_SM_HC_PREEMP_LUT_186) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_186_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_186_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_186_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_186_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_186_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_186_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_186_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_186_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_186_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_186_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_186_ADDRESS (0x15e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_186_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_186_RESET 0x0 // 0x15ec (BB_SM_HC_PREEMP_LUT_187) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_187_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_187_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_187_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_187_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_187_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_187_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_187_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_187_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_187_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_187_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_187_ADDRESS (0x15ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_187_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_187_RESET 0x0 // 0x15f0 (BB_SM_HC_PREEMP_LUT_188) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_188_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_188_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_188_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_188_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_188_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_188_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_188_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_188_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_188_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_188_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_188_ADDRESS (0x15f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_188_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_188_RESET 0x0 // 0x15f4 (BB_SM_HC_PREEMP_LUT_189) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_189_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_189_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_189_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_189_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_189_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_189_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_189_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_189_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_189_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_189_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_189_ADDRESS (0x15f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_189_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_189_RESET 0x0 // 0x15f8 (BB_SM_HC_PREEMP_LUT_190) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_190_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_190_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_190_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_190_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_190_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_190_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_190_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_190_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_190_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_190_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_190_ADDRESS (0x15f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_190_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_190_RESET 0x0 // 0x15fc (BB_SM_HC_PREEMP_LUT_191) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_191_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_191_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_191_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_191_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_191_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_191_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_191_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_191_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_191_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_191_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_191_ADDRESS (0x15fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_191_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_191_RESET 0x0 // 0x1600 (BB_SM_HC_PREEMP_LUT_192) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_192_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_192_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_192_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_192_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_192_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_192_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_192_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_192_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_192_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_192_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_192_ADDRESS (0x1600 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_192_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_192_RESET 0x0 // 0x1604 (BB_SM_HC_PREEMP_LUT_193) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_193_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_193_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_193_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_193_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_193_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_193_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_193_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_193_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_193_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_193_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_193_ADDRESS (0x1604 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_193_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_193_RESET 0x0 // 0x1608 (BB_SM_HC_PREEMP_LUT_194) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_194_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_194_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_194_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_194_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_194_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_194_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_194_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_194_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_194_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_194_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_194_ADDRESS (0x1608 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_194_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_194_RESET 0x0 // 0x160c (BB_SM_HC_PREEMP_LUT_195) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_195_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_195_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_195_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_195_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_195_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_195_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_195_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_195_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_195_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_195_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_195_ADDRESS (0x160c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_195_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_195_RESET 0x0 // 0x1610 (BB_SM_HC_PREEMP_LUT_196) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_196_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_196_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_196_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_196_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_196_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_196_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_196_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_196_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_196_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_196_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_196_ADDRESS (0x1610 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_196_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_196_RESET 0x0 // 0x1614 (BB_SM_HC_PREEMP_LUT_197) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_197_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_197_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_197_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_197_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_197_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_197_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_197_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_197_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_197_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_197_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_197_ADDRESS (0x1614 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_197_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_197_RESET 0x0 // 0x1618 (BB_SM_HC_PREEMP_LUT_198) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_198_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_198_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_198_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_198_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_198_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_198_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_198_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_198_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_198_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_198_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_198_ADDRESS (0x1618 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_198_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_198_RESET 0x0 // 0x161c (BB_SM_HC_PREEMP_LUT_199) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_199_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_199_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_199_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_199_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_199_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_199_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_199_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_199_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_199_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_199_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_199_ADDRESS (0x161c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_199_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_199_RESET 0x0 // 0x1620 (BB_SM_HC_PREEMP_LUT_200) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_200_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_200_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_200_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_200_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_200_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_200_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_200_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_200_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_200_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_200_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_200_ADDRESS (0x1620 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_200_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_200_RESET 0x0 // 0x1624 (BB_SM_HC_PREEMP_LUT_201) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_201_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_201_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_201_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_201_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_201_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_201_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_201_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_201_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_201_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_201_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_201_ADDRESS (0x1624 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_201_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_201_RESET 0x0 // 0x1628 (BB_SM_HC_PREEMP_LUT_202) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_202_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_202_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_202_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_202_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_202_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_202_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_202_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_202_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_202_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_202_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_202_ADDRESS (0x1628 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_202_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_202_RESET 0x0 // 0x162c (BB_SM_HC_PREEMP_LUT_203) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_203_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_203_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_203_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_203_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_203_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_203_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_203_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_203_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_203_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_203_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_203_ADDRESS (0x162c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_203_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_203_RESET 0x0 // 0x1630 (BB_SM_HC_PREEMP_LUT_204) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_204_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_204_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_204_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_204_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_204_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_204_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_204_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_204_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_204_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_204_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_204_ADDRESS (0x1630 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_204_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_204_RESET 0x0 // 0x1634 (BB_SM_HC_PREEMP_LUT_205) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_205_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_205_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_205_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_205_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_205_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_205_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_205_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_205_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_205_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_205_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_205_ADDRESS (0x1634 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_205_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_205_RESET 0x0 // 0x1638 (BB_SM_HC_PREEMP_LUT_206) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_206_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_206_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_206_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_206_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_206_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_206_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_206_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_206_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_206_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_206_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_206_ADDRESS (0x1638 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_206_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_206_RESET 0x0 // 0x163c (BB_SM_HC_PREEMP_LUT_207) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_207_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_207_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_207_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_207_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_207_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_207_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_207_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_207_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_207_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_207_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_207_ADDRESS (0x163c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_207_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_207_RESET 0x0 // 0x1640 (BB_SM_HC_PREEMP_LUT_208) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_208_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_208_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_208_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_208_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_208_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_208_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_208_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_208_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_208_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_208_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_208_ADDRESS (0x1640 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_208_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_208_RESET 0x0 // 0x1644 (BB_SM_HC_PREEMP_LUT_209) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_209_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_209_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_209_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_209_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_209_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_209_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_209_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_209_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_209_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_209_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_209_ADDRESS (0x1644 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_209_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_209_RESET 0x0 // 0x1648 (BB_SM_HC_PREEMP_LUT_210) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_210_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_210_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_210_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_210_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_210_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_210_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_210_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_210_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_210_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_210_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_210_ADDRESS (0x1648 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_210_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_210_RESET 0x0 // 0x164c (BB_SM_HC_PREEMP_LUT_211) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_211_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_211_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_211_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_211_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_211_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_211_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_211_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_211_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_211_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_211_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_211_ADDRESS (0x164c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_211_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_211_RESET 0x0 // 0x1650 (BB_SM_HC_PREEMP_LUT_212) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_212_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_212_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_212_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_212_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_212_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_212_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_212_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_212_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_212_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_212_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_212_ADDRESS (0x1650 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_212_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_212_RESET 0x0 // 0x1654 (BB_SM_HC_PREEMP_LUT_213) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_213_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_213_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_213_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_213_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_213_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_213_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_213_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_213_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_213_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_213_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_213_ADDRESS (0x1654 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_213_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_213_RESET 0x0 // 0x1658 (BB_SM_HC_PREEMP_LUT_214) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_214_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_214_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_214_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_214_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_214_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_214_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_214_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_214_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_214_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_214_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_214_ADDRESS (0x1658 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_214_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_214_RESET 0x0 // 0x165c (BB_SM_HC_PREEMP_LUT_215) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_215_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_215_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_215_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_215_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_215_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_215_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_215_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_215_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_215_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_215_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_215_ADDRESS (0x165c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_215_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_215_RESET 0x0 // 0x1660 (BB_SM_HC_PREEMP_LUT_216) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_216_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_216_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_216_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_216_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_216_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_216_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_216_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_216_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_216_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_216_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_216_ADDRESS (0x1660 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_216_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_216_RESET 0x0 // 0x1664 (BB_SM_HC_PREEMP_LUT_217) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_217_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_217_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_217_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_217_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_217_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_217_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_217_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_217_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_217_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_217_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_217_ADDRESS (0x1664 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_217_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_217_RESET 0x0 // 0x1668 (BB_SM_HC_PREEMP_LUT_218) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_218_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_218_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_218_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_218_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_218_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_218_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_218_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_218_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_218_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_218_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_218_ADDRESS (0x1668 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_218_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_218_RESET 0x0 // 0x166c (BB_SM_HC_PREEMP_LUT_219) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_219_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_219_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_219_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_219_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_219_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_219_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_219_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_219_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_219_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_219_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_219_ADDRESS (0x166c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_219_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_219_RESET 0x0 // 0x1670 (BB_SM_HC_PREEMP_LUT_220) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_220_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_220_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_220_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_220_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_220_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_220_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_220_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_220_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_220_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_220_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_220_ADDRESS (0x1670 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_220_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_220_RESET 0x0 // 0x1674 (BB_SM_HC_PREEMP_LUT_221) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_221_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_221_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_221_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_221_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_221_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_221_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_221_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_221_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_221_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_221_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_221_ADDRESS (0x1674 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_221_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_221_RESET 0x0 // 0x1678 (BB_SM_HC_PREEMP_LUT_222) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_222_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_222_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_222_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_222_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_222_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_222_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_222_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_222_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_222_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_222_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_222_ADDRESS (0x1678 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_222_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_222_RESET 0x0 // 0x167c (BB_SM_HC_PREEMP_LUT_223) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_223_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_223_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_223_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_223_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_223_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_223_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_223_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_223_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_223_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_223_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_223_ADDRESS (0x167c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_223_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_223_RESET 0x0 // 0x1680 (BB_SM_HC_PREEMP_LUT_224) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_224_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_224_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_224_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_224_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_224_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_224_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_224_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_224_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_224_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_224_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_224_ADDRESS (0x1680 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_224_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_224_RESET 0x0 // 0x1684 (BB_SM_HC_PREEMP_LUT_225) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_225_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_225_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_225_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_225_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_225_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_225_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_225_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_225_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_225_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_225_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_225_ADDRESS (0x1684 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_225_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_225_RESET 0x0 // 0x1688 (BB_SM_HC_PREEMP_LUT_226) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_226_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_226_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_226_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_226_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_226_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_226_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_226_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_226_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_226_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_226_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_226_ADDRESS (0x1688 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_226_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_226_RESET 0x0 // 0x168c (BB_SM_HC_PREEMP_LUT_227) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_227_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_227_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_227_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_227_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_227_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_227_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_227_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_227_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_227_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_227_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_227_ADDRESS (0x168c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_227_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_227_RESET 0x0 // 0x1690 (BB_SM_HC_PREEMP_LUT_228) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_228_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_228_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_228_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_228_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_228_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_228_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_228_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_228_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_228_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_228_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_228_ADDRESS (0x1690 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_228_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_228_RESET 0x0 // 0x1694 (BB_SM_HC_PREEMP_LUT_229) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_229_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_229_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_229_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_229_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_229_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_229_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_229_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_229_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_229_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_229_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_229_ADDRESS (0x1694 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_229_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_229_RESET 0x0 // 0x1698 (BB_SM_HC_PREEMP_LUT_230) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_230_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_230_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_230_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_230_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_230_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_230_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_230_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_230_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_230_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_230_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_230_ADDRESS (0x1698 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_230_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_230_RESET 0x0 // 0x169c (BB_SM_HC_PREEMP_LUT_231) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_231_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_231_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_231_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_231_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_231_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_231_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_231_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_231_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_231_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_231_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_231_ADDRESS (0x169c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_231_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_231_RESET 0x0 // 0x16a0 (BB_SM_HC_PREEMP_LUT_232) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_232_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_232_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_232_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_232_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_232_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_232_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_232_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_232_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_232_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_232_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_232_ADDRESS (0x16a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_232_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_232_RESET 0x0 // 0x16a4 (BB_SM_HC_PREEMP_LUT_233) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_233_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_233_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_233_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_233_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_233_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_233_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_233_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_233_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_233_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_233_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_233_ADDRESS (0x16a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_233_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_233_RESET 0x0 // 0x16a8 (BB_SM_HC_PREEMP_LUT_234) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_234_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_234_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_234_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_234_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_234_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_234_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_234_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_234_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_234_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_234_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_234_ADDRESS (0x16a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_234_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_234_RESET 0x0 // 0x16ac (BB_SM_HC_PREEMP_LUT_235) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_235_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_235_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_235_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_235_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_235_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_235_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_235_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_235_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_235_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_235_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_235_ADDRESS (0x16ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_235_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_235_RESET 0x0 // 0x16b0 (BB_SM_HC_PREEMP_LUT_236) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_236_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_236_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_236_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_236_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_236_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_236_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_236_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_236_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_236_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_236_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_236_ADDRESS (0x16b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_236_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_236_RESET 0x0 // 0x16b4 (BB_SM_HC_PREEMP_LUT_237) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_237_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_237_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_237_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_237_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_237_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_237_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_237_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_237_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_237_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_237_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_237_ADDRESS (0x16b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_237_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_237_RESET 0x0 // 0x16b8 (BB_SM_HC_PREEMP_LUT_238) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_238_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_238_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_238_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_238_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_238_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_238_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_238_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_238_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_238_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_238_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_238_ADDRESS (0x16b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_238_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_238_RESET 0x0 // 0x16bc (BB_SM_HC_PREEMP_LUT_239) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_239_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_239_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_239_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_239_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_239_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_239_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_239_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_239_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_239_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_239_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_239_ADDRESS (0x16bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_239_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_239_RESET 0x0 // 0x16c0 (BB_SM_HC_PREEMP_LUT_240) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_240_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_240_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_240_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_240_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_240_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_240_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_240_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_240_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_240_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_240_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_240_ADDRESS (0x16c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_240_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_240_RESET 0x0 // 0x16c4 (BB_SM_HC_PREEMP_LUT_241) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_241_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_241_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_241_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_241_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_241_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_241_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_241_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_241_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_241_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_241_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_241_ADDRESS (0x16c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_241_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_241_RESET 0x0 // 0x16c8 (BB_SM_HC_PREEMP_LUT_242) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_242_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_242_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_242_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_242_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_242_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_242_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_242_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_242_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_242_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_242_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_242_ADDRESS (0x16c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_242_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_242_RESET 0x0 // 0x16cc (BB_SM_HC_PREEMP_LUT_243) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_243_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_243_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_243_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_243_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_243_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_243_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_243_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_243_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_243_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_243_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_243_ADDRESS (0x16cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_243_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_243_RESET 0x0 // 0x16d0 (BB_SM_HC_PREEMP_LUT_244) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_244_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_244_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_244_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_244_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_244_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_244_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_244_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_244_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_244_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_244_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_244_ADDRESS (0x16d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_244_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_244_RESET 0x0 // 0x16d4 (BB_SM_HC_PREEMP_LUT_245) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_245_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_245_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_245_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_245_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_245_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_245_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_245_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_245_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_245_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_245_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_245_ADDRESS (0x16d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_245_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_245_RESET 0x0 // 0x16d8 (BB_SM_HC_PREEMP_LUT_246) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_246_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_246_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_246_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_246_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_246_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_246_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_246_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_246_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_246_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_246_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_246_ADDRESS (0x16d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_246_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_246_RESET 0x0 // 0x16dc (BB_SM_HC_PREEMP_LUT_247) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_247_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_247_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_247_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_247_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_247_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_247_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_247_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_247_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_247_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_247_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_247_ADDRESS (0x16dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_247_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_247_RESET 0x0 // 0x16e0 (BB_SM_HC_PREEMP_LUT_248) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_248_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_248_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_248_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_248_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_248_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_248_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_248_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_248_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_248_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_248_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_248_ADDRESS (0x16e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_248_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_248_RESET 0x0 // 0x16e4 (BB_SM_HC_PREEMP_LUT_249) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_249_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_249_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_249_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_249_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_249_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_249_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_249_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_249_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_249_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_249_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_249_ADDRESS (0x16e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_249_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_249_RESET 0x0 // 0x16e8 (BB_SM_HC_PREEMP_LUT_250) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_250_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_250_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_250_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_250_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_250_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_250_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_250_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_250_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_250_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_250_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_250_ADDRESS (0x16e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_250_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_250_RESET 0x0 // 0x16ec (BB_SM_HC_PREEMP_LUT_251) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_251_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_251_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_251_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_251_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_251_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_251_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_251_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_251_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_251_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_251_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_251_ADDRESS (0x16ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_251_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_251_RESET 0x0 // 0x16f0 (BB_SM_HC_PREEMP_LUT_252) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_252_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_252_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_252_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_252_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_252_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_252_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_252_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_252_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_252_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_252_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_252_ADDRESS (0x16f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_252_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_252_RESET 0x0 // 0x16f4 (BB_SM_HC_PREEMP_LUT_253) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_253_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_253_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_253_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_253_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_253_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_253_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_253_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_253_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_253_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_253_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_253_ADDRESS (0x16f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_253_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_253_RESET 0x0 // 0x16f8 (BB_SM_HC_PREEMP_LUT_254) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_254_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_254_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_254_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_254_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_254_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_254_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_254_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_254_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_254_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_254_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_254_ADDRESS (0x16f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_254_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_254_RESET 0x0 // 0x16fc (BB_SM_HC_PREEMP_LUT_255) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_255_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_255_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_255_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_255_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_255_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_255_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_255_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_255_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_255_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_255_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_255_ADDRESS (0x16fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_255_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_255_RESET 0x0 // 0x1700 (BB_SM_HC_PREEMP_LUT_256) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_256_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_256_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_256_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_256_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_256_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_256_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_256_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_256_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_256_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_256_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_256_ADDRESS (0x1700 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_256_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_256_RESET 0x0 // 0x1704 (BB_SM_HC_PREEMP_LUT_257) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_257_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_257_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_257_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_257_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_257_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_257_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_257_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_257_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_257_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_257_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_257_ADDRESS (0x1704 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_257_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_257_RESET 0x0 // 0x1708 (BB_SM_HC_PREEMP_LUT_258) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_258_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_258_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_258_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_258_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_258_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_258_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_258_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_258_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_258_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_258_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_258_ADDRESS (0x1708 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_258_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_258_RESET 0x0 // 0x170c (BB_SM_HC_PREEMP_LUT_259) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_259_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_259_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_259_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_259_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_259_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_259_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_259_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_259_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_259_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_259_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_259_ADDRESS (0x170c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_259_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_259_RESET 0x0 // 0x1710 (BB_SM_HC_PREEMP_LUT_260) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_260_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_260_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_260_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_260_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_260_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_260_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_260_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_260_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_260_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_260_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_260_ADDRESS (0x1710 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_260_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_260_RESET 0x0 // 0x1714 (BB_SM_HC_PREEMP_LUT_261) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_261_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_261_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_261_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_261_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_261_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_261_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_261_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_261_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_261_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_261_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_261_ADDRESS (0x1714 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_261_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_261_RESET 0x0 // 0x1718 (BB_SM_HC_PREEMP_LUT_262) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_262_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_262_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_262_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_262_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_262_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_262_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_262_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_262_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_262_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_262_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_262_ADDRESS (0x1718 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_262_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_262_RESET 0x0 // 0x171c (BB_SM_HC_PREEMP_LUT_263) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_263_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_263_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_263_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_263_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_263_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_263_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_263_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_263_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_263_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_263_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_263_ADDRESS (0x171c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_263_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_263_RESET 0x0 // 0x1720 (BB_SM_HC_PREEMP_LUT_264) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_264_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_264_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_264_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_264_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_264_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_264_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_264_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_264_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_264_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_264_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_264_ADDRESS (0x1720 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_264_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_264_RESET 0x0 // 0x1724 (BB_SM_HC_PREEMP_LUT_265) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_265_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_265_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_265_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_265_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_265_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_265_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_265_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_265_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_265_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_265_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_265_ADDRESS (0x1724 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_265_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_265_RESET 0x0 // 0x1728 (BB_SM_HC_PREEMP_LUT_266) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_266_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_266_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_266_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_266_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_266_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_266_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_266_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_266_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_266_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_266_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_266_ADDRESS (0x1728 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_266_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_266_RESET 0x0 // 0x172c (BB_SM_HC_PREEMP_LUT_267) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_267_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_267_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_267_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_267_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_267_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_267_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_267_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_267_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_267_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_267_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_267_ADDRESS (0x172c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_267_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_267_RESET 0x0 // 0x1730 (BB_SM_HC_PREEMP_LUT_268) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_268_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_268_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_268_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_268_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_268_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_268_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_268_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_268_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_268_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_268_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_268_ADDRESS (0x1730 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_268_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_268_RESET 0x0 // 0x1734 (BB_SM_HC_PREEMP_LUT_269) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_269_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_269_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_269_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_269_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_269_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_269_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_269_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_269_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_269_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_269_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_269_ADDRESS (0x1734 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_269_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_269_RESET 0x0 // 0x1738 (BB_SM_HC_PREEMP_LUT_270) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_270_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_270_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_270_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_270_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_270_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_270_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_270_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_270_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_270_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_270_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_270_ADDRESS (0x1738 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_270_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_270_RESET 0x0 // 0x173c (BB_SM_HC_PREEMP_LUT_271) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_271_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_271_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_271_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_271_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_271_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_271_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_271_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_271_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_271_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_271_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_271_ADDRESS (0x173c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_271_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_271_RESET 0x0 // 0x1740 (BB_SM_HC_PREEMP_LUT_272) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_272_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_272_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_272_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_272_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_272_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_272_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_272_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_272_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_272_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_272_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_272_ADDRESS (0x1740 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_272_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_272_RESET 0x0 // 0x1744 (BB_SM_HC_PREEMP_LUT_273) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_273_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_273_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_273_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_273_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_273_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_273_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_273_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_273_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_273_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_273_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_273_ADDRESS (0x1744 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_273_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_273_RESET 0x0 // 0x1748 (BB_SM_HC_PREEMP_LUT_274) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_274_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_274_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_274_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_274_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_274_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_274_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_274_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_274_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_274_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_274_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_274_ADDRESS (0x1748 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_274_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_274_RESET 0x0 // 0x174c (BB_SM_HC_PREEMP_LUT_275) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_275_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_275_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_275_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_275_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_275_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_275_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_275_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_275_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_275_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_275_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_275_ADDRESS (0x174c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_275_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_275_RESET 0x0 // 0x1750 (BB_SM_HC_PREEMP_LUT_276) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_276_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_276_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_276_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_276_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_276_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_276_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_276_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_276_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_276_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_276_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_276_ADDRESS (0x1750 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_276_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_276_RESET 0x0 // 0x1754 (BB_SM_HC_PREEMP_LUT_277) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_277_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_277_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_277_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_277_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_277_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_277_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_277_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_277_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_277_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_277_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_277_ADDRESS (0x1754 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_277_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_277_RESET 0x0 // 0x1758 (BB_SM_HC_PREEMP_LUT_278) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_278_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_278_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_278_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_278_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_278_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_278_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_278_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_278_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_278_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_278_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_278_ADDRESS (0x1758 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_278_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_278_RESET 0x0 // 0x175c (BB_SM_HC_PREEMP_LUT_279) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_279_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_279_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_279_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_279_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_279_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_279_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_279_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_279_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_279_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_279_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_279_ADDRESS (0x175c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_279_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_279_RESET 0x0 // 0x1760 (BB_SM_HC_PREEMP_LUT_280) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_280_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_280_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_280_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_280_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_280_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_280_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_280_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_280_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_280_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_280_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_280_ADDRESS (0x1760 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_280_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_280_RESET 0x0 // 0x1764 (BB_SM_HC_PREEMP_LUT_281) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_281_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_281_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_281_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_281_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_281_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_281_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_281_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_281_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_281_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_281_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_281_ADDRESS (0x1764 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_281_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_281_RESET 0x0 // 0x1768 (BB_SM_HC_PREEMP_LUT_282) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_282_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_282_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_282_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_282_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_282_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_282_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_282_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_282_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_282_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_282_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_282_ADDRESS (0x1768 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_282_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_282_RESET 0x0 // 0x176c (BB_SM_HC_PREEMP_LUT_283) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_283_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_283_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_283_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_283_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_283_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_283_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_283_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_283_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_283_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_283_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_283_ADDRESS (0x176c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_283_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_283_RESET 0x0 // 0x1770 (BB_SM_HC_PREEMP_LUT_284) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_284_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_284_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_284_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_284_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_284_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_284_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_284_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_284_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_284_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_284_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_284_ADDRESS (0x1770 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_284_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_284_RESET 0x0 // 0x1774 (BB_SM_HC_PREEMP_LUT_285) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_285_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_285_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_285_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_285_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_285_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_285_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_285_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_285_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_285_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_285_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_285_ADDRESS (0x1774 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_285_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_285_RESET 0x0 // 0x1778 (BB_SM_HC_PREEMP_LUT_286) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_286_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_286_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_286_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_286_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_286_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_286_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_286_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_286_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_286_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_286_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_286_ADDRESS (0x1778 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_286_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_286_RESET 0x0 // 0x177c (BB_SM_HC_PREEMP_LUT_287) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_287_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_287_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_287_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_287_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_287_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_287_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_287_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_287_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_287_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_287_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_287_ADDRESS (0x177c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_287_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_287_RESET 0x0 // 0x1780 (BB_SM_HC_PREEMP_LUT_288) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_288_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_288_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_288_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_288_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_288_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_288_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_288_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_288_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_288_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_288_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_288_ADDRESS (0x1780 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_288_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_288_RESET 0x0 // 0x1784 (BB_SM_HC_PREEMP_LUT_289) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_289_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_289_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_289_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_289_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_289_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_289_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_289_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_289_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_289_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_289_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_289_ADDRESS (0x1784 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_289_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_289_RESET 0x0 // 0x1788 (BB_SM_HC_PREEMP_LUT_290) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_290_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_290_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_290_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_290_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_290_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_290_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_290_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_290_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_290_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_290_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_290_ADDRESS (0x1788 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_290_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_290_RESET 0x0 // 0x178c (BB_SM_HC_PREEMP_LUT_291) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_291_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_291_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_291_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_291_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_291_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_291_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_291_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_291_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_291_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_291_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_291_ADDRESS (0x178c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_291_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_291_RESET 0x0 // 0x1790 (BB_SM_HC_PREEMP_LUT_292) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_292_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_292_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_292_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_292_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_292_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_292_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_292_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_292_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_292_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_292_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_292_ADDRESS (0x1790 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_292_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_292_RESET 0x0 // 0x1794 (BB_SM_HC_PREEMP_LUT_293) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_293_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_293_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_293_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_293_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_293_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_293_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_293_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_293_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_293_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_293_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_293_ADDRESS (0x1794 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_293_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_293_RESET 0x0 // 0x1798 (BB_SM_HC_PREEMP_LUT_294) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_294_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_294_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_294_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_294_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_294_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_294_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_294_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_294_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_294_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_294_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_294_ADDRESS (0x1798 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_294_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_294_RESET 0x0 // 0x179c (BB_SM_HC_PREEMP_LUT_295) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_295_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_295_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_295_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_295_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_295_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_295_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_295_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_295_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_295_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_295_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_295_ADDRESS (0x179c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_295_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_295_RESET 0x0 // 0x17a0 (BB_SM_HC_PREEMP_LUT_296) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_296_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_296_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_296_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_296_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_296_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_296_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_296_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_296_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_296_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_296_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_296_ADDRESS (0x17a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_296_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_296_RESET 0x0 // 0x17a4 (BB_SM_HC_PREEMP_LUT_297) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_297_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_297_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_297_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_297_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_297_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_297_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_297_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_297_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_297_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_297_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_297_ADDRESS (0x17a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_297_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_297_RESET 0x0 // 0x17a8 (BB_SM_HC_PREEMP_LUT_298) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_298_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_298_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_298_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_298_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_298_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_298_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_298_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_298_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_298_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_298_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_298_ADDRESS (0x17a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_298_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_298_RESET 0x0 // 0x17ac (BB_SM_HC_PREEMP_LUT_299) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_299_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_299_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_299_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_299_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_299_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_299_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_299_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_299_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_299_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_299_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_299_ADDRESS (0x17ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_299_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_299_RESET 0x0 // 0x17b0 (BB_SM_HC_PREEMP_LUT_300) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_300_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_300_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_300_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_300_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_300_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_300_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_300_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_300_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_300_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_300_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_300_ADDRESS (0x17b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_300_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_300_RESET 0x0 // 0x17b4 (BB_SM_HC_PREEMP_LUT_301) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_301_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_301_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_301_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_301_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_301_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_301_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_301_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_301_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_301_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_301_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_301_ADDRESS (0x17b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_301_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_301_RESET 0x0 // 0x17b8 (BB_SM_HC_PREEMP_LUT_302) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_302_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_302_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_302_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_302_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_302_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_302_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_302_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_302_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_302_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_302_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_302_ADDRESS (0x17b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_302_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_302_RESET 0x0 // 0x17bc (BB_SM_HC_PREEMP_LUT_303) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_303_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_303_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_303_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_303_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_303_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_303_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_303_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_303_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_303_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_303_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_303_ADDRESS (0x17bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_303_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_303_RESET 0x0 // 0x17c0 (BB_SM_HC_PREEMP_LUT_304) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_304_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_304_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_304_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_304_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_304_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_304_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_304_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_304_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_304_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_304_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_304_ADDRESS (0x17c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_304_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_304_RESET 0x0 // 0x17c4 (BB_SM_HC_PREEMP_LUT_305) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_305_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_305_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_305_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_305_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_305_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_305_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_305_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_305_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_305_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_305_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_305_ADDRESS (0x17c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_305_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_305_RESET 0x0 // 0x17c8 (BB_SM_HC_PREEMP_LUT_306) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_306_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_306_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_306_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_306_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_306_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_306_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_306_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_306_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_306_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_306_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_306_ADDRESS (0x17c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_306_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_306_RESET 0x0 // 0x17cc (BB_SM_HC_PREEMP_LUT_307) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_307_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_307_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_307_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_307_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_307_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_307_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_307_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_307_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_307_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_307_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_307_ADDRESS (0x17cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_307_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_307_RESET 0x0 // 0x17d0 (BB_SM_HC_PREEMP_LUT_308) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_308_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_308_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_308_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_308_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_308_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_308_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_308_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_308_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_308_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_308_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_308_ADDRESS (0x17d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_308_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_308_RESET 0x0 // 0x17d4 (BB_SM_HC_PREEMP_LUT_309) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_309_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_309_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_309_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_309_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_309_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_309_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_309_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_309_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_309_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_309_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_309_ADDRESS (0x17d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_309_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_309_RESET 0x0 // 0x17d8 (BB_SM_HC_PREEMP_LUT_310) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_310_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_310_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_310_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_310_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_310_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_310_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_310_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_310_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_310_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_310_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_310_ADDRESS (0x17d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_310_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_310_RESET 0x0 // 0x17dc (BB_SM_HC_PREEMP_LUT_311) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_311_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_311_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_311_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_311_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_311_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_311_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_311_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_311_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_311_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_311_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_311_ADDRESS (0x17dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_311_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_311_RESET 0x0 // 0x17e0 (BB_SM_HC_PREEMP_LUT_312) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_312_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_312_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_312_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_312_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_312_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_312_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_312_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_312_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_312_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_312_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_312_ADDRESS (0x17e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_312_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_312_RESET 0x0 // 0x17e4 (BB_SM_HC_PREEMP_LUT_313) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_313_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_313_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_313_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_313_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_313_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_313_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_313_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_313_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_313_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_313_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_313_ADDRESS (0x17e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_313_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_313_RESET 0x0 // 0x17e8 (BB_SM_HC_PREEMP_LUT_314) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_314_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_314_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_314_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_314_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_314_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_314_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_314_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_314_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_314_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_314_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_314_ADDRESS (0x17e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_314_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_314_RESET 0x0 // 0x17ec (BB_SM_HC_PREEMP_LUT_315) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_315_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_315_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_315_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_315_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_315_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_315_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_315_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_315_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_315_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_315_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_315_ADDRESS (0x17ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_315_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_315_RESET 0x0 // 0x17f0 (BB_SM_HC_PREEMP_LUT_316) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_316_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_316_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_316_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_316_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_316_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_316_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_316_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_316_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_316_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_316_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_316_ADDRESS (0x17f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_316_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_316_RESET 0x0 // 0x17f4 (BB_SM_HC_PREEMP_LUT_317) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_317_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_317_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_317_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_317_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_317_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_317_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_317_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_317_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_317_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_317_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_317_ADDRESS (0x17f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_317_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_317_RESET 0x0 // 0x17f8 (BB_SM_HC_PREEMP_LUT_318) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_318_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_318_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_318_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_318_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_318_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_318_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_318_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_318_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_318_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_318_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_318_ADDRESS (0x17f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_318_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_318_RESET 0x0 // 0x17fc (BB_SM_HC_PREEMP_LUT_319) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_319_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_319_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_319_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_319_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_319_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_319_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_319_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_319_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_319_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_319_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_319_ADDRESS (0x17fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_319_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_319_RESET 0x0 // 0x1800 (BB_SM_HC_PREEMP_LUT_320) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_320_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_320_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_320_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_320_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_320_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_320_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_320_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_320_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_320_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_320_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_320_ADDRESS (0x1800 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_320_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_320_RESET 0x0 // 0x1804 (BB_SM_HC_PREEMP_LUT_321) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_321_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_321_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_321_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_321_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_321_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_321_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_321_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_321_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_321_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_321_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_321_ADDRESS (0x1804 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_321_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_321_RESET 0x0 // 0x1808 (BB_SM_HC_PREEMP_LUT_322) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_322_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_322_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_322_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_322_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_322_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_322_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_322_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_322_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_322_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_322_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_322_ADDRESS (0x1808 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_322_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_322_RESET 0x0 // 0x180c (BB_SM_HC_PREEMP_LUT_323) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_323_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_323_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_323_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_323_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_323_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_323_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_323_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_323_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_323_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_323_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_323_ADDRESS (0x180c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_323_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_323_RESET 0x0 // 0x1810 (BB_SM_HC_PREEMP_LUT_324) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_324_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_324_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_324_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_324_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_324_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_324_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_324_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_324_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_324_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_324_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_324_ADDRESS (0x1810 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_324_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_324_RESET 0x0 // 0x1814 (BB_SM_HC_PREEMP_LUT_325) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_325_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_325_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_325_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_325_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_325_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_325_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_325_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_325_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_325_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_325_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_325_ADDRESS (0x1814 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_325_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_325_RESET 0x0 // 0x1818 (BB_SM_HC_PREEMP_LUT_326) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_326_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_326_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_326_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_326_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_326_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_326_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_326_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_326_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_326_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_326_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_326_ADDRESS (0x1818 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_326_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_326_RESET 0x0 // 0x181c (BB_SM_HC_PREEMP_LUT_327) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_327_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_327_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_327_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_327_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_327_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_327_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_327_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_327_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_327_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_327_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_327_ADDRESS (0x181c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_327_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_327_RESET 0x0 // 0x1820 (BB_SM_HC_PREEMP_LUT_328) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_328_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_328_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_328_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_328_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_328_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_328_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_328_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_328_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_328_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_328_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_328_ADDRESS (0x1820 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_328_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_328_RESET 0x0 // 0x1824 (BB_SM_HC_PREEMP_LUT_329) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_329_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_329_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_329_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_329_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_329_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_329_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_329_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_329_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_329_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_329_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_329_ADDRESS (0x1824 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_329_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_329_RESET 0x0 // 0x1828 (BB_SM_HC_PREEMP_LUT_330) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_330_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_330_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_330_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_330_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_330_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_330_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_330_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_330_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_330_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_330_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_330_ADDRESS (0x1828 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_330_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_330_RESET 0x0 // 0x182c (BB_SM_HC_PREEMP_LUT_331) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_331_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_331_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_331_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_331_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_331_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_331_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_331_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_331_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_331_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_331_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_331_ADDRESS (0x182c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_331_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_331_RESET 0x0 // 0x1830 (BB_SM_HC_PREEMP_LUT_332) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_332_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_332_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_332_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_332_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_332_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_332_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_332_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_332_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_332_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_332_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_332_ADDRESS (0x1830 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_332_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_332_RESET 0x0 // 0x1834 (BB_SM_HC_PREEMP_LUT_333) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_333_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_333_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_333_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_333_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_333_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_333_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_333_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_333_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_333_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_333_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_333_ADDRESS (0x1834 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_333_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_333_RESET 0x0 // 0x1838 (BB_SM_HC_PREEMP_LUT_334) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_334_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_334_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_334_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_334_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_334_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_334_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_334_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_334_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_334_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_334_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_334_ADDRESS (0x1838 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_334_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_334_RESET 0x0 // 0x183c (BB_SM_HC_PREEMP_LUT_335) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_335_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_335_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_335_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_335_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_335_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_335_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_335_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_335_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_335_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_335_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_335_ADDRESS (0x183c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_335_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_335_RESET 0x0 // 0x1840 (BB_SM_HC_PREEMP_LUT_336) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_336_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_336_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_336_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_336_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_336_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_336_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_336_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_336_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_336_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_336_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_336_ADDRESS (0x1840 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_336_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_336_RESET 0x0 // 0x1844 (BB_SM_HC_PREEMP_LUT_337) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_337_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_337_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_337_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_337_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_337_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_337_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_337_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_337_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_337_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_337_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_337_ADDRESS (0x1844 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_337_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_337_RESET 0x0 // 0x1848 (BB_SM_HC_PREEMP_LUT_338) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_338_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_338_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_338_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_338_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_338_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_338_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_338_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_338_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_338_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_338_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_338_ADDRESS (0x1848 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_338_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_338_RESET 0x0 // 0x184c (BB_SM_HC_PREEMP_LUT_339) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_339_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_339_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_339_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_339_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_339_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_339_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_339_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_339_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_339_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_339_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_339_ADDRESS (0x184c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_339_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_339_RESET 0x0 // 0x1850 (BB_SM_HC_PREEMP_LUT_340) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_340_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_340_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_340_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_340_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_340_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_340_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_340_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_340_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_340_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_340_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_340_ADDRESS (0x1850 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_340_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_340_RESET 0x0 // 0x1854 (BB_SM_HC_PREEMP_LUT_341) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_341_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_341_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_341_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_341_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_341_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_341_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_341_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_341_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_341_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_341_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_341_ADDRESS (0x1854 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_341_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_341_RESET 0x0 // 0x1858 (BB_SM_HC_PREEMP_LUT_342) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_342_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_342_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_342_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_342_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_342_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_342_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_342_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_342_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_342_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_342_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_342_ADDRESS (0x1858 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_342_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_342_RESET 0x0 // 0x185c (BB_SM_HC_PREEMP_LUT_343) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_343_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_343_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_343_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_343_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_343_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_343_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_343_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_343_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_343_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_343_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_343_ADDRESS (0x185c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_343_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_343_RESET 0x0 // 0x1860 (BB_SM_HC_PREEMP_LUT_344) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_344_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_344_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_344_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_344_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_344_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_344_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_344_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_344_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_344_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_344_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_344_ADDRESS (0x1860 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_344_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_344_RESET 0x0 // 0x1864 (BB_SM_HC_PREEMP_LUT_345) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_345_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_345_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_345_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_345_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_345_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_345_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_345_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_345_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_345_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_345_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_345_ADDRESS (0x1864 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_345_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_345_RESET 0x0 // 0x1868 (BB_SM_HC_PREEMP_LUT_346) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_346_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_346_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_346_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_346_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_346_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_346_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_346_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_346_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_346_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_346_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_346_ADDRESS (0x1868 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_346_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_346_RESET 0x0 // 0x186c (BB_SM_HC_PREEMP_LUT_347) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_347_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_347_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_347_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_347_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_347_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_347_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_347_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_347_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_347_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_347_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_347_ADDRESS (0x186c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_347_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_347_RESET 0x0 // 0x1870 (BB_SM_HC_PREEMP_LUT_348) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_348_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_348_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_348_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_348_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_348_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_348_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_348_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_348_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_348_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_348_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_348_ADDRESS (0x1870 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_348_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_348_RESET 0x0 // 0x1874 (BB_SM_HC_PREEMP_LUT_349) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_349_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_349_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_349_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_349_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_349_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_349_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_349_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_349_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_349_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_349_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_349_ADDRESS (0x1874 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_349_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_349_RESET 0x0 // 0x1878 (BB_SM_HC_PREEMP_LUT_350) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_350_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_350_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_350_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_350_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_350_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_350_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_350_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_350_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_350_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_350_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_350_ADDRESS (0x1878 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_350_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_350_RESET 0x0 // 0x187c (BB_SM_HC_PREEMP_LUT_351) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_351_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_351_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_351_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_351_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_351_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_351_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_351_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_351_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_351_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_351_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_351_ADDRESS (0x187c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_351_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_351_RESET 0x0 // 0x1880 (BB_SM_HC_PREEMP_LUT_352) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_352_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_352_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_352_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_352_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_352_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_352_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_352_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_352_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_352_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_352_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_352_ADDRESS (0x1880 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_352_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_352_RESET 0x0 // 0x1884 (BB_SM_HC_PREEMP_LUT_353) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_353_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_353_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_353_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_353_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_353_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_353_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_353_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_353_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_353_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_353_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_353_ADDRESS (0x1884 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_353_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_353_RESET 0x0 // 0x1888 (BB_SM_HC_PREEMP_LUT_354) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_354_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_354_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_354_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_354_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_354_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_354_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_354_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_354_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_354_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_354_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_354_ADDRESS (0x1888 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_354_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_354_RESET 0x0 // 0x188c (BB_SM_HC_PREEMP_LUT_355) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_355_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_355_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_355_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_355_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_355_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_355_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_355_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_355_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_355_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_355_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_355_ADDRESS (0x188c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_355_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_355_RESET 0x0 // 0x1890 (BB_SM_HC_PREEMP_LUT_356) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_356_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_356_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_356_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_356_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_356_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_356_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_356_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_356_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_356_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_356_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_356_ADDRESS (0x1890 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_356_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_356_RESET 0x0 // 0x1894 (BB_SM_HC_PREEMP_LUT_357) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_357_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_357_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_357_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_357_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_357_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_357_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_357_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_357_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_357_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_357_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_357_ADDRESS (0x1894 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_357_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_357_RESET 0x0 // 0x1898 (BB_SM_HC_PREEMP_LUT_358) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_358_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_358_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_358_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_358_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_358_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_358_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_358_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_358_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_358_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_358_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_358_ADDRESS (0x1898 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_358_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_358_RESET 0x0 // 0x189c (BB_SM_HC_PREEMP_LUT_359) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_359_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_359_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_359_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_359_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_359_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_359_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_359_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_359_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_359_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_359_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_359_ADDRESS (0x189c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_359_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_359_RESET 0x0 // 0x18a0 (BB_SM_HC_PREEMP_LUT_360) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_360_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_360_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_360_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_360_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_360_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_360_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_360_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_360_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_360_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_360_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_360_ADDRESS (0x18a0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_360_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_360_RESET 0x0 // 0x18a4 (BB_SM_HC_PREEMP_LUT_361) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_361_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_361_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_361_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_361_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_361_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_361_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_361_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_361_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_361_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_361_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_361_ADDRESS (0x18a4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_361_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_361_RESET 0x0 // 0x18a8 (BB_SM_HC_PREEMP_LUT_362) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_362_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_362_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_362_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_362_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_362_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_362_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_362_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_362_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_362_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_362_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_362_ADDRESS (0x18a8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_362_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_362_RESET 0x0 // 0x18ac (BB_SM_HC_PREEMP_LUT_363) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_363_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_363_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_363_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_363_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_363_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_363_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_363_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_363_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_363_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_363_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_363_ADDRESS (0x18ac + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_363_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_363_RESET 0x0 // 0x18b0 (BB_SM_HC_PREEMP_LUT_364) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_364_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_364_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_364_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_364_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_364_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_364_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_364_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_364_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_364_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_364_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_364_ADDRESS (0x18b0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_364_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_364_RESET 0x0 // 0x18b4 (BB_SM_HC_PREEMP_LUT_365) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_365_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_365_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_365_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_365_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_365_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_365_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_365_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_365_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_365_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_365_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_365_ADDRESS (0x18b4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_365_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_365_RESET 0x0 // 0x18b8 (BB_SM_HC_PREEMP_LUT_366) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_366_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_366_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_366_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_366_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_366_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_366_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_366_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_366_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_366_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_366_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_366_ADDRESS (0x18b8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_366_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_366_RESET 0x0 // 0x18bc (BB_SM_HC_PREEMP_LUT_367) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_367_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_367_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_367_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_367_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_367_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_367_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_367_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_367_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_367_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_367_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_367_ADDRESS (0x18bc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_367_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_367_RESET 0x0 // 0x18c0 (BB_SM_HC_PREEMP_LUT_368) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_368_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_368_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_368_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_368_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_368_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_368_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_368_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_368_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_368_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_368_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_368_ADDRESS (0x18c0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_368_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_368_RESET 0x0 // 0x18c4 (BB_SM_HC_PREEMP_LUT_369) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_369_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_369_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_369_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_369_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_369_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_369_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_369_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_369_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_369_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_369_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_369_ADDRESS (0x18c4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_369_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_369_RESET 0x0 // 0x18c8 (BB_SM_HC_PREEMP_LUT_370) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_370_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_370_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_370_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_370_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_370_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_370_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_370_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_370_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_370_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_370_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_370_ADDRESS (0x18c8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_370_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_370_RESET 0x0 // 0x18cc (BB_SM_HC_PREEMP_LUT_371) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_371_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_371_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_371_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_371_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_371_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_371_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_371_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_371_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_371_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_371_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_371_ADDRESS (0x18cc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_371_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_371_RESET 0x0 // 0x18d0 (BB_SM_HC_PREEMP_LUT_372) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_372_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_372_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_372_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_372_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_372_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_372_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_372_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_372_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_372_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_372_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_372_ADDRESS (0x18d0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_372_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_372_RESET 0x0 // 0x18d4 (BB_SM_HC_PREEMP_LUT_373) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_373_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_373_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_373_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_373_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_373_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_373_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_373_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_373_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_373_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_373_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_373_ADDRESS (0x18d4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_373_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_373_RESET 0x0 // 0x18d8 (BB_SM_HC_PREEMP_LUT_374) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_374_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_374_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_374_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_374_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_374_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_374_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_374_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_374_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_374_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_374_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_374_ADDRESS (0x18d8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_374_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_374_RESET 0x0 // 0x18dc (BB_SM_HC_PREEMP_LUT_375) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_375_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_375_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_375_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_375_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_375_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_375_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_375_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_375_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_375_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_375_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_375_ADDRESS (0x18dc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_375_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_375_RESET 0x0 // 0x18e0 (BB_SM_HC_PREEMP_LUT_376) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_376_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_376_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_376_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_376_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_376_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_376_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_376_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_376_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_376_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_376_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_376_ADDRESS (0x18e0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_376_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_376_RESET 0x0 // 0x18e4 (BB_SM_HC_PREEMP_LUT_377) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_377_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_377_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_377_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_377_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_377_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_377_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_377_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_377_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_377_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_377_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_377_ADDRESS (0x18e4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_377_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_377_RESET 0x0 // 0x18e8 (BB_SM_HC_PREEMP_LUT_378) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_378_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_378_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_378_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_378_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_378_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_378_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_378_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_378_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_378_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_378_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_378_ADDRESS (0x18e8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_378_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_378_RESET 0x0 // 0x18ec (BB_SM_HC_PREEMP_LUT_379) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_379_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_379_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_379_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_379_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_379_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_379_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_379_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_379_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_379_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_379_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_379_ADDRESS (0x18ec + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_379_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_379_RESET 0x0 // 0x18f0 (BB_SM_HC_PREEMP_LUT_380) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_380_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_380_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_380_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_380_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_380_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_380_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_380_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_380_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_380_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_380_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_380_ADDRESS (0x18f0 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_380_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_380_RESET 0x0 // 0x18f4 (BB_SM_HC_PREEMP_LUT_381) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_381_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_381_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_381_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_381_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_381_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_381_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_381_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_381_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_381_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_381_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_381_ADDRESS (0x18f4 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_381_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_381_RESET 0x0 // 0x18f8 (BB_SM_HC_PREEMP_LUT_382) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_382_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_382_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_382_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_382_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_382_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_382_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_382_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_382_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_382_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_382_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_382_ADDRESS (0x18f8 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_382_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_382_RESET 0x0 // 0x18fc (BB_SM_HC_PREEMP_LUT_383) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_383_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_383_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_383_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_383_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_383_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_383_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_383_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_383_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_383_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_383_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_383_ADDRESS (0x18fc + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_383_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_383_RESET 0x0 // 0x1900 (BB_SM_HC_PREEMP_LUT_384) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_384_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_384_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_384_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_384_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_384_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_384_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_384_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_384_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_384_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_384_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_384_ADDRESS (0x1900 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_384_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_384_RESET 0x0 // 0x1904 (BB_SM_HC_PREEMP_LUT_385) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_385_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_385_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_385_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_385_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_385_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_385_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_385_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_385_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_385_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_385_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_385_ADDRESS (0x1904 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_385_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_385_RESET 0x0 // 0x1908 (BB_SM_HC_PREEMP_LUT_386) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_386_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_386_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_386_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_386_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_386_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_386_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_386_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_386_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_386_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_386_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_386_ADDRESS (0x1908 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_386_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_386_RESET 0x0 // 0x190c (BB_SM_HC_PREEMP_LUT_387) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_387_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_387_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_387_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_387_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_387_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_387_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_387_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_387_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_387_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_387_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_387_ADDRESS (0x190c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_387_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_387_RESET 0x0 // 0x1910 (BB_SM_HC_PREEMP_LUT_388) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_388_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_388_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_388_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_388_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_388_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_388_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_388_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_388_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_388_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_388_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_388_ADDRESS (0x1910 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_388_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_388_RESET 0x0 // 0x1914 (BB_SM_HC_PREEMP_LUT_389) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_389_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_389_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_389_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_389_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_389_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_389_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_389_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_389_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_389_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_389_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_389_ADDRESS (0x1914 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_389_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_389_RESET 0x0 // 0x1918 (BB_SM_HC_PREEMP_LUT_390) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_390_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_390_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_390_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_390_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_390_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_390_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_390_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_390_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_390_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_390_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_390_ADDRESS (0x1918 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_390_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_390_RESET 0x0 // 0x191c (BB_SM_HC_PREEMP_LUT_391) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_391_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_391_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_391_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_391_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_391_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_391_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_391_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_391_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_391_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_391_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_391_ADDRESS (0x191c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_391_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_391_RESET 0x0 // 0x1920 (BB_SM_HC_PREEMP_LUT_392) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_392_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_392_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_392_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_392_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_392_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_392_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_392_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_392_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_392_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_392_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_392_ADDRESS (0x1920 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_392_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_392_RESET 0x0 // 0x1924 (BB_SM_HC_PREEMP_LUT_393) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_393_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_393_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_393_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_393_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_393_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_393_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_393_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_393_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_393_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_393_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_393_ADDRESS (0x1924 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_393_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_393_RESET 0x0 // 0x1928 (BB_SM_HC_PREEMP_LUT_394) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_394_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_394_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_394_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_394_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_394_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_394_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_394_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_394_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_394_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_394_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_394_ADDRESS (0x1928 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_394_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_394_RESET 0x0 // 0x192c (BB_SM_HC_PREEMP_LUT_395) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_395_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_395_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_395_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_395_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_395_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_395_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_395_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_395_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_395_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_395_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_395_ADDRESS (0x192c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_395_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_395_RESET 0x0 // 0x1930 (BB_SM_HC_PREEMP_LUT_396) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_396_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_396_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_396_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_396_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_396_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_396_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_396_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_396_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_396_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_396_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_396_ADDRESS (0x1930 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_396_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_396_RESET 0x0 // 0x1934 (BB_SM_HC_PREEMP_LUT_397) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_397_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_397_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_397_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_397_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_397_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_397_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_397_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_397_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_397_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_397_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_397_ADDRESS (0x1934 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_397_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_397_RESET 0x0 // 0x1938 (BB_SM_HC_PREEMP_LUT_398) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_398_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_398_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_398_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_398_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_398_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_398_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_398_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_398_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_398_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_398_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_398_ADDRESS (0x1938 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_398_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_398_RESET 0x0 // 0x193c (BB_SM_HC_PREEMP_LUT_399) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_399_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_399_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_399_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_399_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_399_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_399_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_399_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_399_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_399_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_399_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_399_ADDRESS (0x193c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_399_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_399_RESET 0x0 // 0x1940 (BB_SM_HC_PREEMP_LUT_400) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_400_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_400_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_400_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_400_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_400_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_400_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_400_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_400_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_400_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_400_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_400_ADDRESS (0x1940 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_400_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_400_RESET 0x0 // 0x1944 (BB_SM_HC_PREEMP_LUT_401) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_401_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_401_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_401_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_401_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_401_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_401_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_401_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_401_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_401_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_401_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_401_ADDRESS (0x1944 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_401_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_401_RESET 0x0 // 0x1948 (BB_SM_HC_PREEMP_LUT_402) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_402_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_402_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_402_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_402_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_402_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_402_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_402_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_402_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_402_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_402_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_402_ADDRESS (0x1948 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_402_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_402_RESET 0x0 // 0x194c (BB_SM_HC_PREEMP_LUT_403) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_403_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_403_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_403_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_403_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_403_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_403_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_403_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_403_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_403_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_403_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_403_ADDRESS (0x194c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_403_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_403_RESET 0x0 // 0x1950 (BB_SM_HC_PREEMP_LUT_404) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_404_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_404_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_404_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_404_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_404_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_404_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_404_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_404_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_404_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_404_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_404_ADDRESS (0x1950 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_404_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_404_RESET 0x0 // 0x1954 (BB_SM_HC_PREEMP_LUT_405) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_405_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_405_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_405_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_405_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_405_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_405_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_405_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_405_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_405_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_405_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_405_ADDRESS (0x1954 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_405_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_405_RESET 0x0 // 0x1958 (BB_SM_HC_PREEMP_LUT_406) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_406_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_406_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_406_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_406_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_406_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_406_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_406_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_406_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_406_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_406_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_406_ADDRESS (0x1958 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_406_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_406_RESET 0x0 // 0x195c (BB_SM_HC_PREEMP_LUT_407) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_407_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_407_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_407_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_407_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_407_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_407_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_407_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_407_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_407_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_407_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_407_ADDRESS (0x195c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_407_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_407_RESET 0x0 // 0x1960 (BB_SM_HC_PREEMP_LUT_408) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_408_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_408_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_408_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_408_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_408_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_408_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_408_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_408_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_408_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_408_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_408_ADDRESS (0x1960 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_408_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_408_RESET 0x0 // 0x1964 (BB_SM_HC_PREEMP_LUT_409) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_409_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_409_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_409_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_409_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_409_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_409_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_409_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_409_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_409_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_409_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_409_ADDRESS (0x1964 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_409_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_409_RESET 0x0 // 0x1968 (BB_SM_HC_PREEMP_LUT_410) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_410_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_410_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_410_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_410_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_410_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_410_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_410_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_410_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_410_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_410_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_410_ADDRESS (0x1968 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_410_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_410_RESET 0x0 // 0x196c (BB_SM_HC_PREEMP_LUT_411) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_411_LSB 0 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_411_MSB 17 #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_411_MASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_411_GET(x) (((x) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_411_MASK) >> BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_411_LSB) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_411_SET(x) (((0 | (x)) << BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_411_LSB) & BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_411_MASK) #define BB_SM_HC_PREEMP_LUT_SM_HC_PREEMP_LUT_WORD_411_RESET 0x0 #define BB_SM_HC_PREEMP_LUT_411_ADDRESS (0x196c + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_HC_PREEMP_LUT_411_RSTMASK 0x3ffff #define BB_SM_HC_PREEMP_LUT_411_RESET 0x0 // 0x1970 (BB_SM_TABLES_DUMMY2) #define BB_SM_TABLES_DUMMY2_DUMMY2_LSB 0 #define BB_SM_TABLES_DUMMY2_DUMMY2_MSB 31 #define BB_SM_TABLES_DUMMY2_DUMMY2_MASK 0xffffffff #define BB_SM_TABLES_DUMMY2_DUMMY2_GET(x) (((x) & BB_SM_TABLES_DUMMY2_DUMMY2_MASK) >> BB_SM_TABLES_DUMMY2_DUMMY2_LSB) #define BB_SM_TABLES_DUMMY2_DUMMY2_SET(x) (((0 | (x)) << BB_SM_TABLES_DUMMY2_DUMMY2_LSB) & BB_SM_TABLES_DUMMY2_DUMMY2_MASK) #define BB_SM_TABLES_DUMMY2_DUMMY2_RESET 0x0 #define BB_SM_TABLES_DUMMY2_ADDRESS (0x1970 + __SM_TABLE_MAP_BASE_ADDRESS) #define BB_SM_TABLES_DUMMY2_RSTMASK 0xffffffff #define BB_SM_TABLES_DUMMY2_RESET 0x0 #endif /* _SM_TABLE_MAP_H_ */