// // ----------------------------------------------------------------------------- // Copyright (c) 2011-2014 Qualcomm Atheros, Inc. All rights reserved. // ----------------------------------------------------------------------------- // FILE : sm_reg_map.h // DESCRIPTION : Software Header File for WiFi 2.0 // THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT // ----------------------------------------------------------------------------- // #ifndef _PHY_SM_REG_MAP_H_ #define _PHY_SM_REG_MAP_H_ #ifndef __PHY_SM_REG_MAP_BASE_ADDRESS #define __PHY_SM_REG_MAP_BASE_ADDRESS (0x10600) #endif // 0x4 (PHY_BB_GEN_CONTROLS) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TPC_MISS_LSB 30 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TPC_MISS_MSB 30 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TPC_MISS_MASK 0x40000000 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TPC_MISS_GET(x) (((x) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_TPC_MISS_MASK) >> PHY_BB_GEN_CONTROLS_ENABLE_ERR_TPC_MISS_LSB) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TPC_MISS_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_ENABLE_ERR_TPC_MISS_LSB) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_TPC_MISS_MASK) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TPC_MISS_RESET 0x0 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_ILLEGAL_RATE_LSB 29 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_ILLEGAL_RATE_MSB 29 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_ILLEGAL_RATE_MASK 0x20000000 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_ILLEGAL_RATE_GET(x) (((x) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_ILLEGAL_RATE_MASK) >> PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_ILLEGAL_RATE_LSB) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_ILLEGAL_RATE_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_ILLEGAL_RATE_LSB) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_ILLEGAL_RATE_MASK) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_ILLEGAL_RATE_RESET 0x1 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_BW_GT_DYN_BW_LSB 28 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_BW_GT_DYN_BW_MSB 28 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_BW_GT_DYN_BW_MASK 0x10000000 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_BW_GT_DYN_BW_GET(x) (((x) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_BW_GT_DYN_BW_MASK) >> PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_BW_GT_DYN_BW_LSB) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_BW_GT_DYN_BW_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_BW_GT_DYN_BW_LSB) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_BW_GT_DYN_BW_MASK) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_BW_GT_DYN_BW_RESET 0x1 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_LSIG_LENGTH_CHECK_LSB 27 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_LSIG_LENGTH_CHECK_MSB 27 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_LSIG_LENGTH_CHECK_MASK 0x8000000 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_LSIG_LENGTH_CHECK_GET(x) (((x) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_LSIG_LENGTH_CHECK_MASK) >> PHY_BB_GEN_CONTROLS_ENABLE_ERR_LSIG_LENGTH_CHECK_LSB) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_LSIG_LENGTH_CHECK_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_ENABLE_ERR_LSIG_LENGTH_CHECK_LSB) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_LSIG_LENGTH_CHECK_MASK) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_LSIG_LENGTH_CHECK_RESET 0x1 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_EXTRA_SYM_MISMATCH_LSB 26 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_EXTRA_SYM_MISMATCH_MSB 26 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_EXTRA_SYM_MISMATCH_MASK 0x4000000 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_EXTRA_SYM_MISMATCH_GET(x) (((x) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_EXTRA_SYM_MISMATCH_MASK) >> PHY_BB_GEN_CONTROLS_ENABLE_ERR_EXTRA_SYM_MISMATCH_LSB) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_EXTRA_SYM_MISMATCH_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_ENABLE_ERR_EXTRA_SYM_MISMATCH_LSB) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_EXTRA_SYM_MISMATCH_MASK) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_EXTRA_SYM_MISMATCH_RESET 0x1 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_CHAIN_MASK_ZERO_LSB 25 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_CHAIN_MASK_ZERO_MSB 25 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_CHAIN_MASK_ZERO_MASK 0x2000000 #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_CHAIN_MASK_ZERO_GET(x) (((x) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_CHAIN_MASK_ZERO_MASK) >> PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_CHAIN_MASK_ZERO_LSB) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_CHAIN_MASK_ZERO_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_CHAIN_MASK_ZERO_LSB) & PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_CHAIN_MASK_ZERO_MASK) #define PHY_BB_GEN_CONTROLS_ENABLE_ERR_TX_CHAIN_MASK_ZERO_RESET 0x1 #define PHY_BB_GEN_CONTROLS_UNSUPP_HT_RATE_THRESHOLD_LSB 18 #define PHY_BB_GEN_CONTROLS_UNSUPP_HT_RATE_THRESHOLD_MSB 24 #define PHY_BB_GEN_CONTROLS_UNSUPP_HT_RATE_THRESHOLD_MASK 0x1fc0000 #define PHY_BB_GEN_CONTROLS_UNSUPP_HT_RATE_THRESHOLD_GET(x) (((x) & PHY_BB_GEN_CONTROLS_UNSUPP_HT_RATE_THRESHOLD_MASK) >> PHY_BB_GEN_CONTROLS_UNSUPP_HT_RATE_THRESHOLD_LSB) #define PHY_BB_GEN_CONTROLS_UNSUPP_HT_RATE_THRESHOLD_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_UNSUPP_HT_RATE_THRESHOLD_LSB) & PHY_BB_GEN_CONTROLS_UNSUPP_HT_RATE_THRESHOLD_MASK) #define PHY_BB_GEN_CONTROLS_UNSUPP_HT_RATE_THRESHOLD_RESET 0x4c #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_ERROR_RPT_LSB 16 #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_ERROR_RPT_MSB 16 #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_ERROR_RPT_MASK 0x10000 #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_ERROR_RPT_GET(x) (((x) & PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_ERROR_RPT_MASK) >> PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_ERROR_RPT_LSB) #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_ERROR_RPT_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_ERROR_RPT_LSB) & PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_ERROR_RPT_MASK) #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_ERROR_RPT_RESET 0x0 #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_HANDLING_LSB 15 #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_HANDLING_MSB 15 #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_HANDLING_MASK 0x8000 #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_HANDLING_GET(x) (((x) & PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_HANDLING_MASK) >> PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_HANDLING_LSB) #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_HANDLING_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_HANDLING_LSB) & PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_HANDLING_MASK) #define PHY_BB_GEN_CONTROLS_STATIC20_MODE_HT40_PACKET_HANDLING_RESET 0x0 #define PHY_BB_GEN_CONTROLS_ENABLE_ADC_ASYNC_FIFO_LSB 13 #define PHY_BB_GEN_CONTROLS_ENABLE_ADC_ASYNC_FIFO_MSB 13 #define PHY_BB_GEN_CONTROLS_ENABLE_ADC_ASYNC_FIFO_MASK 0x2000 #define PHY_BB_GEN_CONTROLS_ENABLE_ADC_ASYNC_FIFO_GET(x) (((x) & PHY_BB_GEN_CONTROLS_ENABLE_ADC_ASYNC_FIFO_MASK) >> PHY_BB_GEN_CONTROLS_ENABLE_ADC_ASYNC_FIFO_LSB) #define PHY_BB_GEN_CONTROLS_ENABLE_ADC_ASYNC_FIFO_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_ENABLE_ADC_ASYNC_FIFO_LSB) & PHY_BB_GEN_CONTROLS_ENABLE_ADC_ASYNC_FIFO_MASK) #define PHY_BB_GEN_CONTROLS_ENABLE_ADC_ASYNC_FIFO_RESET 0x1 #define PHY_BB_GEN_CONTROLS_ENABLE_DAC_ASYNC_FIFO_LSB 12 #define PHY_BB_GEN_CONTROLS_ENABLE_DAC_ASYNC_FIFO_MSB 12 #define PHY_BB_GEN_CONTROLS_ENABLE_DAC_ASYNC_FIFO_MASK 0x1000 #define PHY_BB_GEN_CONTROLS_ENABLE_DAC_ASYNC_FIFO_GET(x) (((x) & PHY_BB_GEN_CONTROLS_ENABLE_DAC_ASYNC_FIFO_MASK) >> PHY_BB_GEN_CONTROLS_ENABLE_DAC_ASYNC_FIFO_LSB) #define PHY_BB_GEN_CONTROLS_ENABLE_DAC_ASYNC_FIFO_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_ENABLE_DAC_ASYNC_FIFO_LSB) & PHY_BB_GEN_CONTROLS_ENABLE_DAC_ASYNC_FIFO_MASK) #define PHY_BB_GEN_CONTROLS_ENABLE_DAC_ASYNC_FIFO_RESET 0x1 #define PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB 11 #define PHY_BB_GEN_CONTROLS_GF_ENABLE_MSB 11 #define PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK 0x800 #define PHY_BB_GEN_CONTROLS_GF_ENABLE_GET(x) (((x) & PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK) >> PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB) #define PHY_BB_GEN_CONTROLS_GF_ENABLE_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB) & PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK) #define PHY_BB_GEN_CONTROLS_GF_ENABLE_RESET 0x0 #define PHY_BB_GEN_CONTROLS_APPLY_WALSH_ON_LEGACY_LSB 10 #define PHY_BB_GEN_CONTROLS_APPLY_WALSH_ON_LEGACY_MSB 10 #define PHY_BB_GEN_CONTROLS_APPLY_WALSH_ON_LEGACY_MASK 0x400 #define PHY_BB_GEN_CONTROLS_APPLY_WALSH_ON_LEGACY_GET(x) (((x) & PHY_BB_GEN_CONTROLS_APPLY_WALSH_ON_LEGACY_MASK) >> PHY_BB_GEN_CONTROLS_APPLY_WALSH_ON_LEGACY_LSB) #define PHY_BB_GEN_CONTROLS_APPLY_WALSH_ON_LEGACY_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_APPLY_WALSH_ON_LEGACY_LSB) & PHY_BB_GEN_CONTROLS_APPLY_WALSH_ON_LEGACY_MASK) #define PHY_BB_GEN_CONTROLS_APPLY_WALSH_ON_LEGACY_RESET 0x1 #define PHY_BB_GEN_CONTROLS_USE_WALSH_FOR_NSTS_EQ_NTX_LSB 9 #define PHY_BB_GEN_CONTROLS_USE_WALSH_FOR_NSTS_EQ_NTX_MSB 9 #define PHY_BB_GEN_CONTROLS_USE_WALSH_FOR_NSTS_EQ_NTX_MASK 0x200 #define PHY_BB_GEN_CONTROLS_USE_WALSH_FOR_NSTS_EQ_NTX_GET(x) (((x) & PHY_BB_GEN_CONTROLS_USE_WALSH_FOR_NSTS_EQ_NTX_MASK) >> PHY_BB_GEN_CONTROLS_USE_WALSH_FOR_NSTS_EQ_NTX_LSB) #define PHY_BB_GEN_CONTROLS_USE_WALSH_FOR_NSTS_EQ_NTX_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_USE_WALSH_FOR_NSTS_EQ_NTX_LSB) & PHY_BB_GEN_CONTROLS_USE_WALSH_FOR_NSTS_EQ_NTX_MASK) #define PHY_BB_GEN_CONTROLS_USE_WALSH_FOR_NSTS_EQ_NTX_RESET 0x1 #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB 8 #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MSB 8 #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK 0x100 #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_GET(x) (((x) & PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK) >> PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB) #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB) & PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK) #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_RESET 0x1 #define PHY_BB_GEN_CONTROLS_VHT_ENABLE_LSB 7 #define PHY_BB_GEN_CONTROLS_VHT_ENABLE_MSB 7 #define PHY_BB_GEN_CONTROLS_VHT_ENABLE_MASK 0x80 #define PHY_BB_GEN_CONTROLS_VHT_ENABLE_GET(x) (((x) & PHY_BB_GEN_CONTROLS_VHT_ENABLE_MASK) >> PHY_BB_GEN_CONTROLS_VHT_ENABLE_LSB) #define PHY_BB_GEN_CONTROLS_VHT_ENABLE_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_VHT_ENABLE_LSB) & PHY_BB_GEN_CONTROLS_VHT_ENABLE_MASK) #define PHY_BB_GEN_CONTROLS_VHT_ENABLE_RESET 0x1 #define PHY_BB_GEN_CONTROLS_DYN_NON_CONTIG_LSB 6 #define PHY_BB_GEN_CONTROLS_DYN_NON_CONTIG_MSB 6 #define PHY_BB_GEN_CONTROLS_DYN_NON_CONTIG_MASK 0x40 #define PHY_BB_GEN_CONTROLS_DYN_NON_CONTIG_GET(x) (((x) & PHY_BB_GEN_CONTROLS_DYN_NON_CONTIG_MASK) >> PHY_BB_GEN_CONTROLS_DYN_NON_CONTIG_LSB) #define PHY_BB_GEN_CONTROLS_DYN_NON_CONTIG_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_DYN_NON_CONTIG_LSB) & PHY_BB_GEN_CONTROLS_DYN_NON_CONTIG_MASK) #define PHY_BB_GEN_CONTROLS_DYN_NON_CONTIG_RESET 0x0 #define PHY_BB_GEN_CONTROLS_DYN_CHN_GAP_LSB 5 #define PHY_BB_GEN_CONTROLS_DYN_CHN_GAP_MSB 5 #define PHY_BB_GEN_CONTROLS_DYN_CHN_GAP_MASK 0x20 #define PHY_BB_GEN_CONTROLS_DYN_CHN_GAP_GET(x) (((x) & PHY_BB_GEN_CONTROLS_DYN_CHN_GAP_MASK) >> PHY_BB_GEN_CONTROLS_DYN_CHN_GAP_LSB) #define PHY_BB_GEN_CONTROLS_DYN_CHN_GAP_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_DYN_CHN_GAP_LSB) & PHY_BB_GEN_CONTROLS_DYN_CHN_GAP_MASK) #define PHY_BB_GEN_CONTROLS_DYN_CHN_GAP_RESET 0x0 #define PHY_BB_GEN_CONTROLS_DYN_PRI_CHN_LSB 2 #define PHY_BB_GEN_CONTROLS_DYN_PRI_CHN_MSB 4 #define PHY_BB_GEN_CONTROLS_DYN_PRI_CHN_MASK 0x1c #define PHY_BB_GEN_CONTROLS_DYN_PRI_CHN_GET(x) (((x) & PHY_BB_GEN_CONTROLS_DYN_PRI_CHN_MASK) >> PHY_BB_GEN_CONTROLS_DYN_PRI_CHN_LSB) #define PHY_BB_GEN_CONTROLS_DYN_PRI_CHN_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_DYN_PRI_CHN_LSB) & PHY_BB_GEN_CONTROLS_DYN_PRI_CHN_MASK) #define PHY_BB_GEN_CONTROLS_DYN_PRI_CHN_RESET 0x0 #define PHY_BB_GEN_CONTROLS_DYN_BW_LSB 0 #define PHY_BB_GEN_CONTROLS_DYN_BW_MSB 1 #define PHY_BB_GEN_CONTROLS_DYN_BW_MASK 0x3 #define PHY_BB_GEN_CONTROLS_DYN_BW_GET(x) (((x) & PHY_BB_GEN_CONTROLS_DYN_BW_MASK) >> PHY_BB_GEN_CONTROLS_DYN_BW_LSB) #define PHY_BB_GEN_CONTROLS_DYN_BW_SET(x) (((0 | (x)) << PHY_BB_GEN_CONTROLS_DYN_BW_LSB) & PHY_BB_GEN_CONTROLS_DYN_BW_MASK) #define PHY_BB_GEN_CONTROLS_DYN_BW_RESET 0x0 #define PHY_BB_GEN_CONTROLS_ADDRESS (0x4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_GEN_CONTROLS_RSTMASK 0x7ffdbfff #define PHY_BB_GEN_CONTROLS_RESET 0x3f303780 // 0x8 (PHY_BB_MODES_SELECT) #define PHY_BB_MODES_SELECT_PMI_FIFO_THRESHOLD_LSB 19 #define PHY_BB_MODES_SELECT_PMI_FIFO_THRESHOLD_MSB 23 #define PHY_BB_MODES_SELECT_PMI_FIFO_THRESHOLD_MASK 0xf80000 #define PHY_BB_MODES_SELECT_PMI_FIFO_THRESHOLD_GET(x) (((x) & PHY_BB_MODES_SELECT_PMI_FIFO_THRESHOLD_MASK) >> PHY_BB_MODES_SELECT_PMI_FIFO_THRESHOLD_LSB) #define PHY_BB_MODES_SELECT_PMI_FIFO_THRESHOLD_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_PMI_FIFO_THRESHOLD_LSB) & PHY_BB_MODES_SELECT_PMI_FIFO_THRESHOLD_MASK) #define PHY_BB_MODES_SELECT_PMI_FIFO_THRESHOLD_RESET 0x18 #define PHY_BB_MODES_SELECT_EN_ERR_CRC_ABORT_LSB 18 #define PHY_BB_MODES_SELECT_EN_ERR_CRC_ABORT_MSB 18 #define PHY_BB_MODES_SELECT_EN_ERR_CRC_ABORT_MASK 0x40000 #define PHY_BB_MODES_SELECT_EN_ERR_CRC_ABORT_GET(x) (((x) & PHY_BB_MODES_SELECT_EN_ERR_CRC_ABORT_MASK) >> PHY_BB_MODES_SELECT_EN_ERR_CRC_ABORT_LSB) #define PHY_BB_MODES_SELECT_EN_ERR_CRC_ABORT_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_EN_ERR_CRC_ABORT_LSB) & PHY_BB_MODES_SELECT_EN_ERR_CRC_ABORT_MASK) #define PHY_BB_MODES_SELECT_EN_ERR_CRC_ABORT_RESET 0x1 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_GRP1TO62_LSB 17 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_GRP1TO62_MSB 17 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_GRP1TO62_MASK 0x20000 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_GRP1TO62_GET(x) (((x) & PHY_BB_MODES_SELECT_EN_ERR_VHT_GRP1TO62_MASK) >> PHY_BB_MODES_SELECT_EN_ERR_VHT_GRP1TO62_LSB) #define PHY_BB_MODES_SELECT_EN_ERR_VHT_GRP1TO62_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_EN_ERR_VHT_GRP1TO62_LSB) & PHY_BB_MODES_SELECT_EN_ERR_VHT_GRP1TO62_MASK) #define PHY_BB_MODES_SELECT_EN_ERR_VHT_GRP1TO62_RESET 0x1 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NSYM_LT_ZERO_LSB 16 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NSYM_LT_ZERO_MSB 16 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NSYM_LT_ZERO_MASK 0x10000 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NSYM_LT_ZERO_GET(x) (((x) & PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NSYM_LT_ZERO_MASK) >> PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NSYM_LT_ZERO_LSB) #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NSYM_LT_ZERO_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NSYM_LT_ZERO_LSB) & PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NSYM_LT_ZERO_MASK) #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NSYM_LT_ZERO_RESET 0x1 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NDP_OR_ZLF_LSB 15 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NDP_OR_ZLF_MSB 15 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NDP_OR_ZLF_MASK 0x8000 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NDP_OR_ZLF_GET(x) (((x) & PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NDP_OR_ZLF_MASK) >> PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NDP_OR_ZLF_LSB) #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NDP_OR_ZLF_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NDP_OR_ZLF_LSB) & PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NDP_OR_ZLF_MASK) #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_NDP_OR_ZLF_RESET 0x1 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_LSIG_LEN_INVALID_LSB 14 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_LSIG_LEN_INVALID_MSB 14 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_LSIG_LEN_INVALID_MASK 0x4000 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_LSIG_LEN_INVALID_GET(x) (((x) & PHY_BB_MODES_SELECT_EN_ERR_VHT_LSIG_LEN_INVALID_MASK) >> PHY_BB_MODES_SELECT_EN_ERR_VHT_LSIG_LEN_INVALID_LSB) #define PHY_BB_MODES_SELECT_EN_ERR_VHT_LSIG_LEN_INVALID_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_EN_ERR_VHT_LSIG_LEN_INVALID_LSB) & PHY_BB_MODES_SELECT_EN_ERR_VHT_LSIG_LEN_INVALID_MASK) #define PHY_BB_MODES_SELECT_EN_ERR_VHT_LSIG_LEN_INVALID_RESET 0x1 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_SIGA_UNSUP_LSB 13 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_SIGA_UNSUP_MSB 13 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_SIGA_UNSUP_MASK 0x2000 #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_SIGA_UNSUP_GET(x) (((x) & PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_SIGA_UNSUP_MASK) >> PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_SIGA_UNSUP_LSB) #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_SIGA_UNSUP_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_SIGA_UNSUP_LSB) & PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_SIGA_UNSUP_MASK) #define PHY_BB_MODES_SELECT_EN_ERR_VHT_RX_SIGA_UNSUP_RESET 0x1 #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_63_LSB 12 #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_63_MSB 12 #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_63_MASK 0x1000 #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_63_GET(x) (((x) & PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_63_MASK) >> PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_63_LSB) #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_63_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_63_LSB) & PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_63_MASK) #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_63_RESET 0x0 #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_0_LSB 11 #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_0_MSB 11 #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_0_MASK 0x800 #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_0_GET(x) (((x) & PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_0_MASK) >> PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_0_LSB) #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_0_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_0_LSB) & PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_0_MASK) #define PHY_BB_MODES_SELECT_SKIP_RX_GRP_ID_0_RESET 0x0 #define PHY_BB_MODES_SELECT_OVSAMP_CLK_MODE_LSB 10 #define PHY_BB_MODES_SELECT_OVSAMP_CLK_MODE_MSB 10 #define PHY_BB_MODES_SELECT_OVSAMP_CLK_MODE_MASK 0x400 #define PHY_BB_MODES_SELECT_OVSAMP_CLK_MODE_GET(x) (((x) & PHY_BB_MODES_SELECT_OVSAMP_CLK_MODE_MASK) >> PHY_BB_MODES_SELECT_OVSAMP_CLK_MODE_LSB) #define PHY_BB_MODES_SELECT_OVSAMP_CLK_MODE_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_OVSAMP_CLK_MODE_LSB) & PHY_BB_MODES_SELECT_OVSAMP_CLK_MODE_MASK) #define PHY_BB_MODES_SELECT_OVSAMP_CLK_MODE_RESET 0x0 #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB 8 #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MSB 8 #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK 0x100 #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_GET(x) (((x) & PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK) >> PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB) #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB) & PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK) #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_RESET 0x0 #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB 7 #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MSB 7 #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK 0x80 #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_GET(x) (((x) & PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK) >> PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB) #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB) & PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK) #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_RESET 0x0 #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB 6 #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MSB 6 #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK 0x40 #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_GET(x) (((x) & PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK) >> PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB) #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB) & PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK) #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_RESET 0x0 #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB 5 #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MSB 5 #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK 0x20 #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_GET(x) (((x) & PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK) >> PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB) #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB) & PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK) #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_RESET 0x0 #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB 2 #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MSB 2 #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK 0x4 #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_GET(x) (((x) & PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK) >> PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB) #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB) & PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK) #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_RESET 0x0 #define PHY_BB_MODES_SELECT_CCK_MODE_LSB 0 #define PHY_BB_MODES_SELECT_CCK_MODE_MSB 0 #define PHY_BB_MODES_SELECT_CCK_MODE_MASK 0x1 #define PHY_BB_MODES_SELECT_CCK_MODE_GET(x) (((x) & PHY_BB_MODES_SELECT_CCK_MODE_MASK) >> PHY_BB_MODES_SELECT_CCK_MODE_LSB) #define PHY_BB_MODES_SELECT_CCK_MODE_SET(x) (((0 | (x)) << PHY_BB_MODES_SELECT_CCK_MODE_LSB) & PHY_BB_MODES_SELECT_CCK_MODE_MASK) #define PHY_BB_MODES_SELECT_CCK_MODE_RESET 0x0 #define PHY_BB_MODES_SELECT_ADDRESS (0x8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_MODES_SELECT_RSTMASK 0xfffde5 #define PHY_BB_MODES_SELECT_RESET 0xc7e000 // 0xc (PHY_BB_ACTIVE) #define PHY_BB_ACTIVE_CF_RESET_CORE_LSB 1 #define PHY_BB_ACTIVE_CF_RESET_CORE_MSB 1 #define PHY_BB_ACTIVE_CF_RESET_CORE_MASK 0x2 #define PHY_BB_ACTIVE_CF_RESET_CORE_GET(x) (((x) & PHY_BB_ACTIVE_CF_RESET_CORE_MASK) >> PHY_BB_ACTIVE_CF_RESET_CORE_LSB) #define PHY_BB_ACTIVE_CF_RESET_CORE_SET(x) (((0 | (x)) << PHY_BB_ACTIVE_CF_RESET_CORE_LSB) & PHY_BB_ACTIVE_CF_RESET_CORE_MASK) #define PHY_BB_ACTIVE_CF_RESET_CORE_RESET 0x0 #define PHY_BB_ACTIVE_CF_ACTIVE_LSB 0 #define PHY_BB_ACTIVE_CF_ACTIVE_MSB 0 #define PHY_BB_ACTIVE_CF_ACTIVE_MASK 0x1 #define PHY_BB_ACTIVE_CF_ACTIVE_GET(x) (((x) & PHY_BB_ACTIVE_CF_ACTIVE_MASK) >> PHY_BB_ACTIVE_CF_ACTIVE_LSB) #define PHY_BB_ACTIVE_CF_ACTIVE_SET(x) (((0 | (x)) << PHY_BB_ACTIVE_CF_ACTIVE_LSB) & PHY_BB_ACTIVE_CF_ACTIVE_MASK) #define PHY_BB_ACTIVE_CF_ACTIVE_RESET 0x0 #define PHY_BB_ACTIVE_ADDRESS (0xc + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_ACTIVE_RSTMASK 0x3 #define PHY_BB_ACTIVE_RESET 0x0 // 0x28 (PHY_BB_SPECTRAL_SCAN) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_RESTART_ENA_LSB 31 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_RESTART_ENA_MSB 31 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_RESTART_ENA_MASK 0x80000000 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_RESTART_ENA_GET(x) (((x) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_RESTART_ENA_MASK) >> PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_RESTART_ENA_LSB) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_RESTART_ENA_SET(x) (((0 | (x)) << PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_RESTART_ENA_LSB) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_RESTART_ENA_MASK) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_RESTART_ENA_RESET 0x1 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_GC_ENA_LSB 30 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_GC_ENA_MSB 30 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_GC_ENA_MASK 0x40000000 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_GC_ENA_GET(x) (((x) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_GC_ENA_MASK) >> PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_GC_ENA_LSB) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_GC_ENA_SET(x) (((0 | (x)) << PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_GC_ENA_LSB) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_GC_ENA_MASK) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_GC_ENA_RESET 0x1 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB 29 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MSB 29 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK 0x20000000 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_GET(x) (((x) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK) >> PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_SET(x) (((0 | (x)) << PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_RESET 0x1 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB 16 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MSB 27 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK 0xfff0000 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_GET(x) (((x) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK) >> PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_SET(x) (((0 | (x)) << PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_RESET 0x0 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB 8 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MSB 15 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK 0xff00 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_GET(x) (((x) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK) >> PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_SET(x) (((0 | (x)) << PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_RESET 0x23 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_SIZE_LSB 4 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_SIZE_MSB 7 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_SIZE_MASK 0xf0 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_SIZE_GET(x) (((x) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_SIZE_MASK) >> PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_SIZE_LSB) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_SIZE_SET(x) (((0 | (x)) << PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_SIZE_LSB) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_SIZE_MASK) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_SIZE_RESET 0x9 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB 1 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MSB 1 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK 0x2 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_GET(x) (((x) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK) >> PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_SET(x) (((0 | (x)) << PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_RESET 0x0 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB 0 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MSB 0 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK 0x1 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_GET(x) (((x) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK) >> PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_SET(x) (((0 | (x)) << PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB) & PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK) #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_RESET 0x0 #define PHY_BB_SPECTRAL_SCAN_ADDRESS (0x28 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_SPECTRAL_SCAN_RSTMASK 0xeffffff3 #define PHY_BB_SPECTRAL_SCAN_RESET 0xe0002390 // 0x30 (PHY_BB_SEARCH_START_DELAY) #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_MASK_SIFS_LSB 28 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_MASK_SIFS_MSB 31 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_MASK_SIFS_MASK 0xf0000000 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_MASK_SIFS_GET(x) (((x) & PHY_BB_SEARCH_START_DELAY_SEARCH_START_MASK_SIFS_MASK) >> PHY_BB_SEARCH_START_DELAY_SEARCH_START_MASK_SIFS_LSB) #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_MASK_SIFS_SET(x) (((0 | (x)) << PHY_BB_SEARCH_START_DELAY_SEARCH_START_MASK_SIFS_LSB) & PHY_BB_SEARCH_START_DELAY_SEARCH_START_MASK_SIFS_MASK) #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_MASK_SIFS_RESET 0x1 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SIFS_LSB 16 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SIFS_MSB 27 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SIFS_MASK 0xfff0000 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SIFS_GET(x) (((x) & PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SIFS_MASK) >> PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SIFS_LSB) #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SIFS_SET(x) (((0 | (x)) << PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SIFS_LSB) & PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SIFS_MASK) #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SIFS_RESET 0xf0 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_RIFS_LSB 0 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_RIFS_MSB 11 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_RIFS_MASK 0xfff #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_RIFS_GET(x) (((x) & PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_RIFS_MASK) >> PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_RIFS_LSB) #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_RIFS_SET(x) (((0 | (x)) << PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_RIFS_LSB) & PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_RIFS_MASK) #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_RIFS_RESET 0x14 #define PHY_BB_SEARCH_START_DELAY_ADDRESS (0x30 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_SEARCH_START_DELAY_RSTMASK 0xffff0fff #define PHY_BB_SEARCH_START_DELAY_RESET 0x10f00014 // 0x34 (PHY_BB_MAX_RX_LENGTH) #define PHY_BB_MAX_RX_LENGTH_MAX_HT_DURATION_LSB 30 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_DURATION_MSB 31 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_DURATION_MASK 0xc0000000 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_DURATION_GET(x) (((x) & PHY_BB_MAX_RX_LENGTH_MAX_HT_DURATION_MASK) >> PHY_BB_MAX_RX_LENGTH_MAX_HT_DURATION_LSB) #define PHY_BB_MAX_RX_LENGTH_MAX_HT_DURATION_SET(x) (((0 | (x)) << PHY_BB_MAX_RX_LENGTH_MAX_HT_DURATION_LSB) & PHY_BB_MAX_RX_LENGTH_MAX_HT_DURATION_MASK) #define PHY_BB_MAX_RX_LENGTH_MAX_HT_DURATION_RESET 0x3 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB 12 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MSB 29 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK 0x3ffff000 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_GET(x) (((x) & PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK) >> PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB) #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_SET(x) (((0 | (x)) << PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB) & PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK) #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_RESET 0x0 #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB 0 #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MSB 11 #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK 0xfff #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_GET(x) (((x) & PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK) >> PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB) #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_SET(x) (((0 | (x)) << PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB) & PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK) #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_RESET 0xfff #define PHY_BB_MAX_RX_LENGTH_ADDRESS (0x34 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_MAX_RX_LENGTH_RSTMASK 0xffffffff #define PHY_BB_MAX_RX_LENGTH_RESET 0xc0000fff // 0x38 (PHY_BB_FRAME_CONTROL) #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB 31 #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MSB 31 #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK 0x80000000 #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB 30 #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MSB 30 #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK 0x40000000 #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB 29 #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MSB 29 #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK 0x20000000 #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_RESET 0x0 #define PHY_BB_FRAME_CONTROL_NO_6MBPS_SERVICE_ERR_LSB 28 #define PHY_BB_FRAME_CONTROL_NO_6MBPS_SERVICE_ERR_MSB 28 #define PHY_BB_FRAME_CONTROL_NO_6MBPS_SERVICE_ERR_MASK 0x10000000 #define PHY_BB_FRAME_CONTROL_NO_6MBPS_SERVICE_ERR_GET(x) (((x) & PHY_BB_FRAME_CONTROL_NO_6MBPS_SERVICE_ERR_MASK) >> PHY_BB_FRAME_CONTROL_NO_6MBPS_SERVICE_ERR_LSB) #define PHY_BB_FRAME_CONTROL_NO_6MBPS_SERVICE_ERR_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_NO_6MBPS_SERVICE_ERR_LSB) & PHY_BB_FRAME_CONTROL_NO_6MBPS_SERVICE_ERR_MASK) #define PHY_BB_FRAME_CONTROL_NO_6MBPS_SERVICE_ERR_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB 27 #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MSB 27 #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK 0x8000000 #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB 26 #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MSB 26 #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK 0x4000000 #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB 25 #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MSB 25 #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK 0x2000000 #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB 24 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MSB 24 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK 0x1000000 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB 23 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MSB 23 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK 0x800000 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB 22 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MSB 22 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK 0x400000 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB 21 #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MSB 21 #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK 0x200000 #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB 20 #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MSB 20 #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK 0x100000 #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_STATIC20_MODE_HT40_PACKET_LSB 19 #define PHY_BB_FRAME_CONTROL_EN_ERR_STATIC20_MODE_HT40_PACKET_MSB 19 #define PHY_BB_FRAME_CONTROL_EN_ERR_STATIC20_MODE_HT40_PACKET_MASK 0x80000 #define PHY_BB_FRAME_CONTROL_EN_ERR_STATIC20_MODE_HT40_PACKET_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_STATIC20_MODE_HT40_PACKET_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_STATIC20_MODE_HT40_PACKET_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_STATIC20_MODE_HT40_PACKET_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_STATIC20_MODE_HT40_PACKET_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_STATIC20_MODE_HT40_PACKET_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_STATIC20_MODE_HT40_PACKET_RESET 0x0 #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB 18 #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MSB 18 #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK 0x40000 #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_GET(x) (((x) & PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK) >> PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB) #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB) & PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK) #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_RESET 0x0 #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB 17 #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MSB 17 #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK 0x20000 #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_GET(x) (((x) & PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK) >> PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB) #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB) & PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK) #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_RESET 0x0 #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB 16 #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MSB 16 #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK 0x10000 #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_GET(x) (((x) & PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK) >> PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB) #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB) & PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK) #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_RESET 0x0 #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB 8 #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MSB 15 #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK 0xff00 #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_GET(x) (((x) & PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK) >> PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB) #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB) & PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK) #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_RESET 0x10 #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB 6 #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MSB 7 #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK 0xc0 #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_GET(x) (((x) & PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK) >> PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB) #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB) & PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK) #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_RESET 0x0 #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB 3 #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MSB 5 #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK 0x38 #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_GET(x) (((x) & PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK) >> PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB) #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB) & PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK) #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_RESET 0x3 #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB 0 #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MSB 1 #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK 0x3 #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_GET(x) (((x) & PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK) >> PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB) #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_SET(x) (((0 | (x)) << PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB) & PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK) #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_RESET 0x0 #define PHY_BB_FRAME_CONTROL_ADDRESS (0x38 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_FRAME_CONTROL_RSTMASK 0xfffffffb #define PHY_BB_FRAME_CONTROL_RESET 0x1018 // 0x3c (PHY_BB_RFBUS_REQUEST) #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB 0 #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MSB 0 #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK 0x1 #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_GET(x) (((x) & PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK) >> PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB) #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_SET(x) (((0 | (x)) << PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB) & PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK) #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_RESET 0x0 #define PHY_BB_RFBUS_REQUEST_ADDRESS (0x3c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RFBUS_REQUEST_RSTMASK 0x1 #define PHY_BB_RFBUS_REQUEST_RESET 0x0 // 0x40 (PHY_BB_RFBUS_GRANT) #define PHY_BB_RFBUS_GRANT_BT_ANT_LSB 1 #define PHY_BB_RFBUS_GRANT_BT_ANT_MSB 1 #define PHY_BB_RFBUS_GRANT_BT_ANT_MASK 0x2 #define PHY_BB_RFBUS_GRANT_BT_ANT_GET(x) (((x) & PHY_BB_RFBUS_GRANT_BT_ANT_MASK) >> PHY_BB_RFBUS_GRANT_BT_ANT_LSB) #define PHY_BB_RFBUS_GRANT_BT_ANT_SET(x) (((0 | (x)) << PHY_BB_RFBUS_GRANT_BT_ANT_LSB) & PHY_BB_RFBUS_GRANT_BT_ANT_MASK) #define PHY_BB_RFBUS_GRANT_BT_ANT_RESET 0x0 #define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB 0 #define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MSB 0 #define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK 0x1 #define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_GET(x) (((x) & PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK) >> PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB) #define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_SET(x) (((0 | (x)) << PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB) & PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK) #define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_RESET 0x0 #define PHY_BB_RFBUS_GRANT_ADDRESS (0x40 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RFBUS_GRANT_RSTMASK 0x3 #define PHY_BB_RFBUS_GRANT_RESET 0x0 // 0x44 (PHY_BB_RIFS) #define PHY_BB_RIFS_DISABLE_RX_MASK_MAC_WAIT_LSB 27 #define PHY_BB_RIFS_DISABLE_RX_MASK_MAC_WAIT_MSB 27 #define PHY_BB_RIFS_DISABLE_RX_MASK_MAC_WAIT_MASK 0x8000000 #define PHY_BB_RIFS_DISABLE_RX_MASK_MAC_WAIT_GET(x) (((x) & PHY_BB_RIFS_DISABLE_RX_MASK_MAC_WAIT_MASK) >> PHY_BB_RIFS_DISABLE_RX_MASK_MAC_WAIT_LSB) #define PHY_BB_RIFS_DISABLE_RX_MASK_MAC_WAIT_SET(x) (((0 | (x)) << PHY_BB_RIFS_DISABLE_RX_MASK_MAC_WAIT_LSB) & PHY_BB_RIFS_DISABLE_RX_MASK_MAC_WAIT_MASK) #define PHY_BB_RIFS_DISABLE_RX_MASK_MAC_WAIT_RESET 0x0 #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB 26 #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MSB 26 #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK 0x4000000 #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_GET(x) (((x) & PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK) >> PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB) #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_SET(x) (((0 | (x)) << PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB) & PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK) #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_RESET 0x0 #define PHY_BB_RIFS_RIFS_ECO_DISABLE_LSB 0 #define PHY_BB_RIFS_RIFS_ECO_DISABLE_MSB 23 #define PHY_BB_RIFS_RIFS_ECO_DISABLE_MASK 0xffffff #define PHY_BB_RIFS_RIFS_ECO_DISABLE_GET(x) (((x) & PHY_BB_RIFS_RIFS_ECO_DISABLE_MASK) >> PHY_BB_RIFS_RIFS_ECO_DISABLE_LSB) #define PHY_BB_RIFS_RIFS_ECO_DISABLE_SET(x) (((0 | (x)) << PHY_BB_RIFS_RIFS_ECO_DISABLE_LSB) & PHY_BB_RIFS_RIFS_ECO_DISABLE_MASK) #define PHY_BB_RIFS_RIFS_ECO_DISABLE_RESET 0x0 #define PHY_BB_RIFS_ADDRESS (0x44 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RIFS_RSTMASK 0xcffffff #define PHY_BB_RIFS_RESET 0x0 // 0x48 (PHY_BB_PMI_DEBUG_STATUS) #define PHY_BB_PMI_DEBUG_STATUS_PMI_DEBUG_STATUS_LSB 0 #define PHY_BB_PMI_DEBUG_STATUS_PMI_DEBUG_STATUS_MSB 31 #define PHY_BB_PMI_DEBUG_STATUS_PMI_DEBUG_STATUS_MASK 0xffffffff #define PHY_BB_PMI_DEBUG_STATUS_PMI_DEBUG_STATUS_GET(x) (((x) & PHY_BB_PMI_DEBUG_STATUS_PMI_DEBUG_STATUS_MASK) >> PHY_BB_PMI_DEBUG_STATUS_PMI_DEBUG_STATUS_LSB) #define PHY_BB_PMI_DEBUG_STATUS_PMI_DEBUG_STATUS_SET(x) (((0 | (x)) << PHY_BB_PMI_DEBUG_STATUS_PMI_DEBUG_STATUS_LSB) & PHY_BB_PMI_DEBUG_STATUS_PMI_DEBUG_STATUS_MASK) #define PHY_BB_PMI_DEBUG_STATUS_PMI_DEBUG_STATUS_RESET 0xff #define PHY_BB_PMI_DEBUG_STATUS_ADDRESS (0x48 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PMI_DEBUG_STATUS_RSTMASK 0xffffffff #define PHY_BB_PMI_DEBUG_STATUS_RESET 0xff // 0x50 (PHY_BB_RX_CLEAR_DELAY) #define PHY_BB_RX_CLEAR_DELAY_NDP_TIMEOUT_FDOMAIN_DELAY_LSB 10 #define PHY_BB_RX_CLEAR_DELAY_NDP_TIMEOUT_FDOMAIN_DELAY_MSB 12 #define PHY_BB_RX_CLEAR_DELAY_NDP_TIMEOUT_FDOMAIN_DELAY_MASK 0x1c00 #define PHY_BB_RX_CLEAR_DELAY_NDP_TIMEOUT_FDOMAIN_DELAY_GET(x) (((x) & PHY_BB_RX_CLEAR_DELAY_NDP_TIMEOUT_FDOMAIN_DELAY_MASK) >> PHY_BB_RX_CLEAR_DELAY_NDP_TIMEOUT_FDOMAIN_DELAY_LSB) #define PHY_BB_RX_CLEAR_DELAY_NDP_TIMEOUT_FDOMAIN_DELAY_SET(x) (((0 | (x)) << PHY_BB_RX_CLEAR_DELAY_NDP_TIMEOUT_FDOMAIN_DELAY_LSB) & PHY_BB_RX_CLEAR_DELAY_NDP_TIMEOUT_FDOMAIN_DELAY_MASK) #define PHY_BB_RX_CLEAR_DELAY_NDP_TIMEOUT_FDOMAIN_DELAY_RESET 0x4 #define PHY_BB_RX_CLEAR_DELAY_OFDM_RX_CLEAR_DELAY_LSB 0 #define PHY_BB_RX_CLEAR_DELAY_OFDM_RX_CLEAR_DELAY_MSB 9 #define PHY_BB_RX_CLEAR_DELAY_OFDM_RX_CLEAR_DELAY_MASK 0x3ff #define PHY_BB_RX_CLEAR_DELAY_OFDM_RX_CLEAR_DELAY_GET(x) (((x) & PHY_BB_RX_CLEAR_DELAY_OFDM_RX_CLEAR_DELAY_MASK) >> PHY_BB_RX_CLEAR_DELAY_OFDM_RX_CLEAR_DELAY_LSB) #define PHY_BB_RX_CLEAR_DELAY_OFDM_RX_CLEAR_DELAY_SET(x) (((0 | (x)) << PHY_BB_RX_CLEAR_DELAY_OFDM_RX_CLEAR_DELAY_LSB) & PHY_BB_RX_CLEAR_DELAY_OFDM_RX_CLEAR_DELAY_MASK) #define PHY_BB_RX_CLEAR_DELAY_OFDM_RX_CLEAR_DELAY_RESET 0x0 #define PHY_BB_RX_CLEAR_DELAY_ADDRESS (0x50 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RX_CLEAR_DELAY_RSTMASK 0x1fff #define PHY_BB_RX_CLEAR_DELAY_RESET 0x1000 // 0x54 (PHY_BB_ANALOG_POWER_ON_TIME) #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB 0 #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MSB 13 #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK 0x3fff #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_GET(x) (((x) & PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK) >> PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB) #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_SET(x) (((0 | (x)) << PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB) & PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK) #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_RESET 0x0 #define PHY_BB_ANALOG_POWER_ON_TIME_ADDRESS (0x54 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_ANALOG_POWER_ON_TIME_RSTMASK 0x3fff #define PHY_BB_ANALOG_POWER_ON_TIME_RESET 0x0 // 0x58 (PHY_BB_TX_TIMING_1) #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB 24 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MSB 31 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK 0xff000000 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_GET(x) (((x) & PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK) >> PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB) #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB) & PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK) #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_RESET 0x0 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB 16 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MSB 23 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK 0xff0000 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_GET(x) (((x) & PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK) >> PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB) #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB) & PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK) #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_RESET 0x0 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB 8 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MSB 15 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK 0xff00 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_GET(x) (((x) & PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK) >> PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB) #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB) & PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK) #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_RESET 0x0 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB 0 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MSB 7 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK 0xff #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_GET(x) (((x) & PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK) >> PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB) #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB) & PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK) #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_RESET 0x0 #define PHY_BB_TX_TIMING_1_ADDRESS (0x58 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TX_TIMING_1_RSTMASK 0xffffffff #define PHY_BB_TX_TIMING_1_RESET 0x0 // 0x5c (PHY_BB_TX_TIMING_2) #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB 24 #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MSB 31 #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK 0xff000000 #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_GET(x) (((x) & PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK) >> PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB) #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB) & PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK) #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_RESET 0x0 #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB 16 #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MSB 23 #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK 0xff0000 #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_GET(x) (((x) & PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK) >> PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB) #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB) & PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK) #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_RESET 0x0 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB 8 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MSB 15 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK 0xff00 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_GET(x) (((x) & PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK) >> PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB) #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB) & PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK) #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_RESET 0x0 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB 0 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MSB 7 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK 0xff #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_GET(x) (((x) & PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK) >> PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB) #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB) & PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK) #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_RESET 0x0 #define PHY_BB_TX_TIMING_2_ADDRESS (0x5c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TX_TIMING_2_RSTMASK 0xffffffff #define PHY_BB_TX_TIMING_2_RESET 0x0 // 0x60 (PHY_BB_TX_TIMING_3) #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB 24 #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MSB 31 #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK 0xff000000 #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_GET(x) (((x) & PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK) >> PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB) #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB) & PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK) #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_RESET 0x0 #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB 16 #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MSB 23 #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK 0xff0000 #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_GET(x) (((x) & PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK) >> PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB) #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB) & PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK) #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_RESET 0x0 #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB 8 #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MSB 15 #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK 0xff00 #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_GET(x) (((x) & PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK) >> PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB) #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB) & PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK) #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_RESET 0x0 #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB 0 #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MSB 7 #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK 0xff #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_GET(x) (((x) & PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK) >> PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB) #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_SET(x) (((0 | (x)) << PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB) & PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK) #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_RESET 0x0 #define PHY_BB_TX_TIMING_3_ADDRESS (0x60 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TX_TIMING_3_RSTMASK 0xffffffff #define PHY_BB_TX_TIMING_3_RESET 0x0 // 0x64 (PHY_BB_XPA_TIMING_CONTROL) #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB 24 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MSB 31 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK 0xff000000 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_GET(x) (((x) & PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK) >> PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB) #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_SET(x) (((0 | (x)) << PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB) & PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK) #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_RESET 0x0 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB 16 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MSB 23 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK 0xff0000 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_GET(x) (((x) & PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK) >> PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB) #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_SET(x) (((0 | (x)) << PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB) & PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK) #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_RESET 0x0 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB 8 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MSB 15 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK 0xff00 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_GET(x) (((x) & PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK) >> PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB) #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_SET(x) (((0 | (x)) << PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB) & PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK) #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_RESET 0x0 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB 0 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MSB 7 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK 0xff #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_GET(x) (((x) & PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK) >> PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB) #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_SET(x) (((0 | (x)) << PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB) & PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK) #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_RESET 0x0 #define PHY_BB_XPA_TIMING_CONTROL_ADDRESS (0x64 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_XPA_TIMING_CONTROL_RSTMASK 0xffffffff #define PHY_BB_XPA_TIMING_CONTROL_RESET 0x0 // 0x68 (PHY_BB_WARM_TX) #define PHY_BB_WARM_TX_NUM_EXTRA_LSTF_SAMPLES_LSB 1 #define PHY_BB_WARM_TX_NUM_EXTRA_LSTF_SAMPLES_MSB 8 #define PHY_BB_WARM_TX_NUM_EXTRA_LSTF_SAMPLES_MASK 0x1fe #define PHY_BB_WARM_TX_NUM_EXTRA_LSTF_SAMPLES_GET(x) (((x) & PHY_BB_WARM_TX_NUM_EXTRA_LSTF_SAMPLES_MASK) >> PHY_BB_WARM_TX_NUM_EXTRA_LSTF_SAMPLES_LSB) #define PHY_BB_WARM_TX_NUM_EXTRA_LSTF_SAMPLES_SET(x) (((0 | (x)) << PHY_BB_WARM_TX_NUM_EXTRA_LSTF_SAMPLES_LSB) & PHY_BB_WARM_TX_NUM_EXTRA_LSTF_SAMPLES_MASK) #define PHY_BB_WARM_TX_NUM_EXTRA_LSTF_SAMPLES_RESET 0x80 #define PHY_BB_WARM_TX_ENABLE_WARM_TX_LSB 0 #define PHY_BB_WARM_TX_ENABLE_WARM_TX_MSB 0 #define PHY_BB_WARM_TX_ENABLE_WARM_TX_MASK 0x1 #define PHY_BB_WARM_TX_ENABLE_WARM_TX_GET(x) (((x) & PHY_BB_WARM_TX_ENABLE_WARM_TX_MASK) >> PHY_BB_WARM_TX_ENABLE_WARM_TX_LSB) #define PHY_BB_WARM_TX_ENABLE_WARM_TX_SET(x) (((0 | (x)) << PHY_BB_WARM_TX_ENABLE_WARM_TX_LSB) & PHY_BB_WARM_TX_ENABLE_WARM_TX_MASK) #define PHY_BB_WARM_TX_ENABLE_WARM_TX_RESET 0x0 #define PHY_BB_WARM_TX_ADDRESS (0x68 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_WARM_TX_RSTMASK 0x1ff #define PHY_BB_WARM_TX_RESET 0x100 // 0x6c (PHY_BB_EN_POWER_OPTIM) #define PHY_BB_EN_POWER_OPTIM_RSSI_NAP_THR_LSB 24 #define PHY_BB_EN_POWER_OPTIM_RSSI_NAP_THR_MSB 31 #define PHY_BB_EN_POWER_OPTIM_RSSI_NAP_THR_MASK 0xff000000 #define PHY_BB_EN_POWER_OPTIM_RSSI_NAP_THR_GET(x) (((x) & PHY_BB_EN_POWER_OPTIM_RSSI_NAP_THR_MASK) >> PHY_BB_EN_POWER_OPTIM_RSSI_NAP_THR_LSB) #define PHY_BB_EN_POWER_OPTIM_RSSI_NAP_THR_SET(x) (((0 | (x)) << PHY_BB_EN_POWER_OPTIM_RSSI_NAP_THR_LSB) & PHY_BB_EN_POWER_OPTIM_RSSI_NAP_THR_MASK) #define PHY_BB_EN_POWER_OPTIM_RSSI_NAP_THR_RESET 0x0 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_PAPRD_LSB 3 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_PAPRD_MSB 3 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_PAPRD_MASK 0x8 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_PAPRD_GET(x) (((x) & PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_PAPRD_MASK) >> PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_PAPRD_LSB) #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_PAPRD_SET(x) (((0 | (x)) << PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_PAPRD_LSB) & PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_PAPRD_MASK) #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_PAPRD_RESET 0x0 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_SM_LSB 2 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_SM_MSB 2 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_SM_MASK 0x4 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_SM_GET(x) (((x) & PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_SM_MASK) >> PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_SM_LSB) #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_SM_SET(x) (((0 | (x)) << PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_SM_LSB) & PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_SM_MASK) #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_SM_RESET 0x0 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_MRC_LSB 1 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_MRC_MSB 1 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_MRC_MASK 0x2 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_MRC_GET(x) (((x) & PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_MRC_MASK) >> PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_MRC_LSB) #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_MRC_SET(x) (((0 | (x)) << PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_MRC_LSB) & PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_MRC_MASK) #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_MRC_RESET 0x0 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_CHN_LSB 0 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_CHN_MSB 0 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_CHN_MASK 0x1 #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_CHN_GET(x) (((x) & PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_CHN_MASK) >> PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_CHN_LSB) #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_CHN_SET(x) (((0 | (x)) << PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_CHN_LSB) & PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_CHN_MASK) #define PHY_BB_EN_POWER_OPTIM_ENABLE_POWER_OPTIM_CHN_RESET 0x0 #define PHY_BB_EN_POWER_OPTIM_ADDRESS (0x6c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_EN_POWER_OPTIM_RSTMASK 0xff00000f #define PHY_BB_EN_POWER_OPTIM_RESET 0x0 // 0x80 (PHY_BB_MISC_PA_CONTROL) #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB 3 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MSB 3 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK 0x8 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_GET(x) (((x) & PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK) >> PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB) #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_SET(x) (((0 | (x)) << PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB) & PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK) #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_RESET 0x0 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB 2 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MSB 2 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK 0x4 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_GET(x) (((x) & PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK) >> PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB) #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_SET(x) (((0 | (x)) << PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB) & PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK) #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_RESET 0x0 #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB 1 #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MSB 1 #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK 0x2 #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_GET(x) (((x) & PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK) >> PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB) #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_SET(x) (((0 | (x)) << PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB) & PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK) #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_RESET 0x1 #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB 0 #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MSB 0 #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK 0x1 #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_GET(x) (((x) & PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK) >> PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB) #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_SET(x) (((0 | (x)) << PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB) & PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK) #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_RESET 0x1 #define PHY_BB_MISC_PA_CONTROL_ADDRESS (0x80 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_MISC_PA_CONTROL_RSTMASK 0xf #define PHY_BB_MISC_PA_CONTROL_RESET 0x3 // 0x84 (PHY_BB_SWITCH_TABLE_CHN_B0) #define PHY_BB_SWITCH_TABLE_CHN_B0_ENABLE_BT_OVERRIDE_LSB 31 #define PHY_BB_SWITCH_TABLE_CHN_B0_ENABLE_BT_OVERRIDE_MSB 31 #define PHY_BB_SWITCH_TABLE_CHN_B0_ENABLE_BT_OVERRIDE_MASK 0x80000000 #define PHY_BB_SWITCH_TABLE_CHN_B0_ENABLE_BT_OVERRIDE_GET(x) (((x) & PHY_BB_SWITCH_TABLE_CHN_B0_ENABLE_BT_OVERRIDE_MASK) >> PHY_BB_SWITCH_TABLE_CHN_B0_ENABLE_BT_OVERRIDE_LSB) #define PHY_BB_SWITCH_TABLE_CHN_B0_ENABLE_BT_OVERRIDE_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_CHN_B0_ENABLE_BT_OVERRIDE_LSB) & PHY_BB_SWITCH_TABLE_CHN_B0_ENABLE_BT_OVERRIDE_MASK) #define PHY_BB_SWITCH_TABLE_CHN_B0_ENABLE_BT_OVERRIDE_RESET 0x0 #define PHY_BB_SWITCH_TABLE_CHN_B0_BT_IN_TX_XLNA_OVERRIDE_LSB 30 #define PHY_BB_SWITCH_TABLE_CHN_B0_BT_IN_TX_XLNA_OVERRIDE_MSB 30 #define PHY_BB_SWITCH_TABLE_CHN_B0_BT_IN_TX_XLNA_OVERRIDE_MASK 0x40000000 #define PHY_BB_SWITCH_TABLE_CHN_B0_BT_IN_TX_XLNA_OVERRIDE_GET(x) (((x) & PHY_BB_SWITCH_TABLE_CHN_B0_BT_IN_TX_XLNA_OVERRIDE_MASK) >> PHY_BB_SWITCH_TABLE_CHN_B0_BT_IN_TX_XLNA_OVERRIDE_LSB) #define PHY_BB_SWITCH_TABLE_CHN_B0_BT_IN_TX_XLNA_OVERRIDE_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_CHN_B0_BT_IN_TX_XLNA_OVERRIDE_LSB) & PHY_BB_SWITCH_TABLE_CHN_B0_BT_IN_TX_XLNA_OVERRIDE_MASK) #define PHY_BB_SWITCH_TABLE_CHN_B0_BT_IN_TX_XLNA_OVERRIDE_RESET 0x1 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB 10 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MSB 11 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK 0xc00 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_GET(x) (((x) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK) >> PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_RESET 0x0 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB 8 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MSB 9 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK 0x300 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_GET(x) (((x) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK) >> PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_RESET 0x0 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB 6 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MSB 7 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK 0xc0 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_GET(x) (((x) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK) >> PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_RESET 0x0 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB 4 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MSB 5 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK 0x30 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_GET(x) (((x) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK) >> PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_RESET 0x0 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB 2 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MSB 3 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK 0xc #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_GET(x) (((x) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK) >> PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_RESET 0x0 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB 0 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MSB 1 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK 0x3 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_GET(x) (((x) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK) >> PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB) & PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK) #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_RESET 0x0 #define PHY_BB_SWITCH_TABLE_CHN_B0_ADDRESS (0x84 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_SWITCH_TABLE_CHN_B0_RSTMASK 0xc0000fff #define PHY_BB_SWITCH_TABLE_CHN_B0_RESET 0x40000000 // 0x88 (PHY_BB_SWITCH_TABLE_COM1) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_TX_1CHN_LSB 28 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_TX_1CHN_MSB 31 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_TX_1CHN_MASK 0xf0000000 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_TX_1CHN_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_TX_1CHN_MASK) >> PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_TX_1CHN_LSB) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_TX_1CHN_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_TX_1CHN_LSB) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_TX_1CHN_MASK) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_TX_1CHN_RESET 0x0 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_ALT_LSB 22 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_ALT_MSB 27 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_ALT_MASK 0xfc00000 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_ALT_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_ALT_MASK) >> PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_ALT_LSB) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_ALT_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_ALT_LSB) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_ALT_MASK) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_ALT_RESET 0xa #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB 16 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MSB 21 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK 0x3f0000 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK) >> PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_RESET 0x0 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB 12 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MSB 15 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK 0xf000 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK) >> PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_RESET 0x0 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB 6 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MSB 11 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK 0xfc0 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK) >> PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_RESET 0x0 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB 0 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MSB 5 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK 0x3f #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK) >> PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB) & PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK) #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_RESET 0x0 #define PHY_BB_SWITCH_TABLE_COM1_ADDRESS (0x88 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_SWITCH_TABLE_COM1_RSTMASK 0xffffffff #define PHY_BB_SWITCH_TABLE_COM1_RESET 0x2800000 // 0x8c (PHY_BB_SWITCH_TABLE_COM2) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA12_LSB 18 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA12_MSB 21 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA12_MASK 0x3c0000 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA12_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA12_MASK) >> PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA12_LSB) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA12_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA12_LSB) & PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA12_MASK) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA12_RESET 0x0 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L2_LSB 14 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L2_MSB 17 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L2_MASK 0x3c000 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L2_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L2_MASK) >> PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L2_LSB) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L2_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L2_LSB) & PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L2_MASK) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L2_RESET 0x0 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L2_LSB 10 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L2_MSB 13 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L2_MASK 0x3c00 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L2_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L2_MASK) >> PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L2_LSB) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L2_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L2_LSB) & PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L2_MASK) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L2_RESET 0x0 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L1_LSB 6 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L1_MSB 9 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L1_MASK 0x3c0 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L1_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L1_MASK) >> PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L1_LSB) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L1_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L1_LSB) & PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L1_MASK) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2L1_RESET 0x0 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L1_LSB 0 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L1_MSB 5 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L1_MASK 0x3f #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L1_GET(x) (((x) & PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L1_MASK) >> PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L1_LSB) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L1_SET(x) (((0 | (x)) << PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L1_LSB) & PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L1_MASK) #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1L1_RESET 0x0 #define PHY_BB_SWITCH_TABLE_COM2_ADDRESS (0x8c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_SWITCH_TABLE_COM2_RSTMASK 0x3fffff #define PHY_BB_SWITCH_TABLE_COM2_RESET 0x0 // 0xa0 (PHY_BB_MULTICHAIN_ENABLE) #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB 0 #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MSB 3 #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK 0xf #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_GET(x) (((x) & PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK) >> PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB) #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_SET(x) (((0 | (x)) << PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB) & PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK) #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_RESET 0x1 #define PHY_BB_MULTICHAIN_ENABLE_ADDRESS (0xa0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_MULTICHAIN_ENABLE_RSTMASK 0xf #define PHY_BB_MULTICHAIN_ENABLE_RESET 0x1 // 0xc0 (PHY_BB_CAL_CHAIN_MASK) #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB 0 #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MSB 3 #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK 0xf #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_GET(x) (((x) & PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK) >> PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB) #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_SET(x) (((0 | (x)) << PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB) & PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK) #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_RESET 0xf #define PHY_BB_CAL_CHAIN_MASK_ADDRESS (0xc0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CAL_CHAIN_MASK_RSTMASK 0xf #define PHY_BB_CAL_CHAIN_MASK_RESET 0xf // 0xc4 (PHY_BB_AGC_CONTROL) #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB 20 #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MSB 20 #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK 0x100000 #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_GET(x) (((x) & PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK) >> PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB) #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB) & PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK) #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_RESET 0x0 #define PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB 19 #define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MSB 19 #define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK 0x80000 #define PHY_BB_AGC_CONTROL_CLC_SUCCESS_GET(x) (((x) & PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK) >> PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB) #define PHY_BB_AGC_CONTROL_CLC_SUCCESS_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB) & PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK) #define PHY_BB_AGC_CONTROL_CLC_SUCCESS_RESET 0x0 #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB 18 #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MSB 18 #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK 0x40000 #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_GET(x) (((x) & PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK) >> PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB) #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB) & PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK) #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_RESET 0x1 #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB 17 #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MSB 17 #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK 0x20000 #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_GET(x) (((x) & PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK) >> PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB) #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB) & PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK) #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_RESET 0x0 #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB 16 #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MSB 16 #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK 0x10000 #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_GET(x) (((x) & PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK) >> PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB) #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB) & PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK) #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_RESET 0x0 #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB 15 #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MSB 15 #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK 0x8000 #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_GET(x) (((x) & PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK) >> PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB) #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB) & PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK) #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_RESET 0x1 #define PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB 11 #define PHY_BB_AGC_CONTROL_CAL_ENABLE_MSB 11 #define PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK 0x800 #define PHY_BB_AGC_CONTROL_CAL_ENABLE_GET(x) (((x) & PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK) >> PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB) #define PHY_BB_AGC_CONTROL_CAL_ENABLE_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB) & PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK) #define PHY_BB_AGC_CONTROL_CAL_ENABLE_RESET 0x0 #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB 10 #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MSB 10 #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK 0x400 #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_GET(x) (((x) & PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK) >> PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB) #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB) & PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK) #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_RESET 0x0 #define PHY_BB_AGC_CONTROL_YCOK_MAX_LSB 6 #define PHY_BB_AGC_CONTROL_YCOK_MAX_MSB 9 #define PHY_BB_AGC_CONTROL_YCOK_MAX_MASK 0x3c0 #define PHY_BB_AGC_CONTROL_YCOK_MAX_GET(x) (((x) & PHY_BB_AGC_CONTROL_YCOK_MAX_MASK) >> PHY_BB_AGC_CONTROL_YCOK_MAX_LSB) #define PHY_BB_AGC_CONTROL_YCOK_MAX_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_YCOK_MAX_LSB) & PHY_BB_AGC_CONTROL_YCOK_MAX_MASK) #define PHY_BB_AGC_CONTROL_YCOK_MAX_RESET 0x0 #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB 3 #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MSB 5 #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK 0x38 #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_GET(x) (((x) & PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK) >> PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB) #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB) & PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK) #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_RESET 0x0 #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB 1 #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MSB 1 #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK 0x2 #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_GET(x) (((x) & PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK) >> PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB) #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB) & PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK) #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_RESET 0x0 #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB 0 #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MSB 0 #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK 0x1 #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_GET(x) (((x) & PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK) >> PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB) #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_SET(x) (((0 | (x)) << PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB) & PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK) #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_RESET 0x0 #define PHY_BB_AGC_CONTROL_ADDRESS (0xc4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_AGC_CONTROL_RSTMASK 0x1f8ffb #define PHY_BB_AGC_CONTROL_RESET 0x48000 // 0xc8 (PHY_BB_IQ_ADC_CAL_MODE) #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB 2 #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MSB 2 #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK 0x4 #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_GET(x) (((x) & PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK) >> PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB) #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB) & PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK) #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_RESET 0x0 #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB 0 #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MSB 1 #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK 0x3 #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_GET(x) (((x) & PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK) >> PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB) #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_SET(x) (((0 | (x)) << PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB) & PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK) #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_RESET 0x0 #define PHY_BB_IQ_ADC_CAL_MODE_ADDRESS (0xc8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_IQ_ADC_CAL_MODE_RSTMASK 0x7 #define PHY_BB_IQ_ADC_CAL_MODE_RESET 0x0 // 0xcc (PHY_BB_FCAL_1) #define PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB 25 #define PHY_BB_FCAL_1_FLC_SB_ATTEN_MSB 29 #define PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK 0x3e000000 #define PHY_BB_FCAL_1_FLC_SB_ATTEN_GET(x) (((x) & PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK) >> PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB) #define PHY_BB_FCAL_1_FLC_SB_ATTEN_SET(x) (((0 | (x)) << PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB) & PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK) #define PHY_BB_FCAL_1_FLC_SB_ATTEN_RESET 0xc #define PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB 20 #define PHY_BB_FCAL_1_FLC_PB_ATTEN_MSB 24 #define PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK 0x1f00000 #define PHY_BB_FCAL_1_FLC_PB_ATTEN_GET(x) (((x) & PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK) >> PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB) #define PHY_BB_FCAL_1_FLC_PB_ATTEN_SET(x) (((0 | (x)) << PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB) & PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK) #define PHY_BB_FCAL_1_FLC_PB_ATTEN_RESET 0xc #define PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB 10 #define PHY_BB_FCAL_1_FLC_SB_FSTEP_MSB 19 #define PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK 0xffc00 #define PHY_BB_FCAL_1_FLC_SB_FSTEP_GET(x) (((x) & PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK) >> PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB) #define PHY_BB_FCAL_1_FLC_SB_FSTEP_SET(x) (((0 | (x)) << PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB) & PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK) #define PHY_BB_FCAL_1_FLC_SB_FSTEP_RESET 0x10d #define PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB 0 #define PHY_BB_FCAL_1_FLC_PB_FSTEP_MSB 9 #define PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK 0x3ff #define PHY_BB_FCAL_1_FLC_PB_FSTEP_GET(x) (((x) & PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK) >> PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB) #define PHY_BB_FCAL_1_FLC_PB_FSTEP_SET(x) (((0 | (x)) << PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB) & PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK) #define PHY_BB_FCAL_1_FLC_PB_FSTEP_RESET 0x33 #define PHY_BB_FCAL_1_ADDRESS (0xcc + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_FCAL_1_RSTMASK 0x3fffffff #define PHY_BB_FCAL_1_RESET 0x18c43433 // 0xd0 (PHY_BB_FCAL_2_B0) #define PHY_BB_FCAL_2_B0_FLC_TXBB6DBGAIN_LSB 29 #define PHY_BB_FCAL_2_B0_FLC_TXBB6DBGAIN_MSB 30 #define PHY_BB_FCAL_2_B0_FLC_TXBB6DBGAIN_MASK 0x60000000 #define PHY_BB_FCAL_2_B0_FLC_TXBB6DBGAIN_GET(x) (((x) & PHY_BB_FCAL_2_B0_FLC_TXBB6DBGAIN_MASK) >> PHY_BB_FCAL_2_B0_FLC_TXBB6DBGAIN_LSB) #define PHY_BB_FCAL_2_B0_FLC_TXBB6DBGAIN_SET(x) (((0 | (x)) << PHY_BB_FCAL_2_B0_FLC_TXBB6DBGAIN_LSB) & PHY_BB_FCAL_2_B0_FLC_TXBB6DBGAIN_MASK) #define PHY_BB_FCAL_2_B0_FLC_TXBB6DBGAIN_RESET 0x0 #define PHY_BB_FCAL_2_B0_FLC_TXBB1DBGAIN_LSB 25 #define PHY_BB_FCAL_2_B0_FLC_TXBB1DBGAIN_MSB 28 #define PHY_BB_FCAL_2_B0_FLC_TXBB1DBGAIN_MASK 0x1e000000 #define PHY_BB_FCAL_2_B0_FLC_TXBB1DBGAIN_GET(x) (((x) & PHY_BB_FCAL_2_B0_FLC_TXBB1DBGAIN_MASK) >> PHY_BB_FCAL_2_B0_FLC_TXBB1DBGAIN_LSB) #define PHY_BB_FCAL_2_B0_FLC_TXBB1DBGAIN_SET(x) (((0 | (x)) << PHY_BB_FCAL_2_B0_FLC_TXBB1DBGAIN_LSB) & PHY_BB_FCAL_2_B0_FLC_TXBB1DBGAIN_MASK) #define PHY_BB_FCAL_2_B0_FLC_TXBB1DBGAIN_RESET 0x0 #define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB 20 #define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MSB 24 #define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK 0x1f00000 #define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_GET(x) (((x) & PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK) >> PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB) #define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_SET(x) (((0 | (x)) << PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB) & PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK) #define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_RESET 0x0 #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB 17 #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MSB 19 #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK 0xe0000 #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_GET(x) (((x) & PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK) >> PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB) #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_SET(x) (((0 | (x)) << PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB) & PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK) #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_RESET 0x3 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB 16 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MSB 16 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK 0x10000 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_GET(x) (((x) & PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK) >> PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB) #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_SET(x) (((0 | (x)) << PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB) & PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK) #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_RESET 0x0 #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB 14 #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MSB 15 #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK 0xc000 #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_GET(x) (((x) & PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK) >> PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB) #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_SET(x) (((0 | (x)) << PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB) & PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK) #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_RESET 0x0 #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB 10 #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MSB 13 #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK 0x3c00 #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_GET(x) (((x) & PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK) >> PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB) #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_SET(x) (((0 | (x)) << PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB) & PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK) #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_RESET 0x0 #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB 8 #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MSB 9 #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK 0x300 #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_GET(x) (((x) & PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK) >> PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB) #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_SET(x) (((0 | (x)) << PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB) & PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK) #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_RESET 0x0 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB 3 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MSB 7 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK 0xf8 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_GET(x) (((x) & PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK) >> PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB) #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_SET(x) (((0 | (x)) << PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB) & PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK) #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_RESET 0xf #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB 0 #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MSB 2 #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK 0x7 #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_GET(x) (((x) & PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK) >> PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB) #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_SET(x) (((0 | (x)) << PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB) & PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK) #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_RESET 0x1 #define PHY_BB_FCAL_2_B0_ADDRESS (0xd0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_FCAL_2_B0_RSTMASK 0x7fffffff #define PHY_BB_FCAL_2_B0_RESET 0x60079 // 0xd4 (PHY_BB_DFT_TONE_CTRL_B0) #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB 4 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MSB 12 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK 0x1ff0 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_GET(x) (((x) & PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK) >> PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB) #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_SET(x) (((0 | (x)) << PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB) & PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK) #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_RESET 0x0 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB 2 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MSB 3 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK 0xc #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_GET(x) (((x) & PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK) >> PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB) #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_SET(x) (((0 | (x)) << PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB) & PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK) #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_RESET 0x0 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB 0 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MSB 0 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK 0x1 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_GET(x) (((x) & PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK) >> PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB) #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_SET(x) (((0 | (x)) << PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB) & PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK) #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_RESET 0x0 #define PHY_BB_DFT_TONE_CTRL_B0_ADDRESS (0xd4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DFT_TONE_CTRL_B0_RSTMASK 0x1ffd #define PHY_BB_DFT_TONE_CTRL_B0_RESET 0x0 // 0xd8 (PHY_BB_CL_CAL_CTRL) #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB 31 #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MSB 31 #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK 0x80000000 #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_GET(x) (((x) & PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK) >> PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB) #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_SET(x) (((0 | (x)) << PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB) & PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK) #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_RESET 0x0 #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB 30 #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MSB 30 #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK 0x40000000 #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_GET(x) (((x) & PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK) >> PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB) #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_SET(x) (((0 | (x)) << PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB) & PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK) #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_RESET 0x0 #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB 22 #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MSB 29 #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK 0x3fc00000 #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_GET(x) (((x) & PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK) >> PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB) #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_SET(x) (((0 | (x)) << PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB) & PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK) #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_RESET 0x0 #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB 16 #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MSB 21 #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK 0x3f0000 #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_GET(x) (((x) & PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK) >> PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB) #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_SET(x) (((0 | (x)) << PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB) & PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK) #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_RESET 0x19 #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB 8 #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MSB 15 #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK 0xff00 #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_GET(x) (((x) & PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK) >> PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB) #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_SET(x) (((0 | (x)) << PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB) & PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK) #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_RESET 0x0 #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB 4 #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MSB 7 #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK 0xf0 #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_GET(x) (((x) & PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK) >> PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB) #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_SET(x) (((0 | (x)) << PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB) & PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK) #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_RESET 0x0 #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB 2 #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MSB 3 #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK 0xc #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_GET(x) (((x) & PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK) >> PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB) #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_SET(x) (((0 | (x)) << PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB) & PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK) #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_RESET 0x0 #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB 1 #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MSB 1 #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK 0x2 #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_GET(x) (((x) & PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK) >> PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB) #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_SET(x) (((0 | (x)) << PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB) & PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK) #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_RESET 0x0 #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB 0 #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MSB 0 #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK 0x1 #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_GET(x) (((x) & PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK) >> PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB) #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_SET(x) (((0 | (x)) << PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB) & PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK) #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_RESET 0x0 #define PHY_BB_CL_CAL_CTRL_ADDRESS (0xd8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_CAL_CTRL_RSTMASK 0xffffffff #define PHY_BB_CL_CAL_CTRL_RESET 0x190000 // 0xdc (PHY_BB_CL_MAP_0_B0) #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB 0 #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MSB 31 #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK 0xffffffff #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_GET(x) (((x) & PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK) >> PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB) #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_SET(x) (((0 | (x)) << PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB) & PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK) #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_RESET 0x0 #define PHY_BB_CL_MAP_0_B0_ADDRESS (0xdc + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_MAP_0_B0_RSTMASK 0xffffffff #define PHY_BB_CL_MAP_0_B0_RESET 0x0 // 0xe0 (PHY_BB_CL_MAP_1_B0) #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB 0 #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MSB 31 #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK 0xffffffff #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_GET(x) (((x) & PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK) >> PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB) #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_SET(x) (((0 | (x)) << PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB) & PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK) #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_RESET 0x0 #define PHY_BB_CL_MAP_1_B0_ADDRESS (0xe0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_MAP_1_B0_RSTMASK 0xffffffff #define PHY_BB_CL_MAP_1_B0_RESET 0x0 // 0xe4 (PHY_BB_CL_MAP_2_B0) #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB 0 #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MSB 31 #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK 0xffffffff #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_GET(x) (((x) & PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK) >> PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB) #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_SET(x) (((0 | (x)) << PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB) & PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK) #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_RESET 0x0 #define PHY_BB_CL_MAP_2_B0_ADDRESS (0xe4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_MAP_2_B0_RSTMASK 0xffffffff #define PHY_BB_CL_MAP_2_B0_RESET 0x0 // 0xe8 (PHY_BB_CL_MAP_3_B0) #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB 0 #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MSB 31 #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK 0xffffffff #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_GET(x) (((x) & PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK) >> PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB) #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_SET(x) (((0 | (x)) << PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB) & PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK) #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_RESET 0x0 #define PHY_BB_CL_MAP_3_B0_ADDRESS (0xe8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_MAP_3_B0_RSTMASK 0xffffffff #define PHY_BB_CL_MAP_3_B0_RESET 0x0 // 0x100 (PHY_BB_CL_TAB_B0) #define PHY_BB_CL_TAB_B0_BB_GAIN_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_RESET 0x0 #define PHY_BB_CL_TAB_B0_ADDRESS (0x100 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_RESET 0x0 // 0x100 (PHY_BB_CL_TAB_B0_0) #define PHY_BB_CL_TAB_B0_BB_GAIN_0_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_0_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_0_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_0_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_0_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_0_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_0_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_0_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_0_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_0_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_0_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_0_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_0_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_0_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_0_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_0_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_0_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_0_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_0_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_0_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_0_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_0_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_0_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_0_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_0_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_0_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_0_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_0_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_0_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_0_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_0_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_0_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_0_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_0_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_0_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_0_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_0_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_0_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_0_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_0_RESET 0x0 #define PHY_BB_CL_TAB_B0_0_ADDRESS (0x100 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_0_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_0_RESET 0x0 // 0x104 (PHY_BB_CL_TAB_B0_1) #define PHY_BB_CL_TAB_B0_BB_GAIN_1_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_1_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_1_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_1_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_1_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_1_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_1_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_1_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_1_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_1_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_1_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_1_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_1_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_1_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_1_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_1_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_1_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_1_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_1_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_1_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_1_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_1_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_1_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_1_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_1_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_1_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_1_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_1_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_1_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_1_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_1_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_1_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_1_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_1_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_1_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_1_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_1_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_1_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_1_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_1_RESET 0x0 #define PHY_BB_CL_TAB_B0_1_ADDRESS (0x104 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_1_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_1_RESET 0x0 // 0x108 (PHY_BB_CL_TAB_B0_2) #define PHY_BB_CL_TAB_B0_BB_GAIN_2_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_2_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_2_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_2_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_2_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_2_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_2_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_2_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_2_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_2_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_2_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_2_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_2_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_2_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_2_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_2_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_2_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_2_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_2_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_2_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_2_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_2_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_2_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_2_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_2_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_2_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_2_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_2_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_2_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_2_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_2_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_2_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_2_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_2_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_2_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_2_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_2_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_2_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_2_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_2_RESET 0x0 #define PHY_BB_CL_TAB_B0_2_ADDRESS (0x108 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_2_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_2_RESET 0x0 // 0x10c (PHY_BB_CL_TAB_B0_3) #define PHY_BB_CL_TAB_B0_BB_GAIN_3_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_3_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_3_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_3_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_3_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_3_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_3_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_3_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_3_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_3_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_3_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_3_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_3_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_3_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_3_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_3_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_3_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_3_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_3_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_3_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_3_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_3_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_3_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_3_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_3_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_3_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_3_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_3_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_3_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_3_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_3_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_3_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_3_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_3_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_3_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_3_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_3_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_3_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_3_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_3_RESET 0x0 #define PHY_BB_CL_TAB_B0_3_ADDRESS (0x10c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_3_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_3_RESET 0x0 // 0x110 (PHY_BB_CL_TAB_B0_4) #define PHY_BB_CL_TAB_B0_BB_GAIN_4_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_4_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_4_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_4_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_4_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_4_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_4_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_4_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_4_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_4_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_4_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_4_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_4_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_4_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_4_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_4_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_4_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_4_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_4_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_4_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_4_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_4_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_4_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_4_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_4_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_4_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_4_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_4_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_4_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_4_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_4_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_4_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_4_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_4_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_4_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_4_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_4_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_4_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_4_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_4_RESET 0x0 #define PHY_BB_CL_TAB_B0_4_ADDRESS (0x110 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_4_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_4_RESET 0x0 // 0x114 (PHY_BB_CL_TAB_B0_5) #define PHY_BB_CL_TAB_B0_BB_GAIN_5_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_5_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_5_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_5_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_5_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_5_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_5_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_5_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_5_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_5_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_5_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_5_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_5_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_5_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_5_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_5_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_5_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_5_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_5_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_5_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_5_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_5_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_5_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_5_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_5_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_5_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_5_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_5_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_5_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_5_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_5_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_5_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_5_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_5_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_5_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_5_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_5_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_5_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_5_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_5_RESET 0x0 #define PHY_BB_CL_TAB_B0_5_ADDRESS (0x114 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_5_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_5_RESET 0x0 // 0x118 (PHY_BB_CL_TAB_B0_6) #define PHY_BB_CL_TAB_B0_BB_GAIN_6_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_6_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_6_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_6_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_6_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_6_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_6_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_6_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_6_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_6_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_6_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_6_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_6_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_6_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_6_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_6_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_6_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_6_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_6_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_6_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_6_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_6_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_6_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_6_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_6_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_6_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_6_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_6_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_6_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_6_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_6_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_6_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_6_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_6_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_6_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_6_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_6_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_6_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_6_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_6_RESET 0x0 #define PHY_BB_CL_TAB_B0_6_ADDRESS (0x118 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_6_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_6_RESET 0x0 // 0x11c (PHY_BB_CL_TAB_B0_7) #define PHY_BB_CL_TAB_B0_BB_GAIN_7_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_7_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_7_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_7_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_7_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_7_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_7_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_7_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_7_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_7_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_7_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_7_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_7_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_7_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_7_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_7_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_7_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_7_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_7_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_7_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_7_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_7_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_7_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_7_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_7_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_7_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_7_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_7_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_7_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_7_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_7_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_7_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_7_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_7_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_7_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_7_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_7_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_7_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_7_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_7_RESET 0x0 #define PHY_BB_CL_TAB_B0_7_ADDRESS (0x11c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_7_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_7_RESET 0x0 // 0x120 (PHY_BB_CL_TAB_B0_8) #define PHY_BB_CL_TAB_B0_BB_GAIN_8_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_8_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_8_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_8_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_8_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_8_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_8_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_8_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_8_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_8_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_8_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_8_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_8_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_8_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_8_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_8_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_8_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_8_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_8_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_8_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_8_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_8_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_8_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_8_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_8_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_8_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_8_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_8_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_8_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_8_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_8_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_8_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_8_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_8_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_8_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_8_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_8_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_8_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_8_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_8_RESET 0x0 #define PHY_BB_CL_TAB_B0_8_ADDRESS (0x120 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_8_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_8_RESET 0x0 // 0x124 (PHY_BB_CL_TAB_B0_9) #define PHY_BB_CL_TAB_B0_BB_GAIN_9_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_9_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_9_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_9_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_9_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_9_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_9_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_9_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_9_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_9_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_9_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_9_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_9_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_9_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_9_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_9_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_9_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_9_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_9_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_9_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_9_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_9_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_9_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_9_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_9_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_9_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_9_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_9_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_9_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_9_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_9_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_9_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_9_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_9_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_9_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_9_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_9_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_9_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_9_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_9_RESET 0x0 #define PHY_BB_CL_TAB_B0_9_ADDRESS (0x124 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_9_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_9_RESET 0x0 // 0x128 (PHY_BB_CL_TAB_B0_10) #define PHY_BB_CL_TAB_B0_BB_GAIN_10_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_10_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_10_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_10_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_10_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_10_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_10_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_10_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_10_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_10_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_10_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_10_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_10_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_10_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_10_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_10_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_10_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_10_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_10_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_10_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_10_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_10_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_10_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_10_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_10_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_10_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_10_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_10_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_10_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_10_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_10_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_10_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_10_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_10_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_10_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_10_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_10_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_10_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_10_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_10_RESET 0x0 #define PHY_BB_CL_TAB_B0_10_ADDRESS (0x128 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_10_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_10_RESET 0x0 // 0x12c (PHY_BB_CL_TAB_B0_11) #define PHY_BB_CL_TAB_B0_BB_GAIN_11_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_11_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_11_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_11_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_11_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_11_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_11_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_11_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_11_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_11_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_11_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_11_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_11_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_11_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_11_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_11_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_11_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_11_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_11_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_11_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_11_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_11_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_11_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_11_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_11_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_11_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_11_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_11_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_11_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_11_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_11_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_11_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_11_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_11_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_11_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_11_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_11_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_11_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_11_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_11_RESET 0x0 #define PHY_BB_CL_TAB_B0_11_ADDRESS (0x12c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_11_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_11_RESET 0x0 // 0x130 (PHY_BB_CL_TAB_B0_12) #define PHY_BB_CL_TAB_B0_BB_GAIN_12_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_12_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_12_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_12_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_12_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_12_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_12_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_12_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_12_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_12_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_12_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_12_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_12_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_12_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_12_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_12_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_12_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_12_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_12_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_12_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_12_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_12_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_12_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_12_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_12_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_12_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_12_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_12_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_12_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_12_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_12_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_12_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_12_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_12_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_12_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_12_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_12_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_12_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_12_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_12_RESET 0x0 #define PHY_BB_CL_TAB_B0_12_ADDRESS (0x130 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_12_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_12_RESET 0x0 // 0x134 (PHY_BB_CL_TAB_B0_13) #define PHY_BB_CL_TAB_B0_BB_GAIN_13_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_13_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_13_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_13_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_13_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_13_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_13_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_13_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_13_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_13_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_13_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_13_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_13_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_13_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_13_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_13_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_13_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_13_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_13_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_13_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_13_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_13_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_13_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_13_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_13_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_13_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_13_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_13_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_13_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_13_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_13_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_13_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_13_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_13_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_13_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_13_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_13_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_13_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_13_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_13_RESET 0x0 #define PHY_BB_CL_TAB_B0_13_ADDRESS (0x134 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_13_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_13_RESET 0x0 // 0x138 (PHY_BB_CL_TAB_B0_14) #define PHY_BB_CL_TAB_B0_BB_GAIN_14_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_14_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_14_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_14_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_14_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_14_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_14_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_14_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_14_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_14_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_14_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_14_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_14_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_14_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_14_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_14_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_14_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_14_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_14_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_14_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_14_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_14_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_14_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_14_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_14_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_14_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_14_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_14_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_14_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_14_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_14_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_14_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_14_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_14_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_14_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_14_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_14_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_14_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_14_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_14_RESET 0x0 #define PHY_BB_CL_TAB_B0_14_ADDRESS (0x138 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_14_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_14_RESET 0x0 // 0x13c (PHY_BB_CL_TAB_B0_15) #define PHY_BB_CL_TAB_B0_BB_GAIN_15_LSB 27 #define PHY_BB_CL_TAB_B0_BB_GAIN_15_MSB 30 #define PHY_BB_CL_TAB_B0_BB_GAIN_15_MASK 0x78000000 #define PHY_BB_CL_TAB_B0_BB_GAIN_15_GET(x) (((x) & PHY_BB_CL_TAB_B0_BB_GAIN_15_MASK) >> PHY_BB_CL_TAB_B0_BB_GAIN_15_LSB) #define PHY_BB_CL_TAB_B0_BB_GAIN_15_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_BB_GAIN_15_LSB) & PHY_BB_CL_TAB_B0_BB_GAIN_15_MASK) #define PHY_BB_CL_TAB_B0_BB_GAIN_15_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_15_LSB 16 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_15_MSB 26 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_15_MASK 0x7ff0000 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_15_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_15_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_15_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_15_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_15_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_15_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_15_RESET 0x0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_15_LSB 5 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_15_MSB 15 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_15_MASK 0xffe0 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_15_GET(x) (((x) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_15_MASK) >> PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_15_LSB) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_15_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_15_LSB) & PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_15_MASK) #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_15_RESET 0x0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_15_LSB 0 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_15_MSB 4 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_15_MASK 0x1f #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_15_GET(x) (((x) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_15_MASK) >> PHY_BB_CL_TAB_B0_CL_GAIN_MOD_15_LSB) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_15_SET(x) (((0 | (x)) << PHY_BB_CL_TAB_B0_CL_GAIN_MOD_15_LSB) & PHY_BB_CL_TAB_B0_CL_GAIN_MOD_15_MASK) #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_15_RESET 0x0 #define PHY_BB_CL_TAB_B0_15_ADDRESS (0x13c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CL_TAB_B0_15_RSTMASK 0x7fffffff #define PHY_BB_CL_TAB_B0_15_RESET 0x0 // 0x140 (PHY_BB_SYNTH_CONTROL) #define PHY_BB_SYNTH_CONTROL_SEL_ALT_TABLES_LSB 31 #define PHY_BB_SYNTH_CONTROL_SEL_ALT_TABLES_MSB 31 #define PHY_BB_SYNTH_CONTROL_SEL_ALT_TABLES_MASK 0x80000000 #define PHY_BB_SYNTH_CONTROL_SEL_ALT_TABLES_GET(x) (((x) & PHY_BB_SYNTH_CONTROL_SEL_ALT_TABLES_MASK) >> PHY_BB_SYNTH_CONTROL_SEL_ALT_TABLES_LSB) #define PHY_BB_SYNTH_CONTROL_SEL_ALT_TABLES_SET(x) (((0 | (x)) << PHY_BB_SYNTH_CONTROL_SEL_ALT_TABLES_LSB) & PHY_BB_SYNTH_CONTROL_SEL_ALT_TABLES_MASK) #define PHY_BB_SYNTH_CONTROL_SEL_ALT_TABLES_RESET 0x0 #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB 30 #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MSB 30 #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK 0x40000000 #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_GET(x) (((x) & PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK) >> PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB) #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_SET(x) (((0 | (x)) << PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB) & PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK) #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_RESET 0x0 #define PHY_BB_SYNTH_CONTROL_RFBMODE_LSB 29 #define PHY_BB_SYNTH_CONTROL_RFBMODE_MSB 29 #define PHY_BB_SYNTH_CONTROL_RFBMODE_MASK 0x20000000 #define PHY_BB_SYNTH_CONTROL_RFBMODE_GET(x) (((x) & PHY_BB_SYNTH_CONTROL_RFBMODE_MASK) >> PHY_BB_SYNTH_CONTROL_RFBMODE_LSB) #define PHY_BB_SYNTH_CONTROL_RFBMODE_SET(x) (((0 | (x)) << PHY_BB_SYNTH_CONTROL_RFBMODE_LSB) & PHY_BB_SYNTH_CONTROL_RFBMODE_MASK) #define PHY_BB_SYNTH_CONTROL_RFBMODE_RESET 0x0 #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB 28 #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MSB 28 #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK 0x10000000 #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_GET(x) (((x) & PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK) >> PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB) #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_SET(x) (((0 | (x)) << PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB) & PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK) #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_RESET 0x0 #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB 26 #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MSB 27 #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK 0xc000000 #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_GET(x) (((x) & PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK) >> PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB) #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_SET(x) (((0 | (x)) << PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB) & PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK) #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_RESET 0x0 #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB 17 #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MSB 25 #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK 0x3fe0000 #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_GET(x) (((x) & PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK) >> PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB) #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_SET(x) (((0 | (x)) << PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB) & PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK) #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_RESET 0x0 #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB 0 #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MSB 16 #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK 0x1ffff #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_GET(x) (((x) & PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK) >> PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB) #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_SET(x) (((0 | (x)) << PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB) & PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK) #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_RESET 0x0 #define PHY_BB_SYNTH_CONTROL_ADDRESS (0x140 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_SYNTH_CONTROL_RSTMASK 0xffffffff #define PHY_BB_SYNTH_CONTROL_RESET 0x0 // 0x144 (PHY_BB_ADDAC_CLK_SELECT) #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH3_LSB 10 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH3_MSB 11 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH3_MASK 0xc00 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH3_GET(x) (((x) & PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH3_MASK) >> PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH3_LSB) #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH3_SET(x) (((0 | (x)) << PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH3_LSB) & PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH3_MASK) #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH3_RESET 0x0 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH2_LSB 8 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH2_MSB 9 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH2_MASK 0x300 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH2_GET(x) (((x) & PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH2_MASK) >> PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH2_LSB) #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH2_SET(x) (((0 | (x)) << PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH2_LSB) & PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH2_MASK) #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH2_RESET 0x0 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH1_LSB 6 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH1_MSB 7 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH1_MASK 0xc0 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH1_GET(x) (((x) & PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH1_MASK) >> PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH1_LSB) #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH1_SET(x) (((0 | (x)) << PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH1_LSB) & PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH1_MASK) #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH1_RESET 0x0 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH0_LSB 4 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH0_MSB 5 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH0_MASK 0x30 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH0_GET(x) (((x) & PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH0_MASK) >> PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH0_LSB) #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH0_SET(x) (((0 | (x)) << PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH0_LSB) & PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH0_MASK) #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_CH0_RESET 0x0 #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB 0 #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MSB 3 #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK 0xf #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_GET(x) (((x) & PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK) >> PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB) #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_SET(x) (((0 | (x)) << PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB) & PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK) #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_RESET 0x0 #define PHY_BB_ADDAC_CLK_SELECT_ADDRESS (0x144 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_ADDAC_CLK_SELECT_RSTMASK 0xfff #define PHY_BB_ADDAC_CLK_SELECT_RESET 0x0 // 0x148 (PHY_BB_PLL_CNTL) #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB 17 #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MSB 27 #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK 0xffe0000 #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_GET(x) (((x) & PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK) >> PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB) #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_SET(x) (((0 | (x)) << PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB) & PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK) #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_RESET 0x400 #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB 16 #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MSB 16 #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK 0x10000 #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_GET(x) (((x) & PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK) >> PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB) #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_SET(x) (((0 | (x)) << PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB) & PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK) #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_RESET 0x1 #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB 14 #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MSB 15 #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK 0xc000 #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_GET(x) (((x) & PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK) >> PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB) #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_SET(x) (((0 | (x)) << PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB) & PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK) #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_RESET 0x0 #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB 10 #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MSB 13 #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK 0x3c00 #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_GET(x) (((x) & PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK) >> PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB) #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_SET(x) (((0 | (x)) << PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB) & PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK) #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_RESET 0x5 #define PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB 0 #define PHY_BB_PLL_CNTL_BB_PLL_DIV_MSB 9 #define PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK 0x3ff #define PHY_BB_PLL_CNTL_BB_PLL_DIV_GET(x) (((x) & PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK) >> PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB) #define PHY_BB_PLL_CNTL_BB_PLL_DIV_SET(x) (((0 | (x)) << PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB) & PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK) #define PHY_BB_PLL_CNTL_BB_PLL_DIV_RESET 0x32 #define PHY_BB_PLL_CNTL_ADDRESS (0x148 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PLL_CNTL_RSTMASK 0xfffffff #define PHY_BB_PLL_CNTL_RESET 0x8011432 // 0x14c (PHY_BB_ANALOG_SWAP) #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB 8 #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MSB 8 #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK 0x100 #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_GET(x) (((x) & PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK) >> PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB) #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_SET(x) (((0 | (x)) << PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB) & PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK) #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_RESET 0x0 #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB 7 #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MSB 7 #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK 0x80 #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_GET(x) (((x) & PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK) >> PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB) #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_SET(x) (((0 | (x)) << PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB) & PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK) #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_RESET 0x0 #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB 6 #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MSB 6 #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK 0x40 #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_GET(x) (((x) & PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK) >> PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB) #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_SET(x) (((0 | (x)) << PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB) & PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK) #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_RESET 0x0 #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB 3 #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MSB 5 #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK 0x38 #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_GET(x) (((x) & PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK) >> PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB) #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_SET(x) (((0 | (x)) << PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB) & PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK) #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_RESET 0x0 #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB 0 #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MSB 2 #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK 0x7 #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_GET(x) (((x) & PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK) >> PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB) #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_SET(x) (((0 | (x)) << PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB) & PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK) #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_RESET 0x0 #define PHY_BB_ANALOG_SWAP_ADDRESS (0x14c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_ANALOG_SWAP_RSTMASK 0x1ff #define PHY_BB_ANALOG_SWAP_RESET 0x0 // 0x150 (PHY_BB_ADDAC_PARALLEL_CONTROL) #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB 31 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MSB 31 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK 0x80000000 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_GET(x) (((x) & PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK) >> PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB) #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_SET(x) (((0 | (x)) << PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB) & PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK) #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_RESET 0x0 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB 29 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MSB 29 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK 0x20000000 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_GET(x) (((x) & PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK) >> PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB) #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_SET(x) (((0 | (x)) << PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB) & PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK) #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_RESET 0x0 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB 28 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MSB 28 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK 0x10000000 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_GET(x) (((x) & PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK) >> PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB) #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_SET(x) (((0 | (x)) << PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB) & PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK) #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_RESET 0x0 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB 15 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MSB 15 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK 0x8000 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_GET(x) (((x) & PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK) >> PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB) #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_SET(x) (((0 | (x)) << PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB) & PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK) #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_RESET 0x1 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB 13 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MSB 13 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK 0x2000 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_GET(x) (((x) & PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK) >> PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB) #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_SET(x) (((0 | (x)) << PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB) & PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK) #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_RESET 0x1 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB 12 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MSB 12 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK 0x1000 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_GET(x) (((x) & PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK) >> PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB) #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_SET(x) (((0 | (x)) << PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB) & PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK) #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_RESET 0x0 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ADDRESS (0x150 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_ADDAC_PARALLEL_CONTROL_RSTMASK 0xb000b000 #define PHY_BB_ADDAC_PARALLEL_CONTROL_RESET 0xa000 // 0x154 (PHY_BB_FORCE_CLOCK) #define PHY_BB_FORCE_CLOCK_ENA_REG_CLK_GATING_LSB 26 #define PHY_BB_FORCE_CLOCK_ENA_REG_CLK_GATING_MSB 26 #define PHY_BB_FORCE_CLOCK_ENA_REG_CLK_GATING_MASK 0x4000000 #define PHY_BB_FORCE_CLOCK_ENA_REG_CLK_GATING_GET(x) (((x) & PHY_BB_FORCE_CLOCK_ENA_REG_CLK_GATING_MASK) >> PHY_BB_FORCE_CLOCK_ENA_REG_CLK_GATING_LSB) #define PHY_BB_FORCE_CLOCK_ENA_REG_CLK_GATING_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_ENA_REG_CLK_GATING_LSB) & PHY_BB_FORCE_CLOCK_ENA_REG_CLK_GATING_MASK) #define PHY_BB_FORCE_CLOCK_ENA_REG_CLK_GATING_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_DPD_TX_RADIO_BW_LSB 23 #define PHY_BB_FORCE_CLOCK_CF_DPD_TX_RADIO_BW_MSB 25 #define PHY_BB_FORCE_CLOCK_CF_DPD_TX_RADIO_BW_MASK 0x3800000 #define PHY_BB_FORCE_CLOCK_CF_DPD_TX_RADIO_BW_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_DPD_TX_RADIO_BW_MASK) >> PHY_BB_FORCE_CLOCK_CF_DPD_TX_RADIO_BW_LSB) #define PHY_BB_FORCE_CLOCK_CF_DPD_TX_RADIO_BW_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_DPD_TX_RADIO_BW_LSB) & PHY_BB_FORCE_CLOCK_CF_DPD_TX_RADIO_BW_MASK) #define PHY_BB_FORCE_CLOCK_CF_DPD_TX_RADIO_BW_RESET 0x2 #define PHY_BB_FORCE_CLOCK_CF_FORCED_TX_RADIO_BW_LSB 20 #define PHY_BB_FORCE_CLOCK_CF_FORCED_TX_RADIO_BW_MSB 22 #define PHY_BB_FORCE_CLOCK_CF_FORCED_TX_RADIO_BW_MASK 0x700000 #define PHY_BB_FORCE_CLOCK_CF_FORCED_TX_RADIO_BW_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_FORCED_TX_RADIO_BW_MASK) >> PHY_BB_FORCE_CLOCK_CF_FORCED_TX_RADIO_BW_LSB) #define PHY_BB_FORCE_CLOCK_CF_FORCED_TX_RADIO_BW_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_FORCED_TX_RADIO_BW_LSB) & PHY_BB_FORCE_CLOCK_CF_FORCED_TX_RADIO_BW_MASK) #define PHY_BB_FORCE_CLOCK_CF_FORCED_TX_RADIO_BW_RESET 0x5 #define PHY_BB_FORCE_CLOCK_CF_FORCE_TX_RADIO_BW_LSB 19 #define PHY_BB_FORCE_CLOCK_CF_FORCE_TX_RADIO_BW_MSB 19 #define PHY_BB_FORCE_CLOCK_CF_FORCE_TX_RADIO_BW_MASK 0x80000 #define PHY_BB_FORCE_CLOCK_CF_FORCE_TX_RADIO_BW_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_FORCE_TX_RADIO_BW_MASK) >> PHY_BB_FORCE_CLOCK_CF_FORCE_TX_RADIO_BW_LSB) #define PHY_BB_FORCE_CLOCK_CF_FORCE_TX_RADIO_BW_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_FORCE_TX_RADIO_BW_LSB) & PHY_BB_FORCE_CLOCK_CF_FORCE_TX_RADIO_BW_MASK) #define PHY_BB_FORCE_CLOCK_CF_FORCE_TX_RADIO_BW_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_SYNTHON_IN_ACTIVELOW_LSB 18 #define PHY_BB_FORCE_CLOCK_CF_SYNTHON_IN_ACTIVELOW_MSB 18 #define PHY_BB_FORCE_CLOCK_CF_SYNTHON_IN_ACTIVELOW_MASK 0x40000 #define PHY_BB_FORCE_CLOCK_CF_SYNTHON_IN_ACTIVELOW_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_SYNTHON_IN_ACTIVELOW_MASK) >> PHY_BB_FORCE_CLOCK_CF_SYNTHON_IN_ACTIVELOW_LSB) #define PHY_BB_FORCE_CLOCK_CF_SYNTHON_IN_ACTIVELOW_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_SYNTHON_IN_ACTIVELOW_LSB) & PHY_BB_FORCE_CLOCK_CF_SYNTHON_IN_ACTIVELOW_MASK) #define PHY_BB_FORCE_CLOCK_CF_SYNTHON_IN_ACTIVELOW_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_DOUBLE_TX_RADIO_BW_LSB 17 #define PHY_BB_FORCE_CLOCK_CF_DOUBLE_TX_RADIO_BW_MSB 17 #define PHY_BB_FORCE_CLOCK_CF_DOUBLE_TX_RADIO_BW_MASK 0x20000 #define PHY_BB_FORCE_CLOCK_CF_DOUBLE_TX_RADIO_BW_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_DOUBLE_TX_RADIO_BW_MASK) >> PHY_BB_FORCE_CLOCK_CF_DOUBLE_TX_RADIO_BW_LSB) #define PHY_BB_FORCE_CLOCK_CF_DOUBLE_TX_RADIO_BW_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_DOUBLE_TX_RADIO_BW_LSB) & PHY_BB_FORCE_CLOCK_CF_DOUBLE_TX_RADIO_BW_MASK) #define PHY_BB_FORCE_CLOCK_CF_DOUBLE_TX_RADIO_BW_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKTADC_LSB 14 #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKTADC_MSB 16 #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKTADC_MASK 0x1c000 #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKTADC_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_FORCED_CLKTADC_MASK) >> PHY_BB_FORCE_CLOCK_CF_FORCED_CLKTADC_LSB) #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKTADC_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_FORCED_CLKTADC_LSB) & PHY_BB_FORCE_CLOCK_CF_FORCED_CLKTADC_MASK) #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKTADC_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKTADC_LSB 13 #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKTADC_MSB 13 #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKTADC_MASK 0x2000 #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKTADC_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_FORCE_CLKTADC_MASK) >> PHY_BB_FORCE_CLOCK_CF_FORCE_CLKTADC_LSB) #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKTADC_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_FORCE_CLKTADC_LSB) & PHY_BB_FORCE_CLOCK_CF_FORCE_CLKTADC_MASK) #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKTADC_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKGEN_BW_LSB 10 #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKGEN_BW_MSB 12 #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKGEN_BW_MASK 0x1c00 #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKGEN_BW_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_FORCED_CLKGEN_BW_MASK) >> PHY_BB_FORCE_CLOCK_CF_FORCED_CLKGEN_BW_LSB) #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKGEN_BW_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_FORCED_CLKGEN_BW_LSB) & PHY_BB_FORCE_CLOCK_CF_FORCED_CLKGEN_BW_MASK) #define PHY_BB_FORCE_CLOCK_CF_FORCED_CLKGEN_BW_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKGEN_BW_LSB 9 #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKGEN_BW_MSB 9 #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKGEN_BW_MASK 0x200 #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKGEN_BW_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_FORCE_CLKGEN_BW_MASK) >> PHY_BB_FORCE_CLOCK_CF_FORCE_CLKGEN_BW_LSB) #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKGEN_BW_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_FORCE_CLKGEN_BW_LSB) & PHY_BB_FORCE_CLOCK_CF_FORCE_CLKGEN_BW_MASK) #define PHY_BB_FORCE_CLOCK_CF_FORCE_CLKGEN_BW_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_FORCED_RADIO_BW_LSB 6 #define PHY_BB_FORCE_CLOCK_CF_FORCED_RADIO_BW_MSB 8 #define PHY_BB_FORCE_CLOCK_CF_FORCED_RADIO_BW_MASK 0x1c0 #define PHY_BB_FORCE_CLOCK_CF_FORCED_RADIO_BW_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_FORCED_RADIO_BW_MASK) >> PHY_BB_FORCE_CLOCK_CF_FORCED_RADIO_BW_LSB) #define PHY_BB_FORCE_CLOCK_CF_FORCED_RADIO_BW_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_FORCED_RADIO_BW_LSB) & PHY_BB_FORCE_CLOCK_CF_FORCED_RADIO_BW_MASK) #define PHY_BB_FORCE_CLOCK_CF_FORCED_RADIO_BW_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_FORCE_RADIO_BW_LSB 5 #define PHY_BB_FORCE_CLOCK_CF_FORCE_RADIO_BW_MSB 5 #define PHY_BB_FORCE_CLOCK_CF_FORCE_RADIO_BW_MASK 0x20 #define PHY_BB_FORCE_CLOCK_CF_FORCE_RADIO_BW_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_FORCE_RADIO_BW_MASK) >> PHY_BB_FORCE_CLOCK_CF_FORCE_RADIO_BW_LSB) #define PHY_BB_FORCE_CLOCK_CF_FORCE_RADIO_BW_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_FORCE_RADIO_BW_LSB) & PHY_BB_FORCE_CLOCK_CF_FORCE_RADIO_BW_MASK) #define PHY_BB_FORCE_CLOCK_CF_FORCE_RADIO_BW_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_FORCED_ADC_CLK_RATE_LSB 1 #define PHY_BB_FORCE_CLOCK_CF_FORCED_ADC_CLK_RATE_MSB 2 #define PHY_BB_FORCE_CLOCK_CF_FORCED_ADC_CLK_RATE_MASK 0x6 #define PHY_BB_FORCE_CLOCK_CF_FORCED_ADC_CLK_RATE_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_FORCED_ADC_CLK_RATE_MASK) >> PHY_BB_FORCE_CLOCK_CF_FORCED_ADC_CLK_RATE_LSB) #define PHY_BB_FORCE_CLOCK_CF_FORCED_ADC_CLK_RATE_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_FORCED_ADC_CLK_RATE_LSB) & PHY_BB_FORCE_CLOCK_CF_FORCED_ADC_CLK_RATE_MASK) #define PHY_BB_FORCE_CLOCK_CF_FORCED_ADC_CLK_RATE_RESET 0x0 #define PHY_BB_FORCE_CLOCK_CF_FORCE_ADC_CLK_RATE_LSB 0 #define PHY_BB_FORCE_CLOCK_CF_FORCE_ADC_CLK_RATE_MSB 0 #define PHY_BB_FORCE_CLOCK_CF_FORCE_ADC_CLK_RATE_MASK 0x1 #define PHY_BB_FORCE_CLOCK_CF_FORCE_ADC_CLK_RATE_GET(x) (((x) & PHY_BB_FORCE_CLOCK_CF_FORCE_ADC_CLK_RATE_MASK) >> PHY_BB_FORCE_CLOCK_CF_FORCE_ADC_CLK_RATE_LSB) #define PHY_BB_FORCE_CLOCK_CF_FORCE_ADC_CLK_RATE_SET(x) (((0 | (x)) << PHY_BB_FORCE_CLOCK_CF_FORCE_ADC_CLK_RATE_LSB) & PHY_BB_FORCE_CLOCK_CF_FORCE_ADC_CLK_RATE_MASK) #define PHY_BB_FORCE_CLOCK_CF_FORCE_ADC_CLK_RATE_RESET 0x0 #define PHY_BB_FORCE_CLOCK_ADDRESS (0x154 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_FORCE_CLOCK_RSTMASK 0x7ffffe7 #define PHY_BB_FORCE_CLOCK_RESET 0x1500000 // 0x158 (PHY_BB_FORCE_ANALOG) #define PHY_BB_FORCE_ANALOG_FORCED_PAPRD_XPAON_LSB 5 #define PHY_BB_FORCE_ANALOG_FORCED_PAPRD_XPAON_MSB 8 #define PHY_BB_FORCE_ANALOG_FORCED_PAPRD_XPAON_MASK 0x1e0 #define PHY_BB_FORCE_ANALOG_FORCED_PAPRD_XPAON_GET(x) (((x) & PHY_BB_FORCE_ANALOG_FORCED_PAPRD_XPAON_MASK) >> PHY_BB_FORCE_ANALOG_FORCED_PAPRD_XPAON_LSB) #define PHY_BB_FORCE_ANALOG_FORCED_PAPRD_XPAON_SET(x) (((0 | (x)) << PHY_BB_FORCE_ANALOG_FORCED_PAPRD_XPAON_LSB) & PHY_BB_FORCE_ANALOG_FORCED_PAPRD_XPAON_MASK) #define PHY_BB_FORCE_ANALOG_FORCED_PAPRD_XPAON_RESET 0x0 #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB 1 #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MSB 3 #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK 0xe #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_GET(x) (((x) & PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK) >> PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB) #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_SET(x) (((0 | (x)) << PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB) & PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK) #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_RESET 0x0 #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB 0 #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MSB 0 #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK 0x1 #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_GET(x) (((x) & PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK) >> PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB) #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_SET(x) (((0 | (x)) << PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB) & PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK) #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_RESET 0x0 #define PHY_BB_FORCE_ANALOG_ADDRESS (0x158 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_FORCE_ANALOG_RSTMASK 0x1ef #define PHY_BB_FORCE_ANALOG_RESET 0x0 // 0x15c (PHY_BB_FORCE_SS_CTRL) #define PHY_BB_FORCE_SS_CTRL_UPDATE_OFFSET_SW_EN_LSB 0 #define PHY_BB_FORCE_SS_CTRL_UPDATE_OFFSET_SW_EN_MSB 0 #define PHY_BB_FORCE_SS_CTRL_UPDATE_OFFSET_SW_EN_MASK 0x1 #define PHY_BB_FORCE_SS_CTRL_UPDATE_OFFSET_SW_EN_GET(x) (((x) & PHY_BB_FORCE_SS_CTRL_UPDATE_OFFSET_SW_EN_MASK) >> PHY_BB_FORCE_SS_CTRL_UPDATE_OFFSET_SW_EN_LSB) #define PHY_BB_FORCE_SS_CTRL_UPDATE_OFFSET_SW_EN_SET(x) (((0 | (x)) << PHY_BB_FORCE_SS_CTRL_UPDATE_OFFSET_SW_EN_LSB) & PHY_BB_FORCE_SS_CTRL_UPDATE_OFFSET_SW_EN_MASK) #define PHY_BB_FORCE_SS_CTRL_UPDATE_OFFSET_SW_EN_RESET 0x0 #define PHY_BB_FORCE_SS_CTRL_ADDRESS (0x15c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_FORCE_SS_CTRL_RSTMASK 0x1 #define PHY_BB_FORCE_SS_CTRL_RESET 0x0 // 0x160 (PHY_BB_TEST_CONTROLS) #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB 30 #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MSB 31 #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK 0xc0000000 #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_GET(x) (((x) & PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK) >> PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB) #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB) & PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK) #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_RESET 0x0 #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB 28 #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MSB 28 #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK 0x10000000 #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_GET(x) (((x) & PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK) >> PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB) #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB) & PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK) #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_RESET 0x0 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB 24 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MSB 24 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK 0x1000000 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_GET(x) (((x) & PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK) >> PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB) #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB) & PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK) #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_RESET 0x0 #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB 23 #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MSB 23 #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK 0x800000 #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_GET(x) (((x) & PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK) >> PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB) #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB) & PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK) #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_RESET 0x0 #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB 19 #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MSB 22 #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK 0x780000 #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_GET(x) (((x) & PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK) >> PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB) #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB) & PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK) #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_RESET 0x0 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB 18 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MSB 18 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK 0x40000 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_GET(x) (((x) & PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK) >> PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB) #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB) & PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK) #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_RESET 0x0 #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB 17 #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MSB 17 #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK 0x20000 #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_GET(x) (((x) & PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK) >> PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB) #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB) & PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK) #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_RESET 0x0 #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB 15 #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MSB 15 #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK 0x8000 #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_GET(x) (((x) & PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK) >> PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB) #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB) & PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK) #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_RESET 0x0 #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB 13 #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MSB 13 #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK 0x2000 #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_GET(x) (((x) & PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK) >> PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB) #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB) & PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK) #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_RESET 0x0 #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB 10 #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MSB 10 #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK 0x400 #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_GET(x) (((x) & PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK) >> PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB) #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB) & PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK) #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_RESET 0x0 #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB 8 #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MSB 9 #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK 0x300 #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_GET(x) (((x) & PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK) >> PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB) #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB) & PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK) #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_RESET 0x0 #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB 5 #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MSB 6 #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK 0x60 #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_GET(x) (((x) & PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK) >> PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB) #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB) & PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK) #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_RESET 0x0 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB 4 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MSB 4 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK 0x10 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_GET(x) (((x) & PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK) >> PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB) #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB) & PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK) #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_RESET 0x0 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB 0 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MSB 3 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK 0xf #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_GET(x) (((x) & PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK) >> PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB) #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB) & PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK) #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_RESET 0x0 #define PHY_BB_TEST_CONTROLS_ADDRESS (0x160 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TEST_CONTROLS_RSTMASK 0xd1fea77f #define PHY_BB_TEST_CONTROLS_RESET 0x0 // 0x164 (PHY_BB_TEST_CONTROLS_STATUS) #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB 29 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MSB 31 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK 0xe0000000 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB 28 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MSB 28 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK 0x10000000 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB 27 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MSB 27 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK 0x8000000 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB) & PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB 23 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MSB 23 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK 0x800000 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB 19 #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MSB 19 #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK 0x80000 #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB 16 #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MSB 18 #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK 0x70000 #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB) & PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB 15 #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MSB 15 #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK 0x8000 #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB) & PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB 14 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MSB 14 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK 0x4000 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB) & PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB 10 #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MSB 13 #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK 0x3c00 #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB) & PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB 9 #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MSB 9 #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK 0x200 #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB 8 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MSB 8 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK 0x100 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB 7 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MSB 7 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK 0x80 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB 5 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MSB 6 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK 0x60 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB 2 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MSB 4 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK 0x1c #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB 1 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MSB 1 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK 0x2 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB 0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MSB 0 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK 0x1 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_GET(x) (((x) & PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK) >> PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_SET(x) (((0 | (x)) << PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB) & PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK) #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_RESET 0x0 #define PHY_BB_TEST_CONTROLS_STATUS_ADDRESS (0x164 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TEST_CONTROLS_STATUS_RSTMASK 0xf88fffff #define PHY_BB_TEST_CONTROLS_STATUS_RESET 0x0 // 0x168 (PHY_BB_TSTDAC) #define PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB 12 #define PHY_BB_TSTDAC_TSTDAC_OUT_I_MSB 23 #define PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK 0xfff000 #define PHY_BB_TSTDAC_TSTDAC_OUT_I_GET(x) (((x) & PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK) >> PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB) #define PHY_BB_TSTDAC_TSTDAC_OUT_I_SET(x) (((0 | (x)) << PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB) & PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK) #define PHY_BB_TSTDAC_TSTDAC_OUT_I_RESET 0x0 #define PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB 0 #define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MSB 11 #define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK 0xfff #define PHY_BB_TSTDAC_TSTDAC_OUT_Q_GET(x) (((x) & PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK) >> PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB) #define PHY_BB_TSTDAC_TSTDAC_OUT_Q_SET(x) (((0 | (x)) << PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB) & PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK) #define PHY_BB_TSTDAC_TSTDAC_OUT_Q_RESET 0x0 #define PHY_BB_TSTDAC_ADDRESS (0x168 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TSTDAC_RSTMASK 0xffffff #define PHY_BB_TSTDAC_RESET 0x0 // 0x16c (PHY_BB_CHANNEL_STATUS) #define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB 18 #define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MSB 20 #define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK 0x1c0000 #define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_GET(x) (((x) & PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK) >> PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB) #define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_SET(x) (((0 | (x)) << PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB) & PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK) #define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_RESET 0x0 #define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB 12 #define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MSB 17 #define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK 0x3f000 #define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_GET(x) (((x) & PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK) >> PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB) #define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_SET(x) (((0 | (x)) << PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB) & PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK) #define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_RESET 0x0 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_3_LSB 10 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_3_MSB 11 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_3_MASK 0xc00 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_3_GET(x) (((x) & PHY_BB_CHANNEL_STATUS_BB_SW_OUT_3_MASK) >> PHY_BB_CHANNEL_STATUS_BB_SW_OUT_3_LSB) #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_3_SET(x) (((0 | (x)) << PHY_BB_CHANNEL_STATUS_BB_SW_OUT_3_LSB) & PHY_BB_CHANNEL_STATUS_BB_SW_OUT_3_MASK) #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_3_RESET 0x0 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB 8 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MSB 9 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK 0x300 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_GET(x) (((x) & PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK) >> PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB) #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_SET(x) (((0 | (x)) << PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB) & PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK) #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_RESET 0x0 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB 6 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MSB 7 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK 0xc0 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_GET(x) (((x) & PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK) >> PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB) #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_SET(x) (((0 | (x)) << PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB) & PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK) #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_RESET 0x0 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB 4 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MSB 5 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK 0x30 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_GET(x) (((x) & PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK) >> PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB) #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_SET(x) (((0 | (x)) << PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB) & PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK) #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_RESET 0x0 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB 3 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MSB 3 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK 0x8 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_GET(x) (((x) & PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK) >> PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB) #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_SET(x) (((0 | (x)) << PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB) & PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK) #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_RESET 0x0 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB 2 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MSB 2 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK 0x4 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_GET(x) (((x) & PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK) >> PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB) #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_SET(x) (((0 | (x)) << PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB) & PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK) #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_RESET 0x0 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB 1 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MSB 1 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK 0x2 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_GET(x) (((x) & PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK) >> PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB) #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_SET(x) (((0 | (x)) << PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB) & PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK) #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_RESET 0x0 #define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB 0 #define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MSB 0 #define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK 0x1 #define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_GET(x) (((x) & PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK) >> PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB) #define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_SET(x) (((0 | (x)) << PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB) & PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK) #define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_RESET 0x0 #define PHY_BB_CHANNEL_STATUS_ADDRESS (0x16c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHANNEL_STATUS_RSTMASK 0x1fffff #define PHY_BB_CHANNEL_STATUS_RESET 0x0 // 0x170 (PHY_BB_CHANINFO_CTRL) #define PHY_BB_CHANINFO_CTRL_RTT_RXSM_DELAY_ENABLE_LSB 31 #define PHY_BB_CHANINFO_CTRL_RTT_RXSM_DELAY_ENABLE_MSB 31 #define PHY_BB_CHANINFO_CTRL_RTT_RXSM_DELAY_ENABLE_MASK 0x80000000 #define PHY_BB_CHANINFO_CTRL_RTT_RXSM_DELAY_ENABLE_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_RTT_RXSM_DELAY_ENABLE_MASK) >> PHY_BB_CHANINFO_CTRL_RTT_RXSM_DELAY_ENABLE_LSB) #define PHY_BB_CHANINFO_CTRL_RTT_RXSM_DELAY_ENABLE_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_RTT_RXSM_DELAY_ENABLE_LSB) & PHY_BB_CHANINFO_CTRL_RTT_RXSM_DELAY_ENABLE_MASK) #define PHY_BB_CHANINFO_CTRL_RTT_RXSM_DELAY_ENABLE_RESET 0x0 #define PHY_BB_CHANINFO_CTRL_RTT_MU_FILT_ENABLE_LSB 30 #define PHY_BB_CHANINFO_CTRL_RTT_MU_FILT_ENABLE_MSB 30 #define PHY_BB_CHANINFO_CTRL_RTT_MU_FILT_ENABLE_MASK 0x40000000 #define PHY_BB_CHANINFO_CTRL_RTT_MU_FILT_ENABLE_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_RTT_MU_FILT_ENABLE_MASK) >> PHY_BB_CHANINFO_CTRL_RTT_MU_FILT_ENABLE_LSB) #define PHY_BB_CHANINFO_CTRL_RTT_MU_FILT_ENABLE_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_RTT_MU_FILT_ENABLE_LSB) & PHY_BB_CHANINFO_CTRL_RTT_MU_FILT_ENABLE_MASK) #define PHY_BB_CHANINFO_CTRL_RTT_MU_FILT_ENABLE_RESET 0x1 #define PHY_BB_CHANINFO_CTRL_RTT_MIMO_STBC_FILT_ENABLE_LSB 29 #define PHY_BB_CHANINFO_CTRL_RTT_MIMO_STBC_FILT_ENABLE_MSB 29 #define PHY_BB_CHANINFO_CTRL_RTT_MIMO_STBC_FILT_ENABLE_MASK 0x20000000 #define PHY_BB_CHANINFO_CTRL_RTT_MIMO_STBC_FILT_ENABLE_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_RTT_MIMO_STBC_FILT_ENABLE_MASK) >> PHY_BB_CHANINFO_CTRL_RTT_MIMO_STBC_FILT_ENABLE_LSB) #define PHY_BB_CHANINFO_CTRL_RTT_MIMO_STBC_FILT_ENABLE_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_RTT_MIMO_STBC_FILT_ENABLE_LSB) & PHY_BB_CHANINFO_CTRL_RTT_MIMO_STBC_FILT_ENABLE_MASK) #define PHY_BB_CHANINFO_CTRL_RTT_MIMO_STBC_FILT_ENABLE_RESET 0x1 #define PHY_BB_CHANINFO_CTRL_RTT_ITP_CNT_RX_BEGIN_DATA_LSB 25 #define PHY_BB_CHANINFO_CTRL_RTT_ITP_CNT_RX_BEGIN_DATA_MSB 28 #define PHY_BB_CHANINFO_CTRL_RTT_ITP_CNT_RX_BEGIN_DATA_MASK 0x1e000000 #define PHY_BB_CHANINFO_CTRL_RTT_ITP_CNT_RX_BEGIN_DATA_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_RTT_ITP_CNT_RX_BEGIN_DATA_MASK) >> PHY_BB_CHANINFO_CTRL_RTT_ITP_CNT_RX_BEGIN_DATA_LSB) #define PHY_BB_CHANINFO_CTRL_RTT_ITP_CNT_RX_BEGIN_DATA_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_RTT_ITP_CNT_RX_BEGIN_DATA_LSB) & PHY_BB_CHANINFO_CTRL_RTT_ITP_CNT_RX_BEGIN_DATA_MASK) #define PHY_BB_CHANINFO_CTRL_RTT_ITP_CNT_RX_BEGIN_DATA_RESET 0x0 #define PHY_BB_CHANINFO_CTRL_AGC_STR_CHAIN_RTT_LSB 23 #define PHY_BB_CHANINFO_CTRL_AGC_STR_CHAIN_RTT_MSB 24 #define PHY_BB_CHANINFO_CTRL_AGC_STR_CHAIN_RTT_MASK 0x1800000 #define PHY_BB_CHANINFO_CTRL_AGC_STR_CHAIN_RTT_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_AGC_STR_CHAIN_RTT_MASK) >> PHY_BB_CHANINFO_CTRL_AGC_STR_CHAIN_RTT_LSB) #define PHY_BB_CHANINFO_CTRL_AGC_STR_CHAIN_RTT_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_AGC_STR_CHAIN_RTT_LSB) & PHY_BB_CHANINFO_CTRL_AGC_STR_CHAIN_RTT_MASK) #define PHY_BB_CHANINFO_CTRL_AGC_STR_CHAIN_RTT_RESET 0x0 #define PHY_BB_CHANINFO_CTRL_RTT_POST_CHAN_MASK_EN_LSB 22 #define PHY_BB_CHANINFO_CTRL_RTT_POST_CHAN_MASK_EN_MSB 22 #define PHY_BB_CHANINFO_CTRL_RTT_POST_CHAN_MASK_EN_MASK 0x400000 #define PHY_BB_CHANINFO_CTRL_RTT_POST_CHAN_MASK_EN_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_RTT_POST_CHAN_MASK_EN_MASK) >> PHY_BB_CHANINFO_CTRL_RTT_POST_CHAN_MASK_EN_LSB) #define PHY_BB_CHANINFO_CTRL_RTT_POST_CHAN_MASK_EN_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_RTT_POST_CHAN_MASK_EN_LSB) & PHY_BB_CHANINFO_CTRL_RTT_POST_CHAN_MASK_EN_MASK) #define PHY_BB_CHANINFO_CTRL_RTT_POST_CHAN_MASK_EN_RESET 0x1 #define PHY_BB_CHANINFO_CTRL_RTT_DET_THR_LSB 17 #define PHY_BB_CHANINFO_CTRL_RTT_DET_THR_MSB 21 #define PHY_BB_CHANINFO_CTRL_RTT_DET_THR_MASK 0x3e0000 #define PHY_BB_CHANINFO_CTRL_RTT_DET_THR_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_RTT_DET_THR_MASK) >> PHY_BB_CHANINFO_CTRL_RTT_DET_THR_LSB) #define PHY_BB_CHANINFO_CTRL_RTT_DET_THR_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_RTT_DET_THR_LSB) & PHY_BB_CHANINFO_CTRL_RTT_DET_THR_MASK) #define PHY_BB_CHANINFO_CTRL_RTT_DET_THR_RESET 0x9 #define PHY_BB_CHANINFO_CTRL_RTT_SRCH_WINDOW_LSB 9 #define PHY_BB_CHANINFO_CTRL_RTT_SRCH_WINDOW_MSB 16 #define PHY_BB_CHANINFO_CTRL_RTT_SRCH_WINDOW_MASK 0x1fe00 #define PHY_BB_CHANINFO_CTRL_RTT_SRCH_WINDOW_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_RTT_SRCH_WINDOW_MASK) >> PHY_BB_CHANINFO_CTRL_RTT_SRCH_WINDOW_LSB) #define PHY_BB_CHANINFO_CTRL_RTT_SRCH_WINDOW_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_RTT_SRCH_WINDOW_LSB) & PHY_BB_CHANINFO_CTRL_RTT_SRCH_WINDOW_MASK) #define PHY_BB_CHANINFO_CTRL_RTT_SRCH_WINDOW_RESET 0x14 #define PHY_BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_LSB 8 #define PHY_BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_MSB 8 #define PHY_BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_MASK 0x100 #define PHY_BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_MASK) >> PHY_BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_LSB) #define PHY_BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_LSB) & PHY_BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_MASK) #define PHY_BB_CHANINFO_CTRL_RTT_HARDWARE_IFFT_RESET 0x1 #define PHY_BB_CHANINFO_CTRL_RTT_ENABLE_CCH_ROT_LSB 7 #define PHY_BB_CHANINFO_CTRL_RTT_ENABLE_CCH_ROT_MSB 7 #define PHY_BB_CHANINFO_CTRL_RTT_ENABLE_CCH_ROT_MASK 0x80 #define PHY_BB_CHANINFO_CTRL_RTT_ENABLE_CCH_ROT_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_RTT_ENABLE_CCH_ROT_MASK) >> PHY_BB_CHANINFO_CTRL_RTT_ENABLE_CCH_ROT_LSB) #define PHY_BB_CHANINFO_CTRL_RTT_ENABLE_CCH_ROT_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_RTT_ENABLE_CCH_ROT_LSB) & PHY_BB_CHANINFO_CTRL_RTT_ENABLE_CCH_ROT_MASK) #define PHY_BB_CHANINFO_CTRL_RTT_ENABLE_CCH_ROT_RESET 0x0 #define PHY_BB_CHANINFO_CTRL_RTT_MAC_PHY_PHASE_LSB 6 #define PHY_BB_CHANINFO_CTRL_RTT_MAC_PHY_PHASE_MSB 6 #define PHY_BB_CHANINFO_CTRL_RTT_MAC_PHY_PHASE_MASK 0x40 #define PHY_BB_CHANINFO_CTRL_RTT_MAC_PHY_PHASE_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_RTT_MAC_PHY_PHASE_MASK) >> PHY_BB_CHANINFO_CTRL_RTT_MAC_PHY_PHASE_LSB) #define PHY_BB_CHANINFO_CTRL_RTT_MAC_PHY_PHASE_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_RTT_MAC_PHY_PHASE_LSB) & PHY_BB_CHANINFO_CTRL_RTT_MAC_PHY_PHASE_MASK) #define PHY_BB_CHANINFO_CTRL_RTT_MAC_PHY_PHASE_RESET 0x0 #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_BW_LSB 4 #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_BW_MSB 5 #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_BW_MASK 0x30 #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_BW_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_CHANINFOMEM_BW_MASK) >> PHY_BB_CHANINFO_CTRL_CHANINFOMEM_BW_LSB) #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_BW_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_CHANINFOMEM_BW_LSB) & PHY_BB_CHANINFO_CTRL_CHANINFOMEM_BW_MASK) #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_BW_RESET 0x0 #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_LSB 3 #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_MSB 3 #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_MASK 0x8 #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_MASK) >> PHY_BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_LSB) #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_LSB) & PHY_BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_MASK) #define PHY_BB_CHANINFO_CTRL_CHANINFOMEM_S2_READ_RESET 0x0 #define PHY_BB_CHANINFO_CTRL_CAPTURE_SOUNDING_PACKET_LSB 2 #define PHY_BB_CHANINFO_CTRL_CAPTURE_SOUNDING_PACKET_MSB 2 #define PHY_BB_CHANINFO_CTRL_CAPTURE_SOUNDING_PACKET_MASK 0x4 #define PHY_BB_CHANINFO_CTRL_CAPTURE_SOUNDING_PACKET_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_CAPTURE_SOUNDING_PACKET_MASK) >> PHY_BB_CHANINFO_CTRL_CAPTURE_SOUNDING_PACKET_LSB) #define PHY_BB_CHANINFO_CTRL_CAPTURE_SOUNDING_PACKET_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_CAPTURE_SOUNDING_PACKET_LSB) & PHY_BB_CHANINFO_CTRL_CAPTURE_SOUNDING_PACKET_MASK) #define PHY_BB_CHANINFO_CTRL_CAPTURE_SOUNDING_PACKET_RESET 0x0 #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB 1 #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MSB 1 #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK 0x2 #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK) >> PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB) #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB) & PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK) #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_RESET 0x0 #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB 0 #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MSB 0 #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK 0x1 #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_GET(x) (((x) & PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK) >> PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB) #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_SET(x) (((0 | (x)) << PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB) & PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK) #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_RESET 0x0 #define PHY_BB_CHANINFO_CTRL_ADDRESS (0x170 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHANINFO_CTRL_RSTMASK 0xffffffff #define PHY_BB_CHANINFO_CTRL_RESET 0x60522900 // 0x174 (PHY_BB_CHAN_INFO_NOISE_PWR_B0) #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_Q_0_LSB 20 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_Q_0_MSB 27 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_Q_0_MASK 0xff00000 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_Q_0_GET(x) (((x) & PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_Q_0_MASK) >> PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_Q_0_LSB) #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_Q_0_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_Q_0_LSB) & PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_Q_0_MASK) #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_Q_0_RESET 0x0 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_I_0_LSB 12 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_I_0_MSB 19 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_I_0_MASK 0xff000 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_I_0_GET(x) (((x) & PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_I_0_MASK) >> PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_I_0_LSB) #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_I_0_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_I_0_LSB) & PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_I_0_MASK) #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_CHAN_INFO_FINE_DC_I_0_RESET 0x0 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_NOISE_POWER_LSB 0 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_NOISE_POWER_MSB 11 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_NOISE_POWER_MASK 0xfff #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_NOISE_POWER_GET(x) (((x) & PHY_BB_CHAN_INFO_NOISE_PWR_B0_NOISE_POWER_MASK) >> PHY_BB_CHAN_INFO_NOISE_PWR_B0_NOISE_POWER_LSB) #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_NOISE_POWER_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_NOISE_PWR_B0_NOISE_POWER_LSB) & PHY_BB_CHAN_INFO_NOISE_PWR_B0_NOISE_POWER_MASK) #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_NOISE_POWER_RESET 0x0 #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_ADDRESS (0x174 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_RSTMASK 0xfffffff #define PHY_BB_CHAN_INFO_NOISE_PWR_B0_RESET 0x0 // 0x178 (PHY_BB_CHAN_INFO_GAIN_DIFF) #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_03_LSB 14 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_03_MSB 20 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_03_MASK 0x1fc000 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_03_GET(x) (((x) & PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_03_MASK) >> PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_03_LSB) #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_03_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_03_LSB) & PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_03_MASK) #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_03_RESET 0x0 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_02_LSB 7 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_02_MSB 13 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_02_MASK 0x3f80 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_02_GET(x) (((x) & PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_02_MASK) >> PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_02_LSB) #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_02_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_02_LSB) & PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_02_MASK) #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_02_RESET 0x0 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_01_LSB 0 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_01_MSB 6 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_01_MASK 0x7f #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_01_GET(x) (((x) & PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_01_MASK) >> PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_01_LSB) #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_01_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_01_LSB) & PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_01_MASK) #define PHY_BB_CHAN_INFO_GAIN_DIFF_ANALOG_GAIN_DIFF_01_RESET 0x0 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ADDRESS (0x178 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHAN_INFO_GAIN_DIFF_RSTMASK 0x1fffff #define PHY_BB_CHAN_INFO_GAIN_DIFF_RESET 0x0 // 0x17c (PHY_BB_CHAN_INFO_FINE_TIMING) #define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB 12 #define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MSB 21 #define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK 0x3ff000 #define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_GET(x) (((x) & PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK) >> PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB) #define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB) & PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK) #define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_RESET 0x0 #define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB 0 #define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MSB 11 #define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK 0xfff #define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_GET(x) (((x) & PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK) >> PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB) #define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB) & PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK) #define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_RESET 0x0 #define PHY_BB_CHAN_INFO_FINE_TIMING_ADDRESS (0x17c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHAN_INFO_FINE_TIMING_RSTMASK 0x3fffff #define PHY_BB_CHAN_INFO_FINE_TIMING_RESET 0x0 // 0x180 (PHY_BB_CHAN_INFO_GAIN_B0) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB 24 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MSB 24 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK 0x1000000 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_GET(x) (((x) & PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK) >> PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB) & PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_RESET 0x0 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB 23 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MSB 23 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK 0x800000 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_GET(x) (((x) & PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK) >> PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB) & PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_RESET 0x0 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_MB_GAIN_0_LSB 16 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_MB_GAIN_0_MSB 22 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_MB_GAIN_0_MASK 0x7f0000 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_MB_GAIN_0_GET(x) (((x) & PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_MB_GAIN_0_MASK) >> PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_MB_GAIN_0_LSB) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_MB_GAIN_0_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_MB_GAIN_0_LSB) & PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_MB_GAIN_0_MASK) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_MB_GAIN_0_RESET 0x0 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB 8 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MSB 15 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK 0xff00 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_GET(x) (((x) & PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK) >> PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB) & PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_RESET 0x0 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB 0 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MSB 7 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK 0xff #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_GET(x) (((x) & PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK) >> PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB) & PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK) #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_RESET 0x0 #define PHY_BB_CHAN_INFO_GAIN_B0_ADDRESS (0x180 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHAN_INFO_GAIN_B0_RSTMASK 0x1ffffff #define PHY_BB_CHAN_INFO_GAIN_B0_RESET 0x0 // 0x184 (PHY_BB_RTT_CORR_VALUE) #define PHY_BB_RTT_CORR_VALUE_RTT_TM_RX_RXCLR_PHASE_LSB 31 #define PHY_BB_RTT_CORR_VALUE_RTT_TM_RX_RXCLR_PHASE_MSB 31 #define PHY_BB_RTT_CORR_VALUE_RTT_TM_RX_RXCLR_PHASE_MASK 0x80000000 #define PHY_BB_RTT_CORR_VALUE_RTT_TM_RX_RXCLR_PHASE_GET(x) (((x) & PHY_BB_RTT_CORR_VALUE_RTT_TM_RX_RXCLR_PHASE_MASK) >> PHY_BB_RTT_CORR_VALUE_RTT_TM_RX_RXCLR_PHASE_LSB) #define PHY_BB_RTT_CORR_VALUE_RTT_TM_RX_RXCLR_PHASE_SET(x) (((0 | (x)) << PHY_BB_RTT_CORR_VALUE_RTT_TM_RX_RXCLR_PHASE_LSB) & PHY_BB_RTT_CORR_VALUE_RTT_TM_RX_RXCLR_PHASE_MASK) #define PHY_BB_RTT_CORR_VALUE_RTT_TM_RX_RXCLR_PHASE_RESET 0x0 #define PHY_BB_RTT_CORR_VALUE_RTT_TX_DATA_START_X_PHASE_LSB 30 #define PHY_BB_RTT_CORR_VALUE_RTT_TX_DATA_START_X_PHASE_MSB 30 #define PHY_BB_RTT_CORR_VALUE_RTT_TX_DATA_START_X_PHASE_MASK 0x40000000 #define PHY_BB_RTT_CORR_VALUE_RTT_TX_DATA_START_X_PHASE_GET(x) (((x) & PHY_BB_RTT_CORR_VALUE_RTT_TX_DATA_START_X_PHASE_MASK) >> PHY_BB_RTT_CORR_VALUE_RTT_TX_DATA_START_X_PHASE_LSB) #define PHY_BB_RTT_CORR_VALUE_RTT_TX_DATA_START_X_PHASE_SET(x) (((0 | (x)) << PHY_BB_RTT_CORR_VALUE_RTT_TX_DATA_START_X_PHASE_LSB) & PHY_BB_RTT_CORR_VALUE_RTT_TX_DATA_START_X_PHASE_MASK) #define PHY_BB_RTT_CORR_VALUE_RTT_TX_DATA_START_X_PHASE_RESET 0x0 #define PHY_BB_RTT_CORR_VALUE_RTT_CFR_READY_LSB 29 #define PHY_BB_RTT_CORR_VALUE_RTT_CFR_READY_MSB 29 #define PHY_BB_RTT_CORR_VALUE_RTT_CFR_READY_MASK 0x20000000 #define PHY_BB_RTT_CORR_VALUE_RTT_CFR_READY_GET(x) (((x) & PHY_BB_RTT_CORR_VALUE_RTT_CFR_READY_MASK) >> PHY_BB_RTT_CORR_VALUE_RTT_CFR_READY_LSB) #define PHY_BB_RTT_CORR_VALUE_RTT_CFR_READY_SET(x) (((0 | (x)) << PHY_BB_RTT_CORR_VALUE_RTT_CFR_READY_LSB) & PHY_BB_RTT_CORR_VALUE_RTT_CFR_READY_MASK) #define PHY_BB_RTT_CORR_VALUE_RTT_CFR_READY_RESET 0x0 #define PHY_BB_RTT_CORR_VALUE_RTT_CIR_READY_LSB 28 #define PHY_BB_RTT_CORR_VALUE_RTT_CIR_READY_MSB 28 #define PHY_BB_RTT_CORR_VALUE_RTT_CIR_READY_MASK 0x10000000 #define PHY_BB_RTT_CORR_VALUE_RTT_CIR_READY_GET(x) (((x) & PHY_BB_RTT_CORR_VALUE_RTT_CIR_READY_MASK) >> PHY_BB_RTT_CORR_VALUE_RTT_CIR_READY_LSB) #define PHY_BB_RTT_CORR_VALUE_RTT_CIR_READY_SET(x) (((0 | (x)) << PHY_BB_RTT_CORR_VALUE_RTT_CIR_READY_LSB) & PHY_BB_RTT_CORR_VALUE_RTT_CIR_READY_MASK) #define PHY_BB_RTT_CORR_VALUE_RTT_CIR_READY_RESET 0x0 #define PHY_BB_RTT_CORR_VALUE_RTT_FAC_STATUS_LSB 26 #define PHY_BB_RTT_CORR_VALUE_RTT_FAC_STATUS_MSB 27 #define PHY_BB_RTT_CORR_VALUE_RTT_FAC_STATUS_MASK 0xc000000 #define PHY_BB_RTT_CORR_VALUE_RTT_FAC_STATUS_GET(x) (((x) & PHY_BB_RTT_CORR_VALUE_RTT_FAC_STATUS_MASK) >> PHY_BB_RTT_CORR_VALUE_RTT_FAC_STATUS_LSB) #define PHY_BB_RTT_CORR_VALUE_RTT_FAC_STATUS_SET(x) (((0 | (x)) << PHY_BB_RTT_CORR_VALUE_RTT_FAC_STATUS_LSB) & PHY_BB_RTT_CORR_VALUE_RTT_FAC_STATUS_MASK) #define PHY_BB_RTT_CORR_VALUE_RTT_FAC_STATUS_RESET 0x0 #define PHY_BB_RTT_CORR_VALUE_RTT_ASYNC_FIFO_PHASE_LSB 21 #define PHY_BB_RTT_CORR_VALUE_RTT_ASYNC_FIFO_PHASE_MSB 25 #define PHY_BB_RTT_CORR_VALUE_RTT_ASYNC_FIFO_PHASE_MASK 0x3e00000 #define PHY_BB_RTT_CORR_VALUE_RTT_ASYNC_FIFO_PHASE_GET(x) (((x) & PHY_BB_RTT_CORR_VALUE_RTT_ASYNC_FIFO_PHASE_MASK) >> PHY_BB_RTT_CORR_VALUE_RTT_ASYNC_FIFO_PHASE_LSB) #define PHY_BB_RTT_CORR_VALUE_RTT_ASYNC_FIFO_PHASE_SET(x) (((0 | (x)) << PHY_BB_RTT_CORR_VALUE_RTT_ASYNC_FIFO_PHASE_LSB) & PHY_BB_RTT_CORR_VALUE_RTT_ASYNC_FIFO_PHASE_MASK) #define PHY_BB_RTT_CORR_VALUE_RTT_ASYNC_FIFO_PHASE_RESET 0x0 #define PHY_BB_RTT_CORR_VALUE_RTT_TX_FRAME_PHASE_LSB 17 #define PHY_BB_RTT_CORR_VALUE_RTT_TX_FRAME_PHASE_MSB 20 #define PHY_BB_RTT_CORR_VALUE_RTT_TX_FRAME_PHASE_MASK 0x1e0000 #define PHY_BB_RTT_CORR_VALUE_RTT_TX_FRAME_PHASE_GET(x) (((x) & PHY_BB_RTT_CORR_VALUE_RTT_TX_FRAME_PHASE_MASK) >> PHY_BB_RTT_CORR_VALUE_RTT_TX_FRAME_PHASE_LSB) #define PHY_BB_RTT_CORR_VALUE_RTT_TX_FRAME_PHASE_SET(x) (((0 | (x)) << PHY_BB_RTT_CORR_VALUE_RTT_TX_FRAME_PHASE_LSB) & PHY_BB_RTT_CORR_VALUE_RTT_TX_FRAME_PHASE_MASK) #define PHY_BB_RTT_CORR_VALUE_RTT_TX_FRAME_PHASE_RESET 0x0 #define PHY_BB_RTT_CORR_VALUE_RTT_CORR_VALUE_LSB 0 #define PHY_BB_RTT_CORR_VALUE_RTT_CORR_VALUE_MSB 16 #define PHY_BB_RTT_CORR_VALUE_RTT_CORR_VALUE_MASK 0x1ffff #define PHY_BB_RTT_CORR_VALUE_RTT_CORR_VALUE_GET(x) (((x) & PHY_BB_RTT_CORR_VALUE_RTT_CORR_VALUE_MASK) >> PHY_BB_RTT_CORR_VALUE_RTT_CORR_VALUE_LSB) #define PHY_BB_RTT_CORR_VALUE_RTT_CORR_VALUE_SET(x) (((0 | (x)) << PHY_BB_RTT_CORR_VALUE_RTT_CORR_VALUE_LSB) & PHY_BB_RTT_CORR_VALUE_RTT_CORR_VALUE_MASK) #define PHY_BB_RTT_CORR_VALUE_RTT_CORR_VALUE_RESET 0x0 #define PHY_BB_RTT_CORR_VALUE_ADDRESS (0x184 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RTT_CORR_VALUE_RSTMASK 0xffffffff #define PHY_BB_RTT_CORR_VALUE_RESET 0x0 // 0x188 (PHY_BB_NF_DCOFF_B0) #define PHY_BB_NF_DCOFF_B0_DC_OFF_Q_0_LSB 8 #define PHY_BB_NF_DCOFF_B0_DC_OFF_Q_0_MSB 15 #define PHY_BB_NF_DCOFF_B0_DC_OFF_Q_0_MASK 0xff00 #define PHY_BB_NF_DCOFF_B0_DC_OFF_Q_0_GET(x) (((x) & PHY_BB_NF_DCOFF_B0_DC_OFF_Q_0_MASK) >> PHY_BB_NF_DCOFF_B0_DC_OFF_Q_0_LSB) #define PHY_BB_NF_DCOFF_B0_DC_OFF_Q_0_SET(x) (((0 | (x)) << PHY_BB_NF_DCOFF_B0_DC_OFF_Q_0_LSB) & PHY_BB_NF_DCOFF_B0_DC_OFF_Q_0_MASK) #define PHY_BB_NF_DCOFF_B0_DC_OFF_Q_0_RESET 0x0 #define PHY_BB_NF_DCOFF_B0_DC_OFF_I_0_LSB 0 #define PHY_BB_NF_DCOFF_B0_DC_OFF_I_0_MSB 7 #define PHY_BB_NF_DCOFF_B0_DC_OFF_I_0_MASK 0xff #define PHY_BB_NF_DCOFF_B0_DC_OFF_I_0_GET(x) (((x) & PHY_BB_NF_DCOFF_B0_DC_OFF_I_0_MASK) >> PHY_BB_NF_DCOFF_B0_DC_OFF_I_0_LSB) #define PHY_BB_NF_DCOFF_B0_DC_OFF_I_0_SET(x) (((0 | (x)) << PHY_BB_NF_DCOFF_B0_DC_OFF_I_0_LSB) & PHY_BB_NF_DCOFF_B0_DC_OFF_I_0_MASK) #define PHY_BB_NF_DCOFF_B0_DC_OFF_I_0_RESET 0x0 #define PHY_BB_NF_DCOFF_B0_ADDRESS (0x188 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_NF_DCOFF_B0_RSTMASK 0xffff #define PHY_BB_NF_DCOFF_B0_RESET 0x0 // 0x18c (PHY_BB_CHAN_INFO_FINE_PPM) #define PHY_BB_CHAN_INFO_FINE_PPM_FINE_PPM_LSB 0 #define PHY_BB_CHAN_INFO_FINE_PPM_FINE_PPM_MSB 11 #define PHY_BB_CHAN_INFO_FINE_PPM_FINE_PPM_MASK 0xfff #define PHY_BB_CHAN_INFO_FINE_PPM_FINE_PPM_GET(x) (((x) & PHY_BB_CHAN_INFO_FINE_PPM_FINE_PPM_MASK) >> PHY_BB_CHAN_INFO_FINE_PPM_FINE_PPM_LSB) #define PHY_BB_CHAN_INFO_FINE_PPM_FINE_PPM_SET(x) (((0 | (x)) << PHY_BB_CHAN_INFO_FINE_PPM_FINE_PPM_LSB) & PHY_BB_CHAN_INFO_FINE_PPM_FINE_PPM_MASK) #define PHY_BB_CHAN_INFO_FINE_PPM_FINE_PPM_RESET 0x0 #define PHY_BB_CHAN_INFO_FINE_PPM_ADDRESS (0x18c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CHAN_INFO_FINE_PPM_RSTMASK 0xfff #define PHY_BB_CHAN_INFO_FINE_PPM_RESET 0x0 // 0x190 (PHY_BB_SCRAMBLER_SEED) #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB 0 #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MSB 6 #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK 0x7f #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_GET(x) (((x) & PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK) >> PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB) #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_SET(x) (((0 | (x)) << PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB) & PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK) #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_RESET 0x0 #define PHY_BB_SCRAMBLER_SEED_ADDRESS (0x190 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_SCRAMBLER_SEED_RSTMASK 0x7f #define PHY_BB_SCRAMBLER_SEED_RESET 0x0 // 0x194 (PHY_BB_BBB_TX_CTRL) #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_3_LSB 12 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_3_MSB 14 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_3_MASK 0x7000 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_3_GET(x) (((x) & PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_3_MASK) >> PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_3_LSB) #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_3_SET(x) (((0 | (x)) << PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_3_LSB) & PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_3_MASK) #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_3_RESET 0x0 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB 9 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MSB 11 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK 0xe00 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_GET(x) (((x) & PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK) >> PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB) #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_SET(x) (((0 | (x)) << PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB) & PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK) #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_RESET 0x0 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB 6 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MSB 8 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK 0x1c0 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_GET(x) (((x) & PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK) >> PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB) #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_SET(x) (((0 | (x)) << PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB) & PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK) #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_RESET 0x0 #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB 5 #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MSB 5 #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK 0x20 #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_GET(x) (((x) & PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK) >> PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB) #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_SET(x) (((0 | (x)) << PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB) & PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK) #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_RESET 0x0 #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB 4 #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MSB 4 #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK 0x10 #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_GET(x) (((x) & PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK) >> PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB) #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_SET(x) (((0 | (x)) << PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB) & PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK) #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_RESET 0x0 #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB 2 #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MSB 3 #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK 0xc #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_GET(x) (((x) & PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK) >> PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB) #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_SET(x) (((0 | (x)) << PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB) & PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK) #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_RESET 0x0 #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB 1 #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MSB 1 #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK 0x2 #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_GET(x) (((x) & PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK) >> PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB) #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_SET(x) (((0 | (x)) << PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB) & PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK) #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_RESET 0x0 #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB 0 #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MSB 0 #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK 0x1 #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_GET(x) (((x) & PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK) >> PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB) #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_SET(x) (((0 | (x)) << PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB) & PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK) #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_RESET 0x0 #define PHY_BB_BBB_TX_CTRL_ADDRESS (0x194 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_BBB_TX_CTRL_RSTMASK 0x7fff #define PHY_BB_BBB_TX_CTRL_RESET 0x0 // 0x198 (PHY_BB_BBB_TXFIR_0) #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB 24 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MSB 28 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK 0x1f000000 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_GET(x) (((x) & PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK) >> PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB) #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB) & PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK) #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_RESET 0x0 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB 16 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MSB 20 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK 0x1f0000 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_GET(x) (((x) & PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK) >> PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB) #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB) & PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK) #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_RESET 0x0 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB 8 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MSB 11 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK 0xf00 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_GET(x) (((x) & PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK) >> PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB) #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB) & PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK) #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_RESET 0x0 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB 0 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MSB 3 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK 0xf #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_GET(x) (((x) & PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK) >> PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB) #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB) & PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK) #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_RESET 0x0 #define PHY_BB_BBB_TXFIR_0_ADDRESS (0x198 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_BBB_TXFIR_0_RSTMASK 0x1f1f0f0f #define PHY_BB_BBB_TXFIR_0_RESET 0x0 // 0x19c (PHY_BB_BBB_TXFIR_1) #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB 24 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MSB 30 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK 0x7f000000 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_GET(x) (((x) & PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK) >> PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB) #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB) & PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK) #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_RESET 0x0 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB 16 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MSB 22 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK 0x7f0000 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_GET(x) (((x) & PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK) >> PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB) #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB) & PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK) #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_RESET 0x0 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB 8 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MSB 13 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK 0x3f00 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_GET(x) (((x) & PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK) >> PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB) #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB) & PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK) #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_RESET 0x0 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB 0 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MSB 5 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK 0x3f #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_GET(x) (((x) & PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK) >> PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB) #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB) & PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK) #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_RESET 0x0 #define PHY_BB_BBB_TXFIR_1_ADDRESS (0x19c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_BBB_TXFIR_1_RSTMASK 0x7f7f3f3f #define PHY_BB_BBB_TXFIR_1_RESET 0x0 // 0x1a0 (PHY_BB_BBB_TXFIR_2) #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB 24 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MSB 31 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK 0xff000000 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_GET(x) (((x) & PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK) >> PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB) #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB) & PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK) #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_RESET 0x0 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB 16 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MSB 23 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK 0xff0000 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_GET(x) (((x) & PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK) >> PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB) #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB) & PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK) #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_RESET 0x0 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB 8 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MSB 15 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK 0xff00 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_GET(x) (((x) & PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK) >> PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB) #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB) & PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK) #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_RESET 0x0 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB 0 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MSB 7 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK 0xff #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_GET(x) (((x) & PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK) >> PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB) #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_SET(x) (((0 | (x)) << PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB) & PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK) #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_RESET 0x0 #define PHY_BB_BBB_TXFIR_2_ADDRESS (0x1a0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_BBB_TXFIR_2_RSTMASK 0xffffffff #define PHY_BB_BBB_TXFIR_2_RESET 0x0 // 0x1a4 (PHY_BB_HEAVY_CLIP_0) #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM3_LSB 24 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM3_MSB 31 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM3_MASK 0xff000000 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM3_GET(x) (((x) & PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM3_MASK) >> PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM3_LSB) #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM3_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM3_LSB) & PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM3_MASK) #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM3_RESET 0x0 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM2_LSB 16 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM2_MSB 23 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM2_MASK 0xff0000 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM2_GET(x) (((x) & PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM2_MASK) >> PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM2_LSB) #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM2_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM2_LSB) & PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM2_MASK) #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM2_RESET 0x0 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM1_LSB 8 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM1_MSB 15 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM1_MASK 0xff00 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM1_GET(x) (((x) & PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM1_MASK) >> PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM1_LSB) #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM1_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM1_LSB) & PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM1_MASK) #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM1_RESET 0x0 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM0_LSB 0 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM0_MSB 7 #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM0_MASK 0xff #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM0_GET(x) (((x) & PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM0_MASK) >> PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM0_LSB) #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM0_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM0_LSB) & PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM0_MASK) #define PHY_BB_HEAVY_CLIP_0_HEAVY_CLIP_FACTOR_QAM0_RESET 0x0 #define PHY_BB_HEAVY_CLIP_0_ADDRESS (0x1a4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_HEAVY_CLIP_0_RSTMASK 0xffffffff #define PHY_BB_HEAVY_CLIP_0_RESET 0x0 // 0x1a8 (PHY_BB_HEAVY_CLIP_1) #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM7_LSB 24 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM7_MSB 31 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM7_MASK 0xff000000 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM7_GET(x) (((x) & PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM7_MASK) >> PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM7_LSB) #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM7_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM7_LSB) & PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM7_MASK) #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM7_RESET 0x0 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM6_LSB 16 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM6_MSB 23 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM6_MASK 0xff0000 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM6_GET(x) (((x) & PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM6_MASK) >> PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM6_LSB) #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM6_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM6_LSB) & PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM6_MASK) #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM6_RESET 0x0 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM5_LSB 8 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM5_MSB 15 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM5_MASK 0xff00 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM5_GET(x) (((x) & PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM5_MASK) >> PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM5_LSB) #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM5_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM5_LSB) & PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM5_MASK) #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM5_RESET 0x0 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM4_LSB 0 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM4_MSB 7 #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM4_MASK 0xff #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM4_GET(x) (((x) & PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM4_MASK) >> PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM4_LSB) #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM4_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM4_LSB) & PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM4_MASK) #define PHY_BB_HEAVY_CLIP_1_HEAVY_CLIP_FACTOR_QAM4_RESET 0x0 #define PHY_BB_HEAVY_CLIP_1_ADDRESS (0x1a8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_HEAVY_CLIP_1_RSTMASK 0xffffffff #define PHY_BB_HEAVY_CLIP_1_RESET 0x0 // 0x1ac (PHY_BB_HEAVY_CLIP_2) #define PHY_BB_HEAVY_CLIP_2_USE_PRE_EMP_LSB 26 #define PHY_BB_HEAVY_CLIP_2_USE_PRE_EMP_MSB 26 #define PHY_BB_HEAVY_CLIP_2_USE_PRE_EMP_MASK 0x4000000 #define PHY_BB_HEAVY_CLIP_2_USE_PRE_EMP_GET(x) (((x) & PHY_BB_HEAVY_CLIP_2_USE_PRE_EMP_MASK) >> PHY_BB_HEAVY_CLIP_2_USE_PRE_EMP_LSB) #define PHY_BB_HEAVY_CLIP_2_USE_PRE_EMP_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_2_USE_PRE_EMP_LSB) & PHY_BB_HEAVY_CLIP_2_USE_PRE_EMP_MASK) #define PHY_BB_HEAVY_CLIP_2_USE_PRE_EMP_RESET 0x1 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_ENABLE_LSB 16 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_ENABLE_MSB 25 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_ENABLE_MASK 0x3ff0000 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_ENABLE_GET(x) (((x) & PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_ENABLE_MASK) >> PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_ENABLE_LSB) #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_ENABLE_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_ENABLE_LSB) & PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_ENABLE_MASK) #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_ENABLE_RESET 0x0 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM9_LSB 8 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM9_MSB 15 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM9_MASK 0xff00 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM9_GET(x) (((x) & PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM9_MASK) >> PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM9_LSB) #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM9_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM9_LSB) & PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM9_MASK) #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM9_RESET 0x0 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM8_LSB 0 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM8_MSB 7 #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM8_MASK 0xff #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM8_GET(x) (((x) & PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM8_MASK) >> PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM8_LSB) #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM8_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM8_LSB) & PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM8_MASK) #define PHY_BB_HEAVY_CLIP_2_HEAVY_CLIP_FACTOR_QAM8_RESET 0x0 #define PHY_BB_HEAVY_CLIP_2_ADDRESS (0x1ac + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_HEAVY_CLIP_2_RSTMASK 0x7ffffff #define PHY_BB_HEAVY_CLIP_2_RESET 0x4000000 // 0x1b0 (PHY_BB_HEAVY_CLIP_3) #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_2_LSB 16 #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_2_MSB 23 #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_2_MASK 0xff0000 #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_2_GET(x) (((x) & PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_2_MASK) >> PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_2_LSB) #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_2_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_2_LSB) & PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_2_MASK) #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_2_RESET 0x0 #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_1_LSB 8 #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_1_MSB 14 #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_1_MASK 0x7f00 #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_1_GET(x) (((x) & PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_1_MASK) >> PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_1_LSB) #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_1_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_1_LSB) & PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_1_MASK) #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_1_RESET 0x0 #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_0_LSB 0 #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_0_MSB 6 #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_0_MASK 0x7f #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_0_GET(x) (((x) & PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_0_MASK) >> PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_0_LSB) #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_0_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_0_LSB) & PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_0_MASK) #define PHY_BB_HEAVY_CLIP_3_HEAVY_CLIP_COE_0_RESET 0x0 #define PHY_BB_HEAVY_CLIP_3_ADDRESS (0x1b0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_HEAVY_CLIP_3_RSTMASK 0xff7f7f #define PHY_BB_HEAVY_CLIP_3_RESET 0x0 // 0x1b4 (PHY_BB_SM_HIST_0) #define PHY_BB_SM_HIST_0_SM_REC_MAC_TRIG_LSB 23 #define PHY_BB_SM_HIST_0_SM_REC_MAC_TRIG_MSB 25 #define PHY_BB_SM_HIST_0_SM_REC_MAC_TRIG_MASK 0x3800000 #define PHY_BB_SM_HIST_0_SM_REC_MAC_TRIG_GET(x) (((x) & PHY_BB_SM_HIST_0_SM_REC_MAC_TRIG_MASK) >> PHY_BB_SM_HIST_0_SM_REC_MAC_TRIG_LSB) #define PHY_BB_SM_HIST_0_SM_REC_MAC_TRIG_SET(x) (((0 | (x)) << PHY_BB_SM_HIST_0_SM_REC_MAC_TRIG_LSB) & PHY_BB_SM_HIST_0_SM_REC_MAC_TRIG_MASK) #define PHY_BB_SM_HIST_0_SM_REC_MAC_TRIG_RESET 0x0 #define PHY_BB_SM_HIST_0_SM_REC_AGC_SEL_LSB 22 #define PHY_BB_SM_HIST_0_SM_REC_AGC_SEL_MSB 22 #define PHY_BB_SM_HIST_0_SM_REC_AGC_SEL_MASK 0x400000 #define PHY_BB_SM_HIST_0_SM_REC_AGC_SEL_GET(x) (((x) & PHY_BB_SM_HIST_0_SM_REC_AGC_SEL_MASK) >> PHY_BB_SM_HIST_0_SM_REC_AGC_SEL_LSB) #define PHY_BB_SM_HIST_0_SM_REC_AGC_SEL_SET(x) (((0 | (x)) << PHY_BB_SM_HIST_0_SM_REC_AGC_SEL_LSB) & PHY_BB_SM_HIST_0_SM_REC_AGC_SEL_MASK) #define PHY_BB_SM_HIST_0_SM_REC_AGC_SEL_RESET 0x0 #define PHY_BB_SM_HIST_0_SM_REC_DATA_NUM_LSB 18 #define PHY_BB_SM_HIST_0_SM_REC_DATA_NUM_MSB 21 #define PHY_BB_SM_HIST_0_SM_REC_DATA_NUM_MASK 0x3c0000 #define PHY_BB_SM_HIST_0_SM_REC_DATA_NUM_GET(x) (((x) & PHY_BB_SM_HIST_0_SM_REC_DATA_NUM_MASK) >> PHY_BB_SM_HIST_0_SM_REC_DATA_NUM_LSB) #define PHY_BB_SM_HIST_0_SM_REC_DATA_NUM_SET(x) (((0 | (x)) << PHY_BB_SM_HIST_0_SM_REC_DATA_NUM_LSB) & PHY_BB_SM_HIST_0_SM_REC_DATA_NUM_MASK) #define PHY_BB_SM_HIST_0_SM_REC_DATA_NUM_RESET 0x8 #define PHY_BB_SM_HIST_0_SM_REC_CHN_EN_LSB 14 #define PHY_BB_SM_HIST_0_SM_REC_CHN_EN_MSB 17 #define PHY_BB_SM_HIST_0_SM_REC_CHN_EN_MASK 0x3c000 #define PHY_BB_SM_HIST_0_SM_REC_CHN_EN_GET(x) (((x) & PHY_BB_SM_HIST_0_SM_REC_CHN_EN_MASK) >> PHY_BB_SM_HIST_0_SM_REC_CHN_EN_LSB) #define PHY_BB_SM_HIST_0_SM_REC_CHN_EN_SET(x) (((0 | (x)) << PHY_BB_SM_HIST_0_SM_REC_CHN_EN_LSB) & PHY_BB_SM_HIST_0_SM_REC_CHN_EN_MASK) #define PHY_BB_SM_HIST_0_SM_REC_CHN_EN_RESET 0x1 #define PHY_BB_SM_HIST_0_SM_REC_PART_EN_LSB 4 #define PHY_BB_SM_HIST_0_SM_REC_PART_EN_MSB 13 #define PHY_BB_SM_HIST_0_SM_REC_PART_EN_MASK 0x3ff0 #define PHY_BB_SM_HIST_0_SM_REC_PART_EN_GET(x) (((x) & PHY_BB_SM_HIST_0_SM_REC_PART_EN_MASK) >> PHY_BB_SM_HIST_0_SM_REC_PART_EN_LSB) #define PHY_BB_SM_HIST_0_SM_REC_PART_EN_SET(x) (((0 | (x)) << PHY_BB_SM_HIST_0_SM_REC_PART_EN_LSB) & PHY_BB_SM_HIST_0_SM_REC_PART_EN_MASK) #define PHY_BB_SM_HIST_0_SM_REC_PART_EN_RESET 0x7f #define PHY_BB_SM_HIST_0_SM_REC_TIME_RES_LSB 2 #define PHY_BB_SM_HIST_0_SM_REC_TIME_RES_MSB 3 #define PHY_BB_SM_HIST_0_SM_REC_TIME_RES_MASK 0xc #define PHY_BB_SM_HIST_0_SM_REC_TIME_RES_GET(x) (((x) & PHY_BB_SM_HIST_0_SM_REC_TIME_RES_MASK) >> PHY_BB_SM_HIST_0_SM_REC_TIME_RES_LSB) #define PHY_BB_SM_HIST_0_SM_REC_TIME_RES_SET(x) (((0 | (x)) << PHY_BB_SM_HIST_0_SM_REC_TIME_RES_LSB) & PHY_BB_SM_HIST_0_SM_REC_TIME_RES_MASK) #define PHY_BB_SM_HIST_0_SM_REC_TIME_RES_RESET 0x0 #define PHY_BB_SM_HIST_0_SM_REC_MODE_LSB 1 #define PHY_BB_SM_HIST_0_SM_REC_MODE_MSB 1 #define PHY_BB_SM_HIST_0_SM_REC_MODE_MASK 0x2 #define PHY_BB_SM_HIST_0_SM_REC_MODE_GET(x) (((x) & PHY_BB_SM_HIST_0_SM_REC_MODE_MASK) >> PHY_BB_SM_HIST_0_SM_REC_MODE_LSB) #define PHY_BB_SM_HIST_0_SM_REC_MODE_SET(x) (((0 | (x)) << PHY_BB_SM_HIST_0_SM_REC_MODE_LSB) & PHY_BB_SM_HIST_0_SM_REC_MODE_MASK) #define PHY_BB_SM_HIST_0_SM_REC_MODE_RESET 0x0 #define PHY_BB_SM_HIST_0_SM_REC_EN_LSB 0 #define PHY_BB_SM_HIST_0_SM_REC_EN_MSB 0 #define PHY_BB_SM_HIST_0_SM_REC_EN_MASK 0x1 #define PHY_BB_SM_HIST_0_SM_REC_EN_GET(x) (((x) & PHY_BB_SM_HIST_0_SM_REC_EN_MASK) >> PHY_BB_SM_HIST_0_SM_REC_EN_LSB) #define PHY_BB_SM_HIST_0_SM_REC_EN_SET(x) (((0 | (x)) << PHY_BB_SM_HIST_0_SM_REC_EN_LSB) & PHY_BB_SM_HIST_0_SM_REC_EN_MASK) #define PHY_BB_SM_HIST_0_SM_REC_EN_RESET 0x0 #define PHY_BB_SM_HIST_0_ADDRESS (0x1b4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_SM_HIST_0_RSTMASK 0x3ffffff #define PHY_BB_SM_HIST_0_RESET 0x2047f0 // 0x1b8 (PHY_BB_SM_HIST_1) #define PHY_BB_SM_HIST_1_SM_REC_LAST_ADDR_LSB 24 #define PHY_BB_SM_HIST_1_SM_REC_LAST_ADDR_MSB 31 #define PHY_BB_SM_HIST_1_SM_REC_LAST_ADDR_MASK 0xff000000 #define PHY_BB_SM_HIST_1_SM_REC_LAST_ADDR_GET(x) (((x) & PHY_BB_SM_HIST_1_SM_REC_LAST_ADDR_MASK) >> PHY_BB_SM_HIST_1_SM_REC_LAST_ADDR_LSB) #define PHY_BB_SM_HIST_1_SM_REC_LAST_ADDR_SET(x) (((0 | (x)) << PHY_BB_SM_HIST_1_SM_REC_LAST_ADDR_LSB) & PHY_BB_SM_HIST_1_SM_REC_LAST_ADDR_MASK) #define PHY_BB_SM_HIST_1_SM_REC_LAST_ADDR_RESET 0x0 #define PHY_BB_SM_HIST_1_SM_REC_SS_FORMAT_LSB 0 #define PHY_BB_SM_HIST_1_SM_REC_SS_FORMAT_MSB 1 #define PHY_BB_SM_HIST_1_SM_REC_SS_FORMAT_MASK 0x3 #define PHY_BB_SM_HIST_1_SM_REC_SS_FORMAT_GET(x) (((x) & PHY_BB_SM_HIST_1_SM_REC_SS_FORMAT_MASK) >> PHY_BB_SM_HIST_1_SM_REC_SS_FORMAT_LSB) #define PHY_BB_SM_HIST_1_SM_REC_SS_FORMAT_SET(x) (((0 | (x)) << PHY_BB_SM_HIST_1_SM_REC_SS_FORMAT_LSB) & PHY_BB_SM_HIST_1_SM_REC_SS_FORMAT_MASK) #define PHY_BB_SM_HIST_1_SM_REC_SS_FORMAT_RESET 0x0 #define PHY_BB_SM_HIST_1_ADDRESS (0x1b8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_SM_HIST_1_RSTMASK 0xff000003 #define PHY_BB_SM_HIST_1_RESET 0x0 // 0x1bc (PHY_BB_RTT_CNTL) #define PHY_BB_RTT_CNTL_RTT_DO_FAC_INTERP_LSB 3 #define PHY_BB_RTT_CNTL_RTT_DO_FAC_INTERP_MSB 3 #define PHY_BB_RTT_CNTL_RTT_DO_FAC_INTERP_MASK 0x8 #define PHY_BB_RTT_CNTL_RTT_DO_FAC_INTERP_GET(x) (((x) & PHY_BB_RTT_CNTL_RTT_DO_FAC_INTERP_MASK) >> PHY_BB_RTT_CNTL_RTT_DO_FAC_INTERP_LSB) #define PHY_BB_RTT_CNTL_RTT_DO_FAC_INTERP_SET(x) (((0 | (x)) << PHY_BB_RTT_CNTL_RTT_DO_FAC_INTERP_LSB) & PHY_BB_RTT_CNTL_RTT_DO_FAC_INTERP_MASK) #define PHY_BB_RTT_CNTL_RTT_DO_FAC_INTERP_RESET 0x0 #define PHY_BB_RTT_CNTL_CF_RX_ERR_RST_RTT_LSB 2 #define PHY_BB_RTT_CNTL_CF_RX_ERR_RST_RTT_MSB 2 #define PHY_BB_RTT_CNTL_CF_RX_ERR_RST_RTT_MASK 0x4 #define PHY_BB_RTT_CNTL_CF_RX_ERR_RST_RTT_GET(x) (((x) & PHY_BB_RTT_CNTL_CF_RX_ERR_RST_RTT_MASK) >> PHY_BB_RTT_CNTL_CF_RX_ERR_RST_RTT_LSB) #define PHY_BB_RTT_CNTL_CF_RX_ERR_RST_RTT_SET(x) (((0 | (x)) << PHY_BB_RTT_CNTL_CF_RX_ERR_RST_RTT_LSB) & PHY_BB_RTT_CNTL_CF_RX_ERR_RST_RTT_MASK) #define PHY_BB_RTT_CNTL_CF_RX_ERR_RST_RTT_RESET 0x0 #define PHY_BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_LSB 1 #define PHY_BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_MSB 1 #define PHY_BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_MASK 0x2 #define PHY_BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_GET(x) (((x) & PHY_BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_MASK) >> PHY_BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_LSB) #define PHY_BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_SET(x) (((0 | (x)) << PHY_BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_LSB) & PHY_BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_MASK) #define PHY_BB_RTT_CNTL_RTT_VHT_BEAMFORM_FILT_ENABLE_RESET 0x0 #define PHY_BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_LSB 0 #define PHY_BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_MSB 0 #define PHY_BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_MASK 0x1 #define PHY_BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_GET(x) (((x) & PHY_BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_MASK) >> PHY_BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_LSB) #define PHY_BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_SET(x) (((0 | (x)) << PHY_BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_LSB) & PHY_BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_MASK) #define PHY_BB_RTT_CNTL_RTT_HT_BEAMFORM_FILT_ENABLE_RESET 0x0 #define PHY_BB_RTT_CNTL_ADDRESS (0x1bc + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RTT_CNTL_RSTMASK 0xf #define PHY_BB_RTT_CNTL_RESET 0x0 // 0x1c0 (PHY_BB_HEAVY_CLIP_4) #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM3_LSB 24 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM3_MSB 31 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM3_MASK 0xff000000 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM3_GET(x) (((x) & PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM3_MASK) >> PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM3_LSB) #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM3_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM3_LSB) & PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM3_MASK) #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM3_RESET 0x0 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM2_LSB 16 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM2_MSB 23 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM2_MASK 0xff0000 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM2_GET(x) (((x) & PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM2_MASK) >> PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM2_LSB) #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM2_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM2_LSB) & PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM2_MASK) #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM2_RESET 0x0 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM1_LSB 8 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM1_MSB 15 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM1_MASK 0xff00 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM1_GET(x) (((x) & PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM1_MASK) >> PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM1_LSB) #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM1_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM1_LSB) & PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM1_MASK) #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM1_RESET 0x0 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM0_LSB 0 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM0_MSB 7 #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM0_MASK 0xff #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM0_GET(x) (((x) & PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM0_MASK) >> PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM0_LSB) #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM0_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM0_LSB) & PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM0_MASK) #define PHY_BB_HEAVY_CLIP_4_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM0_RESET 0x0 #define PHY_BB_HEAVY_CLIP_4_ADDRESS (0x1c0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_HEAVY_CLIP_4_RSTMASK 0xffffffff #define PHY_BB_HEAVY_CLIP_4_RESET 0x0 // 0x1c4 (PHY_BB_HEAVY_CLIP_5) #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM6_LSB 16 #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM6_MSB 23 #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM6_MASK 0xff0000 #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM6_GET(x) (((x) & PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM6_MASK) >> PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM6_LSB) #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM6_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM6_LSB) & PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM6_MASK) #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM6_RESET 0x0 #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM5_LSB 8 #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM5_MSB 15 #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM5_MASK 0xff00 #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM5_GET(x) (((x) & PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM5_MASK) >> PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM5_LSB) #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM5_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM5_LSB) & PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM5_MASK) #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM5_RESET 0x0 #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM4_LSB 0 #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM4_MSB 7 #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM4_MASK 0xff #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM4_GET(x) (((x) & PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM4_MASK) >> PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM4_LSB) #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM4_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM4_LSB) & PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM4_MASK) #define PHY_BB_HEAVY_CLIP_5_HEAVY_CLIP_FACTOR_NONHTDUP40_QAM4_RESET 0x0 #define PHY_BB_HEAVY_CLIP_5_ADDRESS (0x1c4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_HEAVY_CLIP_5_RSTMASK 0xffffff #define PHY_BB_HEAVY_CLIP_5_RESET 0x0 // 0x1c8 (PHY_BB_HEAVY_CLIP_6) #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM3_LSB 24 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM3_MSB 31 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM3_MASK 0xff000000 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM3_GET(x) (((x) & PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM3_MASK) >> PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM3_LSB) #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM3_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM3_LSB) & PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM3_MASK) #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM3_RESET 0x0 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM2_LSB 16 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM2_MSB 23 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM2_MASK 0xff0000 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM2_GET(x) (((x) & PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM2_MASK) >> PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM2_LSB) #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM2_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM2_LSB) & PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM2_MASK) #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM2_RESET 0x0 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM1_LSB 8 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM1_MSB 15 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM1_MASK 0xff00 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM1_GET(x) (((x) & PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM1_MASK) >> PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM1_LSB) #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM1_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM1_LSB) & PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM1_MASK) #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM1_RESET 0x0 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM0_LSB 0 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM0_MSB 7 #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM0_MASK 0xff #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM0_GET(x) (((x) & PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM0_MASK) >> PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM0_LSB) #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM0_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM0_LSB) & PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM0_MASK) #define PHY_BB_HEAVY_CLIP_6_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM0_RESET 0x0 #define PHY_BB_HEAVY_CLIP_6_ADDRESS (0x1c8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_HEAVY_CLIP_6_RSTMASK 0xffffffff #define PHY_BB_HEAVY_CLIP_6_RESET 0x0 // 0x1cc (PHY_BB_HEAVY_CLIP_7) #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM6_LSB 16 #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM6_MSB 23 #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM6_MASK 0xff0000 #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM6_GET(x) (((x) & PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM6_MASK) >> PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM6_LSB) #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM6_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM6_LSB) & PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM6_MASK) #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM6_RESET 0x0 #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM5_LSB 8 #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM5_MSB 15 #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM5_MASK 0xff00 #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM5_GET(x) (((x) & PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM5_MASK) >> PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM5_LSB) #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM5_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM5_LSB) & PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM5_MASK) #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM5_RESET 0x0 #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM4_LSB 0 #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM4_MSB 7 #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM4_MASK 0xff #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM4_GET(x) (((x) & PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM4_MASK) >> PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM4_LSB) #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM4_SET(x) (((0 | (x)) << PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM4_LSB) & PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM4_MASK) #define PHY_BB_HEAVY_CLIP_7_HEAVY_CLIP_FACTOR_NONHTDUP80_QAM4_RESET 0x0 #define PHY_BB_HEAVY_CLIP_7_ADDRESS (0x1cc + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_HEAVY_CLIP_7_RSTMASK 0xffffff #define PHY_BB_HEAVY_CLIP_7_RESET 0x0 // 0x1d0 (PHY_BB_RTT_PBD_STAT) #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_VLD_LSB 2 #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_VLD_MSB 2 #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_VLD_MASK 0x4 #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_VLD_GET(x) (((x) & PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_VLD_MASK) >> PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_VLD_LSB) #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_VLD_SET(x) (((0 | (x)) << PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_VLD_LSB) & PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_VLD_MASK) #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_VLD_RESET 0x0 #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_LSB 0 #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_MSB 1 #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_MASK 0x3 #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_GET(x) (((x) & PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_MASK) >> PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_LSB) #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_SET(x) (((0 | (x)) << PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_LSB) & PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_MASK) #define PHY_BB_RTT_PBD_STAT_RTT_LEG_BW_RESET 0x0 #define PHY_BB_RTT_PBD_STAT_ADDRESS (0x1d0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RTT_PBD_STAT_RSTMASK 0x7 #define PHY_BB_RTT_PBD_STAT_RESET 0x0 // 0x1f0 (PHY_BB_POWERTX_MAX_SUB) #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_3CHAIN_LSB 14 #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_3CHAIN_MSB 19 #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_3CHAIN_MASK 0xfc000 #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_3CHAIN_GET(x) (((x) & PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_3CHAIN_MASK) >> PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_3CHAIN_LSB) #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_3CHAIN_SET(x) (((0 | (x)) << PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_3CHAIN_LSB) & PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_3CHAIN_MASK) #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_3CHAIN_RESET 0x9 #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB 8 #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_2CHAIN_MSB 13 #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK 0x3f00 #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_2CHAIN_GET(x) (((x) & PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK) >> PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB) #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_2CHAIN_SET(x) (((0 | (x)) << PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB) & PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK) #define PHY_BB_POWERTX_MAX_SUB_POWERTX_SUB_FOR_2CHAIN_RESET 0x6 #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ_LSB 7 #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ_MSB 7 #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ_MASK 0x80 #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ_GET(x) (((x) & PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ_MASK) >> PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ_LSB) #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ_SET(x) (((0 | (x)) << PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ_LSB) & PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ_MASK) #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ_RESET 0x0 #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_POWERTX_MAX_LSB 6 #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_POWERTX_MAX_MSB 6 #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_POWERTX_MAX_MASK 0x40 #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_POWERTX_MAX_GET(x) (((x) & PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_POWERTX_MAX_MASK) >> PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_POWERTX_MAX_LSB) #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_POWERTX_MAX_SET(x) (((0 | (x)) << PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_POWERTX_MAX_LSB) & PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_POWERTX_MAX_MASK) #define PHY_BB_POWERTX_MAX_SUB_USE_PER_PACKET_POWERTX_MAX_RESET 0x0 #define PHY_BB_POWERTX_MAX_SUB_ADDRESS (0x1f0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_POWERTX_MAX_SUB_RSTMASK 0xfffc0 #define PHY_BB_POWERTX_MAX_SUB_RESET 0x24600 // 0x1f8 (PHY_BB_TPC_1) #define PHY_BB_TPC_1_PWR_MEAS_TRIG_SW_LSB 31 #define PHY_BB_TPC_1_PWR_MEAS_TRIG_SW_MSB 31 #define PHY_BB_TPC_1_PWR_MEAS_TRIG_SW_MASK 0x80000000 #define PHY_BB_TPC_1_PWR_MEAS_TRIG_SW_GET(x) (((x) & PHY_BB_TPC_1_PWR_MEAS_TRIG_SW_MASK) >> PHY_BB_TPC_1_PWR_MEAS_TRIG_SW_LSB) #define PHY_BB_TPC_1_PWR_MEAS_TRIG_SW_SET(x) (((0 | (x)) << PHY_BB_TPC_1_PWR_MEAS_TRIG_SW_LSB) & PHY_BB_TPC_1_PWR_MEAS_TRIG_SW_MASK) #define PHY_BB_TPC_1_PWR_MEAS_TRIG_SW_RESET 0x0 #define PHY_BB_TPC_1_CLPC_ERR_UPDATE_DIS_LSB 30 #define PHY_BB_TPC_1_CLPC_ERR_UPDATE_DIS_MSB 30 #define PHY_BB_TPC_1_CLPC_ERR_UPDATE_DIS_MASK 0x40000000 #define PHY_BB_TPC_1_CLPC_ERR_UPDATE_DIS_GET(x) (((x) & PHY_BB_TPC_1_CLPC_ERR_UPDATE_DIS_MASK) >> PHY_BB_TPC_1_CLPC_ERR_UPDATE_DIS_LSB) #define PHY_BB_TPC_1_CLPC_ERR_UPDATE_DIS_SET(x) (((0 | (x)) << PHY_BB_TPC_1_CLPC_ERR_UPDATE_DIS_LSB) & PHY_BB_TPC_1_CLPC_ERR_UPDATE_DIS_MASK) #define PHY_BB_TPC_1_CLPC_ERR_UPDATE_DIS_RESET 0x0 #define PHY_BB_TPC_1_ATB_MEAS_DUR_LSB 27 #define PHY_BB_TPC_1_ATB_MEAS_DUR_MSB 29 #define PHY_BB_TPC_1_ATB_MEAS_DUR_MASK 0x38000000 #define PHY_BB_TPC_1_ATB_MEAS_DUR_GET(x) (((x) & PHY_BB_TPC_1_ATB_MEAS_DUR_MASK) >> PHY_BB_TPC_1_ATB_MEAS_DUR_LSB) #define PHY_BB_TPC_1_ATB_MEAS_DUR_SET(x) (((0 | (x)) << PHY_BB_TPC_1_ATB_MEAS_DUR_LSB) & PHY_BB_TPC_1_ATB_MEAS_DUR_MASK) #define PHY_BB_TPC_1_ATB_MEAS_DUR_RESET 0x7 #define PHY_BB_TPC_1_THERM_MEAS_DUR_LSB 24 #define PHY_BB_TPC_1_THERM_MEAS_DUR_MSB 26 #define PHY_BB_TPC_1_THERM_MEAS_DUR_MASK 0x7000000 #define PHY_BB_TPC_1_THERM_MEAS_DUR_GET(x) (((x) & PHY_BB_TPC_1_THERM_MEAS_DUR_MASK) >> PHY_BB_TPC_1_THERM_MEAS_DUR_LSB) #define PHY_BB_TPC_1_THERM_MEAS_DUR_SET(x) (((0 | (x)) << PHY_BB_TPC_1_THERM_MEAS_DUR_LSB) & PHY_BB_TPC_1_THERM_MEAS_DUR_MASK) #define PHY_BB_TPC_1_THERM_MEAS_DUR_RESET 0x7 #define PHY_BB_TPC_1_VOLT_MEAS_DUR_LSB 21 #define PHY_BB_TPC_1_VOLT_MEAS_DUR_MSB 23 #define PHY_BB_TPC_1_VOLT_MEAS_DUR_MASK 0xe00000 #define PHY_BB_TPC_1_VOLT_MEAS_DUR_GET(x) (((x) & PHY_BB_TPC_1_VOLT_MEAS_DUR_MASK) >> PHY_BB_TPC_1_VOLT_MEAS_DUR_LSB) #define PHY_BB_TPC_1_VOLT_MEAS_DUR_SET(x) (((0 | (x)) << PHY_BB_TPC_1_VOLT_MEAS_DUR_LSB) & PHY_BB_TPC_1_VOLT_MEAS_DUR_MASK) #define PHY_BB_TPC_1_VOLT_MEAS_DUR_RESET 0x7 #define PHY_BB_TPC_1_ATB_INI_DUR_LSB 18 #define PHY_BB_TPC_1_ATB_INI_DUR_MSB 20 #define PHY_BB_TPC_1_ATB_INI_DUR_MASK 0x1c0000 #define PHY_BB_TPC_1_ATB_INI_DUR_GET(x) (((x) & PHY_BB_TPC_1_ATB_INI_DUR_MASK) >> PHY_BB_TPC_1_ATB_INI_DUR_LSB) #define PHY_BB_TPC_1_ATB_INI_DUR_SET(x) (((0 | (x)) << PHY_BB_TPC_1_ATB_INI_DUR_LSB) & PHY_BB_TPC_1_ATB_INI_DUR_MASK) #define PHY_BB_TPC_1_ATB_INI_DUR_RESET 0x1 #define PHY_BB_TPC_1_THERM_INI_DUR_LSB 15 #define PHY_BB_TPC_1_THERM_INI_DUR_MSB 17 #define PHY_BB_TPC_1_THERM_INI_DUR_MASK 0x38000 #define PHY_BB_TPC_1_THERM_INI_DUR_GET(x) (((x) & PHY_BB_TPC_1_THERM_INI_DUR_MASK) >> PHY_BB_TPC_1_THERM_INI_DUR_LSB) #define PHY_BB_TPC_1_THERM_INI_DUR_SET(x) (((0 | (x)) << PHY_BB_TPC_1_THERM_INI_DUR_LSB) & PHY_BB_TPC_1_THERM_INI_DUR_MASK) #define PHY_BB_TPC_1_THERM_INI_DUR_RESET 0x1 #define PHY_BB_TPC_1_VOLT_INI_DUR_LSB 12 #define PHY_BB_TPC_1_VOLT_INI_DUR_MSB 14 #define PHY_BB_TPC_1_VOLT_INI_DUR_MASK 0x7000 #define PHY_BB_TPC_1_VOLT_INI_DUR_GET(x) (((x) & PHY_BB_TPC_1_VOLT_INI_DUR_MASK) >> PHY_BB_TPC_1_VOLT_INI_DUR_LSB) #define PHY_BB_TPC_1_VOLT_INI_DUR_SET(x) (((0 | (x)) << PHY_BB_TPC_1_VOLT_INI_DUR_LSB) & PHY_BB_TPC_1_VOLT_INI_DUR_MASK) #define PHY_BB_TPC_1_VOLT_INI_DUR_RESET 0x1 #define PHY_BB_TPC_1_PD_DC_SEL_LSB 11 #define PHY_BB_TPC_1_PD_DC_SEL_MSB 11 #define PHY_BB_TPC_1_PD_DC_SEL_MASK 0x800 #define PHY_BB_TPC_1_PD_DC_SEL_GET(x) (((x) & PHY_BB_TPC_1_PD_DC_SEL_MASK) >> PHY_BB_TPC_1_PD_DC_SEL_LSB) #define PHY_BB_TPC_1_PD_DC_SEL_SET(x) (((0 | (x)) << PHY_BB_TPC_1_PD_DC_SEL_LSB) & PHY_BB_TPC_1_PD_DC_SEL_MASK) #define PHY_BB_TPC_1_PD_DC_SEL_RESET 0x0 #define PHY_BB_TPC_1_PD_DC_WIN_LSB 8 #define PHY_BB_TPC_1_PD_DC_WIN_MSB 10 #define PHY_BB_TPC_1_PD_DC_WIN_MASK 0x700 #define PHY_BB_TPC_1_PD_DC_WIN_GET(x) (((x) & PHY_BB_TPC_1_PD_DC_WIN_MASK) >> PHY_BB_TPC_1_PD_DC_WIN_LSB) #define PHY_BB_TPC_1_PD_DC_WIN_SET(x) (((0 | (x)) << PHY_BB_TPC_1_PD_DC_WIN_LSB) & PHY_BB_TPC_1_PD_DC_WIN_MASK) #define PHY_BB_TPC_1_PD_DC_WIN_RESET 0x0 #define PHY_BB_TPC_1_PD_DC_START_LSB 0 #define PHY_BB_TPC_1_PD_DC_START_MSB 7 #define PHY_BB_TPC_1_PD_DC_START_MASK 0xff #define PHY_BB_TPC_1_PD_DC_START_GET(x) (((x) & PHY_BB_TPC_1_PD_DC_START_MASK) >> PHY_BB_TPC_1_PD_DC_START_LSB) #define PHY_BB_TPC_1_PD_DC_START_SET(x) (((0 | (x)) << PHY_BB_TPC_1_PD_DC_START_LSB) & PHY_BB_TPC_1_PD_DC_START_MASK) #define PHY_BB_TPC_1_PD_DC_START_RESET 0xa #define PHY_BB_TPC_1_ADDRESS (0x1f8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_1_RSTMASK 0xffffffff #define PHY_BB_TPC_1_RESET 0x3fe4900a // 0x1fc (PHY_BB_TPC_2) #define PHY_BB_TPC_2_PDADC_STROBE_INV_LSB 31 #define PHY_BB_TPC_2_PDADC_STROBE_INV_MSB 31 #define PHY_BB_TPC_2_PDADC_STROBE_INV_MASK 0x80000000 #define PHY_BB_TPC_2_PDADC_STROBE_INV_GET(x) (((x) & PHY_BB_TPC_2_PDADC_STROBE_INV_MASK) >> PHY_BB_TPC_2_PDADC_STROBE_INV_LSB) #define PHY_BB_TPC_2_PDADC_STROBE_INV_SET(x) (((0 | (x)) << PHY_BB_TPC_2_PDADC_STROBE_INV_LSB) & PHY_BB_TPC_2_PDADC_STROBE_INV_MASK) #define PHY_BB_TPC_2_PDADC_STROBE_INV_RESET 0x0 #define PHY_BB_TPC_2_FORCED_TARGET_POWER_LSB 25 #define PHY_BB_TPC_2_FORCED_TARGET_POWER_MSB 30 #define PHY_BB_TPC_2_FORCED_TARGET_POWER_MASK 0x7e000000 #define PHY_BB_TPC_2_FORCED_TARGET_POWER_GET(x) (((x) & PHY_BB_TPC_2_FORCED_TARGET_POWER_MASK) >> PHY_BB_TPC_2_FORCED_TARGET_POWER_LSB) #define PHY_BB_TPC_2_FORCED_TARGET_POWER_SET(x) (((0 | (x)) << PHY_BB_TPC_2_FORCED_TARGET_POWER_LSB) & PHY_BB_TPC_2_FORCED_TARGET_POWER_MASK) #define PHY_BB_TPC_2_FORCED_TARGET_POWER_RESET 0x0 #define PHY_BB_TPC_2_USE_FORCED_TARGET_POWER_LSB 24 #define PHY_BB_TPC_2_USE_FORCED_TARGET_POWER_MSB 24 #define PHY_BB_TPC_2_USE_FORCED_TARGET_POWER_MASK 0x1000000 #define PHY_BB_TPC_2_USE_FORCED_TARGET_POWER_GET(x) (((x) & PHY_BB_TPC_2_USE_FORCED_TARGET_POWER_MASK) >> PHY_BB_TPC_2_USE_FORCED_TARGET_POWER_LSB) #define PHY_BB_TPC_2_USE_FORCED_TARGET_POWER_SET(x) (((0 | (x)) << PHY_BB_TPC_2_USE_FORCED_TARGET_POWER_LSB) & PHY_BB_TPC_2_USE_FORCED_TARGET_POWER_MASK) #define PHY_BB_TPC_2_USE_FORCED_TARGET_POWER_RESET 0x1 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB 16 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MSB 23 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK 0xff0000 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_GET(x) (((x) & PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK) >> PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB) #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_SET(x) (((0 | (x)) << PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB) & PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK) #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_RESET 0x0 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB 8 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MSB 15 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK 0xff00 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_GET(x) (((x) & PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK) >> PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB) #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_SET(x) (((0 | (x)) << PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB) & PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK) #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_RESET 0x0 #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB 0 #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MSB 7 #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK 0xff #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_GET(x) (((x) & PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK) >> PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB) #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_SET(x) (((0 | (x)) << PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB) & PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK) #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_RESET 0x0 #define PHY_BB_TPC_2_ADDRESS (0x1fc + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_2_RSTMASK 0xffffffff #define PHY_BB_TPC_2_RESET 0x1000000 // 0x200 (PHY_BB_TPC_3) #define PHY_BB_TPC_3_PDACC_MODE_LSB 30 #define PHY_BB_TPC_3_PDACC_MODE_MSB 30 #define PHY_BB_TPC_3_PDACC_MODE_MASK 0x40000000 #define PHY_BB_TPC_3_PDACC_MODE_GET(x) (((x) & PHY_BB_TPC_3_PDACC_MODE_MASK) >> PHY_BB_TPC_3_PDACC_MODE_LSB) #define PHY_BB_TPC_3_PDACC_MODE_SET(x) (((0 | (x)) << PHY_BB_TPC_3_PDACC_MODE_LSB) & PHY_BB_TPC_3_PDACC_MODE_MASK) #define PHY_BB_TPC_3_PDACC_MODE_RESET 0x0 #define PHY_BB_TPC_3_PDADC_STROBE_DLY_SEL_LSB 28 #define PHY_BB_TPC_3_PDADC_STROBE_DLY_SEL_MSB 29 #define PHY_BB_TPC_3_PDADC_STROBE_DLY_SEL_MASK 0x30000000 #define PHY_BB_TPC_3_PDADC_STROBE_DLY_SEL_GET(x) (((x) & PHY_BB_TPC_3_PDADC_STROBE_DLY_SEL_MASK) >> PHY_BB_TPC_3_PDADC_STROBE_DLY_SEL_LSB) #define PHY_BB_TPC_3_PDADC_STROBE_DLY_SEL_SET(x) (((0 | (x)) << PHY_BB_TPC_3_PDADC_STROBE_DLY_SEL_LSB) & PHY_BB_TPC_3_PDADC_STROBE_DLY_SEL_MASK) #define PHY_BB_TPC_3_PDADC_STROBE_DLY_SEL_RESET 0x0 #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB 27 #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MSB 27 #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK 0x8000000 #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_GET(x) (((x) & PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK) >> PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB) #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_SET(x) (((0 | (x)) << PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB) & PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK) #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_RESET 0x1 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB 24 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MSB 26 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK 0x7000000 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_GET(x) (((x) & PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK) >> PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB) #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_SET(x) (((0 | (x)) << PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB) & PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK) #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_RESET 0x0 #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB 21 #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MSB 23 #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK 0xe00000 #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_GET(x) (((x) & PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK) >> PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB) #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_SET(x) (((0 | (x)) << PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB) & PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK) #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_RESET 0x0 #define PHY_BB_TPC_3_THERM_GAIN_ERR_DB_MAX_LSB 16 #define PHY_BB_TPC_3_THERM_GAIN_ERR_DB_MAX_MSB 20 #define PHY_BB_TPC_3_THERM_GAIN_ERR_DB_MAX_MASK 0x1f0000 #define PHY_BB_TPC_3_THERM_GAIN_ERR_DB_MAX_GET(x) (((x) & PHY_BB_TPC_3_THERM_GAIN_ERR_DB_MAX_MASK) >> PHY_BB_TPC_3_THERM_GAIN_ERR_DB_MAX_LSB) #define PHY_BB_TPC_3_THERM_GAIN_ERR_DB_MAX_SET(x) (((0 | (x)) << PHY_BB_TPC_3_THERM_GAIN_ERR_DB_MAX_LSB) & PHY_BB_TPC_3_THERM_GAIN_ERR_DB_MAX_MASK) #define PHY_BB_TPC_3_THERM_GAIN_ERR_DB_MAX_RESET 0x0 #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB 8 #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MSB 15 #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK 0xff00 #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_GET(x) (((x) & PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK) >> PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB) #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_SET(x) (((0 | (x)) << PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB) & PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK) #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_RESET 0x0 #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB 0 #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MSB 7 #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK 0xff #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_GET(x) (((x) & PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK) >> PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB) #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_SET(x) (((0 | (x)) << PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB) & PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK) #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_RESET 0x0 #define PHY_BB_TPC_3_ADDRESS (0x200 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_3_RSTMASK 0x7fffffff #define PHY_BB_TPC_3_RESET 0x8000000 // 0x204 (PHY_BB_TPC_4_B0) #define PHY_BB_TPC_4_B0_PDADC_CLIP_2_CNT_0_LSB 8 #define PHY_BB_TPC_4_B0_PDADC_CLIP_2_CNT_0_MSB 15 #define PHY_BB_TPC_4_B0_PDADC_CLIP_2_CNT_0_MASK 0xff00 #define PHY_BB_TPC_4_B0_PDADC_CLIP_2_CNT_0_GET(x) (((x) & PHY_BB_TPC_4_B0_PDADC_CLIP_2_CNT_0_MASK) >> PHY_BB_TPC_4_B0_PDADC_CLIP_2_CNT_0_LSB) #define PHY_BB_TPC_4_B0_PDADC_CLIP_2_CNT_0_SET(x) (((0 | (x)) << PHY_BB_TPC_4_B0_PDADC_CLIP_2_CNT_0_LSB) & PHY_BB_TPC_4_B0_PDADC_CLIP_2_CNT_0_MASK) #define PHY_BB_TPC_4_B0_PDADC_CLIP_2_CNT_0_RESET 0x0 #define PHY_BB_TPC_4_B0_PDADC_CLIP_1_CNT_0_LSB 0 #define PHY_BB_TPC_4_B0_PDADC_CLIP_1_CNT_0_MSB 7 #define PHY_BB_TPC_4_B0_PDADC_CLIP_1_CNT_0_MASK 0xff #define PHY_BB_TPC_4_B0_PDADC_CLIP_1_CNT_0_GET(x) (((x) & PHY_BB_TPC_4_B0_PDADC_CLIP_1_CNT_0_MASK) >> PHY_BB_TPC_4_B0_PDADC_CLIP_1_CNT_0_LSB) #define PHY_BB_TPC_4_B0_PDADC_CLIP_1_CNT_0_SET(x) (((0 | (x)) << PHY_BB_TPC_4_B0_PDADC_CLIP_1_CNT_0_LSB) & PHY_BB_TPC_4_B0_PDADC_CLIP_1_CNT_0_MASK) #define PHY_BB_TPC_4_B0_PDADC_CLIP_1_CNT_0_RESET 0x0 #define PHY_BB_TPC_4_B0_ADDRESS (0x204 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_4_B0_RSTMASK 0xffff #define PHY_BB_TPC_4_B0_RESET 0x0 // 0x208 (PHY_BB_TPC_5) #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM3_LSB 21 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM3_MSB 27 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM3_MASK 0xfe00000 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM3_GET(x) (((x) & PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM3_MASK) >> PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM3_LSB) #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM3_SET(x) (((0 | (x)) << PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM3_LSB) & PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM3_MASK) #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM3_RESET 0x0 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM2_LSB 14 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM2_MSB 20 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM2_MASK 0x1fc000 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM2_GET(x) (((x) & PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM2_MASK) >> PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM2_LSB) #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM2_SET(x) (((0 | (x)) << PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM2_LSB) & PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM2_MASK) #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM2_RESET 0x0 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM1_LSB 7 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM1_MSB 13 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM1_MASK 0x3f80 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM1_GET(x) (((x) & PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM1_MASK) >> PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM1_LSB) #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM1_SET(x) (((0 | (x)) << PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM1_LSB) & PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM1_MASK) #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM1_RESET 0x0 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM0_LSB 0 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM0_MSB 6 #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM0_MASK 0x7f #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM0_GET(x) (((x) & PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM0_MASK) >> PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM0_LSB) #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM0_SET(x) (((0 | (x)) << PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM0_LSB) & PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM0_MASK) #define PHY_BB_TPC_5_HEAVY_CLIP_COMP_FACTOR_QAM0_RESET 0x0 #define PHY_BB_TPC_5_ADDRESS (0x208 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_5_RSTMASK 0xfffffff #define PHY_BB_TPC_5_RESET 0x0 // 0x20c (PHY_BB_TPC_6) #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM7_LSB 21 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM7_MSB 27 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM7_MASK 0xfe00000 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM7_GET(x) (((x) & PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM7_MASK) >> PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM7_LSB) #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM7_SET(x) (((0 | (x)) << PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM7_LSB) & PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM7_MASK) #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM7_RESET 0x0 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM6_LSB 14 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM6_MSB 20 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM6_MASK 0x1fc000 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM6_GET(x) (((x) & PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM6_MASK) >> PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM6_LSB) #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM6_SET(x) (((0 | (x)) << PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM6_LSB) & PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM6_MASK) #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM6_RESET 0x0 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM5_LSB 7 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM5_MSB 13 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM5_MASK 0x3f80 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM5_GET(x) (((x) & PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM5_MASK) >> PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM5_LSB) #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM5_SET(x) (((0 | (x)) << PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM5_LSB) & PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM5_MASK) #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM5_RESET 0x0 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM4_LSB 0 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM4_MSB 6 #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM4_MASK 0x7f #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM4_GET(x) (((x) & PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM4_MASK) >> PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM4_LSB) #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM4_SET(x) (((0 | (x)) << PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM4_LSB) & PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM4_MASK) #define PHY_BB_TPC_6_HEAVY_CLIP_COMP_FACTOR_QAM4_RESET 0x0 #define PHY_BB_TPC_6_ADDRESS (0x20c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_6_RSTMASK 0xfffffff #define PHY_BB_TPC_6_RESET 0x0 // 0x210 (PHY_BB_TPC_7) #define PHY_BB_TPC_7_MAX_GSET_IDX_LSB 25 #define PHY_BB_TPC_7_MAX_GSET_IDX_MSB 26 #define PHY_BB_TPC_7_MAX_GSET_IDX_MASK 0x6000000 #define PHY_BB_TPC_7_MAX_GSET_IDX_GET(x) (((x) & PHY_BB_TPC_7_MAX_GSET_IDX_MASK) >> PHY_BB_TPC_7_MAX_GSET_IDX_LSB) #define PHY_BB_TPC_7_MAX_GSET_IDX_SET(x) (((0 | (x)) << PHY_BB_TPC_7_MAX_GSET_IDX_LSB) & PHY_BB_TPC_7_MAX_GSET_IDX_MASK) #define PHY_BB_TPC_7_MAX_GSET_IDX_RESET 0x0 #define PHY_BB_TPC_7_CLPC_ATTN_EN_LSB 24 #define PHY_BB_TPC_7_CLPC_ATTN_EN_MSB 24 #define PHY_BB_TPC_7_CLPC_ATTN_EN_MASK 0x1000000 #define PHY_BB_TPC_7_CLPC_ATTN_EN_GET(x) (((x) & PHY_BB_TPC_7_CLPC_ATTN_EN_MASK) >> PHY_BB_TPC_7_CLPC_ATTN_EN_LSB) #define PHY_BB_TPC_7_CLPC_ATTN_EN_SET(x) (((0 | (x)) << PHY_BB_TPC_7_CLPC_ATTN_EN_LSB) & PHY_BB_TPC_7_CLPC_ATTN_EN_MASK) #define PHY_BB_TPC_7_CLPC_ATTN_EN_RESET 0x0 #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB 23 #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MSB 23 #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK 0x800000 #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_GET(x) (((x) & PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK) >> PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB) #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_SET(x) (((0 | (x)) << PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB) & PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK) #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_RESET 0x0 #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB 22 #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MSB 22 #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK 0x400000 #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_GET(x) (((x) & PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK) >> PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB) #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_SET(x) (((0 | (x)) << PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB) & PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK) #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_RESET 0x1 #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB 21 #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MSB 21 #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK 0x200000 #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_GET(x) (((x) & PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK) >> PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB) #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_SET(x) (((0 | (x)) << PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB) & PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK) #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_RESET 0x0 #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB 20 #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MSB 20 #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK 0x100000 #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_GET(x) (((x) & PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK) >> PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB) #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_SET(x) (((0 | (x)) << PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB) & PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK) #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_RESET 0x0 #define PHY_BB_TPC_7_ANA_SET_SEL_LSB 19 #define PHY_BB_TPC_7_ANA_SET_SEL_MSB 19 #define PHY_BB_TPC_7_ANA_SET_SEL_MASK 0x80000 #define PHY_BB_TPC_7_ANA_SET_SEL_GET(x) (((x) & PHY_BB_TPC_7_ANA_SET_SEL_MASK) >> PHY_BB_TPC_7_ANA_SET_SEL_LSB) #define PHY_BB_TPC_7_ANA_SET_SEL_SET(x) (((0 | (x)) << PHY_BB_TPC_7_ANA_SET_SEL_LSB) & PHY_BB_TPC_7_ANA_SET_SEL_MASK) #define PHY_BB_TPC_7_ANA_SET_SEL_RESET 0x0 #define PHY_BB_TPC_7_ANA_SET_LST_LSB 16 #define PHY_BB_TPC_7_ANA_SET_LST_MSB 18 #define PHY_BB_TPC_7_ANA_SET_LST_MASK 0x70000 #define PHY_BB_TPC_7_ANA_SET_LST_GET(x) (((x) & PHY_BB_TPC_7_ANA_SET_LST_MASK) >> PHY_BB_TPC_7_ANA_SET_LST_LSB) #define PHY_BB_TPC_7_ANA_SET_LST_SET(x) (((0 | (x)) << PHY_BB_TPC_7_ANA_SET_LST_LSB) & PHY_BB_TPC_7_ANA_SET_LST_MASK) #define PHY_BB_TPC_7_ANA_SET_LST_RESET 0x1 #define PHY_BB_TPC_7_ANA_SET_FST_LSB 13 #define PHY_BB_TPC_7_ANA_SET_FST_MSB 15 #define PHY_BB_TPC_7_ANA_SET_FST_MASK 0xe000 #define PHY_BB_TPC_7_ANA_SET_FST_GET(x) (((x) & PHY_BB_TPC_7_ANA_SET_FST_MASK) >> PHY_BB_TPC_7_ANA_SET_FST_LSB) #define PHY_BB_TPC_7_ANA_SET_FST_SET(x) (((0 | (x)) << PHY_BB_TPC_7_ANA_SET_FST_LSB) & PHY_BB_TPC_7_ANA_SET_FST_MASK) #define PHY_BB_TPC_7_ANA_SET_FST_RESET 0x0 #define PHY_BB_TPC_7_TRY_NXT_SET_LSB 12 #define PHY_BB_TPC_7_TRY_NXT_SET_MSB 12 #define PHY_BB_TPC_7_TRY_NXT_SET_MASK 0x1000 #define PHY_BB_TPC_7_TRY_NXT_SET_GET(x) (((x) & PHY_BB_TPC_7_TRY_NXT_SET_MASK) >> PHY_BB_TPC_7_TRY_NXT_SET_LSB) #define PHY_BB_TPC_7_TRY_NXT_SET_SET(x) (((0 | (x)) << PHY_BB_TPC_7_TRY_NXT_SET_LSB) & PHY_BB_TPC_7_TRY_NXT_SET_MASK) #define PHY_BB_TPC_7_TRY_NXT_SET_RESET 0x1 #define PHY_BB_TPC_7_GAIN_CALC_MODE_LSB 10 #define PHY_BB_TPC_7_GAIN_CALC_MODE_MSB 11 #define PHY_BB_TPC_7_GAIN_CALC_MODE_MASK 0xc00 #define PHY_BB_TPC_7_GAIN_CALC_MODE_GET(x) (((x) & PHY_BB_TPC_7_GAIN_CALC_MODE_MASK) >> PHY_BB_TPC_7_GAIN_CALC_MODE_LSB) #define PHY_BB_TPC_7_GAIN_CALC_MODE_SET(x) (((0 | (x)) << PHY_BB_TPC_7_GAIN_CALC_MODE_LSB) & PHY_BB_TPC_7_GAIN_CALC_MODE_MASK) #define PHY_BB_TPC_7_GAIN_CALC_MODE_RESET 0x1 #define PHY_BB_TPC_7_OLPC_MODE_LSB 9 #define PHY_BB_TPC_7_OLPC_MODE_MSB 9 #define PHY_BB_TPC_7_OLPC_MODE_MASK 0x200 #define PHY_BB_TPC_7_OLPC_MODE_GET(x) (((x) & PHY_BB_TPC_7_OLPC_MODE_MASK) >> PHY_BB_TPC_7_OLPC_MODE_LSB) #define PHY_BB_TPC_7_OLPC_MODE_SET(x) (((0 | (x)) << PHY_BB_TPC_7_OLPC_MODE_LSB) & PHY_BB_TPC_7_OLPC_MODE_MASK) #define PHY_BB_TPC_7_OLPC_MODE_RESET 0x0 #define PHY_BB_TPC_7_FORCE_PA_CFG_LSB 8 #define PHY_BB_TPC_7_FORCE_PA_CFG_MSB 8 #define PHY_BB_TPC_7_FORCE_PA_CFG_MASK 0x100 #define PHY_BB_TPC_7_FORCE_PA_CFG_GET(x) (((x) & PHY_BB_TPC_7_FORCE_PA_CFG_MASK) >> PHY_BB_TPC_7_FORCE_PA_CFG_LSB) #define PHY_BB_TPC_7_FORCE_PA_CFG_SET(x) (((0 | (x)) << PHY_BB_TPC_7_FORCE_PA_CFG_LSB) & PHY_BB_TPC_7_FORCE_PA_CFG_MASK) #define PHY_BB_TPC_7_FORCE_PA_CFG_RESET 0x0 #define PHY_BB_TPC_7_FORCE_TXGAIN_IDX_LSB 7 #define PHY_BB_TPC_7_FORCE_TXGAIN_IDX_MSB 7 #define PHY_BB_TPC_7_FORCE_TXGAIN_IDX_MASK 0x80 #define PHY_BB_TPC_7_FORCE_TXGAIN_IDX_GET(x) (((x) & PHY_BB_TPC_7_FORCE_TXGAIN_IDX_MASK) >> PHY_BB_TPC_7_FORCE_TXGAIN_IDX_LSB) #define PHY_BB_TPC_7_FORCE_TXGAIN_IDX_SET(x) (((0 | (x)) << PHY_BB_TPC_7_FORCE_TXGAIN_IDX_LSB) & PHY_BB_TPC_7_FORCE_TXGAIN_IDX_MASK) #define PHY_BB_TPC_7_FORCE_TXGAIN_IDX_RESET 0x0 #define PHY_BB_TPC_7_FORCE_DAC_GAIN_LSB 6 #define PHY_BB_TPC_7_FORCE_DAC_GAIN_MSB 6 #define PHY_BB_TPC_7_FORCE_DAC_GAIN_MASK 0x40 #define PHY_BB_TPC_7_FORCE_DAC_GAIN_GET(x) (((x) & PHY_BB_TPC_7_FORCE_DAC_GAIN_MASK) >> PHY_BB_TPC_7_FORCE_DAC_GAIN_LSB) #define PHY_BB_TPC_7_FORCE_DAC_GAIN_SET(x) (((0 | (x)) << PHY_BB_TPC_7_FORCE_DAC_GAIN_LSB) & PHY_BB_TPC_7_FORCE_DAC_GAIN_MASK) #define PHY_BB_TPC_7_FORCE_DAC_GAIN_RESET 0x0 #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB 0 #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MSB 5 #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK 0x3f #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_GET(x) (((x) & PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK) >> PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB) #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_SET(x) (((0 | (x)) << PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB) & PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK) #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_RESET 0x0 #define PHY_BB_TPC_7_ADDRESS (0x210 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_7_RSTMASK 0x7ffffff #define PHY_BB_TPC_7_RESET 0x411400 // 0x214 (PHY_BB_TPC_8) #define PHY_BB_TPC_8_POWER_OFFSET_OFDM80_LSB 24 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM80_MSB 31 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM80_MASK 0xff000000 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM80_GET(x) (((x) & PHY_BB_TPC_8_POWER_OFFSET_OFDM80_MASK) >> PHY_BB_TPC_8_POWER_OFFSET_OFDM80_LSB) #define PHY_BB_TPC_8_POWER_OFFSET_OFDM80_SET(x) (((0 | (x)) << PHY_BB_TPC_8_POWER_OFFSET_OFDM80_LSB) & PHY_BB_TPC_8_POWER_OFFSET_OFDM80_MASK) #define PHY_BB_TPC_8_POWER_OFFSET_OFDM80_RESET 0x0 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM40_LSB 16 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM40_MSB 23 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM40_MASK 0xff0000 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM40_GET(x) (((x) & PHY_BB_TPC_8_POWER_OFFSET_OFDM40_MASK) >> PHY_BB_TPC_8_POWER_OFFSET_OFDM40_LSB) #define PHY_BB_TPC_8_POWER_OFFSET_OFDM40_SET(x) (((0 | (x)) << PHY_BB_TPC_8_POWER_OFFSET_OFDM40_LSB) & PHY_BB_TPC_8_POWER_OFFSET_OFDM40_MASK) #define PHY_BB_TPC_8_POWER_OFFSET_OFDM40_RESET 0x0 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM20_LSB 8 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM20_MSB 15 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM20_MASK 0xff00 #define PHY_BB_TPC_8_POWER_OFFSET_OFDM20_GET(x) (((x) & PHY_BB_TPC_8_POWER_OFFSET_OFDM20_MASK) >> PHY_BB_TPC_8_POWER_OFFSET_OFDM20_LSB) #define PHY_BB_TPC_8_POWER_OFFSET_OFDM20_SET(x) (((0 | (x)) << PHY_BB_TPC_8_POWER_OFFSET_OFDM20_LSB) & PHY_BB_TPC_8_POWER_OFFSET_OFDM20_MASK) #define PHY_BB_TPC_8_POWER_OFFSET_OFDM20_RESET 0x0 #define PHY_BB_TPC_8_POWER_OFFSET_CCK_LSB 0 #define PHY_BB_TPC_8_POWER_OFFSET_CCK_MSB 7 #define PHY_BB_TPC_8_POWER_OFFSET_CCK_MASK 0xff #define PHY_BB_TPC_8_POWER_OFFSET_CCK_GET(x) (((x) & PHY_BB_TPC_8_POWER_OFFSET_CCK_MASK) >> PHY_BB_TPC_8_POWER_OFFSET_CCK_LSB) #define PHY_BB_TPC_8_POWER_OFFSET_CCK_SET(x) (((0 | (x)) << PHY_BB_TPC_8_POWER_OFFSET_CCK_LSB) & PHY_BB_TPC_8_POWER_OFFSET_CCK_MASK) #define PHY_BB_TPC_8_POWER_OFFSET_CCK_RESET 0x0 #define PHY_BB_TPC_8_ADDRESS (0x214 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_8_RSTMASK 0xffffffff #define PHY_BB_TPC_8_RESET 0x0 // 0x218 (PHY_BB_TPC_9) #define PHY_BB_TPC_9_WAIT_RESIDUE_SETTLE_LSB 12 #define PHY_BB_TPC_9_WAIT_RESIDUE_SETTLE_MSB 15 #define PHY_BB_TPC_9_WAIT_RESIDUE_SETTLE_MASK 0xf000 #define PHY_BB_TPC_9_WAIT_RESIDUE_SETTLE_GET(x) (((x) & PHY_BB_TPC_9_WAIT_RESIDUE_SETTLE_MASK) >> PHY_BB_TPC_9_WAIT_RESIDUE_SETTLE_LSB) #define PHY_BB_TPC_9_WAIT_RESIDUE_SETTLE_SET(x) (((0 | (x)) << PHY_BB_TPC_9_WAIT_RESIDUE_SETTLE_LSB) & PHY_BB_TPC_9_WAIT_RESIDUE_SETTLE_MASK) #define PHY_BB_TPC_9_WAIT_RESIDUE_SETTLE_RESET 0x0 #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB 7 #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MSB 10 #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK 0x780 #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_GET(x) (((x) & PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK) >> PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB) #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_SET(x) (((0 | (x)) << PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB) & PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK) #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_RESET 0x0 #define PHY_BB_TPC_9_ADDRESS (0x218 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_9_RSTMASK 0xf780 #define PHY_BB_TPC_9_RESET 0x0 // 0x21c (PHY_BB_TPC_10) #define PHY_BB_TPC_10_CLPC_START_OFDM_LSB 16 #define PHY_BB_TPC_10_CLPC_START_OFDM_MSB 31 #define PHY_BB_TPC_10_CLPC_START_OFDM_MASK 0xffff0000 #define PHY_BB_TPC_10_CLPC_START_OFDM_GET(x) (((x) & PHY_BB_TPC_10_CLPC_START_OFDM_MASK) >> PHY_BB_TPC_10_CLPC_START_OFDM_LSB) #define PHY_BB_TPC_10_CLPC_START_OFDM_SET(x) (((0 | (x)) << PHY_BB_TPC_10_CLPC_START_OFDM_LSB) & PHY_BB_TPC_10_CLPC_START_OFDM_MASK) #define PHY_BB_TPC_10_CLPC_START_OFDM_RESET 0x10 #define PHY_BB_TPC_10_CLPC_START_CCK_LSB 0 #define PHY_BB_TPC_10_CLPC_START_CCK_MSB 15 #define PHY_BB_TPC_10_CLPC_START_CCK_MASK 0xffff #define PHY_BB_TPC_10_CLPC_START_CCK_GET(x) (((x) & PHY_BB_TPC_10_CLPC_START_CCK_MASK) >> PHY_BB_TPC_10_CLPC_START_CCK_LSB) #define PHY_BB_TPC_10_CLPC_START_CCK_SET(x) (((0 | (x)) << PHY_BB_TPC_10_CLPC_START_CCK_LSB) & PHY_BB_TPC_10_CLPC_START_CCK_MASK) #define PHY_BB_TPC_10_CLPC_START_CCK_RESET 0x10 #define PHY_BB_TPC_10_ADDRESS (0x21c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_10_RSTMASK 0xffffffff #define PHY_BB_TPC_10_RESET 0x100010 // 0x220 (PHY_BB_TPC_11_B0) #define PHY_BB_TPC_11_B0_FORCED_PA_CFG_0_LSB 24 #define PHY_BB_TPC_11_B0_FORCED_PA_CFG_0_MSB 26 #define PHY_BB_TPC_11_B0_FORCED_PA_CFG_0_MASK 0x7000000 #define PHY_BB_TPC_11_B0_FORCED_PA_CFG_0_GET(x) (((x) & PHY_BB_TPC_11_B0_FORCED_PA_CFG_0_MASK) >> PHY_BB_TPC_11_B0_FORCED_PA_CFG_0_LSB) #define PHY_BB_TPC_11_B0_FORCED_PA_CFG_0_SET(x) (((0 | (x)) << PHY_BB_TPC_11_B0_FORCED_PA_CFG_0_LSB) & PHY_BB_TPC_11_B0_FORCED_PA_CFG_0_MASK) #define PHY_BB_TPC_11_B0_FORCED_PA_CFG_0_RESET 0x0 #define PHY_BB_TPC_11_B0_FORCED_DAC_GAIN_0_LSB 16 #define PHY_BB_TPC_11_B0_FORCED_DAC_GAIN_0_MSB 23 #define PHY_BB_TPC_11_B0_FORCED_DAC_GAIN_0_MASK 0xff0000 #define PHY_BB_TPC_11_B0_FORCED_DAC_GAIN_0_GET(x) (((x) & PHY_BB_TPC_11_B0_FORCED_DAC_GAIN_0_MASK) >> PHY_BB_TPC_11_B0_FORCED_DAC_GAIN_0_LSB) #define PHY_BB_TPC_11_B0_FORCED_DAC_GAIN_0_SET(x) (((0 | (x)) << PHY_BB_TPC_11_B0_FORCED_DAC_GAIN_0_LSB) & PHY_BB_TPC_11_B0_FORCED_DAC_GAIN_0_MASK) #define PHY_BB_TPC_11_B0_FORCED_DAC_GAIN_0_RESET 0x0 #define PHY_BB_TPC_11_B0_FORCED_TXGAIN_IDX_0_LSB 10 #define PHY_BB_TPC_11_B0_FORCED_TXGAIN_IDX_0_MSB 14 #define PHY_BB_TPC_11_B0_FORCED_TXGAIN_IDX_0_MASK 0x7c00 #define PHY_BB_TPC_11_B0_FORCED_TXGAIN_IDX_0_GET(x) (((x) & PHY_BB_TPC_11_B0_FORCED_TXGAIN_IDX_0_MASK) >> PHY_BB_TPC_11_B0_FORCED_TXGAIN_IDX_0_LSB) #define PHY_BB_TPC_11_B0_FORCED_TXGAIN_IDX_0_SET(x) (((0 | (x)) << PHY_BB_TPC_11_B0_FORCED_TXGAIN_IDX_0_LSB) & PHY_BB_TPC_11_B0_FORCED_TXGAIN_IDX_0_MASK) #define PHY_BB_TPC_11_B0_FORCED_TXGAIN_IDX_0_RESET 0x0 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB_EXT_LSB 8 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB_EXT_MSB 9 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB_EXT_MASK 0x300 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB_EXT_GET(x) (((x) & PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB_EXT_MASK) >> PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB_EXT_LSB) #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB_EXT_SET(x) (((0 | (x)) << PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB_EXT_LSB) & PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB_EXT_MASK) #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB_EXT_RESET 0x0 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB 0 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MSB 7 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK 0xff #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_GET(x) (((x) & PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK) >> PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB) #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_SET(x) (((0 | (x)) << PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB) & PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK) #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_RESET 0x0 #define PHY_BB_TPC_11_B0_ADDRESS (0x220 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_11_B0_RSTMASK 0x7ff7fff #define PHY_BB_TPC_11_B0_RESET 0x0 // 0x224 (PHY_BB_TPC_12_B0) #define PHY_BB_TPC_12_B0_PDADC_BIAS_0_LSB 0 #define PHY_BB_TPC_12_B0_PDADC_BIAS_0_MSB 7 #define PHY_BB_TPC_12_B0_PDADC_BIAS_0_MASK 0xff #define PHY_BB_TPC_12_B0_PDADC_BIAS_0_GET(x) (((x) & PHY_BB_TPC_12_B0_PDADC_BIAS_0_MASK) >> PHY_BB_TPC_12_B0_PDADC_BIAS_0_LSB) #define PHY_BB_TPC_12_B0_PDADC_BIAS_0_SET(x) (((0 | (x)) << PHY_BB_TPC_12_B0_PDADC_BIAS_0_LSB) & PHY_BB_TPC_12_B0_PDADC_BIAS_0_MASK) #define PHY_BB_TPC_12_B0_PDADC_BIAS_0_RESET 0x0 #define PHY_BB_TPC_12_B0_ADDRESS (0x224 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_12_B0_RSTMASK 0xff #define PHY_BB_TPC_12_B0_RESET 0x0 // 0x228 (PHY_BB_TPC_13) #define PHY_BB_TPC_13_MIN_DAC_BO_QAM0_LSB 24 #define PHY_BB_TPC_13_MIN_DAC_BO_QAM0_MSB 29 #define PHY_BB_TPC_13_MIN_DAC_BO_QAM0_MASK 0x3f000000 #define PHY_BB_TPC_13_MIN_DAC_BO_QAM0_GET(x) (((x) & PHY_BB_TPC_13_MIN_DAC_BO_QAM0_MASK) >> PHY_BB_TPC_13_MIN_DAC_BO_QAM0_LSB) #define PHY_BB_TPC_13_MIN_DAC_BO_QAM0_SET(x) (((0 | (x)) << PHY_BB_TPC_13_MIN_DAC_BO_QAM0_LSB) & PHY_BB_TPC_13_MIN_DAC_BO_QAM0_MASK) #define PHY_BB_TPC_13_MIN_DAC_BO_QAM0_RESET 0x0 #define PHY_BB_TPC_13_MAX_DAC_BO_QAM0_LSB 16 #define PHY_BB_TPC_13_MAX_DAC_BO_QAM0_MSB 21 #define PHY_BB_TPC_13_MAX_DAC_BO_QAM0_MASK 0x3f0000 #define PHY_BB_TPC_13_MAX_DAC_BO_QAM0_GET(x) (((x) & PHY_BB_TPC_13_MAX_DAC_BO_QAM0_MASK) >> PHY_BB_TPC_13_MAX_DAC_BO_QAM0_LSB) #define PHY_BB_TPC_13_MAX_DAC_BO_QAM0_SET(x) (((0 | (x)) << PHY_BB_TPC_13_MAX_DAC_BO_QAM0_LSB) & PHY_BB_TPC_13_MAX_DAC_BO_QAM0_MASK) #define PHY_BB_TPC_13_MAX_DAC_BO_QAM0_RESET 0x0 #define PHY_BB_TPC_13_MIN_DAC_BO_CCK_LSB 8 #define PHY_BB_TPC_13_MIN_DAC_BO_CCK_MSB 13 #define PHY_BB_TPC_13_MIN_DAC_BO_CCK_MASK 0x3f00 #define PHY_BB_TPC_13_MIN_DAC_BO_CCK_GET(x) (((x) & PHY_BB_TPC_13_MIN_DAC_BO_CCK_MASK) >> PHY_BB_TPC_13_MIN_DAC_BO_CCK_LSB) #define PHY_BB_TPC_13_MIN_DAC_BO_CCK_SET(x) (((0 | (x)) << PHY_BB_TPC_13_MIN_DAC_BO_CCK_LSB) & PHY_BB_TPC_13_MIN_DAC_BO_CCK_MASK) #define PHY_BB_TPC_13_MIN_DAC_BO_CCK_RESET 0x0 #define PHY_BB_TPC_13_MAX_DAC_BO_CCK_LSB 0 #define PHY_BB_TPC_13_MAX_DAC_BO_CCK_MSB 5 #define PHY_BB_TPC_13_MAX_DAC_BO_CCK_MASK 0x3f #define PHY_BB_TPC_13_MAX_DAC_BO_CCK_GET(x) (((x) & PHY_BB_TPC_13_MAX_DAC_BO_CCK_MASK) >> PHY_BB_TPC_13_MAX_DAC_BO_CCK_LSB) #define PHY_BB_TPC_13_MAX_DAC_BO_CCK_SET(x) (((0 | (x)) << PHY_BB_TPC_13_MAX_DAC_BO_CCK_LSB) & PHY_BB_TPC_13_MAX_DAC_BO_CCK_MASK) #define PHY_BB_TPC_13_MAX_DAC_BO_CCK_RESET 0x0 #define PHY_BB_TPC_13_ADDRESS (0x228 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_13_RSTMASK 0x3f3f3f3f #define PHY_BB_TPC_13_RESET 0x0 // 0x22c (PHY_BB_TPC_14) #define PHY_BB_TPC_14_MIN_DAC_BO_QAM2_LSB 24 #define PHY_BB_TPC_14_MIN_DAC_BO_QAM2_MSB 29 #define PHY_BB_TPC_14_MIN_DAC_BO_QAM2_MASK 0x3f000000 #define PHY_BB_TPC_14_MIN_DAC_BO_QAM2_GET(x) (((x) & PHY_BB_TPC_14_MIN_DAC_BO_QAM2_MASK) >> PHY_BB_TPC_14_MIN_DAC_BO_QAM2_LSB) #define PHY_BB_TPC_14_MIN_DAC_BO_QAM2_SET(x) (((0 | (x)) << PHY_BB_TPC_14_MIN_DAC_BO_QAM2_LSB) & PHY_BB_TPC_14_MIN_DAC_BO_QAM2_MASK) #define PHY_BB_TPC_14_MIN_DAC_BO_QAM2_RESET 0x0 #define PHY_BB_TPC_14_MAX_DAC_BO_QAM2_LSB 16 #define PHY_BB_TPC_14_MAX_DAC_BO_QAM2_MSB 21 #define PHY_BB_TPC_14_MAX_DAC_BO_QAM2_MASK 0x3f0000 #define PHY_BB_TPC_14_MAX_DAC_BO_QAM2_GET(x) (((x) & PHY_BB_TPC_14_MAX_DAC_BO_QAM2_MASK) >> PHY_BB_TPC_14_MAX_DAC_BO_QAM2_LSB) #define PHY_BB_TPC_14_MAX_DAC_BO_QAM2_SET(x) (((0 | (x)) << PHY_BB_TPC_14_MAX_DAC_BO_QAM2_LSB) & PHY_BB_TPC_14_MAX_DAC_BO_QAM2_MASK) #define PHY_BB_TPC_14_MAX_DAC_BO_QAM2_RESET 0x0 #define PHY_BB_TPC_14_MIN_DAC_BO_QAM1_LSB 8 #define PHY_BB_TPC_14_MIN_DAC_BO_QAM1_MSB 13 #define PHY_BB_TPC_14_MIN_DAC_BO_QAM1_MASK 0x3f00 #define PHY_BB_TPC_14_MIN_DAC_BO_QAM1_GET(x) (((x) & PHY_BB_TPC_14_MIN_DAC_BO_QAM1_MASK) >> PHY_BB_TPC_14_MIN_DAC_BO_QAM1_LSB) #define PHY_BB_TPC_14_MIN_DAC_BO_QAM1_SET(x) (((0 | (x)) << PHY_BB_TPC_14_MIN_DAC_BO_QAM1_LSB) & PHY_BB_TPC_14_MIN_DAC_BO_QAM1_MASK) #define PHY_BB_TPC_14_MIN_DAC_BO_QAM1_RESET 0x0 #define PHY_BB_TPC_14_MAX_DAC_BO_QAM1_LSB 0 #define PHY_BB_TPC_14_MAX_DAC_BO_QAM1_MSB 5 #define PHY_BB_TPC_14_MAX_DAC_BO_QAM1_MASK 0x3f #define PHY_BB_TPC_14_MAX_DAC_BO_QAM1_GET(x) (((x) & PHY_BB_TPC_14_MAX_DAC_BO_QAM1_MASK) >> PHY_BB_TPC_14_MAX_DAC_BO_QAM1_LSB) #define PHY_BB_TPC_14_MAX_DAC_BO_QAM1_SET(x) (((0 | (x)) << PHY_BB_TPC_14_MAX_DAC_BO_QAM1_LSB) & PHY_BB_TPC_14_MAX_DAC_BO_QAM1_MASK) #define PHY_BB_TPC_14_MAX_DAC_BO_QAM1_RESET 0x0 #define PHY_BB_TPC_14_ADDRESS (0x22c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_14_RSTMASK 0x3f3f3f3f #define PHY_BB_TPC_14_RESET 0x0 // 0x230 (PHY_BB_TPC_15) #define PHY_BB_TPC_15_MIN_DAC_BO_QAM4_LSB 24 #define PHY_BB_TPC_15_MIN_DAC_BO_QAM4_MSB 29 #define PHY_BB_TPC_15_MIN_DAC_BO_QAM4_MASK 0x3f000000 #define PHY_BB_TPC_15_MIN_DAC_BO_QAM4_GET(x) (((x) & PHY_BB_TPC_15_MIN_DAC_BO_QAM4_MASK) >> PHY_BB_TPC_15_MIN_DAC_BO_QAM4_LSB) #define PHY_BB_TPC_15_MIN_DAC_BO_QAM4_SET(x) (((0 | (x)) << PHY_BB_TPC_15_MIN_DAC_BO_QAM4_LSB) & PHY_BB_TPC_15_MIN_DAC_BO_QAM4_MASK) #define PHY_BB_TPC_15_MIN_DAC_BO_QAM4_RESET 0x0 #define PHY_BB_TPC_15_MAX_DAC_BO_QAM4_LSB 16 #define PHY_BB_TPC_15_MAX_DAC_BO_QAM4_MSB 21 #define PHY_BB_TPC_15_MAX_DAC_BO_QAM4_MASK 0x3f0000 #define PHY_BB_TPC_15_MAX_DAC_BO_QAM4_GET(x) (((x) & PHY_BB_TPC_15_MAX_DAC_BO_QAM4_MASK) >> PHY_BB_TPC_15_MAX_DAC_BO_QAM4_LSB) #define PHY_BB_TPC_15_MAX_DAC_BO_QAM4_SET(x) (((0 | (x)) << PHY_BB_TPC_15_MAX_DAC_BO_QAM4_LSB) & PHY_BB_TPC_15_MAX_DAC_BO_QAM4_MASK) #define PHY_BB_TPC_15_MAX_DAC_BO_QAM4_RESET 0x0 #define PHY_BB_TPC_15_MIN_DAC_BO_QAM3_LSB 8 #define PHY_BB_TPC_15_MIN_DAC_BO_QAM3_MSB 13 #define PHY_BB_TPC_15_MIN_DAC_BO_QAM3_MASK 0x3f00 #define PHY_BB_TPC_15_MIN_DAC_BO_QAM3_GET(x) (((x) & PHY_BB_TPC_15_MIN_DAC_BO_QAM3_MASK) >> PHY_BB_TPC_15_MIN_DAC_BO_QAM3_LSB) #define PHY_BB_TPC_15_MIN_DAC_BO_QAM3_SET(x) (((0 | (x)) << PHY_BB_TPC_15_MIN_DAC_BO_QAM3_LSB) & PHY_BB_TPC_15_MIN_DAC_BO_QAM3_MASK) #define PHY_BB_TPC_15_MIN_DAC_BO_QAM3_RESET 0x0 #define PHY_BB_TPC_15_MAX_DAC_BO_QAM3_LSB 0 #define PHY_BB_TPC_15_MAX_DAC_BO_QAM3_MSB 5 #define PHY_BB_TPC_15_MAX_DAC_BO_QAM3_MASK 0x3f #define PHY_BB_TPC_15_MAX_DAC_BO_QAM3_GET(x) (((x) & PHY_BB_TPC_15_MAX_DAC_BO_QAM3_MASK) >> PHY_BB_TPC_15_MAX_DAC_BO_QAM3_LSB) #define PHY_BB_TPC_15_MAX_DAC_BO_QAM3_SET(x) (((0 | (x)) << PHY_BB_TPC_15_MAX_DAC_BO_QAM3_LSB) & PHY_BB_TPC_15_MAX_DAC_BO_QAM3_MASK) #define PHY_BB_TPC_15_MAX_DAC_BO_QAM3_RESET 0x0 #define PHY_BB_TPC_15_ADDRESS (0x230 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_15_RSTMASK 0x3f3f3f3f #define PHY_BB_TPC_15_RESET 0x0 // 0x238 (PHY_BB_TPC_17) #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_EN_LSB 30 #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_EN_MSB 30 #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_EN_MASK 0x40000000 #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_EN_GET(x) (((x) & PHY_BB_TPC_17_TPC_CL_ERR_CLIP_EN_MASK) >> PHY_BB_TPC_17_TPC_CL_ERR_CLIP_EN_LSB) #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_EN_SET(x) (((0 | (x)) << PHY_BB_TPC_17_TPC_CL_ERR_CLIP_EN_LSB) & PHY_BB_TPC_17_TPC_CL_ERR_CLIP_EN_MASK) #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_EN_RESET 0x0 #define PHY_BB_TPC_17_PDADC_CLIP_EN_LSB 29 #define PHY_BB_TPC_17_PDADC_CLIP_EN_MSB 29 #define PHY_BB_TPC_17_PDADC_CLIP_EN_MASK 0x20000000 #define PHY_BB_TPC_17_PDADC_CLIP_EN_GET(x) (((x) & PHY_BB_TPC_17_PDADC_CLIP_EN_MASK) >> PHY_BB_TPC_17_PDADC_CLIP_EN_LSB) #define PHY_BB_TPC_17_PDADC_CLIP_EN_SET(x) (((0 | (x)) << PHY_BB_TPC_17_PDADC_CLIP_EN_LSB) & PHY_BB_TPC_17_PDADC_CLIP_EN_MASK) #define PHY_BB_TPC_17_PDADC_CLIP_EN_RESET 0x0 #define PHY_BB_TPC_17_PDADC_CLIP_THRES_LSB 20 #define PHY_BB_TPC_17_PDADC_CLIP_THRES_MSB 28 #define PHY_BB_TPC_17_PDADC_CLIP_THRES_MASK 0x1ff00000 #define PHY_BB_TPC_17_PDADC_CLIP_THRES_GET(x) (((x) & PHY_BB_TPC_17_PDADC_CLIP_THRES_MASK) >> PHY_BB_TPC_17_PDADC_CLIP_THRES_LSB) #define PHY_BB_TPC_17_PDADC_CLIP_THRES_SET(x) (((0 | (x)) << PHY_BB_TPC_17_PDADC_CLIP_THRES_LSB) & PHY_BB_TPC_17_PDADC_CLIP_THRES_MASK) #define PHY_BB_TPC_17_PDADC_CLIP_THRES_RESET 0x100 #define PHY_BB_TPC_17_MEAS_PWR_SW_LSB 19 #define PHY_BB_TPC_17_MEAS_PWR_SW_MSB 19 #define PHY_BB_TPC_17_MEAS_PWR_SW_MASK 0x80000 #define PHY_BB_TPC_17_MEAS_PWR_SW_GET(x) (((x) & PHY_BB_TPC_17_MEAS_PWR_SW_MASK) >> PHY_BB_TPC_17_MEAS_PWR_SW_LSB) #define PHY_BB_TPC_17_MEAS_PWR_SW_SET(x) (((0 | (x)) << PHY_BB_TPC_17_MEAS_PWR_SW_LSB) & PHY_BB_TPC_17_MEAS_PWR_SW_MASK) #define PHY_BB_TPC_17_MEAS_PWR_SW_RESET 0x0 #define PHY_BB_TPC_17_CL_ERR_IS_COMMON_LSB 18 #define PHY_BB_TPC_17_CL_ERR_IS_COMMON_MSB 18 #define PHY_BB_TPC_17_CL_ERR_IS_COMMON_MASK 0x40000 #define PHY_BB_TPC_17_CL_ERR_IS_COMMON_GET(x) (((x) & PHY_BB_TPC_17_CL_ERR_IS_COMMON_MASK) >> PHY_BB_TPC_17_CL_ERR_IS_COMMON_LSB) #define PHY_BB_TPC_17_CL_ERR_IS_COMMON_SET(x) (((0 | (x)) << PHY_BB_TPC_17_CL_ERR_IS_COMMON_LSB) & PHY_BB_TPC_17_CL_ERR_IS_COMMON_MASK) #define PHY_BB_TPC_17_CL_ERR_IS_COMMON_RESET 0x0 #define PHY_BB_TPC_17_MIN_PWR_TPC_CORR_LSB 12 #define PHY_BB_TPC_17_MIN_PWR_TPC_CORR_MSB 17 #define PHY_BB_TPC_17_MIN_PWR_TPC_CORR_MASK 0x3f000 #define PHY_BB_TPC_17_MIN_PWR_TPC_CORR_GET(x) (((x) & PHY_BB_TPC_17_MIN_PWR_TPC_CORR_MASK) >> PHY_BB_TPC_17_MIN_PWR_TPC_CORR_LSB) #define PHY_BB_TPC_17_MIN_PWR_TPC_CORR_SET(x) (((0 | (x)) << PHY_BB_TPC_17_MIN_PWR_TPC_CORR_LSB) & PHY_BB_TPC_17_MIN_PWR_TPC_CORR_MASK) #define PHY_BB_TPC_17_MIN_PWR_TPC_CORR_RESET 0x0 #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_LSB 6 #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_MSB 11 #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_MASK 0xfc0 #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_GET(x) (((x) & PHY_BB_TPC_17_TPC_CL_ERR_CLIP_MASK) >> PHY_BB_TPC_17_TPC_CL_ERR_CLIP_LSB) #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_SET(x) (((0 | (x)) << PHY_BB_TPC_17_TPC_CL_ERR_CLIP_LSB) & PHY_BB_TPC_17_TPC_CL_ERR_CLIP_MASK) #define PHY_BB_TPC_17_TPC_CL_ERR_CLIP_RESET 0x20 #define PHY_BB_TPC_17_TPC_CL_ERR_SCALE_LSB 0 #define PHY_BB_TPC_17_TPC_CL_ERR_SCALE_MSB 5 #define PHY_BB_TPC_17_TPC_CL_ERR_SCALE_MASK 0x3f #define PHY_BB_TPC_17_TPC_CL_ERR_SCALE_GET(x) (((x) & PHY_BB_TPC_17_TPC_CL_ERR_SCALE_MASK) >> PHY_BB_TPC_17_TPC_CL_ERR_SCALE_LSB) #define PHY_BB_TPC_17_TPC_CL_ERR_SCALE_SET(x) (((0 | (x)) << PHY_BB_TPC_17_TPC_CL_ERR_SCALE_LSB) & PHY_BB_TPC_17_TPC_CL_ERR_SCALE_MASK) #define PHY_BB_TPC_17_TPC_CL_ERR_SCALE_RESET 0x20 #define PHY_BB_TPC_17_ADDRESS (0x238 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_17_RSTMASK 0x7fffffff #define PHY_BB_TPC_17_RESET 0x10000820 // 0x23c (PHY_BB_TPC_18) #define PHY_BB_TPC_18_TPC_ALUT_BASE_LSB 21 #define PHY_BB_TPC_18_TPC_ALUT_BASE_MSB 28 #define PHY_BB_TPC_18_TPC_ALUT_BASE_MASK 0x1fe00000 #define PHY_BB_TPC_18_TPC_ALUT_BASE_GET(x) (((x) & PHY_BB_TPC_18_TPC_ALUT_BASE_MASK) >> PHY_BB_TPC_18_TPC_ALUT_BASE_LSB) #define PHY_BB_TPC_18_TPC_ALUT_BASE_SET(x) (((0 | (x)) << PHY_BB_TPC_18_TPC_ALUT_BASE_LSB) & PHY_BB_TPC_18_TPC_ALUT_BASE_MASK) #define PHY_BB_TPC_18_TPC_ALUT_BASE_RESET 0x80 #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM9_LSB 14 #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM9_MSB 20 #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM9_MASK 0x1fc000 #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM9_GET(x) (((x) & PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM9_MASK) >> PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM9_LSB) #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM9_SET(x) (((0 | (x)) << PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM9_LSB) & PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM9_MASK) #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM9_RESET 0x0 #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM8_LSB 7 #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM8_MSB 13 #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM8_MASK 0x3f80 #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM8_GET(x) (((x) & PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM8_MASK) >> PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM8_LSB) #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM8_SET(x) (((0 | (x)) << PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM8_LSB) & PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM8_MASK) #define PHY_BB_TPC_18_HEAVY_CLIP_COMP_FACTOR_QAM8_RESET 0x0 #define PHY_BB_TPC_18_MIN_POWER_THERM_VOLT_GAIN_CORR_LSB 1 #define PHY_BB_TPC_18_MIN_POWER_THERM_VOLT_GAIN_CORR_MSB 6 #define PHY_BB_TPC_18_MIN_POWER_THERM_VOLT_GAIN_CORR_MASK 0x7e #define PHY_BB_TPC_18_MIN_POWER_THERM_VOLT_GAIN_CORR_GET(x) (((x) & PHY_BB_TPC_18_MIN_POWER_THERM_VOLT_GAIN_CORR_MASK) >> PHY_BB_TPC_18_MIN_POWER_THERM_VOLT_GAIN_CORR_LSB) #define PHY_BB_TPC_18_MIN_POWER_THERM_VOLT_GAIN_CORR_SET(x) (((0 | (x)) << PHY_BB_TPC_18_MIN_POWER_THERM_VOLT_GAIN_CORR_LSB) & PHY_BB_TPC_18_MIN_POWER_THERM_VOLT_GAIN_CORR_MASK) #define PHY_BB_TPC_18_MIN_POWER_THERM_VOLT_GAIN_CORR_RESET 0x0 #define PHY_BB_TPC_18_USE_LEGACY_TPC_LSB 0 #define PHY_BB_TPC_18_USE_LEGACY_TPC_MSB 0 #define PHY_BB_TPC_18_USE_LEGACY_TPC_MASK 0x1 #define PHY_BB_TPC_18_USE_LEGACY_TPC_GET(x) (((x) & PHY_BB_TPC_18_USE_LEGACY_TPC_MASK) >> PHY_BB_TPC_18_USE_LEGACY_TPC_LSB) #define PHY_BB_TPC_18_USE_LEGACY_TPC_SET(x) (((0 | (x)) << PHY_BB_TPC_18_USE_LEGACY_TPC_LSB) & PHY_BB_TPC_18_USE_LEGACY_TPC_MASK) #define PHY_BB_TPC_18_USE_LEGACY_TPC_RESET 0x0 #define PHY_BB_TPC_18_ADDRESS (0x23c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_18_RSTMASK 0x1fffffff #define PHY_BB_TPC_18_RESET 0x10000000 // 0x240 (PHY_BB_TPC_19_B0) #define PHY_BB_TPC_19_B0_BT_CLPC_ERR_UPDT_0_LSB 31 #define PHY_BB_TPC_19_B0_BT_CLPC_ERR_UPDT_0_MSB 31 #define PHY_BB_TPC_19_B0_BT_CLPC_ERR_UPDT_0_MASK 0x80000000 #define PHY_BB_TPC_19_B0_BT_CLPC_ERR_UPDT_0_GET(x) (((x) & PHY_BB_TPC_19_B0_BT_CLPC_ERR_UPDT_0_MASK) >> PHY_BB_TPC_19_B0_BT_CLPC_ERR_UPDT_0_LSB) #define PHY_BB_TPC_19_B0_BT_CLPC_ERR_UPDT_0_SET(x) (((0 | (x)) << PHY_BB_TPC_19_B0_BT_CLPC_ERR_UPDT_0_LSB) & PHY_BB_TPC_19_B0_BT_CLPC_ERR_UPDT_0_MASK) #define PHY_BB_TPC_19_B0_BT_CLPC_ERR_UPDT_0_RESET 0x0 #define PHY_BB_TPC_19_B0_ALPHA_VOLT_0_LSB 24 #define PHY_BB_TPC_19_B0_ALPHA_VOLT_0_MSB 30 #define PHY_BB_TPC_19_B0_ALPHA_VOLT_0_MASK 0x7f000000 #define PHY_BB_TPC_19_B0_ALPHA_VOLT_0_GET(x) (((x) & PHY_BB_TPC_19_B0_ALPHA_VOLT_0_MASK) >> PHY_BB_TPC_19_B0_ALPHA_VOLT_0_LSB) #define PHY_BB_TPC_19_B0_ALPHA_VOLT_0_SET(x) (((0 | (x)) << PHY_BB_TPC_19_B0_ALPHA_VOLT_0_LSB) & PHY_BB_TPC_19_B0_ALPHA_VOLT_0_MASK) #define PHY_BB_TPC_19_B0_ALPHA_VOLT_0_RESET 0x0 #define PHY_BB_TPC_19_B0_ALPHA_THERM_0_LSB 16 #define PHY_BB_TPC_19_B0_ALPHA_THERM_0_MSB 23 #define PHY_BB_TPC_19_B0_ALPHA_THERM_0_MASK 0xff0000 #define PHY_BB_TPC_19_B0_ALPHA_THERM_0_GET(x) (((x) & PHY_BB_TPC_19_B0_ALPHA_THERM_0_MASK) >> PHY_BB_TPC_19_B0_ALPHA_THERM_0_LSB) #define PHY_BB_TPC_19_B0_ALPHA_THERM_0_SET(x) (((0 | (x)) << PHY_BB_TPC_19_B0_ALPHA_THERM_0_LSB) & PHY_BB_TPC_19_B0_ALPHA_THERM_0_MASK) #define PHY_BB_TPC_19_B0_ALPHA_THERM_0_RESET 0x0 #define PHY_BB_TPC_19_B0_VOLT_CAL_VALUE_0_LSB 8 #define PHY_BB_TPC_19_B0_VOLT_CAL_VALUE_0_MSB 15 #define PHY_BB_TPC_19_B0_VOLT_CAL_VALUE_0_MASK 0xff00 #define PHY_BB_TPC_19_B0_VOLT_CAL_VALUE_0_GET(x) (((x) & PHY_BB_TPC_19_B0_VOLT_CAL_VALUE_0_MASK) >> PHY_BB_TPC_19_B0_VOLT_CAL_VALUE_0_LSB) #define PHY_BB_TPC_19_B0_VOLT_CAL_VALUE_0_SET(x) (((0 | (x)) << PHY_BB_TPC_19_B0_VOLT_CAL_VALUE_0_LSB) & PHY_BB_TPC_19_B0_VOLT_CAL_VALUE_0_MASK) #define PHY_BB_TPC_19_B0_VOLT_CAL_VALUE_0_RESET 0x0 #define PHY_BB_TPC_19_B0_THERM_CAL_VALUE_0_LSB 0 #define PHY_BB_TPC_19_B0_THERM_CAL_VALUE_0_MSB 7 #define PHY_BB_TPC_19_B0_THERM_CAL_VALUE_0_MASK 0xff #define PHY_BB_TPC_19_B0_THERM_CAL_VALUE_0_GET(x) (((x) & PHY_BB_TPC_19_B0_THERM_CAL_VALUE_0_MASK) >> PHY_BB_TPC_19_B0_THERM_CAL_VALUE_0_LSB) #define PHY_BB_TPC_19_B0_THERM_CAL_VALUE_0_SET(x) (((0 | (x)) << PHY_BB_TPC_19_B0_THERM_CAL_VALUE_0_LSB) & PHY_BB_TPC_19_B0_THERM_CAL_VALUE_0_MASK) #define PHY_BB_TPC_19_B0_THERM_CAL_VALUE_0_RESET 0x0 #define PHY_BB_TPC_19_B0_ADDRESS (0x240 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_19_B0_RSTMASK 0xffffffff #define PHY_BB_TPC_19_B0_RESET 0x0 // 0x248 (PHY_BB_THERM_ADC_1_B0) #define PHY_BB_THERM_ADC_1_B0_INIT_ATB_SETTING_0_LSB 16 #define PHY_BB_THERM_ADC_1_B0_INIT_ATB_SETTING_0_MSB 23 #define PHY_BB_THERM_ADC_1_B0_INIT_ATB_SETTING_0_MASK 0xff0000 #define PHY_BB_THERM_ADC_1_B0_INIT_ATB_SETTING_0_GET(x) (((x) & PHY_BB_THERM_ADC_1_B0_INIT_ATB_SETTING_0_MASK) >> PHY_BB_THERM_ADC_1_B0_INIT_ATB_SETTING_0_LSB) #define PHY_BB_THERM_ADC_1_B0_INIT_ATB_SETTING_0_SET(x) (((0 | (x)) << PHY_BB_THERM_ADC_1_B0_INIT_ATB_SETTING_0_LSB) & PHY_BB_THERM_ADC_1_B0_INIT_ATB_SETTING_0_MASK) #define PHY_BB_THERM_ADC_1_B0_INIT_ATB_SETTING_0_RESET 0x0 #define PHY_BB_THERM_ADC_1_B0_INIT_VOLT_SETTING_0_LSB 8 #define PHY_BB_THERM_ADC_1_B0_INIT_VOLT_SETTING_0_MSB 15 #define PHY_BB_THERM_ADC_1_B0_INIT_VOLT_SETTING_0_MASK 0xff00 #define PHY_BB_THERM_ADC_1_B0_INIT_VOLT_SETTING_0_GET(x) (((x) & PHY_BB_THERM_ADC_1_B0_INIT_VOLT_SETTING_0_MASK) >> PHY_BB_THERM_ADC_1_B0_INIT_VOLT_SETTING_0_LSB) #define PHY_BB_THERM_ADC_1_B0_INIT_VOLT_SETTING_0_SET(x) (((0 | (x)) << PHY_BB_THERM_ADC_1_B0_INIT_VOLT_SETTING_0_LSB) & PHY_BB_THERM_ADC_1_B0_INIT_VOLT_SETTING_0_MASK) #define PHY_BB_THERM_ADC_1_B0_INIT_VOLT_SETTING_0_RESET 0x0 #define PHY_BB_THERM_ADC_1_B0_INIT_THERM_SETTING_0_LSB 0 #define PHY_BB_THERM_ADC_1_B0_INIT_THERM_SETTING_0_MSB 7 #define PHY_BB_THERM_ADC_1_B0_INIT_THERM_SETTING_0_MASK 0xff #define PHY_BB_THERM_ADC_1_B0_INIT_THERM_SETTING_0_GET(x) (((x) & PHY_BB_THERM_ADC_1_B0_INIT_THERM_SETTING_0_MASK) >> PHY_BB_THERM_ADC_1_B0_INIT_THERM_SETTING_0_LSB) #define PHY_BB_THERM_ADC_1_B0_INIT_THERM_SETTING_0_SET(x) (((0 | (x)) << PHY_BB_THERM_ADC_1_B0_INIT_THERM_SETTING_0_LSB) & PHY_BB_THERM_ADC_1_B0_INIT_THERM_SETTING_0_MASK) #define PHY_BB_THERM_ADC_1_B0_INIT_THERM_SETTING_0_RESET 0x0 #define PHY_BB_THERM_ADC_1_B0_ADDRESS (0x248 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_THERM_ADC_1_B0_RSTMASK 0xffffff #define PHY_BB_THERM_ADC_1_B0_RESET 0x0 // 0x24c (PHY_BB_THERM_ADC_2) #define PHY_BB_THERM_ADC_2_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB 1 #define PHY_BB_THERM_ADC_2_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MSB 1 #define PHY_BB_THERM_ADC_2_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK 0x2 #define PHY_BB_THERM_ADC_2_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_GET(x) (((x) & PHY_BB_THERM_ADC_2_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK) >> PHY_BB_THERM_ADC_2_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB) #define PHY_BB_THERM_ADC_2_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_SET(x) (((0 | (x)) << PHY_BB_THERM_ADC_2_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB) & PHY_BB_THERM_ADC_2_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK) #define PHY_BB_THERM_ADC_2_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_RESET 0x0 #define PHY_BB_THERM_ADC_2_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB 0 #define PHY_BB_THERM_ADC_2_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MSB 0 #define PHY_BB_THERM_ADC_2_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK 0x1 #define PHY_BB_THERM_ADC_2_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_GET(x) (((x) & PHY_BB_THERM_ADC_2_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK) >> PHY_BB_THERM_ADC_2_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB) #define PHY_BB_THERM_ADC_2_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_SET(x) (((0 | (x)) << PHY_BB_THERM_ADC_2_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB) & PHY_BB_THERM_ADC_2_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK) #define PHY_BB_THERM_ADC_2_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_RESET 0x1 #define PHY_BB_THERM_ADC_2_ADDRESS (0x24c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_THERM_ADC_2_RSTMASK 0x3 #define PHY_BB_THERM_ADC_2_RESET 0x1 // 0x250 (PHY_BB_THERM_ADC_3_B0) #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_SCALED_GAIN_0_LSB 8 #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_SCALED_GAIN_0_MSB 16 #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_SCALED_GAIN_0_MASK 0x1ff00 #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_SCALED_GAIN_0_GET(x) (((x) & PHY_BB_THERM_ADC_3_B0_THERM_ADC_SCALED_GAIN_0_MASK) >> PHY_BB_THERM_ADC_3_B0_THERM_ADC_SCALED_GAIN_0_LSB) #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_SCALED_GAIN_0_SET(x) (((0 | (x)) << PHY_BB_THERM_ADC_3_B0_THERM_ADC_SCALED_GAIN_0_LSB) & PHY_BB_THERM_ADC_3_B0_THERM_ADC_SCALED_GAIN_0_MASK) #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_SCALED_GAIN_0_RESET 0x100 #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_OFFSET_0_LSB 0 #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_OFFSET_0_MSB 7 #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_OFFSET_0_MASK 0xff #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_OFFSET_0_GET(x) (((x) & PHY_BB_THERM_ADC_3_B0_THERM_ADC_OFFSET_0_MASK) >> PHY_BB_THERM_ADC_3_B0_THERM_ADC_OFFSET_0_LSB) #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_OFFSET_0_SET(x) (((0 | (x)) << PHY_BB_THERM_ADC_3_B0_THERM_ADC_OFFSET_0_LSB) & PHY_BB_THERM_ADC_3_B0_THERM_ADC_OFFSET_0_MASK) #define PHY_BB_THERM_ADC_3_B0_THERM_ADC_OFFSET_0_RESET 0x0 #define PHY_BB_THERM_ADC_3_B0_ADDRESS (0x250 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_THERM_ADC_3_B0_RSTMASK 0x1ffff #define PHY_BB_THERM_ADC_3_B0_RESET 0x10000 // 0x254 (PHY_BB_THERM_ADC_4_B0) #define PHY_BB_THERM_ADC_4_B0_LATEST_ATB_VALUE_0_LSB 16 #define PHY_BB_THERM_ADC_4_B0_LATEST_ATB_VALUE_0_MSB 23 #define PHY_BB_THERM_ADC_4_B0_LATEST_ATB_VALUE_0_MASK 0xff0000 #define PHY_BB_THERM_ADC_4_B0_LATEST_ATB_VALUE_0_GET(x) (((x) & PHY_BB_THERM_ADC_4_B0_LATEST_ATB_VALUE_0_MASK) >> PHY_BB_THERM_ADC_4_B0_LATEST_ATB_VALUE_0_LSB) #define PHY_BB_THERM_ADC_4_B0_LATEST_ATB_VALUE_0_SET(x) (((0 | (x)) << PHY_BB_THERM_ADC_4_B0_LATEST_ATB_VALUE_0_LSB) & PHY_BB_THERM_ADC_4_B0_LATEST_ATB_VALUE_0_MASK) #define PHY_BB_THERM_ADC_4_B0_LATEST_ATB_VALUE_0_RESET 0x0 #define PHY_BB_THERM_ADC_4_B0_LATEST_VOLT_VALUE_0_LSB 8 #define PHY_BB_THERM_ADC_4_B0_LATEST_VOLT_VALUE_0_MSB 15 #define PHY_BB_THERM_ADC_4_B0_LATEST_VOLT_VALUE_0_MASK 0xff00 #define PHY_BB_THERM_ADC_4_B0_LATEST_VOLT_VALUE_0_GET(x) (((x) & PHY_BB_THERM_ADC_4_B0_LATEST_VOLT_VALUE_0_MASK) >> PHY_BB_THERM_ADC_4_B0_LATEST_VOLT_VALUE_0_LSB) #define PHY_BB_THERM_ADC_4_B0_LATEST_VOLT_VALUE_0_SET(x) (((0 | (x)) << PHY_BB_THERM_ADC_4_B0_LATEST_VOLT_VALUE_0_LSB) & PHY_BB_THERM_ADC_4_B0_LATEST_VOLT_VALUE_0_MASK) #define PHY_BB_THERM_ADC_4_B0_LATEST_VOLT_VALUE_0_RESET 0x0 #define PHY_BB_THERM_ADC_4_B0_LATEST_THERM_VALUE_0_LSB 0 #define PHY_BB_THERM_ADC_4_B0_LATEST_THERM_VALUE_0_MSB 7 #define PHY_BB_THERM_ADC_4_B0_LATEST_THERM_VALUE_0_MASK 0xff #define PHY_BB_THERM_ADC_4_B0_LATEST_THERM_VALUE_0_GET(x) (((x) & PHY_BB_THERM_ADC_4_B0_LATEST_THERM_VALUE_0_MASK) >> PHY_BB_THERM_ADC_4_B0_LATEST_THERM_VALUE_0_LSB) #define PHY_BB_THERM_ADC_4_B0_LATEST_THERM_VALUE_0_SET(x) (((0 | (x)) << PHY_BB_THERM_ADC_4_B0_LATEST_THERM_VALUE_0_LSB) & PHY_BB_THERM_ADC_4_B0_LATEST_THERM_VALUE_0_MASK) #define PHY_BB_THERM_ADC_4_B0_LATEST_THERM_VALUE_0_RESET 0x0 #define PHY_BB_THERM_ADC_4_B0_ADDRESS (0x254 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_THERM_ADC_4_B0_RSTMASK 0xffffff #define PHY_BB_THERM_ADC_4_B0_RESET 0x0 // 0x258 (PHY_BB_TX_FORCED_GAIN) #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB 11 #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MSB 11 #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK 0x800 #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_GET(x) (((x) & PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK) >> PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB) #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_SET(x) (((0 | (x)) << PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB) & PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK) #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_RESET 0x0 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB 7 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MSB 10 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK 0x780 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_GET(x) (((x) & PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK) >> PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB) #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_SET(x) (((0 | (x)) << PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB) & PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK) #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_RESET 0x0 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB 5 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MSB 6 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK 0x60 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_GET(x) (((x) & PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK) >> PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB) #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_SET(x) (((0 | (x)) << PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB) & PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK) #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_RESET 0x0 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB 1 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MSB 4 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK 0x1e #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_GET(x) (((x) & PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK) >> PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB) #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_SET(x) (((0 | (x)) << PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB) & PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK) #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_RESET 0x0 #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB 0 #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MSB 0 #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK 0x1 #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_GET(x) (((x) & PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK) >> PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB) #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_SET(x) (((0 | (x)) << PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB) & PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK) #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_RESET 0x0 #define PHY_BB_TX_FORCED_GAIN_ADDRESS (0x258 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TX_FORCED_GAIN_RSTMASK 0xfff #define PHY_BB_TX_FORCED_GAIN_RESET 0x0 // 0x25c (PHY_BB_TPC_STAT_0_B0) #define PHY_BB_TPC_STAT_0_B0_LATEST_DC_VALUE_0_LSB 17 #define PHY_BB_TPC_STAT_0_B0_LATEST_DC_VALUE_0_MSB 25 #define PHY_BB_TPC_STAT_0_B0_LATEST_DC_VALUE_0_MASK 0x3fe0000 #define PHY_BB_TPC_STAT_0_B0_LATEST_DC_VALUE_0_GET(x) (((x) & PHY_BB_TPC_STAT_0_B0_LATEST_DC_VALUE_0_MASK) >> PHY_BB_TPC_STAT_0_B0_LATEST_DC_VALUE_0_LSB) #define PHY_BB_TPC_STAT_0_B0_LATEST_DC_VALUE_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_0_B0_LATEST_DC_VALUE_0_LSB) & PHY_BB_TPC_STAT_0_B0_LATEST_DC_VALUE_0_MASK) #define PHY_BB_TPC_STAT_0_B0_LATEST_DC_VALUE_0_RESET 0x0 #define PHY_BB_TPC_STAT_0_B0_PDACC_AVG_OUT_0_LSB 9 #define PHY_BB_TPC_STAT_0_B0_PDACC_AVG_OUT_0_MSB 16 #define PHY_BB_TPC_STAT_0_B0_PDACC_AVG_OUT_0_MASK 0x1fe00 #define PHY_BB_TPC_STAT_0_B0_PDACC_AVG_OUT_0_GET(x) (((x) & PHY_BB_TPC_STAT_0_B0_PDACC_AVG_OUT_0_MASK) >> PHY_BB_TPC_STAT_0_B0_PDACC_AVG_OUT_0_LSB) #define PHY_BB_TPC_STAT_0_B0_PDACC_AVG_OUT_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_0_B0_PDACC_AVG_OUT_0_LSB) & PHY_BB_TPC_STAT_0_B0_PDACC_AVG_OUT_0_MASK) #define PHY_BB_TPC_STAT_0_B0_PDACC_AVG_OUT_0_RESET 0x0 #define PHY_BB_TPC_STAT_0_B0_MEAS_PWR_OUT_0_LSB 0 #define PHY_BB_TPC_STAT_0_B0_MEAS_PWR_OUT_0_MSB 8 #define PHY_BB_TPC_STAT_0_B0_MEAS_PWR_OUT_0_MASK 0x1ff #define PHY_BB_TPC_STAT_0_B0_MEAS_PWR_OUT_0_GET(x) (((x) & PHY_BB_TPC_STAT_0_B0_MEAS_PWR_OUT_0_MASK) >> PHY_BB_TPC_STAT_0_B0_MEAS_PWR_OUT_0_LSB) #define PHY_BB_TPC_STAT_0_B0_MEAS_PWR_OUT_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_0_B0_MEAS_PWR_OUT_0_LSB) & PHY_BB_TPC_STAT_0_B0_MEAS_PWR_OUT_0_MASK) #define PHY_BB_TPC_STAT_0_B0_MEAS_PWR_OUT_0_RESET 0x0 #define PHY_BB_TPC_STAT_0_B0_ADDRESS (0x25c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_STAT_0_B0_RSTMASK 0x3ffffff #define PHY_BB_TPC_STAT_0_B0_RESET 0x0 // 0x260 (PHY_BB_TPC_STAT_1_B0) #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_MID_0_LSB 16 #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_MID_0_MSB 23 #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_MID_0_MASK 0xff0000 #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_MID_0_GET(x) (((x) & PHY_BB_TPC_STAT_1_B0_GAIN_MISS_MID_0_MASK) >> PHY_BB_TPC_STAT_1_B0_GAIN_MISS_MID_0_LSB) #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_MID_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_1_B0_GAIN_MISS_MID_0_LSB) & PHY_BB_TPC_STAT_1_B0_GAIN_MISS_MID_0_MASK) #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_MID_0_RESET 0x0 #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_HIGH_0_LSB 8 #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_HIGH_0_MSB 15 #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_HIGH_0_MASK 0xff00 #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_HIGH_0_GET(x) (((x) & PHY_BB_TPC_STAT_1_B0_GAIN_MISS_HIGH_0_MASK) >> PHY_BB_TPC_STAT_1_B0_GAIN_MISS_HIGH_0_LSB) #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_HIGH_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_1_B0_GAIN_MISS_HIGH_0_LSB) & PHY_BB_TPC_STAT_1_B0_GAIN_MISS_HIGH_0_MASK) #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_HIGH_0_RESET 0x0 #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_LOW_0_LSB 0 #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_LOW_0_MSB 7 #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_LOW_0_MASK 0xff #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_LOW_0_GET(x) (((x) & PHY_BB_TPC_STAT_1_B0_GAIN_MISS_LOW_0_MASK) >> PHY_BB_TPC_STAT_1_B0_GAIN_MISS_LOW_0_LSB) #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_LOW_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_1_B0_GAIN_MISS_LOW_0_LSB) & PHY_BB_TPC_STAT_1_B0_GAIN_MISS_LOW_0_MASK) #define PHY_BB_TPC_STAT_1_B0_GAIN_MISS_LOW_0_RESET 0x0 #define PHY_BB_TPC_STAT_1_B0_ADDRESS (0x260 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_STAT_1_B0_RSTMASK 0xffffff #define PHY_BB_TPC_STAT_1_B0_RESET 0x0 // 0x264 (PHY_BB_TPC_STAT_2_B0) #define PHY_BB_TPC_STAT_2_B0_ANA_SET_NDP_0_LSB 18 #define PHY_BB_TPC_STAT_2_B0_ANA_SET_NDP_0_MSB 20 #define PHY_BB_TPC_STAT_2_B0_ANA_SET_NDP_0_MASK 0x1c0000 #define PHY_BB_TPC_STAT_2_B0_ANA_SET_NDP_0_GET(x) (((x) & PHY_BB_TPC_STAT_2_B0_ANA_SET_NDP_0_MASK) >> PHY_BB_TPC_STAT_2_B0_ANA_SET_NDP_0_LSB) #define PHY_BB_TPC_STAT_2_B0_ANA_SET_NDP_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_2_B0_ANA_SET_NDP_0_LSB) & PHY_BB_TPC_STAT_2_B0_ANA_SET_NDP_0_MASK) #define PHY_BB_TPC_STAT_2_B0_ANA_SET_NDP_0_RESET 0x0 #define PHY_BB_TPC_STAT_2_B0_CLPC_ERR_MU_0_LSB 8 #define PHY_BB_TPC_STAT_2_B0_CLPC_ERR_MU_0_MSB 17 #define PHY_BB_TPC_STAT_2_B0_CLPC_ERR_MU_0_MASK 0x3ff00 #define PHY_BB_TPC_STAT_2_B0_CLPC_ERR_MU_0_GET(x) (((x) & PHY_BB_TPC_STAT_2_B0_CLPC_ERR_MU_0_MASK) >> PHY_BB_TPC_STAT_2_B0_CLPC_ERR_MU_0_LSB) #define PHY_BB_TPC_STAT_2_B0_CLPC_ERR_MU_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_2_B0_CLPC_ERR_MU_0_LSB) & PHY_BB_TPC_STAT_2_B0_CLPC_ERR_MU_0_MASK) #define PHY_BB_TPC_STAT_2_B0_CLPC_ERR_MU_0_RESET 0x0 #define PHY_BB_TPC_STAT_2_B0_DAC_GAIN_NDP_0_LSB 0 #define PHY_BB_TPC_STAT_2_B0_DAC_GAIN_NDP_0_MSB 7 #define PHY_BB_TPC_STAT_2_B0_DAC_GAIN_NDP_0_MASK 0xff #define PHY_BB_TPC_STAT_2_B0_DAC_GAIN_NDP_0_GET(x) (((x) & PHY_BB_TPC_STAT_2_B0_DAC_GAIN_NDP_0_MASK) >> PHY_BB_TPC_STAT_2_B0_DAC_GAIN_NDP_0_LSB) #define PHY_BB_TPC_STAT_2_B0_DAC_GAIN_NDP_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_2_B0_DAC_GAIN_NDP_0_LSB) & PHY_BB_TPC_STAT_2_B0_DAC_GAIN_NDP_0_MASK) #define PHY_BB_TPC_STAT_2_B0_DAC_GAIN_NDP_0_RESET 0x0 #define PHY_BB_TPC_STAT_2_B0_ADDRESS (0x264 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_STAT_2_B0_RSTMASK 0x1fffff #define PHY_BB_TPC_STAT_2_B0_RESET 0x0 // 0x268 (PHY_BB_TPC_MAX_MU_DAC) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM4_LSB 24 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM4_MSB 29 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM4_MASK 0x3f000000 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM4_GET(x) (((x) & PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM4_MASK) >> PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM4_LSB) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM4_SET(x) (((0 | (x)) << PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM4_LSB) & PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM4_MASK) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM4_RESET 0x0 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM3_LSB 18 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM3_MSB 23 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM3_MASK 0xfc0000 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM3_GET(x) (((x) & PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM3_MASK) >> PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM3_LSB) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM3_SET(x) (((0 | (x)) << PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM3_LSB) & PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM3_MASK) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM3_RESET 0x0 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM2_LSB 12 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM2_MSB 17 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM2_MASK 0x3f000 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM2_GET(x) (((x) & PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM2_MASK) >> PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM2_LSB) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM2_SET(x) (((0 | (x)) << PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM2_LSB) & PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM2_MASK) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM2_RESET 0x0 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM1_LSB 6 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM1_MSB 11 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM1_MASK 0xfc0 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM1_GET(x) (((x) & PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM1_MASK) >> PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM1_LSB) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM1_SET(x) (((0 | (x)) << PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM1_LSB) & PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM1_MASK) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM1_RESET 0x0 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM0_LSB 0 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM0_MSB 5 #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM0_MASK 0x3f #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM0_GET(x) (((x) & PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM0_MASK) >> PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM0_LSB) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM0_SET(x) (((0 | (x)) << PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM0_LSB) & PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM0_MASK) #define PHY_BB_TPC_MAX_MU_DAC_MAX_MU_DAC_BO_QAM0_RESET 0x0 #define PHY_BB_TPC_MAX_MU_DAC_ADDRESS (0x268 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_MAX_MU_DAC_RSTMASK 0x3fffffff #define PHY_BB_TPC_MAX_MU_DAC_RESET 0x0 // 0x26c (PHY_BB_TPC_MIN_MU_DAC) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM4_LSB 24 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM4_MSB 29 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM4_MASK 0x3f000000 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM4_GET(x) (((x) & PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM4_MASK) >> PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM4_LSB) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM4_SET(x) (((0 | (x)) << PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM4_LSB) & PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM4_MASK) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM4_RESET 0x0 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM3_LSB 18 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM3_MSB 23 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM3_MASK 0xfc0000 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM3_GET(x) (((x) & PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM3_MASK) >> PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM3_LSB) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM3_SET(x) (((0 | (x)) << PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM3_LSB) & PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM3_MASK) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM3_RESET 0x0 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM2_LSB 12 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM2_MSB 17 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM2_MASK 0x3f000 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM2_GET(x) (((x) & PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM2_MASK) >> PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM2_LSB) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM2_SET(x) (((0 | (x)) << PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM2_LSB) & PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM2_MASK) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM2_RESET 0x0 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM1_LSB 6 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM1_MSB 11 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM1_MASK 0xfc0 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM1_GET(x) (((x) & PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM1_MASK) >> PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM1_LSB) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM1_SET(x) (((0 | (x)) << PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM1_LSB) & PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM1_MASK) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM1_RESET 0x0 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM0_LSB 0 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM0_MSB 5 #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM0_MASK 0x3f #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM0_GET(x) (((x) & PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM0_MASK) >> PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM0_LSB) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM0_SET(x) (((0 | (x)) << PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM0_LSB) & PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM0_MASK) #define PHY_BB_TPC_MIN_MU_DAC_MIN_MU_DAC_BO_QAM0_RESET 0x0 #define PHY_BB_TPC_MIN_MU_DAC_ADDRESS (0x26c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_MIN_MU_DAC_RSTMASK 0x3fffffff #define PHY_BB_TPC_MIN_MU_DAC_RESET 0x0 // 0x270 (PHY_BB_TPC_MU_CTRL) #define PHY_BB_TPC_MU_CTRL_TPC_MU_ENABLE_LSB 13 #define PHY_BB_TPC_MU_CTRL_TPC_MU_ENABLE_MSB 13 #define PHY_BB_TPC_MU_CTRL_TPC_MU_ENABLE_MASK 0x2000 #define PHY_BB_TPC_MU_CTRL_TPC_MU_ENABLE_GET(x) (((x) & PHY_BB_TPC_MU_CTRL_TPC_MU_ENABLE_MASK) >> PHY_BB_TPC_MU_CTRL_TPC_MU_ENABLE_LSB) #define PHY_BB_TPC_MU_CTRL_TPC_MU_ENABLE_SET(x) (((0 | (x)) << PHY_BB_TPC_MU_CTRL_TPC_MU_ENABLE_LSB) & PHY_BB_TPC_MU_CTRL_TPC_MU_ENABLE_MASK) #define PHY_BB_TPC_MU_CTRL_TPC_MU_ENABLE_RESET 0x0 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_EN_LSB 12 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_EN_MSB 12 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_EN_MASK 0x1000 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_EN_GET(x) (((x) & PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_EN_MASK) >> PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_EN_LSB) #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_EN_SET(x) (((0 | (x)) << PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_EN_LSB) & PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_EN_MASK) #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_EN_RESET 0x0 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_LSB 6 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_MSB 11 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_MASK 0xfc0 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_GET(x) (((x) & PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_MASK) >> PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_LSB) #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_SET(x) (((0 | (x)) << PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_LSB) & PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_MASK) #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_CLIP_RESET 0x20 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_SCALE_LSB 0 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_SCALE_MSB 5 #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_SCALE_MASK 0x3f #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_SCALE_GET(x) (((x) & PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_SCALE_MASK) >> PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_SCALE_LSB) #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_SCALE_SET(x) (((0 | (x)) << PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_SCALE_LSB) & PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_SCALE_MASK) #define PHY_BB_TPC_MU_CTRL_MU_TPC_CL_ERR_SCALE_RESET 0x20 #define PHY_BB_TPC_MU_CTRL_ADDRESS (0x270 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_MU_CTRL_RSTMASK 0x3fff #define PHY_BB_TPC_MU_CTRL_RESET 0x820 // 0x274 (PHY_BB_TPC_STAT_3_B0) #define PHY_BB_TPC_STAT_3_B0_LATEST_GLUT_SET_0_LSB 18 #define PHY_BB_TPC_STAT_3_B0_LATEST_GLUT_SET_0_MSB 20 #define PHY_BB_TPC_STAT_3_B0_LATEST_GLUT_SET_0_MASK 0x1c0000 #define PHY_BB_TPC_STAT_3_B0_LATEST_GLUT_SET_0_GET(x) (((x) & PHY_BB_TPC_STAT_3_B0_LATEST_GLUT_SET_0_MASK) >> PHY_BB_TPC_STAT_3_B0_LATEST_GLUT_SET_0_LSB) #define PHY_BB_TPC_STAT_3_B0_LATEST_GLUT_SET_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_3_B0_LATEST_GLUT_SET_0_LSB) & PHY_BB_TPC_STAT_3_B0_LATEST_GLUT_SET_0_MASK) #define PHY_BB_TPC_STAT_3_B0_LATEST_GLUT_SET_0_RESET 0x0 #define PHY_BB_TPC_STAT_3_B0_LATEST_CLPC_ERR_0_LSB 8 #define PHY_BB_TPC_STAT_3_B0_LATEST_CLPC_ERR_0_MSB 17 #define PHY_BB_TPC_STAT_3_B0_LATEST_CLPC_ERR_0_MASK 0x3ff00 #define PHY_BB_TPC_STAT_3_B0_LATEST_CLPC_ERR_0_GET(x) (((x) & PHY_BB_TPC_STAT_3_B0_LATEST_CLPC_ERR_0_MASK) >> PHY_BB_TPC_STAT_3_B0_LATEST_CLPC_ERR_0_LSB) #define PHY_BB_TPC_STAT_3_B0_LATEST_CLPC_ERR_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_3_B0_LATEST_CLPC_ERR_0_LSB) & PHY_BB_TPC_STAT_3_B0_LATEST_CLPC_ERR_0_MASK) #define PHY_BB_TPC_STAT_3_B0_LATEST_CLPC_ERR_0_RESET 0x0 #define PHY_BB_TPC_STAT_3_B0_LATEST_DAC_GAIN_0_LSB 0 #define PHY_BB_TPC_STAT_3_B0_LATEST_DAC_GAIN_0_MSB 7 #define PHY_BB_TPC_STAT_3_B0_LATEST_DAC_GAIN_0_MASK 0xff #define PHY_BB_TPC_STAT_3_B0_LATEST_DAC_GAIN_0_GET(x) (((x) & PHY_BB_TPC_STAT_3_B0_LATEST_DAC_GAIN_0_MASK) >> PHY_BB_TPC_STAT_3_B0_LATEST_DAC_GAIN_0_LSB) #define PHY_BB_TPC_STAT_3_B0_LATEST_DAC_GAIN_0_SET(x) (((0 | (x)) << PHY_BB_TPC_STAT_3_B0_LATEST_DAC_GAIN_0_LSB) & PHY_BB_TPC_STAT_3_B0_LATEST_DAC_GAIN_0_MASK) #define PHY_BB_TPC_STAT_3_B0_LATEST_DAC_GAIN_0_RESET 0x0 #define PHY_BB_TPC_STAT_3_B0_ADDRESS (0x274 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_STAT_3_B0_RSTMASK 0x1fffff #define PHY_BB_TPC_STAT_3_B0_RESET 0x0 // 0x278 (PHY_BB_TPC_20) #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM3_LSB 21 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM3_MSB 27 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM3_MASK 0xfe00000 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM3_GET(x) (((x) & PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM3_MASK) >> PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM3_LSB) #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM3_SET(x) (((0 | (x)) << PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM3_LSB) & PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM3_MASK) #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM3_RESET 0x0 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM2_LSB 14 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM2_MSB 20 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM2_MASK 0x1fc000 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM2_GET(x) (((x) & PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM2_MASK) >> PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM2_LSB) #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM2_SET(x) (((0 | (x)) << PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM2_LSB) & PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM2_MASK) #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM2_RESET 0x0 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM1_LSB 7 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM1_MSB 13 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM1_MASK 0x3f80 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM1_GET(x) (((x) & PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM1_MASK) >> PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM1_LSB) #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM1_SET(x) (((0 | (x)) << PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM1_LSB) & PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM1_MASK) #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM1_RESET 0x0 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM0_LSB 0 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM0_MSB 6 #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM0_MASK 0x7f #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM0_GET(x) (((x) & PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM0_MASK) >> PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM0_LSB) #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM0_SET(x) (((0 | (x)) << PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM0_LSB) & PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM0_MASK) #define PHY_BB_TPC_20_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM0_RESET 0x0 #define PHY_BB_TPC_20_ADDRESS (0x278 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_20_RSTMASK 0xfffffff #define PHY_BB_TPC_20_RESET 0x0 // 0x27c (PHY_BB_TPC_21) #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM6_LSB 14 #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM6_MSB 20 #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM6_MASK 0x1fc000 #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM6_GET(x) (((x) & PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM6_MASK) >> PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM6_LSB) #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM6_SET(x) (((0 | (x)) << PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM6_LSB) & PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM6_MASK) #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM6_RESET 0x0 #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM5_LSB 7 #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM5_MSB 13 #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM5_MASK 0x3f80 #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM5_GET(x) (((x) & PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM5_MASK) >> PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM5_LSB) #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM5_SET(x) (((0 | (x)) << PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM5_LSB) & PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM5_MASK) #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM5_RESET 0x0 #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM4_LSB 0 #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM4_MSB 6 #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM4_MASK 0x7f #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM4_GET(x) (((x) & PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM4_MASK) >> PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM4_LSB) #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM4_SET(x) (((0 | (x)) << PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM4_LSB) & PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM4_MASK) #define PHY_BB_TPC_21_HEAVY_CLIP_COMP_FACTOR_NONHTDUP40_QAM4_RESET 0x0 #define PHY_BB_TPC_21_ADDRESS (0x27c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_21_RSTMASK 0x1fffff #define PHY_BB_TPC_21_RESET 0x0 // 0x280 (PHY_BB_TPC_22) #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM3_LSB 21 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM3_MSB 27 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM3_MASK 0xfe00000 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM3_GET(x) (((x) & PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM3_MASK) >> PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM3_LSB) #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM3_SET(x) (((0 | (x)) << PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM3_LSB) & PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM3_MASK) #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM3_RESET 0x0 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM2_LSB 14 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM2_MSB 20 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM2_MASK 0x1fc000 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM2_GET(x) (((x) & PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM2_MASK) >> PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM2_LSB) #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM2_SET(x) (((0 | (x)) << PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM2_LSB) & PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM2_MASK) #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM2_RESET 0x0 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM1_LSB 7 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM1_MSB 13 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM1_MASK 0x3f80 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM1_GET(x) (((x) & PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM1_MASK) >> PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM1_LSB) #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM1_SET(x) (((0 | (x)) << PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM1_LSB) & PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM1_MASK) #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM1_RESET 0x0 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM0_LSB 0 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM0_MSB 6 #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM0_MASK 0x7f #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM0_GET(x) (((x) & PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM0_MASK) >> PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM0_LSB) #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM0_SET(x) (((0 | (x)) << PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM0_LSB) & PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM0_MASK) #define PHY_BB_TPC_22_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM0_RESET 0x0 #define PHY_BB_TPC_22_ADDRESS (0x280 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_22_RSTMASK 0xfffffff #define PHY_BB_TPC_22_RESET 0x0 // 0x284 (PHY_BB_TPC_23) #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM6_LSB 14 #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM6_MSB 20 #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM6_MASK 0x1fc000 #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM6_GET(x) (((x) & PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM6_MASK) >> PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM6_LSB) #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM6_SET(x) (((0 | (x)) << PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM6_LSB) & PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM6_MASK) #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM6_RESET 0x0 #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM5_LSB 7 #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM5_MSB 13 #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM5_MASK 0x3f80 #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM5_GET(x) (((x) & PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM5_MASK) >> PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM5_LSB) #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM5_SET(x) (((0 | (x)) << PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM5_LSB) & PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM5_MASK) #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM5_RESET 0x0 #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM4_LSB 0 #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM4_MSB 6 #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM4_MASK 0x7f #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM4_GET(x) (((x) & PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM4_MASK) >> PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM4_LSB) #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM4_SET(x) (((0 | (x)) << PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM4_LSB) & PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM4_MASK) #define PHY_BB_TPC_23_HEAVY_CLIP_COMP_FACTOR_NONHTDUP80_QAM4_RESET 0x0 #define PHY_BB_TPC_23_ADDRESS (0x284 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_23_RSTMASK 0x1fffff #define PHY_BB_TPC_23_RESET 0x0 // 0x380 (PHY_BB_RRT_CTRL) #define PHY_BB_RRT_CTRL_USE_MASK_ONLY_LSB 8 #define PHY_BB_RRT_CTRL_USE_MASK_ONLY_MSB 8 #define PHY_BB_RRT_CTRL_USE_MASK_ONLY_MASK 0x100 #define PHY_BB_RRT_CTRL_USE_MASK_ONLY_GET(x) (((x) & PHY_BB_RRT_CTRL_USE_MASK_ONLY_MASK) >> PHY_BB_RRT_CTRL_USE_MASK_ONLY_LSB) #define PHY_BB_RRT_CTRL_USE_MASK_ONLY_SET(x) (((0 | (x)) << PHY_BB_RRT_CTRL_USE_MASK_ONLY_LSB) & PHY_BB_RRT_CTRL_USE_MASK_ONLY_MASK) #define PHY_BB_RRT_CTRL_USE_MASK_ONLY_RESET 0x0 #define PHY_BB_RRT_CTRL_FORCE_RADIO_RESTORE_LSB 7 #define PHY_BB_RRT_CTRL_FORCE_RADIO_RESTORE_MSB 7 #define PHY_BB_RRT_CTRL_FORCE_RADIO_RESTORE_MASK 0x80 #define PHY_BB_RRT_CTRL_FORCE_RADIO_RESTORE_GET(x) (((x) & PHY_BB_RRT_CTRL_FORCE_RADIO_RESTORE_MASK) >> PHY_BB_RRT_CTRL_FORCE_RADIO_RESTORE_LSB) #define PHY_BB_RRT_CTRL_FORCE_RADIO_RESTORE_SET(x) (((0 | (x)) << PHY_BB_RRT_CTRL_FORCE_RADIO_RESTORE_LSB) & PHY_BB_RRT_CTRL_FORCE_RADIO_RESTORE_MASK) #define PHY_BB_RRT_CTRL_FORCE_RADIO_RESTORE_RESET 0x0 #define PHY_BB_RRT_CTRL_RESTORE_MASK_LSB 1 #define PHY_BB_RRT_CTRL_RESTORE_MASK_MSB 6 #define PHY_BB_RRT_CTRL_RESTORE_MASK_MASK 0x7e #define PHY_BB_RRT_CTRL_RESTORE_MASK_GET(x) (((x) & PHY_BB_RRT_CTRL_RESTORE_MASK_MASK) >> PHY_BB_RRT_CTRL_RESTORE_MASK_LSB) #define PHY_BB_RRT_CTRL_RESTORE_MASK_SET(x) (((0 | (x)) << PHY_BB_RRT_CTRL_RESTORE_MASK_LSB) & PHY_BB_RRT_CTRL_RESTORE_MASK_MASK) #define PHY_BB_RRT_CTRL_RESTORE_MASK_RESET 0x3c #define PHY_BB_RRT_CTRL_ENA_RADIO_RETENTION_LSB 0 #define PHY_BB_RRT_CTRL_ENA_RADIO_RETENTION_MSB 0 #define PHY_BB_RRT_CTRL_ENA_RADIO_RETENTION_MASK 0x1 #define PHY_BB_RRT_CTRL_ENA_RADIO_RETENTION_GET(x) (((x) & PHY_BB_RRT_CTRL_ENA_RADIO_RETENTION_MASK) >> PHY_BB_RRT_CTRL_ENA_RADIO_RETENTION_LSB) #define PHY_BB_RRT_CTRL_ENA_RADIO_RETENTION_SET(x) (((0 | (x)) << PHY_BB_RRT_CTRL_ENA_RADIO_RETENTION_LSB) & PHY_BB_RRT_CTRL_ENA_RADIO_RETENTION_MASK) #define PHY_BB_RRT_CTRL_ENA_RADIO_RETENTION_RESET 0x0 #define PHY_BB_RRT_CTRL_ADDRESS (0x380 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RRT_CTRL_RSTMASK 0x1ff #define PHY_BB_RRT_CTRL_RESET 0x78 // 0x384 (PHY_BB_RRT_TABLE_SW_INTF_B0) #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_OFFSET_0_LSB 5 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_OFFSET_0_MSB 5 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_OFFSET_0_MASK 0x20 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_OFFSET_0_GET(x) (((x) & PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_OFFSET_0_MASK) >> PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_OFFSET_0_LSB) #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_OFFSET_0_SET(x) (((0 | (x)) << PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_OFFSET_0_LSB) & PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_OFFSET_0_MASK) #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_OFFSET_0_RESET 0x0 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_0_LSB 2 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_0_MSB 4 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_0_MASK 0x1c #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_0_GET(x) (((x) & PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_0_MASK) >> PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_0_LSB) #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_0_SET(x) (((0 | (x)) << PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_0_LSB) & PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_0_MASK) #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ADDR_0_RESET 0x0 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_WRITE_0_LSB 1 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_WRITE_0_MSB 1 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_WRITE_0_MASK 0x2 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_WRITE_0_GET(x) (((x) & PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_WRITE_0_MASK) >> PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_WRITE_0_LSB) #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_WRITE_0_SET(x) (((0 | (x)) << PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_WRITE_0_LSB) & PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_WRITE_0_MASK) #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_WRITE_0_RESET 0x0 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ACCESS_0_LSB 0 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ACCESS_0_MSB 0 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ACCESS_0_MASK 0x1 #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ACCESS_0_GET(x) (((x) & PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ACCESS_0_MASK) >> PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ACCESS_0_LSB) #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ACCESS_0_SET(x) (((0 | (x)) << PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ACCESS_0_LSB) & PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ACCESS_0_MASK) #define PHY_BB_RRT_TABLE_SW_INTF_B0_SW_RRT_TABLE_ACCESS_0_RESET 0x0 #define PHY_BB_RRT_TABLE_SW_INTF_B0_ADDRESS (0x384 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RRT_TABLE_SW_INTF_B0_RSTMASK 0x3f #define PHY_BB_RRT_TABLE_SW_INTF_B0_RESET 0x0 // 0x388 (PHY_BB_RRT_TABLE_SW_INTF_1_B0) #define PHY_BB_RRT_TABLE_SW_INTF_1_B0_SW_RRT_TABLE_DATA_0_LSB 0 #define PHY_BB_RRT_TABLE_SW_INTF_1_B0_SW_RRT_TABLE_DATA_0_MSB 31 #define PHY_BB_RRT_TABLE_SW_INTF_1_B0_SW_RRT_TABLE_DATA_0_MASK 0xffffffff #define PHY_BB_RRT_TABLE_SW_INTF_1_B0_SW_RRT_TABLE_DATA_0_GET(x) (((x) & PHY_BB_RRT_TABLE_SW_INTF_1_B0_SW_RRT_TABLE_DATA_0_MASK) >> PHY_BB_RRT_TABLE_SW_INTF_1_B0_SW_RRT_TABLE_DATA_0_LSB) #define PHY_BB_RRT_TABLE_SW_INTF_1_B0_SW_RRT_TABLE_DATA_0_SET(x) (((0 | (x)) << PHY_BB_RRT_TABLE_SW_INTF_1_B0_SW_RRT_TABLE_DATA_0_LSB) & PHY_BB_RRT_TABLE_SW_INTF_1_B0_SW_RRT_TABLE_DATA_0_MASK) #define PHY_BB_RRT_TABLE_SW_INTF_1_B0_SW_RRT_TABLE_DATA_0_RESET 0x0 #define PHY_BB_RRT_TABLE_SW_INTF_1_B0_ADDRESS (0x388 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RRT_TABLE_SW_INTF_1_B0_RSTMASK 0xffffffff #define PHY_BB_RRT_TABLE_SW_INTF_1_B0_RESET 0x0 // 0x444 (PHY_BB_TXIQCAL_CONTROL_0) #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_TXIQ_CALIBRATE_LSB 31 #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_TXIQ_CALIBRATE_MSB 31 #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_TXIQ_CALIBRATE_MASK 0x80000000 #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_TXIQ_CALIBRATE_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_0_ENABLE_TXIQ_CALIBRATE_MASK) >> PHY_BB_TXIQCAL_CONTROL_0_ENABLE_TXIQ_CALIBRATE_LSB) #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_TXIQ_CALIBRATE_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_0_ENABLE_TXIQ_CALIBRATE_LSB) & PHY_BB_TXIQCAL_CONTROL_0_ENABLE_TXIQ_CALIBRATE_MASK) #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_TXIQ_CALIBRATE_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_COMBINED_CARR_IQ_CAL_LSB 30 #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_COMBINED_CARR_IQ_CAL_MSB 30 #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_COMBINED_CARR_IQ_CAL_MASK 0x40000000 #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_COMBINED_CARR_IQ_CAL_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_0_ENABLE_COMBINED_CARR_IQ_CAL_MASK) >> PHY_BB_TXIQCAL_CONTROL_0_ENABLE_COMBINED_CARR_IQ_CAL_LSB) #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_COMBINED_CARR_IQ_CAL_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_0_ENABLE_COMBINED_CARR_IQ_CAL_LSB) & PHY_BB_TXIQCAL_CONTROL_0_ENABLE_COMBINED_CARR_IQ_CAL_MASK) #define PHY_BB_TXIQCAL_CONTROL_0_ENABLE_COMBINED_CARR_IQ_CAL_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB 23 #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MSB 29 #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK 0x3f800000 #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK) >> PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB) #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB) & PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK) #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_RESET 0x20 #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB 19 #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MSB 22 #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK 0x780000 #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK) >> PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB) #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB) & PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK) #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB 13 #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MSB 18 #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK 0x7e000 #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK) >> PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB) #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB) & PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK) #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_RESET 0x22 #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB 7 #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MSB 12 #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK 0x1f80 #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK) >> PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB) #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB) & PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK) #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB 1 #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MSB 6 #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK 0x7e #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK) >> PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB) #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB) & PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK) #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_0_ADDRESS (0x444 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TXIQCAL_CONTROL_0_RSTMASK 0xfffffffe #define PHY_BB_TXIQCAL_CONTROL_0_RESET 0x10044000 // 0x448 (PHY_BB_TXIQCAL_CONTROL_1) #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_SEL_LSB 30 #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_SEL_MSB 31 #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_SEL_MASK 0xc0000000 #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_SEL_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_SEL_MASK) >> PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_SEL_LSB) #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_SEL_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_SEL_LSB) & PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_SEL_MASK) #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_SEL_RESET 0x1 #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_LEN_LSB 29 #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_LEN_MSB 29 #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_LEN_MASK 0x20000000 #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_LEN_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_LEN_MASK) >> PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_LEN_LSB) #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_LEN_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_LEN_LSB) & PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_LEN_MASK) #define PHY_BB_TXIQCAL_CONTROL_1_ADC_SAT_LEN_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_1_TXCAL_LOOPBACK_MODE_LSB 28 #define PHY_BB_TXIQCAL_CONTROL_1_TXCAL_LOOPBACK_MODE_MSB 28 #define PHY_BB_TXIQCAL_CONTROL_1_TXCAL_LOOPBACK_MODE_MASK 0x10000000 #define PHY_BB_TXIQCAL_CONTROL_1_TXCAL_LOOPBACK_MODE_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_1_TXCAL_LOOPBACK_MODE_MASK) >> PHY_BB_TXIQCAL_CONTROL_1_TXCAL_LOOPBACK_MODE_LSB) #define PHY_BB_TXIQCAL_CONTROL_1_TXCAL_LOOPBACK_MODE_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_1_TXCAL_LOOPBACK_MODE_LSB) & PHY_BB_TXIQCAL_CONTROL_1_TXCAL_LOOPBACK_MODE_MASK) #define PHY_BB_TXIQCAL_CONTROL_1_TXCAL_LOOPBACK_MODE_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_1_IQCAL_DISABLE_MIXER_LSB 27 #define PHY_BB_TXIQCAL_CONTROL_1_IQCAL_DISABLE_MIXER_MSB 27 #define PHY_BB_TXIQCAL_CONTROL_1_IQCAL_DISABLE_MIXER_MASK 0x8000000 #define PHY_BB_TXIQCAL_CONTROL_1_IQCAL_DISABLE_MIXER_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_1_IQCAL_DISABLE_MIXER_MASK) >> PHY_BB_TXIQCAL_CONTROL_1_IQCAL_DISABLE_MIXER_LSB) #define PHY_BB_TXIQCAL_CONTROL_1_IQCAL_DISABLE_MIXER_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_1_IQCAL_DISABLE_MIXER_LSB) & PHY_BB_TXIQCAL_CONTROL_1_IQCAL_DISABLE_MIXER_MASK) #define PHY_BB_TXIQCAL_CONTROL_1_IQCAL_DISABLE_MIXER_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB 18 #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MSB 26 #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK 0x7fc0000 #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK) >> PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB) #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB) & PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK) #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_RESET 0x12 #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB 12 #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MSB 17 #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK 0x3f000 #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK) >> PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB) #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB) & PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK) #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_RESET 0x8 #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB 6 #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MSB 11 #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK 0xfc0 #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK) >> PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB) #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB) & PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK) #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_RESET 0x20 #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB 0 #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MSB 5 #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK 0x3f #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK) >> PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB) #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB) & PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK) #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_RESET 0x14 #define PHY_BB_TXIQCAL_CONTROL_1_ADDRESS (0x448 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TXIQCAL_CONTROL_1_RSTMASK 0xffffffff #define PHY_BB_TXIQCAL_CONTROL_1_RESET 0x40488814 // 0x44c (PHY_BB_TXIQCAL_CONTROL_2) #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_GC_CNT_LSB 28 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_GC_CNT_MSB 31 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_GC_CNT_MASK 0xf0000000 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_GC_CNT_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_GC_CNT_MASK) >> PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_GC_CNT_LSB) #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_GC_CNT_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_GC_CNT_LSB) & PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_GC_CNT_MASK) #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_GC_CNT_RESET 0x8 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MEAS_LEN_LSB 25 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MEAS_LEN_MSB 27 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MEAS_LEN_MASK 0xe000000 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MEAS_LEN_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MEAS_LEN_MASK) >> PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MEAS_LEN_LSB) #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MEAS_LEN_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MEAS_LEN_LSB) & PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MEAS_LEN_MASK) #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MEAS_LEN_RESET 0x2 #define PHY_BB_TXIQCAL_CONTROL_2_DITHER_CTL_LSB 22 #define PHY_BB_TXIQCAL_CONTROL_2_DITHER_CTL_MSB 24 #define PHY_BB_TXIQCAL_CONTROL_2_DITHER_CTL_MASK 0x1c00000 #define PHY_BB_TXIQCAL_CONTROL_2_DITHER_CTL_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_2_DITHER_CTL_MASK) >> PHY_BB_TXIQCAL_CONTROL_2_DITHER_CTL_LSB) #define PHY_BB_TXIQCAL_CONTROL_2_DITHER_CTL_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_2_DITHER_CTL_LSB) & PHY_BB_TXIQCAL_CONTROL_2_DITHER_CTL_MASK) #define PHY_BB_TXIQCAL_CONTROL_2_DITHER_CTL_RESET 0x4 #define PHY_BB_TXIQCAL_CONTROL_2_GAIN_UPDATE_DELAY_LSB 14 #define PHY_BB_TXIQCAL_CONTROL_2_GAIN_UPDATE_DELAY_MSB 21 #define PHY_BB_TXIQCAL_CONTROL_2_GAIN_UPDATE_DELAY_MASK 0x3fc000 #define PHY_BB_TXIQCAL_CONTROL_2_GAIN_UPDATE_DELAY_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_2_GAIN_UPDATE_DELAY_MASK) >> PHY_BB_TXIQCAL_CONTROL_2_GAIN_UPDATE_DELAY_LSB) #define PHY_BB_TXIQCAL_CONTROL_2_GAIN_UPDATE_DELAY_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_2_GAIN_UPDATE_DELAY_LSB) & PHY_BB_TXIQCAL_CONTROL_2_GAIN_UPDATE_DELAY_MASK) #define PHY_BB_TXIQCAL_CONTROL_2_GAIN_UPDATE_DELAY_RESET 0x27 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB 9 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MSB 13 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK 0x3e00 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK) >> PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB) #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB) & PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK) #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_RESET 0x1f #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB 4 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MSB 8 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK 0x1f0 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK) >> PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB) #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB) & PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK) #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_2_ADDRESS (0x44c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TXIQCAL_CONTROL_2_RSTMASK 0xfffffff0 #define PHY_BB_TXIQCAL_CONTROL_2_RESET 0x8509fe00 // 0x450 (PHY_BB_TXIQCAL_CONTROL_3) #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB 31 #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MSB 31 #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK 0x80000000 #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK) >> PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB) #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB) & PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK) #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB 26 #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MSB 30 #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK 0x7c000000 #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK) >> PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB) #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB) & PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK) #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_3_TXIQC_DC_BACKOFF_LSB 24 #define PHY_BB_TXIQCAL_CONTROL_3_TXIQC_DC_BACKOFF_MSB 25 #define PHY_BB_TXIQCAL_CONTROL_3_TXIQC_DC_BACKOFF_MASK 0x3000000 #define PHY_BB_TXIQCAL_CONTROL_3_TXIQC_DC_BACKOFF_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_3_TXIQC_DC_BACKOFF_MASK) >> PHY_BB_TXIQCAL_CONTROL_3_TXIQC_DC_BACKOFF_LSB) #define PHY_BB_TXIQCAL_CONTROL_3_TXIQC_DC_BACKOFF_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_3_TXIQC_DC_BACKOFF_LSB) & PHY_BB_TXIQCAL_CONTROL_3_TXIQC_DC_BACKOFF_MASK) #define PHY_BB_TXIQCAL_CONTROL_3_TXIQC_DC_BACKOFF_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB 22 #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MSB 23 #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK 0xc00000 #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK) >> PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB) #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB) & PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK) #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_RESET 0x1 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB 12 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MSB 21 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK 0x3ff000 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK) >> PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB) #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB) & PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK) #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_RESET 0x80 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB 6 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MSB 11 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK 0xfc0 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK) >> PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB) #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB) & PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK) #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_RESET 0x2e #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB 0 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MSB 5 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK 0x3f #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK) >> PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB) #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB) & PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK) #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_RESET 0x3e #define PHY_BB_TXIQCAL_CONTROL_3_ADDRESS (0x450 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TXIQCAL_CONTROL_3_RSTMASK 0xffffffff #define PHY_BB_TXIQCAL_CONTROL_3_RESET 0x480bbe // 0x454 (PHY_BB_TXIQCAL_CONTROL_4) #define PHY_BB_TXIQCAL_CONTROL_4_EN_RXCAL_TXGAIN_UPDATE_FIX_LSB 5 #define PHY_BB_TXIQCAL_CONTROL_4_EN_RXCAL_TXGAIN_UPDATE_FIX_MSB 5 #define PHY_BB_TXIQCAL_CONTROL_4_EN_RXCAL_TXGAIN_UPDATE_FIX_MASK 0x20 #define PHY_BB_TXIQCAL_CONTROL_4_EN_RXCAL_TXGAIN_UPDATE_FIX_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_4_EN_RXCAL_TXGAIN_UPDATE_FIX_MASK) >> PHY_BB_TXIQCAL_CONTROL_4_EN_RXCAL_TXGAIN_UPDATE_FIX_LSB) #define PHY_BB_TXIQCAL_CONTROL_4_EN_RXCAL_TXGAIN_UPDATE_FIX_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_4_EN_RXCAL_TXGAIN_UPDATE_FIX_LSB) & PHY_BB_TXIQCAL_CONTROL_4_EN_RXCAL_TXGAIN_UPDATE_FIX_MASK) #define PHY_BB_TXIQCAL_CONTROL_4_EN_RXCAL_TXGAIN_UPDATE_FIX_RESET 0x1 #define PHY_BB_TXIQCAL_CONTROL_4_DC_ODAC_LB_LUT_SEL_LSB 4 #define PHY_BB_TXIQCAL_CONTROL_4_DC_ODAC_LB_LUT_SEL_MSB 4 #define PHY_BB_TXIQCAL_CONTROL_4_DC_ODAC_LB_LUT_SEL_MASK 0x10 #define PHY_BB_TXIQCAL_CONTROL_4_DC_ODAC_LB_LUT_SEL_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_4_DC_ODAC_LB_LUT_SEL_MASK) >> PHY_BB_TXIQCAL_CONTROL_4_DC_ODAC_LB_LUT_SEL_LSB) #define PHY_BB_TXIQCAL_CONTROL_4_DC_ODAC_LB_LUT_SEL_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_4_DC_ODAC_LB_LUT_SEL_LSB) & PHY_BB_TXIQCAL_CONTROL_4_DC_ODAC_LB_LUT_SEL_MASK) #define PHY_BB_TXIQCAL_CONTROL_4_DC_ODAC_LB_LUT_SEL_RESET 0x0 #define PHY_BB_TXIQCAL_CONTROL_4_IQCAL_PEAK_EST_CORR_FACTOR_LSB 0 #define PHY_BB_TXIQCAL_CONTROL_4_IQCAL_PEAK_EST_CORR_FACTOR_MSB 3 #define PHY_BB_TXIQCAL_CONTROL_4_IQCAL_PEAK_EST_CORR_FACTOR_MASK 0xf #define PHY_BB_TXIQCAL_CONTROL_4_IQCAL_PEAK_EST_CORR_FACTOR_GET(x) (((x) & PHY_BB_TXIQCAL_CONTROL_4_IQCAL_PEAK_EST_CORR_FACTOR_MASK) >> PHY_BB_TXIQCAL_CONTROL_4_IQCAL_PEAK_EST_CORR_FACTOR_LSB) #define PHY_BB_TXIQCAL_CONTROL_4_IQCAL_PEAK_EST_CORR_FACTOR_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_CONTROL_4_IQCAL_PEAK_EST_CORR_FACTOR_LSB) & PHY_BB_TXIQCAL_CONTROL_4_IQCAL_PEAK_EST_CORR_FACTOR_MASK) #define PHY_BB_TXIQCAL_CONTROL_4_IQCAL_PEAK_EST_CORR_FACTOR_RESET 0x4 #define PHY_BB_TXIQCAL_CONTROL_4_ADDRESS (0x454 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TXIQCAL_CONTROL_4_RSTMASK 0x3f #define PHY_BB_TXIQCAL_CONTROL_4_RESET 0x24 // 0x470 (PHY_BB_CAL_RXBB_GAIN_TBL_0) #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB 24 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MSB 31 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK 0xff000000 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB 16 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MSB 23 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK 0xff0000 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB 8 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MSB 15 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK 0xff00 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB 0 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MSB 7 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK 0xff #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_ADDRESS (0x470 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CAL_RXBB_GAIN_TBL_0_RSTMASK 0xffffffff #define PHY_BB_CAL_RXBB_GAIN_TBL_0_RESET 0x0 // 0x474 (PHY_BB_CAL_RXBB_GAIN_TBL_4) #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB 24 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MSB 31 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK 0xff000000 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB 16 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MSB 23 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK 0xff0000 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB 8 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MSB 15 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK 0xff00 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB 0 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MSB 7 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK 0xff #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_ADDRESS (0x474 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CAL_RXBB_GAIN_TBL_4_RSTMASK 0xffffffff #define PHY_BB_CAL_RXBB_GAIN_TBL_4_RESET 0x0 // 0x478 (PHY_BB_CAL_RXBB_GAIN_TBL_8) #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB 24 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MSB 31 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK 0xff000000 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB 16 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MSB 23 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK 0xff0000 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB 8 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MSB 15 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK 0xff00 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB 0 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MSB 7 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK 0xff #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_ADDRESS (0x478 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CAL_RXBB_GAIN_TBL_8_RSTMASK 0xffffffff #define PHY_BB_CAL_RXBB_GAIN_TBL_8_RESET 0x0 // 0x47c (PHY_BB_CAL_RXBB_GAIN_TBL_12) #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB 24 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MSB 31 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK 0xff000000 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB 16 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MSB 23 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK 0xff0000 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB 8 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MSB 15 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK 0xff00 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB 0 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MSB 7 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK 0xff #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_ADDRESS (0x47c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CAL_RXBB_GAIN_TBL_12_RSTMASK 0xffffffff #define PHY_BB_CAL_RXBB_GAIN_TBL_12_RESET 0x0 // 0x480 (PHY_BB_CAL_RXBB_GAIN_TBL_16) #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB 24 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MSB 31 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK 0xff000000 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB 16 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MSB 23 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK 0xff0000 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB 8 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MSB 15 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK 0xff00 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB 0 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MSB 7 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK 0xff #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_ADDRESS (0x480 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CAL_RXBB_GAIN_TBL_16_RSTMASK 0xffffffff #define PHY_BB_CAL_RXBB_GAIN_TBL_16_RESET 0x0 // 0x484 (PHY_BB_CAL_RXBB_GAIN_TBL_20) #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB 24 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MSB 31 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK 0xff000000 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB 16 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MSB 23 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK 0xff0000 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB 8 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MSB 15 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK 0xff00 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB 0 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MSB 7 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK 0xff #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_ADDRESS (0x484 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CAL_RXBB_GAIN_TBL_20_RSTMASK 0xffffffff #define PHY_BB_CAL_RXBB_GAIN_TBL_20_RESET 0x0 // 0x488 (PHY_BB_CAL_RXBB_GAIN_TBL_24) #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB 0 #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MSB 7 #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK 0xff #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_GET(x) (((x) & PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK) >> PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB) #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB) & PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK) #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_RESET 0x0 #define PHY_BB_CAL_RXBB_GAIN_TBL_24_ADDRESS (0x488 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CAL_RXBB_GAIN_TBL_24_RSTMASK 0xff #define PHY_BB_CAL_RXBB_GAIN_TBL_24_RESET 0x0 // 0x48c (PHY_BB_TXIQCAL_STATUS_B0) #define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB 18 #define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MSB 23 #define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK 0xfc0000 #define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_GET(x) (((x) & PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK) >> PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB) #define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB) & PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK) #define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_RESET 0x0 #define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB 12 #define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MSB 17 #define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK 0x3f000 #define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_GET(x) (((x) & PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK) >> PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB) #define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB) & PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK) #define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_RESET 0x0 #define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB 6 #define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MSB 11 #define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK 0xfc0 #define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_GET(x) (((x) & PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK) >> PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB) #define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB) & PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK) #define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_RESET 0x0 #define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB 1 #define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MSB 5 #define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK 0x3e #define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_GET(x) (((x) & PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK) >> PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB) #define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB) & PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK) #define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_RESET 0x0 #define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB 0 #define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MSB 0 #define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK 0x1 #define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_GET(x) (((x) & PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK) >> PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB) #define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_SET(x) (((0 | (x)) << PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB) & PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK) #define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_RESET 0x0 #define PHY_BB_TXIQCAL_STATUS_B0_ADDRESS (0x48c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TXIQCAL_STATUS_B0_RSTMASK 0xffffff #define PHY_BB_TXIQCAL_STATUS_B0_RESET 0x0 // 0x490 (PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1) #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_TXCAL_RX_BB_TIA_GAIN_TABLE_1_LSB 0 #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_TXCAL_RX_BB_TIA_GAIN_TABLE_1_MSB 31 #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_TXCAL_RX_BB_TIA_GAIN_TABLE_1_MASK 0xffffffff #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_TXCAL_RX_BB_TIA_GAIN_TABLE_1_GET(x) (((x) & PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_TXCAL_RX_BB_TIA_GAIN_TABLE_1_MASK) >> PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_TXCAL_RX_BB_TIA_GAIN_TABLE_1_LSB) #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_TXCAL_RX_BB_TIA_GAIN_TABLE_1_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_TXCAL_RX_BB_TIA_GAIN_TABLE_1_LSB) & PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_TXCAL_RX_BB_TIA_GAIN_TABLE_1_MASK) #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_TXCAL_RX_BB_TIA_GAIN_TABLE_1_RESET 0x0 #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_ADDRESS (0x490 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_RSTMASK 0xffffffff #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_1_RESET 0x0 // 0x494 (PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2) #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_TXCAL_RX_BB_TIA_GAIN_TABLE_2_LSB 0 #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_TXCAL_RX_BB_TIA_GAIN_TABLE_2_MSB 17 #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_TXCAL_RX_BB_TIA_GAIN_TABLE_2_MASK 0x3ffff #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_TXCAL_RX_BB_TIA_GAIN_TABLE_2_GET(x) (((x) & PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_TXCAL_RX_BB_TIA_GAIN_TABLE_2_MASK) >> PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_TXCAL_RX_BB_TIA_GAIN_TABLE_2_LSB) #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_TXCAL_RX_BB_TIA_GAIN_TABLE_2_SET(x) (((0 | (x)) << PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_TXCAL_RX_BB_TIA_GAIN_TABLE_2_LSB) & PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_TXCAL_RX_BB_TIA_GAIN_TABLE_2_MASK) #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_TXCAL_RX_BB_TIA_GAIN_TABLE_2_RESET 0x0 #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_ADDRESS (0x494 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_RSTMASK 0x3ffff #define PHY_BB_CAL_RXBB_TIA_GAIN_TBL_2_RESET 0x0 // 0x4ac (PHY_BB_RXIQCAL_STATUS_B0) #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_LAST_MEAS_ADDR_0_LSB 11 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_LAST_MEAS_ADDR_0_MSB 16 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_LAST_MEAS_ADDR_0_MASK 0x1f800 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_LAST_MEAS_ADDR_0_GET(x) (((x) & PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_LAST_MEAS_ADDR_0_MASK) >> PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_LAST_MEAS_ADDR_0_LSB) #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_LAST_MEAS_ADDR_0_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_LAST_MEAS_ADDR_0_LSB) & PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_LAST_MEAS_ADDR_0_MASK) #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_LAST_MEAS_ADDR_0_RESET 0x0 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_TXGAIN_IDX_USED_0_LSB 6 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_TXGAIN_IDX_USED_0_MSB 10 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_TXGAIN_IDX_USED_0_MASK 0x7c0 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_TXGAIN_IDX_USED_0_GET(x) (((x) & PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_TXGAIN_IDX_USED_0_MASK) >> PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_TXGAIN_IDX_USED_0_LSB) #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_TXGAIN_IDX_USED_0_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_TXGAIN_IDX_USED_0_LSB) & PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_TXGAIN_IDX_USED_0_MASK) #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_TXGAIN_IDX_USED_0_RESET 0x0 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_CALIBRATED_GAINS_0_LSB 1 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_CALIBRATED_GAINS_0_MSB 5 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_CALIBRATED_GAINS_0_MASK 0x3e #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_CALIBRATED_GAINS_0_GET(x) (((x) & PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_CALIBRATED_GAINS_0_MASK) >> PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_CALIBRATED_GAINS_0_LSB) #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_CALIBRATED_GAINS_0_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_CALIBRATED_GAINS_0_LSB) & PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_CALIBRATED_GAINS_0_MASK) #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_CALIBRATED_GAINS_0_RESET 0x0 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_FAILED_0_LSB 0 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_FAILED_0_MSB 0 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_FAILED_0_MASK 0x1 #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_FAILED_0_GET(x) (((x) & PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_FAILED_0_MASK) >> PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_FAILED_0_LSB) #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_FAILED_0_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_FAILED_0_LSB) & PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_FAILED_0_MASK) #define PHY_BB_RXIQCAL_STATUS_B0_RXIQCAL_FAILED_0_RESET 0x0 #define PHY_BB_RXIQCAL_STATUS_B0_ADDRESS (0x4ac + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RXIQCAL_STATUS_B0_RSTMASK 0x1ffff #define PHY_BB_RXIQCAL_STATUS_B0_RESET 0x0 // 0x4d0 (PHY_BB_HSPRD_TRAIN_CNTL_0) #define PHY_BB_HSPRD_TRAIN_CNTL_0_CF_CAL_XPA_LSB 4 #define PHY_BB_HSPRD_TRAIN_CNTL_0_CF_CAL_XPA_MSB 4 #define PHY_BB_HSPRD_TRAIN_CNTL_0_CF_CAL_XPA_MASK 0x10 #define PHY_BB_HSPRD_TRAIN_CNTL_0_CF_CAL_XPA_GET(x) (((x) & PHY_BB_HSPRD_TRAIN_CNTL_0_CF_CAL_XPA_MASK) >> PHY_BB_HSPRD_TRAIN_CNTL_0_CF_CAL_XPA_LSB) #define PHY_BB_HSPRD_TRAIN_CNTL_0_CF_CAL_XPA_SET(x) (((0 | (x)) << PHY_BB_HSPRD_TRAIN_CNTL_0_CF_CAL_XPA_LSB) & PHY_BB_HSPRD_TRAIN_CNTL_0_CF_CAL_XPA_MASK) #define PHY_BB_HSPRD_TRAIN_CNTL_0_CF_CAL_XPA_RESET 0x0 #define PHY_BB_HSPRD_TRAIN_CNTL_0_ADDRESS (0x4d0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_HSPRD_TRAIN_CNTL_0_RSTMASK 0x10 #define PHY_BB_HSPRD_TRAIN_CNTL_0_RESET 0x0 // 0x4ec (PHY_BB_PEFCAL_CNTL_0) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_LB_SEL_LSB 30 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_LB_SEL_MSB 31 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_LB_SEL_MASK 0xc0000000 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_LB_SEL_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_LB_SEL_MASK) >> PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_LB_SEL_LSB) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_LB_SEL_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_LB_SEL_LSB) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_LB_SEL_MASK) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_LB_SEL_RESET 0x0 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_MAG_SEL_LSB 28 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_MAG_SEL_MSB 29 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_MAG_SEL_MASK 0x30000000 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_MAG_SEL_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_MAG_SEL_MASK) >> PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_MAG_SEL_LSB) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_MAG_SEL_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_MAG_SEL_LSB) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_MAG_SEL_MASK) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_MAG_SEL_RESET 0x2 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FSTEP_LSB 22 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FSTEP_MSB 27 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FSTEP_MASK 0xfc00000 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FSTEP_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FSTEP_MASK) >> PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FSTEP_LSB) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FSTEP_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FSTEP_LSB) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FSTEP_MASK) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FSTEP_RESET 0x1 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_F4AGC2_LSB 15 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_F4AGC2_MSB 21 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_F4AGC2_MASK 0x3f8000 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_F4AGC2_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_F4AGC2_MASK) >> PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_F4AGC2_LSB) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_F4AGC2_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_F4AGC2_LSB) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_F4AGC2_MASK) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_F4AGC2_RESET 0x10 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMIN_LSB 8 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMIN_MSB 14 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMIN_MASK 0x7f00 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMIN_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMIN_MASK) >> PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMIN_LSB) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMIN_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMIN_LSB) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMIN_MASK) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMIN_RESET 0x42 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMAX_LSB 1 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMAX_MSB 7 #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMAX_MASK 0xfe #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMAX_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMAX_MASK) >> PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMAX_LSB) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMAX_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMAX_LSB) & PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMAX_MASK) #define PHY_BB_PEFCAL_CNTL_0_CF_PEFCAL_FMAX_RESET 0x3e #define PHY_BB_PEFCAL_CNTL_0_ENABLE_PEF_CALIBRATE_LSB 0 #define PHY_BB_PEFCAL_CNTL_0_ENABLE_PEF_CALIBRATE_MSB 0 #define PHY_BB_PEFCAL_CNTL_0_ENABLE_PEF_CALIBRATE_MASK 0x1 #define PHY_BB_PEFCAL_CNTL_0_ENABLE_PEF_CALIBRATE_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_0_ENABLE_PEF_CALIBRATE_MASK) >> PHY_BB_PEFCAL_CNTL_0_ENABLE_PEF_CALIBRATE_LSB) #define PHY_BB_PEFCAL_CNTL_0_ENABLE_PEF_CALIBRATE_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_0_ENABLE_PEF_CALIBRATE_LSB) & PHY_BB_PEFCAL_CNTL_0_ENABLE_PEF_CALIBRATE_MASK) #define PHY_BB_PEFCAL_CNTL_0_ENABLE_PEF_CALIBRATE_RESET 0x0 #define PHY_BB_PEFCAL_CNTL_0_ADDRESS (0x4ec + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PEFCAL_CNTL_0_RSTMASK 0xffffffff #define PHY_BB_PEFCAL_CNTL_0_RESET 0x2048427c // 0x4f0 (PHY_BB_PEFCAL_CNTL_1) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TABLE_SEL_LSB 19 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TABLE_SEL_MSB 19 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TABLE_SEL_MASK 0x80000 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TABLE_SEL_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TABLE_SEL_MASK) >> PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TABLE_SEL_LSB) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TABLE_SEL_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TABLE_SEL_LSB) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TABLE_SEL_MASK) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TABLE_SEL_RESET 0x0 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CONTINUOUS_CAL_LSB 18 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CONTINUOUS_CAL_MSB 18 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CONTINUOUS_CAL_MASK 0x40000 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CONTINUOUS_CAL_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CONTINUOUS_CAL_MASK) >> PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CONTINUOUS_CAL_LSB) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CONTINUOUS_CAL_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CONTINUOUS_CAL_LSB) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CONTINUOUS_CAL_MASK) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CONTINUOUS_CAL_RESET 0x0 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_SMART_PREAMBLE_LSB 17 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_SMART_PREAMBLE_MSB 17 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_SMART_PREAMBLE_MASK 0x20000 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_SMART_PREAMBLE_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_SMART_PREAMBLE_MASK) >> PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_SMART_PREAMBLE_LSB) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_SMART_PREAMBLE_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_SMART_PREAMBLE_LSB) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_SMART_PREAMBLE_MASK) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_SMART_PREAMBLE_RESET 0x0 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TXGAIN_IDX_LSB 12 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TXGAIN_IDX_MSB 16 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TXGAIN_IDX_MASK 0x1f000 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TXGAIN_IDX_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TXGAIN_IDX_MASK) >> PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TXGAIN_IDX_LSB) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TXGAIN_IDX_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TXGAIN_IDX_LSB) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TXGAIN_IDX_MASK) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TXGAIN_IDX_RESET 0x0 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_LSB 4 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_MSB 11 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_MASK 0xff0 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_MASK) >> PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_LSB) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_LSB) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_MASK) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_RESET 0xa #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CHN_SEL_LSB 2 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CHN_SEL_MSB 3 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CHN_SEL_MASK 0xc #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CHN_SEL_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CHN_SEL_MASK) >> PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CHN_SEL_LSB) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CHN_SEL_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CHN_SEL_LSB) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CHN_SEL_MASK) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_CHN_SEL_RESET 0x0 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_ENABLE_LSB 1 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_ENABLE_MSB 1 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_ENABLE_MASK 0x2 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_ENABLE_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_ENABLE_MASK) >> PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_ENABLE_LSB) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_ENABLE_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_ENABLE_LSB) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_ENABLE_MASK) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TIMEOUT_ENABLE_RESET 0x1 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TRXIQCL_CORRECTED_LSB 0 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TRXIQCL_CORRECTED_MSB 0 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TRXIQCL_CORRECTED_MASK 0x1 #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TRXIQCL_CORRECTED_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TRXIQCL_CORRECTED_MASK) >> PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TRXIQCL_CORRECTED_LSB) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TRXIQCL_CORRECTED_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TRXIQCL_CORRECTED_LSB) & PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TRXIQCL_CORRECTED_MASK) #define PHY_BB_PEFCAL_CNTL_1_CF_PEFCAL_TRXIQCL_CORRECTED_RESET 0x0 #define PHY_BB_PEFCAL_CNTL_1_ADDRESS (0x4f0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PEFCAL_CNTL_1_RSTMASK 0xfffff #define PHY_BB_PEFCAL_CNTL_1_RESET 0xa2 // 0x4f4 (PHY_BB_PEFCAL_CNTL_2) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_CORR_LEN_LSB 26 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_CORR_LEN_MSB 28 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_CORR_LEN_MASK 0x1c000000 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_CORR_LEN_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_CORR_LEN_MASK) >> PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_CORR_LEN_LSB) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_CORR_LEN_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_CORR_LEN_LSB) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_CORR_LEN_MASK) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_CORR_LEN_RESET 0x7 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_SETTLING_TIME_LSB 20 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_SETTLING_TIME_MSB 25 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_SETTLING_TIME_MASK 0x3f00000 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_SETTLING_TIME_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_SETTLING_TIME_MASK) >> PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_SETTLING_TIME_LSB) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_SETTLING_TIME_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_SETTLING_TIME_LSB) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_SETTLING_TIME_MASK) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_SETTLING_TIME_RESET 0x3f #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IDLE_TIME_LSB 14 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IDLE_TIME_MSB 19 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IDLE_TIME_MASK 0xfc000 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IDLE_TIME_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IDLE_TIME_MASK) >> PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IDLE_TIME_LSB) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IDLE_TIME_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IDLE_TIME_LSB) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IDLE_TIME_MASK) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IDLE_TIME_RESET 0x3f #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PREAMBLE_TIME_LSB 2 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PREAMBLE_TIME_MSB 13 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PREAMBLE_TIME_MASK 0x3ffc #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PREAMBLE_TIME_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PREAMBLE_TIME_MASK) >> PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PREAMBLE_TIME_LSB) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PREAMBLE_TIME_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PREAMBLE_TIME_LSB) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PREAMBLE_TIME_MASK) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PREAMBLE_TIME_RESET 0xff #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IS_WAITING_LSB 1 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IS_WAITING_MSB 1 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IS_WAITING_MASK 0x2 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IS_WAITING_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IS_WAITING_MASK) >> PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IS_WAITING_LSB) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IS_WAITING_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IS_WAITING_LSB) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IS_WAITING_MASK) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_IS_WAITING_RESET 0x0 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PHASE_SEL_LSB 0 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PHASE_SEL_MSB 0 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PHASE_SEL_MASK 0x1 #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PHASE_SEL_GET(x) (((x) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PHASE_SEL_MASK) >> PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PHASE_SEL_LSB) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PHASE_SEL_SET(x) (((0 | (x)) << PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PHASE_SEL_LSB) & PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PHASE_SEL_MASK) #define PHY_BB_PEFCAL_CNTL_2_CF_PEFCAL_PHASE_SEL_RESET 0x0 #define PHY_BB_PEFCAL_CNTL_2_ADDRESS (0x4f4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PEFCAL_CNTL_2_RSTMASK 0x1fffffff #define PHY_BB_PEFCAL_CNTL_2_RESET 0x1fffc3fc // 0x4f8 (PHY_BB_PREEMP_CNTL_0) #define PHY_BB_PREEMP_CNTL_0_PREEMP_MASK_LSB 1 #define PHY_BB_PREEMP_CNTL_0_PREEMP_MASK_MSB 31 #define PHY_BB_PREEMP_CNTL_0_PREEMP_MASK_MASK 0xfffffffe #define PHY_BB_PREEMP_CNTL_0_PREEMP_MASK_GET(x) (((x) & PHY_BB_PREEMP_CNTL_0_PREEMP_MASK_MASK) >> PHY_BB_PREEMP_CNTL_0_PREEMP_MASK_LSB) #define PHY_BB_PREEMP_CNTL_0_PREEMP_MASK_SET(x) (((0 | (x)) << PHY_BB_PREEMP_CNTL_0_PREEMP_MASK_LSB) & PHY_BB_PREEMP_CNTL_0_PREEMP_MASK_MASK) #define PHY_BB_PREEMP_CNTL_0_PREEMP_MASK_RESET 0x0 #define PHY_BB_PREEMP_CNTL_0_TX_PREEMP_FIR_EN_LSB 0 #define PHY_BB_PREEMP_CNTL_0_TX_PREEMP_FIR_EN_MSB 0 #define PHY_BB_PREEMP_CNTL_0_TX_PREEMP_FIR_EN_MASK 0x1 #define PHY_BB_PREEMP_CNTL_0_TX_PREEMP_FIR_EN_GET(x) (((x) & PHY_BB_PREEMP_CNTL_0_TX_PREEMP_FIR_EN_MASK) >> PHY_BB_PREEMP_CNTL_0_TX_PREEMP_FIR_EN_LSB) #define PHY_BB_PREEMP_CNTL_0_TX_PREEMP_FIR_EN_SET(x) (((0 | (x)) << PHY_BB_PREEMP_CNTL_0_TX_PREEMP_FIR_EN_LSB) & PHY_BB_PREEMP_CNTL_0_TX_PREEMP_FIR_EN_MASK) #define PHY_BB_PREEMP_CNTL_0_TX_PREEMP_FIR_EN_RESET 0x0 #define PHY_BB_PREEMP_CNTL_0_ADDRESS (0x4f8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PREEMP_CNTL_0_RSTMASK 0xffffffff #define PHY_BB_PREEMP_CNTL_0_RESET 0x0 // 0x4fc (PHY_BB_PREEMP_CNTL_1) #define PHY_BB_PREEMP_CNTL_1_TX_PREEMP_HALF_RATE_EN_LSB 0 #define PHY_BB_PREEMP_CNTL_1_TX_PREEMP_HALF_RATE_EN_MSB 0 #define PHY_BB_PREEMP_CNTL_1_TX_PREEMP_HALF_RATE_EN_MASK 0x1 #define PHY_BB_PREEMP_CNTL_1_TX_PREEMP_HALF_RATE_EN_GET(x) (((x) & PHY_BB_PREEMP_CNTL_1_TX_PREEMP_HALF_RATE_EN_MASK) >> PHY_BB_PREEMP_CNTL_1_TX_PREEMP_HALF_RATE_EN_LSB) #define PHY_BB_PREEMP_CNTL_1_TX_PREEMP_HALF_RATE_EN_SET(x) (((0 | (x)) << PHY_BB_PREEMP_CNTL_1_TX_PREEMP_HALF_RATE_EN_LSB) & PHY_BB_PREEMP_CNTL_1_TX_PREEMP_HALF_RATE_EN_MASK) #define PHY_BB_PREEMP_CNTL_1_TX_PREEMP_HALF_RATE_EN_RESET 0x0 #define PHY_BB_PREEMP_CNTL_1_ADDRESS (0x4fc + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PREEMP_CNTL_1_RSTMASK 0x1 #define PHY_BB_PREEMP_CNTL_1_RESET 0x0 // 0x500 (PHY_BB_PAPRD_BW_CNTL_0) #define PHY_BB_PAPRD_BW_CNTL_0_PAPRD_CONTROL_BW_EN_LSB 0 #define PHY_BB_PAPRD_BW_CNTL_0_PAPRD_CONTROL_BW_EN_MSB 0 #define PHY_BB_PAPRD_BW_CNTL_0_PAPRD_CONTROL_BW_EN_MASK 0x1 #define PHY_BB_PAPRD_BW_CNTL_0_PAPRD_CONTROL_BW_EN_GET(x) (((x) & PHY_BB_PAPRD_BW_CNTL_0_PAPRD_CONTROL_BW_EN_MASK) >> PHY_BB_PAPRD_BW_CNTL_0_PAPRD_CONTROL_BW_EN_LSB) #define PHY_BB_PAPRD_BW_CNTL_0_PAPRD_CONTROL_BW_EN_SET(x) (((0 | (x)) << PHY_BB_PAPRD_BW_CNTL_0_PAPRD_CONTROL_BW_EN_LSB) & PHY_BB_PAPRD_BW_CNTL_0_PAPRD_CONTROL_BW_EN_MASK) #define PHY_BB_PAPRD_BW_CNTL_0_PAPRD_CONTROL_BW_EN_RESET 0x0 #define PHY_BB_PAPRD_BW_CNTL_0_ADDRESS (0x500 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PAPRD_BW_CNTL_0_RSTMASK 0x1 #define PHY_BB_PAPRD_BW_CNTL_0_RESET 0x0 // 0x504 (PHY_BB_RXIQCAL_CONTROL_0) #define PHY_BB_RXIQCAL_CONTROL_0_ENABLE_RXIQ_CALIBRATE_LSB 31 #define PHY_BB_RXIQCAL_CONTROL_0_ENABLE_RXIQ_CALIBRATE_MSB 31 #define PHY_BB_RXIQCAL_CONTROL_0_ENABLE_RXIQ_CALIBRATE_MASK 0x80000000 #define PHY_BB_RXIQCAL_CONTROL_0_ENABLE_RXIQ_CALIBRATE_GET(x) (((x) & PHY_BB_RXIQCAL_CONTROL_0_ENABLE_RXIQ_CALIBRATE_MASK) >> PHY_BB_RXIQCAL_CONTROL_0_ENABLE_RXIQ_CALIBRATE_LSB) #define PHY_BB_RXIQCAL_CONTROL_0_ENABLE_RXIQ_CALIBRATE_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_CONTROL_0_ENABLE_RXIQ_CALIBRATE_LSB) & PHY_BB_RXIQCAL_CONTROL_0_ENABLE_RXIQ_CALIBRATE_MASK) #define PHY_BB_RXIQCAL_CONTROL_0_ENABLE_RXIQ_CALIBRATE_RESET 0x0 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_INIT_DB_LSB 24 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_INIT_DB_MSB 29 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_INIT_DB_MASK 0x3f000000 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_INIT_DB_GET(x) (((x) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_INIT_DB_MASK) >> PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_INIT_DB_LSB) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_INIT_DB_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_INIT_DB_LSB) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_INIT_DB_MASK) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_INIT_DB_RESET 0x3c #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MAX_DB_LSB 18 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MAX_DB_MSB 23 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MAX_DB_MASK 0xfc0000 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MAX_DB_GET(x) (((x) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MAX_DB_MASK) >> PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MAX_DB_LSB) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MAX_DB_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MAX_DB_LSB) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MAX_DB_MASK) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MAX_DB_RESET 0x3c #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MIN_DB_LSB 12 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MIN_DB_MSB 17 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MIN_DB_MASK 0x3f000 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MIN_DB_GET(x) (((x) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MIN_DB_MASK) >> PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MIN_DB_LSB) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MIN_DB_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MIN_DB_LSB) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MIN_DB_MASK) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_TX_GAIN_MIN_DB_RESET 0x0 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MAX_RX_GAIN_LSB 8 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MAX_RX_GAIN_MSB 11 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MAX_RX_GAIN_MASK 0xf00 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MAX_RX_GAIN_GET(x) (((x) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MAX_RX_GAIN_MASK) >> PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MAX_RX_GAIN_LSB) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MAX_RX_GAIN_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MAX_RX_GAIN_LSB) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MAX_RX_GAIN_MASK) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MAX_RX_GAIN_RESET 0xf #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MIN_RX_GAIN_LSB 4 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MIN_RX_GAIN_MSB 7 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MIN_RX_GAIN_MASK 0xf0 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MIN_RX_GAIN_GET(x) (((x) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MIN_RX_GAIN_MASK) >> PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MIN_RX_GAIN_LSB) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MIN_RX_GAIN_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MIN_RX_GAIN_LSB) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MIN_RX_GAIN_MASK) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_MIN_RX_GAIN_RESET 0x0 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_LOOPBACK_MODE_LSB 3 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_LOOPBACK_MODE_MSB 3 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_LOOPBACK_MODE_MASK 0x8 #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_LOOPBACK_MODE_GET(x) (((x) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_LOOPBACK_MODE_MASK) >> PHY_BB_RXIQCAL_CONTROL_0_RXCAL_LOOPBACK_MODE_LSB) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_LOOPBACK_MODE_SET(x) (((0 | (x)) << PHY_BB_RXIQCAL_CONTROL_0_RXCAL_LOOPBACK_MODE_LSB) & PHY_BB_RXIQCAL_CONTROL_0_RXCAL_LOOPBACK_MODE_MASK) #define PHY_BB_RXIQCAL_CONTROL_0_RXCAL_LOOPBACK_MODE_RESET 0x0 #define PHY_BB_RXIQCAL_CONTROL_0_ADDRESS (0x504 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_RXIQCAL_CONTROL_0_RSTMASK 0xbffffff8 #define PHY_BB_RXIQCAL_CONTROL_0_RESET 0x3cf00f00 // 0x508 (PHY_BB_TX_NOTCH_CNTL_0) #define PHY_BB_TX_NOTCH_CNTL_0_NOTCH_MASK_LSB 1 #define PHY_BB_TX_NOTCH_CNTL_0_NOTCH_MASK_MSB 31 #define PHY_BB_TX_NOTCH_CNTL_0_NOTCH_MASK_MASK 0xfffffffe #define PHY_BB_TX_NOTCH_CNTL_0_NOTCH_MASK_GET(x) (((x) & PHY_BB_TX_NOTCH_CNTL_0_NOTCH_MASK_MASK) >> PHY_BB_TX_NOTCH_CNTL_0_NOTCH_MASK_LSB) #define PHY_BB_TX_NOTCH_CNTL_0_NOTCH_MASK_SET(x) (((0 | (x)) << PHY_BB_TX_NOTCH_CNTL_0_NOTCH_MASK_LSB) & PHY_BB_TX_NOTCH_CNTL_0_NOTCH_MASK_MASK) #define PHY_BB_TX_NOTCH_CNTL_0_NOTCH_MASK_RESET 0x0 #define PHY_BB_TX_NOTCH_CNTL_0_CF_TX_NOTCH_IIR_EN_LSB 0 #define PHY_BB_TX_NOTCH_CNTL_0_CF_TX_NOTCH_IIR_EN_MSB 0 #define PHY_BB_TX_NOTCH_CNTL_0_CF_TX_NOTCH_IIR_EN_MASK 0x1 #define PHY_BB_TX_NOTCH_CNTL_0_CF_TX_NOTCH_IIR_EN_GET(x) (((x) & PHY_BB_TX_NOTCH_CNTL_0_CF_TX_NOTCH_IIR_EN_MASK) >> PHY_BB_TX_NOTCH_CNTL_0_CF_TX_NOTCH_IIR_EN_LSB) #define PHY_BB_TX_NOTCH_CNTL_0_CF_TX_NOTCH_IIR_EN_SET(x) (((0 | (x)) << PHY_BB_TX_NOTCH_CNTL_0_CF_TX_NOTCH_IIR_EN_LSB) & PHY_BB_TX_NOTCH_CNTL_0_CF_TX_NOTCH_IIR_EN_MASK) #define PHY_BB_TX_NOTCH_CNTL_0_CF_TX_NOTCH_IIR_EN_RESET 0x0 #define PHY_BB_TX_NOTCH_CNTL_0_ADDRESS (0x508 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TX_NOTCH_CNTL_0_RSTMASK 0xffffffff #define PHY_BB_TX_NOTCH_CNTL_0_RESET 0x0 // 0x510 (PHY_BB_DBG_MASK_AGC) #define PHY_BB_DBG_MASK_AGC_DEBUG_MUX_ENA_LSB 31 #define PHY_BB_DBG_MASK_AGC_DEBUG_MUX_ENA_MSB 31 #define PHY_BB_DBG_MASK_AGC_DEBUG_MUX_ENA_MASK 0x80000000 #define PHY_BB_DBG_MASK_AGC_DEBUG_MUX_ENA_GET(x) (((x) & PHY_BB_DBG_MASK_AGC_DEBUG_MUX_ENA_MASK) >> PHY_BB_DBG_MASK_AGC_DEBUG_MUX_ENA_LSB) #define PHY_BB_DBG_MASK_AGC_DEBUG_MUX_ENA_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_AGC_DEBUG_MUX_ENA_LSB) & PHY_BB_DBG_MASK_AGC_DEBUG_MUX_ENA_MASK) #define PHY_BB_DBG_MASK_AGC_DEBUG_MUX_ENA_RESET 0x0 #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_B_LSB 28 #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_B_MSB 30 #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_B_MASK 0x70000000 #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_B_GET(x) (((x) & PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_B_MASK) >> PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_B_LSB) #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_B_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_B_LSB) & PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_B_MASK) #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_B_RESET 0x0 #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_A_LSB 24 #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_A_MSB 26 #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_A_MASK 0x7000000 #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_A_GET(x) (((x) & PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_A_MASK) >> PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_A_LSB) #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_A_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_A_LSB) & PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_A_MASK) #define PHY_BB_DBG_MASK_AGC_DBG_BUS_AGC_SEL_A_RESET 0x0 #define PHY_BB_DBG_MASK_AGC_DBG_MASK_AGC_LSB 0 #define PHY_BB_DBG_MASK_AGC_DBG_MASK_AGC_MSB 23 #define PHY_BB_DBG_MASK_AGC_DBG_MASK_AGC_MASK 0xffffff #define PHY_BB_DBG_MASK_AGC_DBG_MASK_AGC_GET(x) (((x) & PHY_BB_DBG_MASK_AGC_DBG_MASK_AGC_MASK) >> PHY_BB_DBG_MASK_AGC_DBG_MASK_AGC_LSB) #define PHY_BB_DBG_MASK_AGC_DBG_MASK_AGC_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_AGC_DBG_MASK_AGC_LSB) & PHY_BB_DBG_MASK_AGC_DBG_MASK_AGC_MASK) #define PHY_BB_DBG_MASK_AGC_DBG_MASK_AGC_RESET 0x0 #define PHY_BB_DBG_MASK_AGC_ADDRESS (0x510 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_AGC_RSTMASK 0xf7ffffff #define PHY_BB_DBG_MASK_AGC_RESET 0x0 // 0x514 (PHY_BB_DBG_MASK_RXSM) #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_B_LSB 28 #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_B_MSB 30 #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_B_MASK 0x70000000 #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_B_GET(x) (((x) & PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_B_MASK) >> PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_B_LSB) #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_B_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_B_LSB) & PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_B_MASK) #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_B_RESET 0x0 #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_A_LSB 24 #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_A_MSB 26 #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_A_MASK 0x7000000 #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_A_GET(x) (((x) & PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_A_MASK) >> PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_A_LSB) #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_A_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_A_LSB) & PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_A_MASK) #define PHY_BB_DBG_MASK_RXSM_DBG_BUS_RXSM_SEL_A_RESET 0x0 #define PHY_BB_DBG_MASK_RXSM_DBG_MASK_RXSM_LSB 0 #define PHY_BB_DBG_MASK_RXSM_DBG_MASK_RXSM_MSB 23 #define PHY_BB_DBG_MASK_RXSM_DBG_MASK_RXSM_MASK 0xffffff #define PHY_BB_DBG_MASK_RXSM_DBG_MASK_RXSM_GET(x) (((x) & PHY_BB_DBG_MASK_RXSM_DBG_MASK_RXSM_MASK) >> PHY_BB_DBG_MASK_RXSM_DBG_MASK_RXSM_LSB) #define PHY_BB_DBG_MASK_RXSM_DBG_MASK_RXSM_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_RXSM_DBG_MASK_RXSM_LSB) & PHY_BB_DBG_MASK_RXSM_DBG_MASK_RXSM_MASK) #define PHY_BB_DBG_MASK_RXSM_DBG_MASK_RXSM_RESET 0x0 #define PHY_BB_DBG_MASK_RXSM_ADDRESS (0x514 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_RXSM_RSTMASK 0x77ffffff #define PHY_BB_DBG_MASK_RXSM_RESET 0x0 // 0x518 (PHY_BB_DBG_MASK_TXSM) #define PHY_BB_DBG_MASK_TXSM_DBG_MASK_TXSM_LSB 0 #define PHY_BB_DBG_MASK_TXSM_DBG_MASK_TXSM_MSB 31 #define PHY_BB_DBG_MASK_TXSM_DBG_MASK_TXSM_MASK 0xffffffff #define PHY_BB_DBG_MASK_TXSM_DBG_MASK_TXSM_GET(x) (((x) & PHY_BB_DBG_MASK_TXSM_DBG_MASK_TXSM_MASK) >> PHY_BB_DBG_MASK_TXSM_DBG_MASK_TXSM_LSB) #define PHY_BB_DBG_MASK_TXSM_DBG_MASK_TXSM_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_TXSM_DBG_MASK_TXSM_LSB) & PHY_BB_DBG_MASK_TXSM_DBG_MASK_TXSM_MASK) #define PHY_BB_DBG_MASK_TXSM_DBG_MASK_TXSM_RESET 0x0 #define PHY_BB_DBG_MASK_TXSM_ADDRESS (0x518 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_TXSM_RSTMASK 0xffffffff #define PHY_BB_DBG_MASK_TXSM_RESET 0x0 // 0x51c (PHY_BB_DBG_MASK_TCTL) #define PHY_BB_DBG_MASK_TCTL_DBG_MASK_TCTL_LSB 0 #define PHY_BB_DBG_MASK_TCTL_DBG_MASK_TCTL_MSB 31 #define PHY_BB_DBG_MASK_TCTL_DBG_MASK_TCTL_MASK 0xffffffff #define PHY_BB_DBG_MASK_TCTL_DBG_MASK_TCTL_GET(x) (((x) & PHY_BB_DBG_MASK_TCTL_DBG_MASK_TCTL_MASK) >> PHY_BB_DBG_MASK_TCTL_DBG_MASK_TCTL_LSB) #define PHY_BB_DBG_MASK_TCTL_DBG_MASK_TCTL_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_TCTL_DBG_MASK_TCTL_LSB) & PHY_BB_DBG_MASK_TCTL_DBG_MASK_TCTL_MASK) #define PHY_BB_DBG_MASK_TCTL_DBG_MASK_TCTL_RESET 0x0 #define PHY_BB_DBG_MASK_TCTL_ADDRESS (0x51c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_TCTL_RSTMASK 0xffffffff #define PHY_BB_DBG_MASK_TCTL_RESET 0x0 // 0x520 (PHY_BB_DBG_MASK_VIT) #define PHY_BB_DBG_MASK_VIT_DBG_MASK_VIT_LSB 0 #define PHY_BB_DBG_MASK_VIT_DBG_MASK_VIT_MSB 31 #define PHY_BB_DBG_MASK_VIT_DBG_MASK_VIT_MASK 0xffffffff #define PHY_BB_DBG_MASK_VIT_DBG_MASK_VIT_GET(x) (((x) & PHY_BB_DBG_MASK_VIT_DBG_MASK_VIT_MASK) >> PHY_BB_DBG_MASK_VIT_DBG_MASK_VIT_LSB) #define PHY_BB_DBG_MASK_VIT_DBG_MASK_VIT_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_VIT_DBG_MASK_VIT_LSB) & PHY_BB_DBG_MASK_VIT_DBG_MASK_VIT_MASK) #define PHY_BB_DBG_MASK_VIT_DBG_MASK_VIT_RESET 0x0 #define PHY_BB_DBG_MASK_VIT_ADDRESS (0x520 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_VIT_RSTMASK 0xffffffff #define PHY_BB_DBG_MASK_VIT_RESET 0x0 // 0x524 (PHY_BB_DBG_MASK_DFS) #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_B_LSB 28 #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_B_MSB 30 #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_B_MASK 0x70000000 #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_B_GET(x) (((x) & PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_B_MASK) >> PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_B_LSB) #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_B_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_B_LSB) & PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_B_MASK) #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_B_RESET 0x0 #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_A_LSB 24 #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_A_MSB 26 #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_A_MASK 0x7000000 #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_A_GET(x) (((x) & PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_A_MASK) >> PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_A_LSB) #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_A_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_A_LSB) & PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_A_MASK) #define PHY_BB_DBG_MASK_DFS_DBG_BUS_DFS_SEL_A_RESET 0x0 #define PHY_BB_DBG_MASK_DFS_DBG_MASK_DFS_LSB 0 #define PHY_BB_DBG_MASK_DFS_DBG_MASK_DFS_MSB 23 #define PHY_BB_DBG_MASK_DFS_DBG_MASK_DFS_MASK 0xffffff #define PHY_BB_DBG_MASK_DFS_DBG_MASK_DFS_GET(x) (((x) & PHY_BB_DBG_MASK_DFS_DBG_MASK_DFS_MASK) >> PHY_BB_DBG_MASK_DFS_DBG_MASK_DFS_LSB) #define PHY_BB_DBG_MASK_DFS_DBG_MASK_DFS_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_DFS_DBG_MASK_DFS_LSB) & PHY_BB_DBG_MASK_DFS_DBG_MASK_DFS_MASK) #define PHY_BB_DBG_MASK_DFS_DBG_MASK_DFS_RESET 0x0 #define PHY_BB_DBG_MASK_DFS_ADDRESS (0x524 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_DFS_RSTMASK 0x77ffffff #define PHY_BB_DBG_MASK_DFS_RESET 0x0 // 0x528 (PHY_BB_DBG_MASK_CAL) #define PHY_BB_DBG_MASK_CAL_DBG_MASK_CAL_LSB 0 #define PHY_BB_DBG_MASK_CAL_DBG_MASK_CAL_MSB 31 #define PHY_BB_DBG_MASK_CAL_DBG_MASK_CAL_MASK 0xffffffff #define PHY_BB_DBG_MASK_CAL_DBG_MASK_CAL_GET(x) (((x) & PHY_BB_DBG_MASK_CAL_DBG_MASK_CAL_MASK) >> PHY_BB_DBG_MASK_CAL_DBG_MASK_CAL_LSB) #define PHY_BB_DBG_MASK_CAL_DBG_MASK_CAL_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_CAL_DBG_MASK_CAL_LSB) & PHY_BB_DBG_MASK_CAL_DBG_MASK_CAL_MASK) #define PHY_BB_DBG_MASK_CAL_DBG_MASK_CAL_RESET 0x0 #define PHY_BB_DBG_MASK_CAL_ADDRESS (0x528 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_CAL_RSTMASK 0xffffffff #define PHY_BB_DBG_MASK_CAL_RESET 0x0 // 0x52c (PHY_BB_DBG_MASK_TPC) #define PHY_BB_DBG_MASK_TPC_DBG_MASK_TPC_LSB 0 #define PHY_BB_DBG_MASK_TPC_DBG_MASK_TPC_MSB 31 #define PHY_BB_DBG_MASK_TPC_DBG_MASK_TPC_MASK 0xffffffff #define PHY_BB_DBG_MASK_TPC_DBG_MASK_TPC_GET(x) (((x) & PHY_BB_DBG_MASK_TPC_DBG_MASK_TPC_MASK) >> PHY_BB_DBG_MASK_TPC_DBG_MASK_TPC_LSB) #define PHY_BB_DBG_MASK_TPC_DBG_MASK_TPC_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_TPC_DBG_MASK_TPC_LSB) & PHY_BB_DBG_MASK_TPC_DBG_MASK_TPC_MASK) #define PHY_BB_DBG_MASK_TPC_DBG_MASK_TPC_RESET 0x0 #define PHY_BB_DBG_MASK_TPC_ADDRESS (0x52c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_TPC_RSTMASK 0xffffffff #define PHY_BB_DBG_MASK_TPC_RESET 0x0 // 0x530 (PHY_BB_DBG_MASK_SVD) #define PHY_BB_DBG_MASK_SVD_DBG_MASK_SVD_LSB 0 #define PHY_BB_DBG_MASK_SVD_DBG_MASK_SVD_MSB 31 #define PHY_BB_DBG_MASK_SVD_DBG_MASK_SVD_MASK 0xffffffff #define PHY_BB_DBG_MASK_SVD_DBG_MASK_SVD_GET(x) (((x) & PHY_BB_DBG_MASK_SVD_DBG_MASK_SVD_MASK) >> PHY_BB_DBG_MASK_SVD_DBG_MASK_SVD_LSB) #define PHY_BB_DBG_MASK_SVD_DBG_MASK_SVD_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_SVD_DBG_MASK_SVD_LSB) & PHY_BB_DBG_MASK_SVD_DBG_MASK_SVD_MASK) #define PHY_BB_DBG_MASK_SVD_DBG_MASK_SVD_RESET 0x0 #define PHY_BB_DBG_MASK_SVD_ADDRESS (0x530 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_SVD_RSTMASK 0xffffffff #define PHY_BB_DBG_MASK_SVD_RESET 0x0 // 0x534 (PHY_BB_DBG_MASK_MPI) #define PHY_BB_DBG_MASK_MPI_DBG_MASK_MPI_LSB 0 #define PHY_BB_DBG_MASK_MPI_DBG_MASK_MPI_MSB 31 #define PHY_BB_DBG_MASK_MPI_DBG_MASK_MPI_MASK 0xffffffff #define PHY_BB_DBG_MASK_MPI_DBG_MASK_MPI_GET(x) (((x) & PHY_BB_DBG_MASK_MPI_DBG_MASK_MPI_MASK) >> PHY_BB_DBG_MASK_MPI_DBG_MASK_MPI_LSB) #define PHY_BB_DBG_MASK_MPI_DBG_MASK_MPI_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_MPI_DBG_MASK_MPI_LSB) & PHY_BB_DBG_MASK_MPI_DBG_MASK_MPI_MASK) #define PHY_BB_DBG_MASK_MPI_DBG_MASK_MPI_RESET 0x0 #define PHY_BB_DBG_MASK_MPI_ADDRESS (0x534 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_MPI_RSTMASK 0xffffffff #define PHY_BB_DBG_MASK_MPI_RESET 0x0 // 0x538 (PHY_BB_DBG_MASK_PMI) #define PHY_BB_DBG_MASK_PMI_DBG_MASK_PMI_LSB 0 #define PHY_BB_DBG_MASK_PMI_DBG_MASK_PMI_MSB 31 #define PHY_BB_DBG_MASK_PMI_DBG_MASK_PMI_MASK 0xffffffff #define PHY_BB_DBG_MASK_PMI_DBG_MASK_PMI_GET(x) (((x) & PHY_BB_DBG_MASK_PMI_DBG_MASK_PMI_MASK) >> PHY_BB_DBG_MASK_PMI_DBG_MASK_PMI_LSB) #define PHY_BB_DBG_MASK_PMI_DBG_MASK_PMI_SET(x) (((0 | (x)) << PHY_BB_DBG_MASK_PMI_DBG_MASK_PMI_LSB) & PHY_BB_DBG_MASK_PMI_DBG_MASK_PMI_MASK) #define PHY_BB_DBG_MASK_PMI_DBG_MASK_PMI_RESET 0x0 #define PHY_BB_DBG_MASK_PMI_ADDRESS (0x538 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_MASK_PMI_RSTMASK 0xffffffff #define PHY_BB_DBG_MASK_PMI_RESET 0x0 // 0x53c (PHY_BB_DBG_BUS_SEL_SM) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_RXSM_LSB 9 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_RXSM_MSB 11 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_RXSM_MASK 0xe00 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_RXSM_GET(x) (((x) & PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_RXSM_MASK) >> PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_RXSM_LSB) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_RXSM_SET(x) (((0 | (x)) << PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_RXSM_LSB) & PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_RXSM_MASK) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_RXSM_RESET 0x0 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXBE_LSB 7 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXBE_MSB 8 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXBE_MASK 0x180 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXBE_GET(x) (((x) & PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXBE_MASK) >> PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXBE_LSB) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXBE_SET(x) (((0 | (x)) << PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXBE_LSB) & PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXBE_MASK) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXBE_RESET 0x0 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_MPI_LSB 5 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_MPI_MSB 6 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_MPI_MASK 0x60 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_MPI_GET(x) (((x) & PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_MPI_MASK) >> PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_MPI_LSB) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_MPI_SET(x) (((0 | (x)) << PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_MPI_LSB) & PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_MPI_MASK) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_MPI_RESET 0x0 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXB_LSB 3 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXB_MSB 4 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXB_MASK 0x18 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXB_GET(x) (((x) & PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXB_MASK) >> PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXB_LSB) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXB_SET(x) (((0 | (x)) << PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXB_LSB) & PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXB_MASK) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXB_RESET 0x0 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXA_LSB 0 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXA_MSB 2 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXA_MASK 0x7 #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXA_GET(x) (((x) & PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXA_MASK) >> PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXA_LSB) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXA_SET(x) (((0 | (x)) << PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXA_LSB) & PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXA_MASK) #define PHY_BB_DBG_BUS_SEL_SM_DBG_BUS_SEL_TXA_RESET 0x0 #define PHY_BB_DBG_BUS_SEL_SM_ADDRESS (0x53c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_DBG_BUS_SEL_SM_RSTMASK 0xfff #define PHY_BB_DBG_BUS_SEL_SM_RESET 0x0 // 0x540 (PHY_BB_TXA_STATE_HISTORY) #define PHY_BB_TXA_STATE_HISTORY_TXA_STATE_HISTORY_LSB 0 #define PHY_BB_TXA_STATE_HISTORY_TXA_STATE_HISTORY_MSB 31 #define PHY_BB_TXA_STATE_HISTORY_TXA_STATE_HISTORY_MASK 0xffffffff #define PHY_BB_TXA_STATE_HISTORY_TXA_STATE_HISTORY_GET(x) (((x) & PHY_BB_TXA_STATE_HISTORY_TXA_STATE_HISTORY_MASK) >> PHY_BB_TXA_STATE_HISTORY_TXA_STATE_HISTORY_LSB) #define PHY_BB_TXA_STATE_HISTORY_TXA_STATE_HISTORY_SET(x) (((0 | (x)) << PHY_BB_TXA_STATE_HISTORY_TXA_STATE_HISTORY_LSB) & PHY_BB_TXA_STATE_HISTORY_TXA_STATE_HISTORY_MASK) #define PHY_BB_TXA_STATE_HISTORY_TXA_STATE_HISTORY_RESET 0x0 #define PHY_BB_TXA_STATE_HISTORY_ADDRESS (0x540 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TXA_STATE_HISTORY_RSTMASK 0xffffffff #define PHY_BB_TXA_STATE_HISTORY_RESET 0x0 // 0x544 (PHY_BB_TXB_STATE_HISTORY) #define PHY_BB_TXB_STATE_HISTORY_TXB_STATE_HISTORY_LSB 0 #define PHY_BB_TXB_STATE_HISTORY_TXB_STATE_HISTORY_MSB 31 #define PHY_BB_TXB_STATE_HISTORY_TXB_STATE_HISTORY_MASK 0xffffffff #define PHY_BB_TXB_STATE_HISTORY_TXB_STATE_HISTORY_GET(x) (((x) & PHY_BB_TXB_STATE_HISTORY_TXB_STATE_HISTORY_MASK) >> PHY_BB_TXB_STATE_HISTORY_TXB_STATE_HISTORY_LSB) #define PHY_BB_TXB_STATE_HISTORY_TXB_STATE_HISTORY_SET(x) (((0 | (x)) << PHY_BB_TXB_STATE_HISTORY_TXB_STATE_HISTORY_LSB) & PHY_BB_TXB_STATE_HISTORY_TXB_STATE_HISTORY_MASK) #define PHY_BB_TXB_STATE_HISTORY_TXB_STATE_HISTORY_RESET 0x0 #define PHY_BB_TXB_STATE_HISTORY_ADDRESS (0x544 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TXB_STATE_HISTORY_RSTMASK 0xffffffff #define PHY_BB_TXB_STATE_HISTORY_RESET 0x0 // 0x548 (PHY_BB_TLV_STATE_HISTORY) #define PHY_BB_TLV_STATE_HISTORY_TLV_STATE_HISTORY_LSB 0 #define PHY_BB_TLV_STATE_HISTORY_TLV_STATE_HISTORY_MSB 31 #define PHY_BB_TLV_STATE_HISTORY_TLV_STATE_HISTORY_MASK 0xffffffff #define PHY_BB_TLV_STATE_HISTORY_TLV_STATE_HISTORY_GET(x) (((x) & PHY_BB_TLV_STATE_HISTORY_TLV_STATE_HISTORY_MASK) >> PHY_BB_TLV_STATE_HISTORY_TLV_STATE_HISTORY_LSB) #define PHY_BB_TLV_STATE_HISTORY_TLV_STATE_HISTORY_SET(x) (((0 | (x)) << PHY_BB_TLV_STATE_HISTORY_TLV_STATE_HISTORY_LSB) & PHY_BB_TLV_STATE_HISTORY_TLV_STATE_HISTORY_MASK) #define PHY_BB_TLV_STATE_HISTORY_TLV_STATE_HISTORY_RESET 0x0 #define PHY_BB_TLV_STATE_HISTORY_ADDRESS (0x548 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TLV_STATE_HISTORY_RSTMASK 0xffffffff #define PHY_BB_TLV_STATE_HISTORY_RESET 0x0 // 0x54c (PHY_BB_PACKET_COUNTER) #define PHY_BB_PACKET_COUNTER_PMI_PKT_COUNT_LSB 16 #define PHY_BB_PACKET_COUNTER_PMI_PKT_COUNT_MSB 31 #define PHY_BB_PACKET_COUNTER_PMI_PKT_COUNT_MASK 0xffff0000 #define PHY_BB_PACKET_COUNTER_PMI_PKT_COUNT_GET(x) (((x) & PHY_BB_PACKET_COUNTER_PMI_PKT_COUNT_MASK) >> PHY_BB_PACKET_COUNTER_PMI_PKT_COUNT_LSB) #define PHY_BB_PACKET_COUNTER_PMI_PKT_COUNT_SET(x) (((0 | (x)) << PHY_BB_PACKET_COUNTER_PMI_PKT_COUNT_LSB) & PHY_BB_PACKET_COUNTER_PMI_PKT_COUNT_MASK) #define PHY_BB_PACKET_COUNTER_PMI_PKT_COUNT_RESET 0x0 #define PHY_BB_PACKET_COUNTER_MPI_PKT_COUNT_LSB 0 #define PHY_BB_PACKET_COUNTER_MPI_PKT_COUNT_MSB 15 #define PHY_BB_PACKET_COUNTER_MPI_PKT_COUNT_MASK 0xffff #define PHY_BB_PACKET_COUNTER_MPI_PKT_COUNT_GET(x) (((x) & PHY_BB_PACKET_COUNTER_MPI_PKT_COUNT_MASK) >> PHY_BB_PACKET_COUNTER_MPI_PKT_COUNT_LSB) #define PHY_BB_PACKET_COUNTER_MPI_PKT_COUNT_SET(x) (((0 | (x)) << PHY_BB_PACKET_COUNTER_MPI_PKT_COUNT_LSB) & PHY_BB_PACKET_COUNTER_MPI_PKT_COUNT_MASK) #define PHY_BB_PACKET_COUNTER_MPI_PKT_COUNT_RESET 0x0 #define PHY_BB_PACKET_COUNTER_ADDRESS (0x54c + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PACKET_COUNTER_RSTMASK 0xffffffff #define PHY_BB_PACKET_COUNTER_RESET 0x0 // 0x550 (PHY_BB_IBFCAL_RFCNTL) #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XLNAON_LSB 1 #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XLNAON_MSB 1 #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XLNAON_MASK 0x2 #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XLNAON_GET(x) (((x) & PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XLNAON_MASK) >> PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XLNAON_LSB) #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XLNAON_SET(x) (((0 | (x)) << PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XLNAON_LSB) & PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XLNAON_MASK) #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XLNAON_RESET 0x0 #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XPAON_LSB 0 #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XPAON_MSB 0 #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XPAON_MASK 0x1 #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XPAON_GET(x) (((x) & PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XPAON_MASK) >> PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XPAON_LSB) #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XPAON_SET(x) (((0 | (x)) << PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XPAON_LSB) & PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XPAON_MASK) #define PHY_BB_IBFCAL_RFCNTL_CF_IBFCAL_RX_XPAON_RESET 0x1 #define PHY_BB_IBFCAL_RFCNTL_ADDRESS (0x550 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_IBFCAL_RFCNTL_RSTMASK 0x3 #define PHY_BB_IBFCAL_RFCNTL_RESET 0x1 // 0x554 (PHY_BB_TPC_ERROR_COUNT) #define PHY_BB_TPC_ERROR_COUNT_TPC_ERROR_COUNT_LSB 0 #define PHY_BB_TPC_ERROR_COUNT_TPC_ERROR_COUNT_MSB 15 #define PHY_BB_TPC_ERROR_COUNT_TPC_ERROR_COUNT_MASK 0xffff #define PHY_BB_TPC_ERROR_COUNT_TPC_ERROR_COUNT_GET(x) (((x) & PHY_BB_TPC_ERROR_COUNT_TPC_ERROR_COUNT_MASK) >> PHY_BB_TPC_ERROR_COUNT_TPC_ERROR_COUNT_LSB) #define PHY_BB_TPC_ERROR_COUNT_TPC_ERROR_COUNT_SET(x) (((0 | (x)) << PHY_BB_TPC_ERROR_COUNT_TPC_ERROR_COUNT_LSB) & PHY_BB_TPC_ERROR_COUNT_TPC_ERROR_COUNT_MASK) #define PHY_BB_TPC_ERROR_COUNT_TPC_ERROR_COUNT_RESET 0x0 #define PHY_BB_TPC_ERROR_COUNT_ADDRESS (0x554 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TPC_ERROR_COUNT_RSTMASK 0xffff #define PHY_BB_TPC_ERROR_COUNT_RESET 0x0 // 0x5c0 (PHY_BB_WATCHDOG_STATUS) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_8_LSB 28 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_8_MSB 31 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_8_MASK 0xf0000000 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_8_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_8_MASK) >> PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_8_LSB) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_8_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_8_LSB) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_8_MASK) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_8_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_7_LSB 24 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_7_MSB 27 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_7_MASK 0xf000000 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_7_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_7_MASK) >> PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_7_LSB) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_7_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_7_LSB) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_7_MASK) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_7_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_6_LSB 21 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_6_MSB 23 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_6_MASK 0xe00000 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_6_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_6_MASK) >> PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_6_LSB) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_6_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_6_LSB) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_6_MASK) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_6_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_5_LSB 17 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_5_MSB 20 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_5_MASK 0x1e0000 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_5_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_5_MASK) >> PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_5_LSB) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_5_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_5_LSB) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_5_MASK) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_5_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_4_LSB 13 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_4_MSB 16 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_4_MASK 0x1e000 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_4_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_4_MASK) >> PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_4_LSB) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_4_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_4_LSB) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_4_MASK) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_4_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_3_LSB 8 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_3_MSB 12 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_3_MASK 0x1f00 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_3_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_3_MASK) >> PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_3_LSB) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_3_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_3_LSB) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_3_MASK) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_3_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_2_LSB 4 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_2_MSB 7 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_2_MASK 0xf0 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_2_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_2_MASK) >> PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_2_LSB) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_2_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_2_LSB) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_2_MASK) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_2_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_TIMEOUT_LSB 3 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_TIMEOUT_MSB 3 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_TIMEOUT_MASK 0x8 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_TIMEOUT_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_TIMEOUT_MASK) >> PHY_BB_WATCHDOG_STATUS_WATCHDOG_TIMEOUT_LSB) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_TIMEOUT_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_WATCHDOG_TIMEOUT_LSB) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_TIMEOUT_MASK) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_TIMEOUT_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_1_LSB 0 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_1_MSB 1 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_1_MASK 0x3 #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_1_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_1_MASK) >> PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_1_LSB) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_1_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_1_LSB) & PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_1_MASK) #define PHY_BB_WATCHDOG_STATUS_WATCHDOG_STATUS_1_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_ADDRESS (0x5c0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_WATCHDOG_STATUS_RSTMASK 0xfffffffb #define PHY_BB_WATCHDOG_STATUS_RESET 0x0 // 0x5c4 (PHY_BB_WATCHDOG_CTRL_1) #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT_LSB 16 #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT_MSB 31 #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT_MASK 0xffff0000 #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT_MASK) >> PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT_LSB) #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT_LSB) & PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT_MASK) #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT_LSB 2 #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT_MSB 15 #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT_MASK 0xfffc #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT_MASK) >> PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT_LSB) #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT_LSB) & PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT_MASK) #define PHY_BB_WATCHDOG_CTRL_1_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE_LSB 1 #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE_MSB 1 #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE_MASK 0x2 #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE_MASK) >> PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE_LSB) #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE_LSB) & PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE_MASK) #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LSB 0 #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE_MSB 0 #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE_MASK 0x1 #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE_MASK) >> PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LSB) #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE_LSB) & PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE_MASK) #define PHY_BB_WATCHDOG_CTRL_1_ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_1_ADDRESS (0x5c4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_WATCHDOG_CTRL_1_RSTMASK 0xffffffff #define PHY_BB_WATCHDOG_CTRL_1_RESET 0x0 // 0x5c8 (PHY_BB_WATCHDOG_CTRL_2) #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_AGC_HT_STF_LSB 11 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_AGC_HT_STF_MSB 11 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_AGC_HT_STF_MASK 0x800 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_AGC_HT_STF_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_AGC_HT_STF_MASK) >> PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_AGC_HT_STF_LSB) #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_AGC_HT_STF_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_AGC_HT_STF_LSB) & PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_AGC_HT_STF_MASK) #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_AGC_HT_STF_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_ARB_LSB 10 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_ARB_MSB 10 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_ARB_MASK 0x400 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_ARB_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_ARB_MASK) >> PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_ARB_LSB) #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_ARB_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_ARB_LSB) & PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_ARB_MASK) #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_ARB_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_SSCAN_LSB 9 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_SSCAN_MSB 9 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_SSCAN_MASK 0x200 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_SSCAN_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_SSCAN_MASK) >> PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_SSCAN_LSB) #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_SSCAN_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_SSCAN_LSB) & PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_SSCAN_MASK) #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_SSCAN_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_LSB 8 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_MSB 8 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_MASK 0x100 #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_MASK) >> PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_LSB) #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_LSB) & PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_MASK) #define PHY_BB_WATCHDOG_CTRL_2_ENABLE_WATCHDOG_RADAR_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_2_SW_ABORT_ACTIVE_LSB 3 #define PHY_BB_WATCHDOG_CTRL_2_SW_ABORT_ACTIVE_MSB 3 #define PHY_BB_WATCHDOG_CTRL_2_SW_ABORT_ACTIVE_MASK 0x8 #define PHY_BB_WATCHDOG_CTRL_2_SW_ABORT_ACTIVE_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_2_SW_ABORT_ACTIVE_MASK) >> PHY_BB_WATCHDOG_CTRL_2_SW_ABORT_ACTIVE_LSB) #define PHY_BB_WATCHDOG_CTRL_2_SW_ABORT_ACTIVE_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_2_SW_ABORT_ACTIVE_LSB) & PHY_BB_WATCHDOG_CTRL_2_SW_ABORT_ACTIVE_MASK) #define PHY_BB_WATCHDOG_CTRL_2_SW_ABORT_ACTIVE_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_IRQ_ENA_LSB 2 #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_IRQ_ENA_MSB 2 #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_IRQ_ENA_MASK 0x4 #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_IRQ_ENA_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_IRQ_ENA_MASK) >> PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_IRQ_ENA_LSB) #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_IRQ_ENA_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_IRQ_ENA_LSB) & PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_IRQ_ENA_MASK) #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_IRQ_ENA_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_TIMEOUT_RESET_ENA_LSB 1 #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_TIMEOUT_RESET_ENA_MSB 1 #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_TIMEOUT_RESET_ENA_MASK 0x2 #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_TIMEOUT_RESET_ENA_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_TIMEOUT_RESET_ENA_MASK) >> PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_TIMEOUT_RESET_ENA_LSB) #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_TIMEOUT_RESET_ENA_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_TIMEOUT_RESET_ENA_LSB) & PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_TIMEOUT_RESET_ENA_MASK) #define PHY_BB_WATCHDOG_CTRL_2_WATCHDOG_TIMEOUT_RESET_ENA_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB 0 #define PHY_BB_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MSB 0 #define PHY_BB_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK 0x1 #define PHY_BB_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_GET(x) (((x) & PHY_BB_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK) >> PHY_BB_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB) #define PHY_BB_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB) & PHY_BB_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK) #define PHY_BB_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_RESET 0x0 #define PHY_BB_WATCHDOG_CTRL_2_ADDRESS (0x5c8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_WATCHDOG_CTRL_2_RSTMASK 0xf0f #define PHY_BB_WATCHDOG_CTRL_2_RESET 0x0 // 0x5cc (PHY_BB_BLUETOOTH_CNTL) #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB 1 #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MSB 1 #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK 0x2 #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_GET(x) (((x) & PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK) >> PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB) #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_SET(x) (((0 | (x)) << PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB) & PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK) #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_RESET 0x0 #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB 0 #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MSB 0 #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK 0x1 #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_GET(x) (((x) & PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK) >> PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB) #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_SET(x) (((0 | (x)) << PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB) & PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK) #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_RESET 0x0 #define PHY_BB_BLUETOOTH_CNTL_ADDRESS (0x5cc + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_BLUETOOTH_CNTL_RSTMASK 0x3 #define PHY_BB_BLUETOOTH_CNTL_RESET 0x0 // 0x5d4 (PHY_BB_PHYONLY_CONTROL) #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB 7 #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MSB 7 #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK 0x80 #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_GET(x) (((x) & PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK) >> PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB) #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_SET(x) (((0 | (x)) << PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB) & PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK) #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_RESET 0x0 #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB 6 #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MSB 6 #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK 0x40 #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_GET(x) (((x) & PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK) >> PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB) #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_SET(x) (((0 | (x)) << PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB) & PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK) #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_RESET 0x0 #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB 5 #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MSB 5 #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK 0x20 #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_GET(x) (((x) & PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK) >> PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB) #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_SET(x) (((0 | (x)) << PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB) & PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK) #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_RESET 0x0 #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB 4 #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MSB 4 #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK 0x10 #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_GET(x) (((x) & PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK) >> PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB) #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_SET(x) (((0 | (x)) << PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB) & PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK) #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_RESET 0x0 #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB 3 #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MSB 3 #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK 0x8 #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_GET(x) (((x) & PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK) >> PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB) #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_SET(x) (((0 | (x)) << PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB) & PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK) #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_RESET 0x0 #define PHY_BB_PHYONLY_CONTROL_USE_FIXED_SCRAMBLER_SEED_LSB 2 #define PHY_BB_PHYONLY_CONTROL_USE_FIXED_SCRAMBLER_SEED_MSB 2 #define PHY_BB_PHYONLY_CONTROL_USE_FIXED_SCRAMBLER_SEED_MASK 0x4 #define PHY_BB_PHYONLY_CONTROL_USE_FIXED_SCRAMBLER_SEED_GET(x) (((x) & PHY_BB_PHYONLY_CONTROL_USE_FIXED_SCRAMBLER_SEED_MASK) >> PHY_BB_PHYONLY_CONTROL_USE_FIXED_SCRAMBLER_SEED_LSB) #define PHY_BB_PHYONLY_CONTROL_USE_FIXED_SCRAMBLER_SEED_SET(x) (((0 | (x)) << PHY_BB_PHYONLY_CONTROL_USE_FIXED_SCRAMBLER_SEED_LSB) & PHY_BB_PHYONLY_CONTROL_USE_FIXED_SCRAMBLER_SEED_MASK) #define PHY_BB_PHYONLY_CONTROL_USE_FIXED_SCRAMBLER_SEED_RESET 0x0 #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB 1 #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MSB 1 #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK 0x2 #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_GET(x) (((x) & PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK) >> PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB) #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_SET(x) (((0 | (x)) << PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB) & PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK) #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_RESET 0x0 #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB 0 #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MSB 0 #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK 0x1 #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_GET(x) (((x) & PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK) >> PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB) #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_SET(x) (((0 | (x)) << PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB) & PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK) #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_RESET 0x0 #define PHY_BB_PHYONLY_CONTROL_ADDRESS (0x5d4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PHYONLY_CONTROL_RSTMASK 0xff #define PHY_BB_PHYONLY_CONTROL_RESET 0x0 // 0x5dc (PHY_BB_ECO_CTRL) #define PHY_BB_ECO_CTRL_ECO_CTRL_LSB 0 #define PHY_BB_ECO_CTRL_ECO_CTRL_MSB 31 #define PHY_BB_ECO_CTRL_ECO_CTRL_MASK 0xffffffff #define PHY_BB_ECO_CTRL_ECO_CTRL_GET(x) (((x) & PHY_BB_ECO_CTRL_ECO_CTRL_MASK) >> PHY_BB_ECO_CTRL_ECO_CTRL_LSB) #define PHY_BB_ECO_CTRL_ECO_CTRL_SET(x) (((0 | (x)) << PHY_BB_ECO_CTRL_ECO_CTRL_LSB) & PHY_BB_ECO_CTRL_ECO_CTRL_MASK) #define PHY_BB_ECO_CTRL_ECO_CTRL_RESET 0x0 #define PHY_BB_ECO_CTRL_ADDRESS (0x5dc + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_ECO_CTRL_RSTMASK 0xffffffff #define PHY_BB_ECO_CTRL_RESET 0x0 // 0x5e0 (PHY_BB_WATCHDOG_STATUS_B) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RESERVED_LSB 26 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RESERVED_MSB 31 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RESERVED_MASK 0xfc000000 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RESERVED_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RESERVED_MASK) >> PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RESERVED_LSB) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RESERVED_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RESERVED_LSB) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RESERVED_MASK) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RESERVED_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_PWR_SM_LSB 24 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_PWR_SM_MSB 25 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_PWR_SM_MASK 0x3000000 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_PWR_SM_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_PWR_SM_MASK) >> PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_PWR_SM_LSB) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_PWR_SM_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_PWR_SM_LSB) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_PWR_SM_MASK) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_PWR_SM_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_BW_SM_LSB 20 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_BW_SM_MSB 23 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_BW_SM_MASK 0xf00000 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_BW_SM_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_BW_SM_MASK) >> PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_BW_SM_LSB) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_BW_SM_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_BW_SM_LSB) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_BW_SM_MASK) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_BW_SM_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_OUT_SM_LSB 18 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_OUT_SM_MSB 19 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_OUT_SM_MASK 0xc0000 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_OUT_SM_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_OUT_SM_MASK) >> PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_OUT_SM_LSB) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_OUT_SM_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_OUT_SM_LSB) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_OUT_SM_MASK) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_OUT_SM_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_IN_SM_LSB 16 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_IN_SM_MSB 17 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_IN_SM_MASK 0x30000 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_IN_SM_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_IN_SM_MASK) >> PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_IN_SM_LSB) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_IN_SM_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_IN_SM_LSB) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_IN_SM_MASK) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_IN_SM_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_SEM_LOCK_LSB 12 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_SEM_LOCK_MSB 15 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_SEM_LOCK_MASK 0xf000 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_SEM_LOCK_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_SEM_LOCK_MASK) >> PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_SEM_LOCK_LSB) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_SEM_LOCK_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_SEM_LOCK_LSB) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_SEM_LOCK_MASK) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SRCHFFT_SEM_LOCK_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SSCAN_SM_LSB 8 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SSCAN_SM_MSB 11 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SSCAN_SM_MASK 0xf00 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SSCAN_SM_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SSCAN_SM_MASK) >> PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SSCAN_SM_LSB) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SSCAN_SM_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SSCAN_SM_LSB) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SSCAN_SM_MASK) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_SSCAN_SM_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RADAR_SM_LSB 4 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RADAR_SM_MSB 7 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RADAR_SM_MASK 0xf0 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RADAR_SM_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RADAR_SM_MASK) >> PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RADAR_SM_LSB) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RADAR_SM_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RADAR_SM_LSB) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RADAR_SM_MASK) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_RADAR_SM_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_HANG_FLAGS_LSB 0 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_HANG_FLAGS_MSB 3 #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_HANG_FLAGS_MASK 0xf #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_HANG_FLAGS_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_HANG_FLAGS_MASK) >> PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_HANG_FLAGS_LSB) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_HANG_FLAGS_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_HANG_FLAGS_LSB) & PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_HANG_FLAGS_MASK) #define PHY_BB_WATCHDOG_STATUS_B_WATCHDOG_STATUS_B_HANG_FLAGS_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_B_ADDRESS (0x5e0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_WATCHDOG_STATUS_B_RSTMASK 0xffffffff #define PHY_BB_WATCHDOG_STATUS_B_RESET 0x0 // 0x5e4 (PHY_BB_TLV_CTRL1) #define PHY_BB_TLV_CTRL1_TLV_FLOW_CONTROL_THRESHOLD_LSB 0 #define PHY_BB_TLV_CTRL1_TLV_FLOW_CONTROL_THRESHOLD_MSB 4 #define PHY_BB_TLV_CTRL1_TLV_FLOW_CONTROL_THRESHOLD_MASK 0x1f #define PHY_BB_TLV_CTRL1_TLV_FLOW_CONTROL_THRESHOLD_GET(x) (((x) & PHY_BB_TLV_CTRL1_TLV_FLOW_CONTROL_THRESHOLD_MASK) >> PHY_BB_TLV_CTRL1_TLV_FLOW_CONTROL_THRESHOLD_LSB) #define PHY_BB_TLV_CTRL1_TLV_FLOW_CONTROL_THRESHOLD_SET(x) (((0 | (x)) << PHY_BB_TLV_CTRL1_TLV_FLOW_CONTROL_THRESHOLD_LSB) & PHY_BB_TLV_CTRL1_TLV_FLOW_CONTROL_THRESHOLD_MASK) #define PHY_BB_TLV_CTRL1_TLV_FLOW_CONTROL_THRESHOLD_RESET 0x2 #define PHY_BB_TLV_CTRL1_ADDRESS (0x5e4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TLV_CTRL1_RSTMASK 0x1f #define PHY_BB_TLV_CTRL1_RESET 0x2 // 0x5e8 (PHY_BB_PHY_RX_TIMEOUT) #define PHY_BB_PHY_RX_TIMEOUT_RXSM_TIMEOUT_THRESHOLD_LSB 0 #define PHY_BB_PHY_RX_TIMEOUT_RXSM_TIMEOUT_THRESHOLD_MSB 11 #define PHY_BB_PHY_RX_TIMEOUT_RXSM_TIMEOUT_THRESHOLD_MASK 0xfff #define PHY_BB_PHY_RX_TIMEOUT_RXSM_TIMEOUT_THRESHOLD_GET(x) (((x) & PHY_BB_PHY_RX_TIMEOUT_RXSM_TIMEOUT_THRESHOLD_MASK) >> PHY_BB_PHY_RX_TIMEOUT_RXSM_TIMEOUT_THRESHOLD_LSB) #define PHY_BB_PHY_RX_TIMEOUT_RXSM_TIMEOUT_THRESHOLD_SET(x) (((0 | (x)) << PHY_BB_PHY_RX_TIMEOUT_RXSM_TIMEOUT_THRESHOLD_LSB) & PHY_BB_PHY_RX_TIMEOUT_RXSM_TIMEOUT_THRESHOLD_MASK) #define PHY_BB_PHY_RX_TIMEOUT_RXSM_TIMEOUT_THRESHOLD_RESET 0x7ff #define PHY_BB_PHY_RX_TIMEOUT_ADDRESS (0x5e8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_PHY_RX_TIMEOUT_RSTMASK 0xfff #define PHY_BB_PHY_RX_TIMEOUT_RESET 0x7ff // 0x5ec (PHY_BB_TX_PHASE_DITHER) #define PHY_BB_TX_PHASE_DITHER_ENABLE_CSD_PHASE_DITHERING_LSB 1 #define PHY_BB_TX_PHASE_DITHER_ENABLE_CSD_PHASE_DITHERING_MSB 3 #define PHY_BB_TX_PHASE_DITHER_ENABLE_CSD_PHASE_DITHERING_MASK 0xe #define PHY_BB_TX_PHASE_DITHER_ENABLE_CSD_PHASE_DITHERING_GET(x) (((x) & PHY_BB_TX_PHASE_DITHER_ENABLE_CSD_PHASE_DITHERING_MASK) >> PHY_BB_TX_PHASE_DITHER_ENABLE_CSD_PHASE_DITHERING_LSB) #define PHY_BB_TX_PHASE_DITHER_ENABLE_CSD_PHASE_DITHERING_SET(x) (((0 | (x)) << PHY_BB_TX_PHASE_DITHER_ENABLE_CSD_PHASE_DITHERING_LSB) & PHY_BB_TX_PHASE_DITHER_ENABLE_CSD_PHASE_DITHERING_MASK) #define PHY_BB_TX_PHASE_DITHER_ENABLE_CSD_PHASE_DITHERING_RESET 0x0 #define PHY_BB_TX_PHASE_DITHER_ADDRESS (0x5ec + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TX_PHASE_DITHER_RSTMASK 0xe #define PHY_BB_TX_PHASE_DITHER_RESET 0x0 // 0x5f0 (PHY_BB_TABLES_INTF_ADDR_B0) #define PHY_BB_TABLES_INTF_ADDR_B0_ADDR_AUTO_INCR_0_LSB 31 #define PHY_BB_TABLES_INTF_ADDR_B0_ADDR_AUTO_INCR_0_MSB 31 #define PHY_BB_TABLES_INTF_ADDR_B0_ADDR_AUTO_INCR_0_MASK 0x80000000 #define PHY_BB_TABLES_INTF_ADDR_B0_ADDR_AUTO_INCR_0_GET(x) (((x) & PHY_BB_TABLES_INTF_ADDR_B0_ADDR_AUTO_INCR_0_MASK) >> PHY_BB_TABLES_INTF_ADDR_B0_ADDR_AUTO_INCR_0_LSB) #define PHY_BB_TABLES_INTF_ADDR_B0_ADDR_AUTO_INCR_0_SET(x) (((0 | (x)) << PHY_BB_TABLES_INTF_ADDR_B0_ADDR_AUTO_INCR_0_LSB) & PHY_BB_TABLES_INTF_ADDR_B0_ADDR_AUTO_INCR_0_MASK) #define PHY_BB_TABLES_INTF_ADDR_B0_ADDR_AUTO_INCR_0_RESET 0x0 #define PHY_BB_TABLES_INTF_ADDR_B0_TABLES_ADDR_0_LSB 2 #define PHY_BB_TABLES_INTF_ADDR_B0_TABLES_ADDR_0_MSB 17 #define PHY_BB_TABLES_INTF_ADDR_B0_TABLES_ADDR_0_MASK 0x3fffc #define PHY_BB_TABLES_INTF_ADDR_B0_TABLES_ADDR_0_GET(x) (((x) & PHY_BB_TABLES_INTF_ADDR_B0_TABLES_ADDR_0_MASK) >> PHY_BB_TABLES_INTF_ADDR_B0_TABLES_ADDR_0_LSB) #define PHY_BB_TABLES_INTF_ADDR_B0_TABLES_ADDR_0_SET(x) (((0 | (x)) << PHY_BB_TABLES_INTF_ADDR_B0_TABLES_ADDR_0_LSB) & PHY_BB_TABLES_INTF_ADDR_B0_TABLES_ADDR_0_MASK) #define PHY_BB_TABLES_INTF_ADDR_B0_TABLES_ADDR_0_RESET 0x0 #define PHY_BB_TABLES_INTF_ADDR_B0_ADDRESS (0x5f0 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TABLES_INTF_ADDR_B0_RSTMASK 0x8003fffc #define PHY_BB_TABLES_INTF_ADDR_B0_RESET 0x0 // 0x5f4 (PHY_BB_TABLES_INTF_DATA_B0) #define PHY_BB_TABLES_INTF_DATA_B0_TABLES_DATA_0_LSB 0 #define PHY_BB_TABLES_INTF_DATA_B0_TABLES_DATA_0_MSB 31 #define PHY_BB_TABLES_INTF_DATA_B0_TABLES_DATA_0_MASK 0xffffffff #define PHY_BB_TABLES_INTF_DATA_B0_TABLES_DATA_0_GET(x) (((x) & PHY_BB_TABLES_INTF_DATA_B0_TABLES_DATA_0_MASK) >> PHY_BB_TABLES_INTF_DATA_B0_TABLES_DATA_0_LSB) #define PHY_BB_TABLES_INTF_DATA_B0_TABLES_DATA_0_SET(x) (((0 | (x)) << PHY_BB_TABLES_INTF_DATA_B0_TABLES_DATA_0_LSB) & PHY_BB_TABLES_INTF_DATA_B0_TABLES_DATA_0_MASK) #define PHY_BB_TABLES_INTF_DATA_B0_TABLES_DATA_0_RESET 0x0 #define PHY_BB_TABLES_INTF_DATA_B0_ADDRESS (0x5f4 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_TABLES_INTF_DATA_B0_RSTMASK 0xffffffff #define PHY_BB_TABLES_INTF_DATA_B0_RESET 0x0 // 0x5f8 (PHY_BB_WATCHDOG_STATUS_C) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ERROR_LSB 31 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ERROR_MSB 31 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ERROR_MASK 0x80000000 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ERROR_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ERROR_MASK) >> PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ERROR_LSB) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ERROR_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ERROR_LSB) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ERROR_MASK) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ERROR_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_TERMINATE_LSB 30 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_TERMINATE_MSB 30 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_TERMINATE_MASK 0x40000000 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_TERMINATE_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_TERMINATE_MASK) >> PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_TERMINATE_LSB) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_TERMINATE_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_TERMINATE_LSB) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_TERMINATE_MASK) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_TERMINATE_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ABORT_LSB 29 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ABORT_MSB 29 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ABORT_MASK 0x20000000 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ABORT_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ABORT_MASK) >> PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ABORT_LSB) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ABORT_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ABORT_LSB) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ABORT_MASK) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_ABORT_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TX_UNDERRUN_LSB 28 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TX_UNDERRUN_MSB 28 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TX_UNDERRUN_MASK 0x10000000 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TX_UNDERRUN_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TX_UNDERRUN_MASK) >> PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TX_UNDERRUN_LSB) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TX_UNDERRUN_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TX_UNDERRUN_LSB) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TX_UNDERRUN_MASK) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TX_UNDERRUN_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER2_LSB 24 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER2_MSB 27 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER2_MASK 0xf000000 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER2_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER2_MASK) >> PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER2_LSB) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER2_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER2_LSB) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER2_MASK) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER2_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER1_LSB 20 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER1_MSB 23 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER1_MASK 0xf00000 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER1_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER1_MASK) >> PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER1_LSB) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER1_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER1_LSB) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER1_MASK) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER1_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER0_LSB 16 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER0_MSB 19 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER0_MASK 0xf0000 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER0_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER0_MASK) >> PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER0_LSB) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER0_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER0_LSB) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER0_MASK) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_TLV_COUNT_USER0_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_USER_LSB 14 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_USER_MSB 15 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_USER_MASK 0xc000 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_USER_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_USER_MASK) >> PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_USER_LSB) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_USER_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_USER_LSB) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_USER_MASK) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_USER_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_FILL_LEVEL_LSB 8 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_FILL_LEVEL_MSB 13 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_FILL_LEVEL_MASK 0x3f00 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_FILL_LEVEL_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_FILL_LEVEL_MASK) >> PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_FILL_LEVEL_LSB) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_FILL_LEVEL_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_FILL_LEVEL_LSB) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_FILL_LEVEL_MASK) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_FILL_LEVEL_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_TAG_LSB 0 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_TAG_MSB 7 #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_TAG_MASK 0xff #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_TAG_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_TAG_MASK) >> PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_TAG_LSB) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_TAG_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_TAG_LSB) & PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_TAG_MASK) #define PHY_BB_WATCHDOG_STATUS_C_WATCHDOG_STATUS_C_CURRENT_TAG_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_C_ADDRESS (0x5f8 + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_WATCHDOG_STATUS_C_RSTMASK 0xffffffff #define PHY_BB_WATCHDOG_STATUS_C_RESET 0x0 // 0x5fc (PHY_BB_WATCHDOG_STATUS_D) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_RESERVED_LSB 31 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_RESERVED_MSB 31 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_RESERVED_MASK 0x80000000 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_RESERVED_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_RESERVED_MASK) >> PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_RESERVED_LSB) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_RESERVED_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_RESERVED_LSB) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_RESERVED_MASK) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_RESERVED_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VECTOR_TRANSFER_ACTIVE_LSB 30 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VECTOR_TRANSFER_ACTIVE_MSB 30 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VECTOR_TRANSFER_ACTIVE_MASK 0x40000000 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VECTOR_TRANSFER_ACTIVE_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VECTOR_TRANSFER_ACTIVE_MASK) >> PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VECTOR_TRANSFER_ACTIVE_LSB) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VECTOR_TRANSFER_ACTIVE_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VECTOR_TRANSFER_ACTIVE_LSB) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VECTOR_TRANSFER_ACTIVE_MASK) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VECTOR_TRANSFER_ACTIVE_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VIT_TLV_COUNTER_LSB 26 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VIT_TLV_COUNTER_MSB 29 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VIT_TLV_COUNTER_MASK 0x3c000000 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VIT_TLV_COUNTER_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VIT_TLV_COUNTER_MASK) >> PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VIT_TLV_COUNTER_LSB) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VIT_TLV_COUNTER_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VIT_TLV_COUNTER_LSB) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VIT_TLV_COUNTER_MASK) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_VIT_TLV_COUNTER_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_PILOT_TLV_COUNTER_LSB 22 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_PILOT_TLV_COUNTER_MSB 25 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_PILOT_TLV_COUNTER_MASK 0x3c00000 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_PILOT_TLV_COUNTER_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_PILOT_TLV_COUNTER_MASK) >> PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_PILOT_TLV_COUNTER_LSB) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_PILOT_TLV_COUNTER_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_PILOT_TLV_COUNTER_LSB) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_PILOT_TLV_COUNTER_MASK) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_PILOT_TLV_COUNTER_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_STATE_LSB 19 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_STATE_MSB 21 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_STATE_MASK 0x380000 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_STATE_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_STATE_MASK) >> PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_STATE_LSB) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_STATE_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_STATE_LSB) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_STATE_MASK) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_STATE_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_START_LSB 16 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_START_MSB 18 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_START_MASK 0x70000 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_START_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_START_MASK) >> PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_START_LSB) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_START_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_START_LSB) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_START_MASK) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_MPI_TLV_START_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_SVD_TLV_COUNTER_LSB 12 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_SVD_TLV_COUNTER_MSB 15 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_SVD_TLV_COUNTER_MASK 0xf000 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_SVD_TLV_COUNTER_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_SVD_TLV_COUNTER_MASK) >> PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_SVD_TLV_COUNTER_LSB) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_SVD_TLV_COUNTER_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_SVD_TLV_COUNTER_LSB) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_SVD_TLV_COUNTER_MASK) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_SVD_TLV_COUNTER_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_AGC_TLV_COUNTER_LSB 8 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_AGC_TLV_COUNTER_MSB 11 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_AGC_TLV_COUNTER_MASK 0xf00 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_AGC_TLV_COUNTER_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_AGC_TLV_COUNTER_MASK) >> PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_AGC_TLV_COUNTER_LSB) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_AGC_TLV_COUNTER_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_AGC_TLV_COUNTER_LSB) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_AGC_TLV_COUNTER_MASK) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_AGC_TLV_COUNTER_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_STATE_LSB 5 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_STATE_MSB 7 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_STATE_MASK 0xe0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_STATE_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_STATE_MASK) >> PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_STATE_LSB) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_STATE_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_STATE_LSB) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_STATE_MASK) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_STATE_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_REQ_REGISTER_LSB 0 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_REQ_REGISTER_MSB 4 #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_REQ_REGISTER_MASK 0x1f #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_REQ_REGISTER_GET(x) (((x) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_REQ_REGISTER_MASK) >> PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_REQ_REGISTER_LSB) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_REQ_REGISTER_SET(x) (((0 | (x)) << PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_REQ_REGISTER_LSB) & PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_REQ_REGISTER_MASK) #define PHY_BB_WATCHDOG_STATUS_D_WATCHDOG_STATUS_D_ARBITER_REQ_REGISTER_RESET 0x0 #define PHY_BB_WATCHDOG_STATUS_D_ADDRESS (0x5fc + __PHY_SM_REG_MAP_BASE_ADDRESS) #define PHY_BB_WATCHDOG_STATUS_D_RSTMASK 0xffffffff #define PHY_BB_WATCHDOG_STATUS_D_RESET 0x0 #endif /* _PHY_SM_REG_MAP_H_ */